Commit | Line | Data |
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97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
31 | #include <linux/atomic.h> | |
32 | #include <linux/wait.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
a9f87f64 | 35 | #include <linux/rbtree.h> |
97b2e202 | 36 | #include <linux/hashtable.h> |
f54d1867 | 37 | #include <linux/dma-fence.h> |
97b2e202 | 38 | |
248a1d6f MY |
39 | #include <drm/ttm/ttm_bo_api.h> |
40 | #include <drm/ttm/ttm_bo_driver.h> | |
41 | #include <drm/ttm/ttm_placement.h> | |
42 | #include <drm/ttm/ttm_module.h> | |
43 | #include <drm/ttm/ttm_execbuf_util.h> | |
97b2e202 | 44 | |
d03846af | 45 | #include <drm/drmP.h> |
97b2e202 | 46 | #include <drm/drm_gem.h> |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
1b1f42d8 | 48 | #include <drm/gpu_scheduler.h> |
97b2e202 | 49 | |
78c16834 | 50 | #include <kgd_kfd_interface.h> |
c79563a3 RZ |
51 | #include "dm_pp_interface.h" |
52 | #include "kgd_pp_interface.h" | |
78c16834 | 53 | |
5fc3aeeb | 54 | #include "amd_shared.h" |
97b2e202 AD |
55 | #include "amdgpu_mode.h" |
56 | #include "amdgpu_ih.h" | |
57 | #include "amdgpu_irq.h" | |
58 | #include "amdgpu_ucode.h" | |
c632d799 | 59 | #include "amdgpu_ttm.h" |
0e5ca0d1 | 60 | #include "amdgpu_psp.h" |
97b2e202 | 61 | #include "amdgpu_gds.h" |
56113504 | 62 | #include "amdgpu_sync.h" |
78023016 | 63 | #include "amdgpu_ring.h" |
073440d2 | 64 | #include "amdgpu_vm.h" |
cf097881 | 65 | #include "amdgpu_dpm.h" |
a8fe58ce | 66 | #include "amdgpu_acp.h" |
4df654d2 | 67 | #include "amdgpu_uvd.h" |
5e568178 | 68 | #include "amdgpu_vce.h" |
95aa13f6 | 69 | #include "amdgpu_vcn.h" |
9a189996 | 70 | #include "amdgpu_mn.h" |
4562236b | 71 | #include "amdgpu_dm.h" |
ceeb50ed | 72 | #include "amdgpu_virt.h" |
3490bdb5 | 73 | #include "amdgpu_gart.h" |
75758255 | 74 | #include "amdgpu_debugfs.h" |
c79563a3 | 75 | |
97b2e202 AD |
76 | /* |
77 | * Modules parameters. | |
78 | */ | |
79 | extern int amdgpu_modeset; | |
80 | extern int amdgpu_vram_limit; | |
218b5dcd | 81 | extern int amdgpu_vis_vram_limit; |
83e74db6 | 82 | extern int amdgpu_gart_size; |
36d38372 | 83 | extern int amdgpu_gtt_size; |
95844d20 | 84 | extern int amdgpu_moverate; |
97b2e202 AD |
85 | extern int amdgpu_benchmarking; |
86 | extern int amdgpu_testing; | |
87 | extern int amdgpu_audio; | |
88 | extern int amdgpu_disp_priority; | |
89 | extern int amdgpu_hw_i2c; | |
90 | extern int amdgpu_pcie_gen2; | |
91 | extern int amdgpu_msi; | |
92 | extern int amdgpu_lockup_timeout; | |
93 | extern int amdgpu_dpm; | |
e635ee07 | 94 | extern int amdgpu_fw_load_type; |
97b2e202 AD |
95 | extern int amdgpu_aspm; |
96 | extern int amdgpu_runtime_pm; | |
0b693f0b | 97 | extern uint amdgpu_ip_block_mask; |
97b2e202 AD |
98 | extern int amdgpu_bapm; |
99 | extern int amdgpu_deep_color; | |
100 | extern int amdgpu_vm_size; | |
101 | extern int amdgpu_vm_block_size; | |
d07f14be | 102 | extern int amdgpu_vm_fragment_size; |
d9c13156 | 103 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 104 | extern int amdgpu_vm_debug; |
9a4b7d4c | 105 | extern int amdgpu_vm_update_mode; |
4562236b | 106 | extern int amdgpu_dc; |
02e749dc | 107 | extern int amdgpu_dc_log; |
1333f723 | 108 | extern int amdgpu_sched_jobs; |
4afcb303 | 109 | extern int amdgpu_sched_hw_submission; |
3ca67300 RZ |
110 | extern int amdgpu_no_evict; |
111 | extern int amdgpu_direct_gma_size; | |
0b693f0b RZ |
112 | extern uint amdgpu_pcie_gen_cap; |
113 | extern uint amdgpu_pcie_lane_cap; | |
114 | extern uint amdgpu_cg_mask; | |
115 | extern uint amdgpu_pg_mask; | |
116 | extern uint amdgpu_sdma_phase_quantum; | |
6f8941a2 | 117 | extern char *amdgpu_disable_cu; |
9accf2fd | 118 | extern char *amdgpu_virtual_display; |
0b693f0b | 119 | extern uint amdgpu_pp_feature_mask; |
6a7f76e7 | 120 | extern int amdgpu_vram_page_split; |
bce23e00 AD |
121 | extern int amdgpu_ngg; |
122 | extern int amdgpu_prim_buf_per_se; | |
123 | extern int amdgpu_pos_buf_per_se; | |
124 | extern int amdgpu_cntl_sb_buf_per_se; | |
125 | extern int amdgpu_param_buf_per_se; | |
65781c78 | 126 | extern int amdgpu_job_hang_limit; |
e8835e0e | 127 | extern int amdgpu_lbpw; |
4a75aefe | 128 | extern int amdgpu_compute_multipipe; |
dcebf026 | 129 | extern int amdgpu_gpu_recovery; |
97b2e202 | 130 | |
6dd13096 FK |
131 | #ifdef CONFIG_DRM_AMDGPU_SI |
132 | extern int amdgpu_si_support; | |
133 | #endif | |
7df28986 FK |
134 | #ifdef CONFIG_DRM_AMDGPU_CIK |
135 | extern int amdgpu_cik_support; | |
136 | #endif | |
97b2e202 | 137 | |
55ed8caf | 138 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
4b559c90 | 139 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 AD |
140 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
141 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
142 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | |
143 | #define AMDGPU_IB_POOL_SIZE 16 | |
144 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
145 | #define AMDGPUFB_CONN_LIMIT 4 | |
a5bde2f9 | 146 | #define AMDGPU_BIOS_NUM_SCRATCH 16 |
97b2e202 | 147 | |
36f523a7 JZ |
148 | /* max number of IP instances */ |
149 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | |
150 | ||
97b2e202 AD |
151 | /* hard reset data */ |
152 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
153 | ||
154 | /* reset flags */ | |
155 | #define AMDGPU_RESET_GFX (1 << 0) | |
156 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
157 | #define AMDGPU_RESET_DMA (1 << 2) | |
158 | #define AMDGPU_RESET_CP (1 << 3) | |
159 | #define AMDGPU_RESET_GRBM (1 << 4) | |
160 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
161 | #define AMDGPU_RESET_RLC (1 << 6) | |
162 | #define AMDGPU_RESET_SEM (1 << 7) | |
163 | #define AMDGPU_RESET_IH (1 << 8) | |
164 | #define AMDGPU_RESET_VMC (1 << 9) | |
165 | #define AMDGPU_RESET_MC (1 << 10) | |
166 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
167 | #define AMDGPU_RESET_UVD (1 << 12) | |
168 | #define AMDGPU_RESET_VCE (1 << 13) | |
169 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
170 | ||
97b2e202 AD |
171 | /* GFX current status */ |
172 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L | |
173 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L | |
174 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L | |
175 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L | |
176 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L | |
177 | ||
178 | /* max cursor sizes (in pixels) */ | |
179 | #define CIK_CURSOR_WIDTH 128 | |
180 | #define CIK_CURSOR_HEIGHT 128 | |
181 | ||
5740682e ML |
182 | /* GPU RESET flags */ |
183 | #define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0) | |
184 | #define AMDGPU_RESET_INFO_FULLRESET (1 << 1) | |
185 | ||
97b2e202 | 186 | struct amdgpu_device; |
97b2e202 | 187 | struct amdgpu_ib; |
97b2e202 | 188 | struct amdgpu_cs_parser; |
bb977d37 | 189 | struct amdgpu_job; |
97b2e202 | 190 | struct amdgpu_irq_src; |
0b492a4c | 191 | struct amdgpu_fpriv; |
9cca0b8e | 192 | struct amdgpu_bo_va_mapping; |
97b2e202 AD |
193 | |
194 | enum amdgpu_cp_irq { | |
195 | AMDGPU_CP_IRQ_GFX_EOP = 0, | |
196 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, | |
197 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
198 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
199 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
200 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
201 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
202 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
203 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
204 | ||
205 | AMDGPU_CP_IRQ_LAST | |
206 | }; | |
207 | ||
208 | enum amdgpu_sdma_irq { | |
209 | AMDGPU_SDMA_IRQ_TRAP0 = 0, | |
210 | AMDGPU_SDMA_IRQ_TRAP1, | |
211 | ||
212 | AMDGPU_SDMA_IRQ_LAST | |
213 | }; | |
214 | ||
215 | enum amdgpu_thermal_irq { | |
216 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
217 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
218 | ||
219 | AMDGPU_THERMAL_IRQ_LAST | |
220 | }; | |
221 | ||
4e638ae9 XY |
222 | enum amdgpu_kiq_irq { |
223 | AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, | |
224 | AMDGPU_CP_KIQ_IRQ_LAST | |
225 | }; | |
226 | ||
97b2e202 | 227 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, |
5fc3aeeb | 228 | enum amd_ip_block_type block_type, |
229 | enum amd_clockgating_state state); | |
97b2e202 | 230 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, |
5fc3aeeb | 231 | enum amd_ip_block_type block_type, |
232 | enum amd_powergating_state state); | |
6cb2d4e4 | 233 | void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); |
5dbbb60b AD |
234 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
235 | enum amd_ip_block_type block_type); | |
236 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
237 | enum amd_ip_block_type block_type); | |
97b2e202 | 238 | |
a1255107 AD |
239 | #define AMDGPU_MAX_IP_NUM 16 |
240 | ||
241 | struct amdgpu_ip_block_status { | |
242 | bool valid; | |
243 | bool sw; | |
244 | bool hw; | |
245 | bool late_initialized; | |
246 | bool hang; | |
247 | }; | |
248 | ||
97b2e202 | 249 | struct amdgpu_ip_block_version { |
a1255107 AD |
250 | const enum amd_ip_block_type type; |
251 | const u32 major; | |
252 | const u32 minor; | |
253 | const u32 rev; | |
5fc3aeeb | 254 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
255 | }; |
256 | ||
a1255107 AD |
257 | struct amdgpu_ip_block { |
258 | struct amdgpu_ip_block_status status; | |
259 | const struct amdgpu_ip_block_version *version; | |
260 | }; | |
261 | ||
97b2e202 | 262 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, |
5fc3aeeb | 263 | enum amd_ip_block_type type, |
97b2e202 AD |
264 | u32 major, u32 minor); |
265 | ||
a1255107 AD |
266 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
267 | enum amd_ip_block_type type); | |
268 | ||
269 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
270 | const struct amdgpu_ip_block_version *ip_block_version); | |
97b2e202 AD |
271 | |
272 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ | |
273 | struct amdgpu_buffer_funcs { | |
274 | /* maximum bytes in a single operation */ | |
275 | uint32_t copy_max_bytes; | |
276 | ||
277 | /* number of dw to reserve per operation */ | |
278 | unsigned copy_num_dw; | |
279 | ||
280 | /* used for buffer migration */ | |
c7ae72c0 | 281 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
282 | /* src addr in bytes */ |
283 | uint64_t src_offset, | |
284 | /* dst addr in bytes */ | |
285 | uint64_t dst_offset, | |
286 | /* number of byte to transfer */ | |
287 | uint32_t byte_count); | |
288 | ||
289 | /* maximum bytes in a single operation */ | |
290 | uint32_t fill_max_bytes; | |
291 | ||
292 | /* number of dw to reserve per operation */ | |
293 | unsigned fill_num_dw; | |
294 | ||
295 | /* used for buffer clearing */ | |
6e7a3840 | 296 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
297 | /* value to write to memory */ |
298 | uint32_t src_data, | |
299 | /* dst addr in bytes */ | |
300 | uint64_t dst_offset, | |
301 | /* number of byte to fill */ | |
302 | uint32_t byte_count); | |
303 | }; | |
304 | ||
305 | /* provided by hw blocks that can write ptes, e.g., sdma */ | |
306 | struct amdgpu_vm_pte_funcs { | |
e6d92197 YZ |
307 | /* number of dw to reserve per operation */ |
308 | unsigned copy_pte_num_dw; | |
309 | ||
97b2e202 AD |
310 | /* copy pte entries from GART */ |
311 | void (*copy_pte)(struct amdgpu_ib *ib, | |
312 | uint64_t pe, uint64_t src, | |
313 | unsigned count); | |
e6d92197 | 314 | |
97b2e202 | 315 | /* write pte one entry at a time with addr mapping */ |
de9ea7bd CK |
316 | void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, |
317 | uint64_t value, unsigned count, | |
318 | uint32_t incr); | |
7bdc53f9 YZ |
319 | |
320 | /* maximum nums of PTEs/PDEs in a single operation */ | |
321 | uint32_t set_max_nums_pte_pde; | |
322 | ||
323 | /* number of dw to reserve per operation */ | |
324 | unsigned set_pte_pde_num_dw; | |
325 | ||
97b2e202 AD |
326 | /* for linear pte/pde updates without addr mapping */ |
327 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
328 | uint64_t pe, | |
329 | uint64_t addr, unsigned count, | |
6b777607 | 330 | uint32_t incr, uint64_t flags); |
97b2e202 AD |
331 | }; |
332 | ||
333 | /* provided by the gmc block */ | |
334 | struct amdgpu_gart_funcs { | |
335 | /* flush the vm tlb via mmio */ | |
336 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, | |
337 | uint32_t vmid); | |
338 | /* write pte/pde updates using the cpu */ | |
339 | int (*set_pte_pde)(struct amdgpu_device *adev, | |
340 | void *cpu_pt_addr, /* cpu addr of page table */ | |
341 | uint32_t gpu_page_idx, /* pte/pde to update */ | |
342 | uint64_t addr, /* addr to write into pte/pde */ | |
6b777607 | 343 | uint64_t flags); /* access flags */ |
284710fa CK |
344 | /* enable/disable PRT support */ |
345 | void (*set_prt)(struct amdgpu_device *adev, bool enable); | |
5463545b AX |
346 | /* set pte flags based per asic */ |
347 | uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, | |
348 | uint32_t flags); | |
b1166325 | 349 | /* get the pde for a given mc addr */ |
3de676d8 CK |
350 | void (*get_vm_pde)(struct amdgpu_device *adev, int level, |
351 | u64 *dst, u64 *flags); | |
03f89feb | 352 | uint32_t (*get_invalidate_req)(unsigned int vm_id); |
e60f8db5 AX |
353 | }; |
354 | ||
97b2e202 AD |
355 | /* provided by the ih block */ |
356 | struct amdgpu_ih_funcs { | |
357 | /* ring read/write ptr handling, called from interrupt context */ | |
358 | u32 (*get_wptr)(struct amdgpu_device *adev); | |
00ecd8a2 | 359 | bool (*prescreen_iv)(struct amdgpu_device *adev); |
97b2e202 AD |
360 | void (*decode_iv)(struct amdgpu_device *adev, |
361 | struct amdgpu_iv_entry *entry); | |
362 | void (*set_rptr)(struct amdgpu_device *adev); | |
363 | }; | |
364 | ||
97b2e202 AD |
365 | /* |
366 | * BIOS. | |
367 | */ | |
368 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
369 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
370 | ||
371 | /* | |
372 | * Dummy page | |
373 | */ | |
374 | struct amdgpu_dummy_page { | |
375 | struct page *page; | |
376 | dma_addr_t addr; | |
377 | }; | |
378 | int amdgpu_dummy_page_init(struct amdgpu_device *adev); | |
379 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev); | |
380 | ||
381 | ||
382 | /* | |
383 | * Clocks | |
384 | */ | |
385 | ||
386 | #define AMDGPU_MAX_PPLL 3 | |
387 | ||
388 | struct amdgpu_clock { | |
389 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
390 | struct amdgpu_pll spll; | |
391 | struct amdgpu_pll mpll; | |
392 | /* 10 Khz units */ | |
393 | uint32_t default_mclk; | |
394 | uint32_t default_sclk; | |
395 | uint32_t default_dispclk; | |
396 | uint32_t current_dispclk; | |
397 | uint32_t dp_extclk; | |
398 | uint32_t max_pixel_clock; | |
399 | }; | |
400 | ||
97b2e202 | 401 | /* |
9124a398 | 402 | * GEM. |
97b2e202 | 403 | */ |
97b2e202 | 404 | |
7e5a547f | 405 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
97b2e202 AD |
406 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) |
407 | ||
408 | void amdgpu_gem_object_free(struct drm_gem_object *obj); | |
409 | int amdgpu_gem_object_open(struct drm_gem_object *obj, | |
410 | struct drm_file *file_priv); | |
411 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
412 | struct drm_file *file_priv); | |
413 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); | |
414 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); | |
4d9c514d CK |
415 | struct drm_gem_object * |
416 | amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
417 | struct dma_buf_attachment *attach, | |
418 | struct sg_table *sg); | |
97b2e202 AD |
419 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, |
420 | struct drm_gem_object *gobj, | |
421 | int flags); | |
422 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); | |
423 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); | |
424 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); | |
425 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); | |
426 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
dfced2e4 | 427 | int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
97b2e202 AD |
428 | |
429 | /* sub-allocation manager, it has to be protected by another lock. | |
430 | * By conception this is an helper for other part of the driver | |
431 | * like the indirect buffer or semaphore, which both have their | |
432 | * locking. | |
433 | * | |
434 | * Principe is simple, we keep a list of sub allocation in offset | |
435 | * order (first entry has offset == 0, last entry has the highest | |
436 | * offset). | |
437 | * | |
438 | * When allocating new object we first check if there is room at | |
439 | * the end total_size - (last_object_offset + last_object_size) >= | |
440 | * alloc_size. If so we allocate new object there. | |
441 | * | |
442 | * When there is not enough room at the end, we start waiting for | |
443 | * each sub object until we reach object_offset+object_size >= | |
444 | * alloc_size, this object then become the sub object we return. | |
445 | * | |
446 | * Alignment can't be bigger than page size. | |
447 | * | |
448 | * Hole are not considered for allocation to keep things simple. | |
449 | * Assumption is that there won't be hole (all object on same | |
450 | * alignment). | |
451 | */ | |
6ba60b89 CK |
452 | |
453 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 | |
454 | ||
97b2e202 AD |
455 | struct amdgpu_sa_manager { |
456 | wait_queue_head_t wq; | |
457 | struct amdgpu_bo *bo; | |
458 | struct list_head *hole; | |
6ba60b89 | 459 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
97b2e202 AD |
460 | struct list_head olist; |
461 | unsigned size; | |
462 | uint64_t gpu_addr; | |
463 | void *cpu_ptr; | |
464 | uint32_t domain; | |
465 | uint32_t align; | |
466 | }; | |
467 | ||
97b2e202 AD |
468 | /* sub-allocation buffer */ |
469 | struct amdgpu_sa_bo { | |
470 | struct list_head olist; | |
471 | struct list_head flist; | |
472 | struct amdgpu_sa_manager *manager; | |
473 | unsigned soffset; | |
474 | unsigned eoffset; | |
f54d1867 | 475 | struct dma_fence *fence; |
97b2e202 AD |
476 | }; |
477 | ||
478 | /* | |
479 | * GEM objects. | |
480 | */ | |
418aa0c2 | 481 | void amdgpu_gem_force_release(struct amdgpu_device *adev); |
97b2e202 | 482 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, |
e1eb899b CK |
483 | int alignment, u32 initial_domain, |
484 | u64 flags, bool kernel, | |
485 | struct reservation_object *resv, | |
486 | struct drm_gem_object **obj); | |
97b2e202 AD |
487 | |
488 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
489 | struct drm_device *dev, | |
490 | struct drm_mode_create_dumb *args); | |
491 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
492 | struct drm_device *dev, | |
493 | uint32_t handle, uint64_t *offset_p); | |
d573de2d RZ |
494 | int amdgpu_fence_slab_init(void); |
495 | void amdgpu_fence_slab_fini(void); | |
97b2e202 | 496 | |
e60f8db5 AX |
497 | /* |
498 | * VMHUB structures, functions & helpers | |
499 | */ | |
500 | struct amdgpu_vmhub { | |
501 | uint32_t ctx0_ptb_addr_lo32; | |
502 | uint32_t ctx0_ptb_addr_hi32; | |
503 | uint32_t vm_inv_eng0_req; | |
504 | uint32_t vm_inv_eng0_ack; | |
505 | uint32_t vm_context0_cntl; | |
506 | uint32_t vm_l2_pro_fault_status; | |
507 | uint32_t vm_l2_pro_fault_cntl; | |
e60f8db5 AX |
508 | }; |
509 | ||
97b2e202 AD |
510 | /* |
511 | * GPU MC structures, functions & helpers | |
512 | */ | |
513 | struct amdgpu_mc { | |
514 | resource_size_t aper_size; | |
515 | resource_size_t aper_base; | |
516 | resource_size_t agp_base; | |
517 | /* for some chips with <= 32MB we need to lie | |
518 | * about vram size near mc fb location */ | |
519 | u64 mc_vram_size; | |
520 | u64 visible_vram_size; | |
6f02a696 CK |
521 | u64 gart_size; |
522 | u64 gart_start; | |
523 | u64 gart_end; | |
97b2e202 AD |
524 | u64 vram_start; |
525 | u64 vram_end; | |
526 | unsigned vram_width; | |
527 | u64 real_vram_size; | |
528 | int vram_mtrr; | |
97b2e202 AD |
529 | u64 mc_mask; |
530 | const struct firmware *fw; /* MC firmware */ | |
531 | uint32_t fw_version; | |
532 | struct amdgpu_irq_src vm_fault; | |
81c59f54 | 533 | uint32_t vram_type; |
50b0197a | 534 | uint32_t srbm_soft_reset; |
f7c35abe | 535 | bool prt_warning; |
916910ad | 536 | uint64_t stolen_size; |
8fe73328 JZ |
537 | /* apertures */ |
538 | u64 shared_aperture_start; | |
539 | u64 shared_aperture_end; | |
540 | u64 private_aperture_start; | |
541 | u64 private_aperture_end; | |
e60f8db5 AX |
542 | /* protects concurrent invalidation */ |
543 | spinlock_t invalidate_lock; | |
97b2e202 AD |
544 | }; |
545 | ||
546 | /* | |
547 | * GPU doorbell structures, functions & helpers | |
548 | */ | |
549 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
550 | { | |
551 | AMDGPU_DOORBELL_KIQ = 0x000, | |
552 | AMDGPU_DOORBELL_HIQ = 0x001, | |
553 | AMDGPU_DOORBELL_DIQ = 0x002, | |
554 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
555 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
556 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
557 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
558 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
559 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
560 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
561 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
562 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
563 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
564 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
565 | AMDGPU_DOORBELL_IH = 0x1E8, | |
566 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
567 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
568 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
569 | ||
570 | struct amdgpu_doorbell { | |
571 | /* doorbell mmio */ | |
572 | resource_size_t base; | |
573 | resource_size_t size; | |
574 | u32 __iomem *ptr; | |
575 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
576 | }; | |
577 | ||
39807b93 KW |
578 | /* |
579 | * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space | |
580 | */ | |
581 | typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT | |
582 | { | |
583 | /* | |
584 | * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in | |
585 | * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. | |
586 | * Compute related doorbells are allocated from 0x00 to 0x8a | |
587 | */ | |
588 | ||
589 | ||
590 | /* kernel scheduling */ | |
591 | AMDGPU_DOORBELL64_KIQ = 0x00, | |
592 | ||
593 | /* HSA interface queue and debug queue */ | |
594 | AMDGPU_DOORBELL64_HIQ = 0x01, | |
595 | AMDGPU_DOORBELL64_DIQ = 0x02, | |
596 | ||
597 | /* Compute engines */ | |
598 | AMDGPU_DOORBELL64_MEC_RING0 = 0x03, | |
599 | AMDGPU_DOORBELL64_MEC_RING1 = 0x04, | |
600 | AMDGPU_DOORBELL64_MEC_RING2 = 0x05, | |
601 | AMDGPU_DOORBELL64_MEC_RING3 = 0x06, | |
602 | AMDGPU_DOORBELL64_MEC_RING4 = 0x07, | |
603 | AMDGPU_DOORBELL64_MEC_RING5 = 0x08, | |
604 | AMDGPU_DOORBELL64_MEC_RING6 = 0x09, | |
605 | AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, | |
606 | ||
607 | /* User queue doorbell range (128 doorbells) */ | |
608 | AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, | |
609 | AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, | |
610 | ||
611 | /* Graphics engine */ | |
612 | AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, | |
613 | ||
614 | /* | |
615 | * Other graphics doorbells can be allocated here: from 0x8c to 0xef | |
616 | * Graphics voltage island aperture 1 | |
617 | * default non-graphics QWORD index is 0xF0 - 0xFF inclusive | |
618 | */ | |
619 | ||
620 | /* sDMA engines */ | |
621 | AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, | |
622 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, | |
623 | AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, | |
624 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, | |
625 | ||
626 | /* Interrupt handler */ | |
627 | AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ | |
628 | AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ | |
629 | AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ | |
630 | ||
e6b3ecb4 ML |
631 | /* VCN engine use 32 bits doorbell */ |
632 | AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ | |
633 | AMDGPU_DOORBELL64_VCN2_3 = 0xF9, | |
634 | AMDGPU_DOORBELL64_VCN4_5 = 0xFA, | |
635 | AMDGPU_DOORBELL64_VCN6_7 = 0xFB, | |
636 | ||
637 | /* overlap the doorbell assignment with VCN as they are mutually exclusive | |
638 | * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD | |
639 | */ | |
4ed11d79 FM |
640 | AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, |
641 | AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, | |
642 | AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, | |
643 | AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, | |
644 | ||
645 | AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, | |
646 | AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, | |
647 | AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, | |
648 | AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, | |
39807b93 KW |
649 | |
650 | AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, | |
651 | AMDGPU_DOORBELL64_INVALID = 0xFFFF | |
652 | } AMDGPU_DOORBELL64_ASSIGNMENT; | |
653 | ||
97b2e202 AD |
654 | /* |
655 | * IRQS. | |
656 | */ | |
657 | ||
658 | struct amdgpu_flip_work { | |
325cbba1 | 659 | struct delayed_work flip_work; |
97b2e202 AD |
660 | struct work_struct unpin_work; |
661 | struct amdgpu_device *adev; | |
662 | int crtc_id; | |
325cbba1 | 663 | u32 target_vblank; |
97b2e202 AD |
664 | uint64_t base; |
665 | struct drm_pending_vblank_event *event; | |
765e7fbf | 666 | struct amdgpu_bo *old_abo; |
f54d1867 | 667 | struct dma_fence *excl; |
1ffd2652 | 668 | unsigned shared_count; |
f54d1867 CW |
669 | struct dma_fence **shared; |
670 | struct dma_fence_cb cb; | |
cb9e59d7 | 671 | bool async; |
97b2e202 AD |
672 | }; |
673 | ||
674 | ||
675 | /* | |
676 | * CP & rings. | |
677 | */ | |
678 | ||
679 | struct amdgpu_ib { | |
680 | struct amdgpu_sa_bo *sa_bo; | |
681 | uint32_t length_dw; | |
682 | uint64_t gpu_addr; | |
683 | uint32_t *ptr; | |
de807f81 | 684 | uint32_t flags; |
97b2e202 AD |
685 | }; |
686 | ||
1b1f42d8 | 687 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
c1b69ed0 | 688 | |
50838c8c | 689 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
c5637837 | 690 | struct amdgpu_job **job, struct amdgpu_vm *vm); |
d71518b5 CK |
691 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
692 | struct amdgpu_job **job); | |
b6723c8d | 693 | |
a5fb4ec2 | 694 | void amdgpu_job_free_resources(struct amdgpu_job *job); |
50838c8c | 695 | void amdgpu_job_free(struct amdgpu_job *job); |
d71518b5 | 696 | int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, |
1b1f42d8 | 697 | struct drm_sched_entity *entity, void *owner, |
f54d1867 | 698 | struct dma_fence **f); |
8b4fb00b | 699 | |
effd924d AR |
700 | /* |
701 | * Queue manager | |
702 | */ | |
703 | struct amdgpu_queue_mapper { | |
704 | int hw_ip; | |
705 | struct mutex lock; | |
706 | /* protected by lock */ | |
707 | struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; | |
708 | }; | |
709 | ||
710 | struct amdgpu_queue_mgr { | |
711 | struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; | |
712 | }; | |
713 | ||
714 | int amdgpu_queue_mgr_init(struct amdgpu_device *adev, | |
715 | struct amdgpu_queue_mgr *mgr); | |
716 | int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, | |
717 | struct amdgpu_queue_mgr *mgr); | |
718 | int amdgpu_queue_mgr_map(struct amdgpu_device *adev, | |
719 | struct amdgpu_queue_mgr *mgr, | |
fa7c7939 | 720 | u32 hw_ip, u32 instance, u32 ring, |
effd924d AR |
721 | struct amdgpu_ring **out_ring); |
722 | ||
97b2e202 AD |
723 | /* |
724 | * context related structures | |
725 | */ | |
726 | ||
21c16bf6 | 727 | struct amdgpu_ctx_ring { |
91404fb2 | 728 | uint64_t sequence; |
f54d1867 | 729 | struct dma_fence **fences; |
1b1f42d8 | 730 | struct drm_sched_entity entity; |
21c16bf6 CK |
731 | }; |
732 | ||
97b2e202 | 733 | struct amdgpu_ctx { |
0b492a4c | 734 | struct kref refcount; |
9cb7e5a9 | 735 | struct amdgpu_device *adev; |
effd924d | 736 | struct amdgpu_queue_mgr queue_mgr; |
0b492a4c | 737 | unsigned reset_counter; |
668ca1b4 | 738 | unsigned reset_counter_query; |
e55f2b64 | 739 | uint32_t vram_lost_counter; |
21c16bf6 | 740 | spinlock_t ring_lock; |
f54d1867 | 741 | struct dma_fence **fences; |
21c16bf6 | 742 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; |
e55f2b64 | 743 | bool preamble_presented; |
1b1f42d8 LS |
744 | enum drm_sched_priority init_priority; |
745 | enum drm_sched_priority override_priority; | |
0ae94444 | 746 | struct mutex lock; |
1102900d | 747 | atomic_t guilty; |
97b2e202 AD |
748 | }; |
749 | ||
750 | struct amdgpu_ctx_mgr { | |
0b492a4c AD |
751 | struct amdgpu_device *adev; |
752 | struct mutex lock; | |
753 | /* protected by lock */ | |
754 | struct idr ctx_handles; | |
97b2e202 AD |
755 | }; |
756 | ||
0b492a4c AD |
757 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
758 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); | |
759 | ||
eb01abc7 ML |
760 | int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
761 | struct dma_fence *fence, uint64_t *seq); | |
f54d1867 | 762 | struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
21c16bf6 | 763 | struct amdgpu_ring *ring, uint64_t seq); |
c23be4ae | 764 | void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, |
1b1f42d8 | 765 | enum drm_sched_priority priority); |
21c16bf6 | 766 | |
0b492a4c AD |
767 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
768 | struct drm_file *filp); | |
769 | ||
0ae94444 AG |
770 | int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); |
771 | ||
efd4ccb5 CK |
772 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
773 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); | |
0b492a4c | 774 | |
0ae94444 | 775 | |
97b2e202 AD |
776 | /* |
777 | * file private structure | |
778 | */ | |
779 | ||
780 | struct amdgpu_fpriv { | |
781 | struct amdgpu_vm vm; | |
b85891bd | 782 | struct amdgpu_bo_va *prt_va; |
0f4b3c68 | 783 | struct amdgpu_bo_va *csa_va; |
97b2e202 AD |
784 | struct mutex bo_list_lock; |
785 | struct idr bo_list_handles; | |
0b492a4c | 786 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
787 | }; |
788 | ||
789 | /* | |
790 | * residency list | |
791 | */ | |
9124a398 CK |
792 | struct amdgpu_bo_list_entry { |
793 | struct amdgpu_bo *robj; | |
794 | struct ttm_validate_buffer tv; | |
795 | struct amdgpu_bo_va *bo_va; | |
796 | uint32_t priority; | |
797 | struct page **user_pages; | |
798 | int user_invalidated; | |
799 | }; | |
97b2e202 AD |
800 | |
801 | struct amdgpu_bo_list { | |
802 | struct mutex lock; | |
5ac55629 AX |
803 | struct rcu_head rhead; |
804 | struct kref refcount; | |
97b2e202 AD |
805 | struct amdgpu_bo *gds_obj; |
806 | struct amdgpu_bo *gws_obj; | |
807 | struct amdgpu_bo *oa_obj; | |
211dff55 | 808 | unsigned first_userptr; |
97b2e202 AD |
809 | unsigned num_entries; |
810 | struct amdgpu_bo_list_entry *array; | |
811 | }; | |
812 | ||
813 | struct amdgpu_bo_list * | |
814 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); | |
636ce25c CK |
815 | void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, |
816 | struct list_head *validated); | |
97b2e202 AD |
817 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); |
818 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); | |
819 | ||
820 | /* | |
821 | * GFX stuff | |
822 | */ | |
823 | #include "clearstate_defs.h" | |
824 | ||
79e5412c AD |
825 | struct amdgpu_rlc_funcs { |
826 | void (*enter_safe_mode)(struct amdgpu_device *adev); | |
827 | void (*exit_safe_mode)(struct amdgpu_device *adev); | |
828 | }; | |
829 | ||
97b2e202 AD |
830 | struct amdgpu_rlc { |
831 | /* for power gating */ | |
832 | struct amdgpu_bo *save_restore_obj; | |
833 | uint64_t save_restore_gpu_addr; | |
834 | volatile uint32_t *sr_ptr; | |
835 | const u32 *reg_list; | |
836 | u32 reg_list_size; | |
837 | /* for clear state */ | |
838 | struct amdgpu_bo *clear_state_obj; | |
839 | uint64_t clear_state_gpu_addr; | |
840 | volatile uint32_t *cs_ptr; | |
841 | const struct cs_section_def *cs_data; | |
842 | u32 clear_state_size; | |
843 | /* for cp tables */ | |
844 | struct amdgpu_bo *cp_table_obj; | |
845 | uint64_t cp_table_gpu_addr; | |
846 | volatile uint32_t *cp_table_ptr; | |
847 | u32 cp_table_size; | |
79e5412c AD |
848 | |
849 | /* safe mode for updating CG/PG state */ | |
850 | bool in_safe_mode; | |
851 | const struct amdgpu_rlc_funcs *funcs; | |
2b6cd977 EH |
852 | |
853 | /* for firmware data */ | |
854 | u32 save_and_restore_offset; | |
855 | u32 clear_state_descriptor_offset; | |
856 | u32 avail_scratch_ram_locations; | |
857 | u32 reg_restore_list_size; | |
858 | u32 reg_list_format_start; | |
859 | u32 reg_list_format_separate_start; | |
860 | u32 starting_offsets_start; | |
861 | u32 reg_list_format_size_bytes; | |
862 | u32 reg_list_size_bytes; | |
863 | ||
864 | u32 *register_list_format; | |
865 | u32 *register_restore; | |
97b2e202 AD |
866 | }; |
867 | ||
78c16834 AR |
868 | #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES |
869 | ||
97b2e202 AD |
870 | struct amdgpu_mec { |
871 | struct amdgpu_bo *hpd_eop_obj; | |
872 | u64 hpd_eop_gpu_addr; | |
b1023571 KW |
873 | struct amdgpu_bo *mec_fw_obj; |
874 | u64 mec_fw_gpu_addr; | |
97b2e202 | 875 | u32 num_mec; |
42794b27 AR |
876 | u32 num_pipe_per_mec; |
877 | u32 num_queue_per_pipe; | |
59a82d7d | 878 | void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; |
78c16834 AR |
879 | |
880 | /* These are the resources for which amdgpu takes ownership */ | |
881 | DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); | |
97b2e202 AD |
882 | }; |
883 | ||
4e638ae9 XY |
884 | struct amdgpu_kiq { |
885 | u64 eop_gpu_addr; | |
886 | struct amdgpu_bo *eop_obj; | |
43ca8efa | 887 | spinlock_t ring_lock; |
4e638ae9 XY |
888 | struct amdgpu_ring ring; |
889 | struct amdgpu_irq_src irq; | |
890 | }; | |
891 | ||
97b2e202 AD |
892 | /* |
893 | * GPU scratch registers structures, functions & helpers | |
894 | */ | |
895 | struct amdgpu_scratch { | |
896 | unsigned num_reg; | |
897 | uint32_t reg_base; | |
50261151 | 898 | uint32_t free_mask; |
97b2e202 AD |
899 | }; |
900 | ||
901 | /* | |
902 | * GFX configurations | |
903 | */ | |
e3fa7630 AD |
904 | #define AMDGPU_GFX_MAX_SE 4 |
905 | #define AMDGPU_GFX_MAX_SH_PER_SE 2 | |
906 | ||
907 | struct amdgpu_rb_config { | |
908 | uint32_t rb_backend_disable; | |
909 | uint32_t user_rb_backend_disable; | |
910 | uint32_t raster_config; | |
911 | uint32_t raster_config_1; | |
912 | }; | |
913 | ||
d0e95758 AG |
914 | struct gb_addr_config { |
915 | uint16_t pipe_interleave_size; | |
916 | uint8_t num_pipes; | |
917 | uint8_t max_compress_frags; | |
918 | uint8_t num_banks; | |
919 | uint8_t num_se; | |
920 | uint8_t num_rb_per_se; | |
921 | }; | |
922 | ||
ea323f88 | 923 | struct amdgpu_gfx_config { |
97b2e202 AD |
924 | unsigned max_shader_engines; |
925 | unsigned max_tile_pipes; | |
926 | unsigned max_cu_per_sh; | |
927 | unsigned max_sh_per_se; | |
928 | unsigned max_backends_per_se; | |
929 | unsigned max_texture_channel_caches; | |
930 | unsigned max_gprs; | |
931 | unsigned max_gs_threads; | |
932 | unsigned max_hw_contexts; | |
933 | unsigned sc_prim_fifo_size_frontend; | |
934 | unsigned sc_prim_fifo_size_backend; | |
935 | unsigned sc_hiz_tile_fifo_size; | |
936 | unsigned sc_earlyz_tile_fifo_size; | |
937 | ||
938 | unsigned num_tile_pipes; | |
939 | unsigned backend_enable_mask; | |
940 | unsigned mem_max_burst_length_bytes; | |
941 | unsigned mem_row_size_in_kb; | |
942 | unsigned shader_engine_tile_size; | |
943 | unsigned num_gpus; | |
944 | unsigned multi_gpu_tile_size; | |
945 | unsigned mc_arb_ramcfg; | |
946 | unsigned gb_addr_config; | |
8f8e00c1 | 947 | unsigned num_rbs; |
408bfe7c JZ |
948 | unsigned gs_vgt_table_depth; |
949 | unsigned gs_prim_buffer_depth; | |
97b2e202 AD |
950 | |
951 | uint32_t tile_mode_array[32]; | |
952 | uint32_t macrotile_mode_array[16]; | |
e3fa7630 | 953 | |
d0e95758 | 954 | struct gb_addr_config gb_addr_config_fields; |
e3fa7630 | 955 | struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; |
df6e2c4a JZ |
956 | |
957 | /* gfx configure feature */ | |
958 | uint32_t double_offchip_lds_buf; | |
97b2e202 AD |
959 | }; |
960 | ||
7dae69a2 | 961 | struct amdgpu_cu_info { |
51fd0370 | 962 | uint32_t max_waves_per_simd; |
408bfe7c | 963 | uint32_t wave_front_size; |
51fd0370 HZ |
964 | uint32_t max_scratch_slots_per_cu; |
965 | uint32_t lds_size; | |
dbfe85ea FC |
966 | |
967 | /* total active CU number */ | |
968 | uint32_t number; | |
969 | uint32_t ao_cu_mask; | |
970 | uint32_t ao_cu_bitmap[4][4]; | |
7dae69a2 AD |
971 | uint32_t bitmap[4][4]; |
972 | }; | |
973 | ||
b95e31fd AD |
974 | struct amdgpu_gfx_funcs { |
975 | /* get the gpu clock counter */ | |
976 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); | |
9559ef5b | 977 | void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); |
472259f0 | 978 | void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); |
c5a60ce8 TSD |
979 | void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); |
980 | void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); | |
b95e31fd AD |
981 | }; |
982 | ||
bce23e00 AD |
983 | struct amdgpu_ngg_buf { |
984 | struct amdgpu_bo *bo; | |
985 | uint64_t gpu_addr; | |
986 | uint32_t size; | |
987 | uint32_t bo_size; | |
988 | }; | |
989 | ||
990 | enum { | |
af8baf15 GR |
991 | NGG_PRIM = 0, |
992 | NGG_POS, | |
993 | NGG_CNTL, | |
994 | NGG_PARAM, | |
bce23e00 AD |
995 | NGG_BUF_MAX |
996 | }; | |
997 | ||
998 | struct amdgpu_ngg { | |
999 | struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; | |
1000 | uint32_t gds_reserve_addr; | |
1001 | uint32_t gds_reserve_size; | |
1002 | bool init; | |
1003 | }; | |
1004 | ||
97b2e202 AD |
1005 | struct amdgpu_gfx { |
1006 | struct mutex gpu_clock_mutex; | |
ea323f88 | 1007 | struct amdgpu_gfx_config config; |
97b2e202 AD |
1008 | struct amdgpu_rlc rlc; |
1009 | struct amdgpu_mec mec; | |
4e638ae9 | 1010 | struct amdgpu_kiq kiq; |
97b2e202 AD |
1011 | struct amdgpu_scratch scratch; |
1012 | const struct firmware *me_fw; /* ME firmware */ | |
1013 | uint32_t me_fw_version; | |
1014 | const struct firmware *pfp_fw; /* PFP firmware */ | |
1015 | uint32_t pfp_fw_version; | |
1016 | const struct firmware *ce_fw; /* CE firmware */ | |
1017 | uint32_t ce_fw_version; | |
1018 | const struct firmware *rlc_fw; /* RLC firmware */ | |
1019 | uint32_t rlc_fw_version; | |
1020 | const struct firmware *mec_fw; /* MEC firmware */ | |
1021 | uint32_t mec_fw_version; | |
1022 | const struct firmware *mec2_fw; /* MEC2 firmware */ | |
1023 | uint32_t mec2_fw_version; | |
02558a00 KW |
1024 | uint32_t me_feature_version; |
1025 | uint32_t ce_feature_version; | |
1026 | uint32_t pfp_feature_version; | |
351643d7 JZ |
1027 | uint32_t rlc_feature_version; |
1028 | uint32_t mec_feature_version; | |
1029 | uint32_t mec2_feature_version; | |
97b2e202 AD |
1030 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
1031 | unsigned num_gfx_rings; | |
1032 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; | |
1033 | unsigned num_compute_rings; | |
1034 | struct amdgpu_irq_src eop_irq; | |
1035 | struct amdgpu_irq_src priv_reg_irq; | |
1036 | struct amdgpu_irq_src priv_inst_irq; | |
1037 | /* gfx status */ | |
7dae69a2 | 1038 | uint32_t gfx_current_status; |
a101a899 | 1039 | /* ce ram size*/ |
7dae69a2 AD |
1040 | unsigned ce_ram_size; |
1041 | struct amdgpu_cu_info cu_info; | |
b95e31fd | 1042 | const struct amdgpu_gfx_funcs *funcs; |
3d7c6384 CZ |
1043 | |
1044 | /* reset mask */ | |
1045 | uint32_t grbm_soft_reset; | |
1046 | uint32_t srbm_soft_reset; | |
b4e40676 DP |
1047 | /* s3/s4 mask */ |
1048 | bool in_suspend; | |
bce23e00 AD |
1049 | /* NGG */ |
1050 | struct amdgpu_ngg ngg; | |
b8866c26 AR |
1051 | |
1052 | /* pipe reservation */ | |
1053 | struct mutex pipe_reserve_mutex; | |
1054 | DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); | |
97b2e202 AD |
1055 | }; |
1056 | ||
b07c60c0 | 1057 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
97b2e202 | 1058 | unsigned size, struct amdgpu_ib *ib); |
4d9c514d | 1059 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, |
f54d1867 | 1060 | struct dma_fence *f); |
b07c60c0 | 1061 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
50ddc75e JZ |
1062 | struct amdgpu_ib *ibs, struct amdgpu_job *job, |
1063 | struct dma_fence **f); | |
97b2e202 AD |
1064 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
1065 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
1066 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
97b2e202 AD |
1067 | |
1068 | /* | |
1069 | * CS. | |
1070 | */ | |
1071 | struct amdgpu_cs_chunk { | |
1072 | uint32_t chunk_id; | |
1073 | uint32_t length_dw; | |
758ac17f | 1074 | void *kdata; |
97b2e202 AD |
1075 | }; |
1076 | ||
1077 | struct amdgpu_cs_parser { | |
1078 | struct amdgpu_device *adev; | |
1079 | struct drm_file *filp; | |
3cb485f3 | 1080 | struct amdgpu_ctx *ctx; |
c3cca41e | 1081 | |
97b2e202 AD |
1082 | /* chunks */ |
1083 | unsigned nchunks; | |
1084 | struct amdgpu_cs_chunk *chunks; | |
97b2e202 | 1085 | |
50838c8c CK |
1086 | /* scheduler job object */ |
1087 | struct amdgpu_job *job; | |
97b2e202 | 1088 | |
c3cca41e CK |
1089 | /* buffer objects */ |
1090 | struct ww_acquire_ctx ticket; | |
1091 | struct amdgpu_bo_list *bo_list; | |
3fe89771 | 1092 | struct amdgpu_mn *mn; |
c3cca41e CK |
1093 | struct amdgpu_bo_list_entry vm_pd; |
1094 | struct list_head validated; | |
f54d1867 | 1095 | struct dma_fence *fence; |
c3cca41e | 1096 | uint64_t bytes_moved_threshold; |
00f06b24 | 1097 | uint64_t bytes_moved_vis_threshold; |
c3cca41e | 1098 | uint64_t bytes_moved; |
00f06b24 | 1099 | uint64_t bytes_moved_vis; |
662bfa61 | 1100 | struct amdgpu_bo_list_entry *evictable; |
97b2e202 AD |
1101 | |
1102 | /* user fence */ | |
91acbeb6 | 1103 | struct amdgpu_bo_list_entry uf_entry; |
660e8558 DA |
1104 | |
1105 | unsigned num_post_dep_syncobjs; | |
1106 | struct drm_syncobj **post_dep_syncobjs; | |
97b2e202 AD |
1107 | }; |
1108 | ||
753ad49c ML |
1109 | #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ |
1110 | #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ | |
1111 | #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ | |
1112 | ||
bb977d37 | 1113 | struct amdgpu_job { |
1b1f42d8 | 1114 | struct drm_sched_job base; |
bb977d37 | 1115 | struct amdgpu_device *adev; |
edf600da | 1116 | struct amdgpu_vm *vm; |
b07c60c0 | 1117 | struct amdgpu_ring *ring; |
e86f9cee | 1118 | struct amdgpu_sync sync; |
df83d1eb | 1119 | struct amdgpu_sync sched_sync; |
bb977d37 | 1120 | struct amdgpu_ib *ibs; |
f54d1867 | 1121 | struct dma_fence *fence; /* the hw fence */ |
753ad49c | 1122 | uint32_t preamble_status; |
bb977d37 | 1123 | uint32_t num_ibs; |
e2840221 | 1124 | void *owner; |
3aecd24c | 1125 | uint64_t fence_ctx; /* the fence_context this job uses */ |
fd53be30 | 1126 | bool vm_needs_flush; |
d88bf583 CK |
1127 | unsigned vm_id; |
1128 | uint64_t vm_pd_addr; | |
1129 | uint32_t gds_base, gds_size; | |
1130 | uint32_t gws_base, gws_size; | |
1131 | uint32_t oa_base, oa_size; | |
14e47f93 | 1132 | uint32_t vram_lost_counter; |
758ac17f CK |
1133 | |
1134 | /* user fence handling */ | |
b5f5acbc | 1135 | uint64_t uf_addr; |
758ac17f CK |
1136 | uint64_t uf_sequence; |
1137 | ||
bb977d37 | 1138 | }; |
a6db8a33 JZ |
1139 | #define to_amdgpu_job(sched_job) \ |
1140 | container_of((sched_job), struct amdgpu_job, base) | |
bb977d37 | 1141 | |
7270f839 CK |
1142 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
1143 | uint32_t ib_idx, int idx) | |
97b2e202 | 1144 | { |
50838c8c | 1145 | return p->job->ibs[ib_idx].ptr[idx]; |
97b2e202 AD |
1146 | } |
1147 | ||
7270f839 CK |
1148 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
1149 | uint32_t ib_idx, int idx, | |
1150 | uint32_t value) | |
1151 | { | |
50838c8c | 1152 | p->job->ibs[ib_idx].ptr[idx] = value; |
7270f839 CK |
1153 | } |
1154 | ||
97b2e202 AD |
1155 | /* |
1156 | * Writeback | |
1157 | */ | |
896a664c | 1158 | #define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ |
97b2e202 AD |
1159 | |
1160 | struct amdgpu_wb { | |
1161 | struct amdgpu_bo *wb_obj; | |
1162 | volatile uint32_t *wb; | |
1163 | uint64_t gpu_addr; | |
1164 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
1165 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
1166 | }; | |
1167 | ||
131b4b36 AD |
1168 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); |
1169 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); | |
97b2e202 | 1170 | |
d0dd7f0c AD |
1171 | void amdgpu_get_pcie_info(struct amdgpu_device *adev); |
1172 | ||
97b2e202 AD |
1173 | /* |
1174 | * SDMA | |
1175 | */ | |
c113ea1c | 1176 | struct amdgpu_sdma_instance { |
97b2e202 AD |
1177 | /* SDMA firmware */ |
1178 | const struct firmware *fw; | |
1179 | uint32_t fw_version; | |
cfa2104f | 1180 | uint32_t feature_version; |
97b2e202 AD |
1181 | |
1182 | struct amdgpu_ring ring; | |
18111de0 | 1183 | bool burst_nop; |
97b2e202 AD |
1184 | }; |
1185 | ||
c113ea1c AD |
1186 | struct amdgpu_sdma { |
1187 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; | |
30d1574f KW |
1188 | #ifdef CONFIG_DRM_AMDGPU_SI |
1189 | //SI DMA has a difference trap irq number for the second engine | |
1190 | struct amdgpu_irq_src trap_irq_1; | |
1191 | #endif | |
c113ea1c AD |
1192 | struct amdgpu_irq_src trap_irq; |
1193 | struct amdgpu_irq_src illegal_inst_irq; | |
edf600da | 1194 | int num_instances; |
e702a680 | 1195 | uint32_t srbm_soft_reset; |
c113ea1c AD |
1196 | }; |
1197 | ||
97b2e202 AD |
1198 | /* |
1199 | * Firmware | |
1200 | */ | |
e635ee07 HR |
1201 | enum amdgpu_firmware_load_type { |
1202 | AMDGPU_FW_LOAD_DIRECT = 0, | |
1203 | AMDGPU_FW_LOAD_SMU, | |
1204 | AMDGPU_FW_LOAD_PSP, | |
1205 | }; | |
1206 | ||
97b2e202 AD |
1207 | struct amdgpu_firmware { |
1208 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; | |
e635ee07 | 1209 | enum amdgpu_firmware_load_type load_type; |
97b2e202 AD |
1210 | struct amdgpu_bo *fw_buf; |
1211 | unsigned int fw_size; | |
2445b227 | 1212 | unsigned int max_ucodes; |
0e5ca0d1 HR |
1213 | /* firmwares are loaded by psp instead of smu from vega10 */ |
1214 | const struct amdgpu_psp_funcs *funcs; | |
1215 | struct amdgpu_bo *rbuf; | |
1216 | struct mutex mutex; | |
ab4fe3e1 HR |
1217 | |
1218 | /* gpu info firmware data pointer */ | |
1219 | const struct firmware *gpu_info_fw; | |
d59c026b ML |
1220 | |
1221 | void *fw_buf_ptr; | |
1222 | uint64_t fw_buf_mc; | |
97b2e202 AD |
1223 | }; |
1224 | ||
1225 | /* | |
1226 | * Benchmarking | |
1227 | */ | |
1228 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
1229 | ||
1230 | ||
1231 | /* | |
1232 | * Testing | |
1233 | */ | |
1234 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
97b2e202 | 1235 | |
50ab2533 | 1236 | |
97b2e202 AD |
1237 | /* |
1238 | * amdgpu smumgr functions | |
1239 | */ | |
1240 | struct amdgpu_smumgr_funcs { | |
1241 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); | |
1242 | int (*request_smu_load_fw)(struct amdgpu_device *adev); | |
1243 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); | |
1244 | }; | |
1245 | ||
1246 | /* | |
1247 | * amdgpu smumgr | |
1248 | */ | |
1249 | struct amdgpu_smumgr { | |
1250 | struct amdgpu_bo *toc_buf; | |
1251 | struct amdgpu_bo *smu_buf; | |
1252 | /* asic priv smu data */ | |
1253 | void *priv; | |
1254 | spinlock_t smu_lock; | |
1255 | /* smumgr functions */ | |
1256 | const struct amdgpu_smumgr_funcs *smumgr_funcs; | |
1257 | /* ucode loading complete flag */ | |
1258 | uint32_t fw_flags; | |
1259 | }; | |
1260 | ||
1261 | /* | |
1262 | * ASIC specific register table accessible by UMD | |
1263 | */ | |
1264 | struct amdgpu_allowed_register_entry { | |
1265 | uint32_t reg_offset; | |
97b2e202 AD |
1266 | bool grbm_indexed; |
1267 | }; | |
1268 | ||
97b2e202 AD |
1269 | /* |
1270 | * ASIC specific functions. | |
1271 | */ | |
1272 | struct amdgpu_asic_funcs { | |
1273 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
1274 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
1275 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
1276 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
1277 | u32 sh_num, u32 reg_offset, u32 *value); | |
1278 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
1279 | int (*reset)(struct amdgpu_device *adev); | |
97b2e202 AD |
1280 | /* get the reference clock */ |
1281 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
97b2e202 AD |
1282 | /* MM block clocks */ |
1283 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
1284 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
841686df MB |
1285 | /* static power management */ |
1286 | int (*get_pcie_lanes)(struct amdgpu_device *adev); | |
1287 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); | |
bbf282d8 AD |
1288 | /* get config memsize register */ |
1289 | u32 (*get_config_memsize)(struct amdgpu_device *adev); | |
97b2e202 AD |
1290 | }; |
1291 | ||
1292 | /* | |
1293 | * IOCTL. | |
1294 | */ | |
1295 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
1296 | struct drm_file *filp); | |
1297 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, | |
1298 | struct drm_file *filp); | |
1299 | ||
1300 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, | |
1301 | struct drm_file *filp); | |
1302 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
1303 | struct drm_file *filp); | |
1304 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1305 | struct drm_file *filp); | |
1306 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1307 | struct drm_file *filp); | |
1308 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
1309 | struct drm_file *filp); | |
1310 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
1311 | struct drm_file *filp); | |
1312 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
7ca24cf2 MO |
1313 | int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, |
1314 | struct drm_file *filp); | |
97b2e202 | 1315 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
eef18a82 JZ |
1316 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, |
1317 | struct drm_file *filp); | |
97b2e202 AD |
1318 | |
1319 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
1320 | struct drm_file *filp); | |
1321 | ||
1322 | /* VRAM scratch page for HDP bug, default vram page */ | |
1323 | struct amdgpu_vram_scratch { | |
1324 | struct amdgpu_bo *robj; | |
1325 | volatile uint32_t *ptr; | |
1326 | u64 gpu_addr; | |
1327 | }; | |
1328 | ||
1329 | /* | |
1330 | * ACPI | |
1331 | */ | |
1332 | struct amdgpu_atif_notification_cfg { | |
1333 | bool enabled; | |
1334 | int command_code; | |
1335 | }; | |
1336 | ||
1337 | struct amdgpu_atif_notifications { | |
1338 | bool display_switch; | |
1339 | bool expansion_mode_change; | |
1340 | bool thermal_state; | |
1341 | bool forced_power_state; | |
1342 | bool system_power_state; | |
1343 | bool display_conf_change; | |
1344 | bool px_gfx_switch; | |
1345 | bool brightness_change; | |
1346 | bool dgpu_display_event; | |
1347 | }; | |
1348 | ||
1349 | struct amdgpu_atif_functions { | |
1350 | bool system_params; | |
1351 | bool sbios_requests; | |
1352 | bool select_active_disp; | |
1353 | bool lid_state; | |
1354 | bool get_tv_standard; | |
1355 | bool set_tv_standard; | |
1356 | bool get_panel_expansion_mode; | |
1357 | bool set_panel_expansion_mode; | |
1358 | bool temperature_change; | |
1359 | bool graphics_device_types; | |
1360 | }; | |
1361 | ||
1362 | struct amdgpu_atif { | |
1363 | struct amdgpu_atif_notifications notifications; | |
1364 | struct amdgpu_atif_functions functions; | |
1365 | struct amdgpu_atif_notification_cfg notification_cfg; | |
1366 | struct amdgpu_encoder *encoder_for_bl; | |
1367 | }; | |
1368 | ||
1369 | struct amdgpu_atcs_functions { | |
1370 | bool get_ext_state; | |
1371 | bool pcie_perf_req; | |
1372 | bool pcie_dev_rdy; | |
1373 | bool pcie_bus_width; | |
1374 | }; | |
1375 | ||
1376 | struct amdgpu_atcs { | |
1377 | struct amdgpu_atcs_functions functions; | |
1378 | }; | |
1379 | ||
a05502e5 HC |
1380 | /* |
1381 | * Firmware VRAM reservation | |
1382 | */ | |
1383 | struct amdgpu_fw_vram_usage { | |
1384 | u64 start_offset; | |
1385 | u64 size; | |
1386 | struct amdgpu_bo *reserved_bo; | |
1387 | void *va; | |
1388 | }; | |
1389 | ||
d03846af CZ |
1390 | /* |
1391 | * CGS | |
1392 | */ | |
110e6f26 DA |
1393 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
1394 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); | |
a8fe58ce | 1395 | |
97b2e202 AD |
1396 | /* |
1397 | * Core structure, functions and helpers. | |
1398 | */ | |
1399 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
1400 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1401 | ||
1402 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1403 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
1404 | ||
946a4d5b SL |
1405 | |
1406 | /* | |
1407 | * amdgpu nbio functions | |
1408 | * | |
946a4d5b | 1409 | */ |
bf383fb6 AD |
1410 | struct nbio_hdp_flush_reg { |
1411 | u32 ref_and_mask_cp0; | |
1412 | u32 ref_and_mask_cp1; | |
1413 | u32 ref_and_mask_cp2; | |
1414 | u32 ref_and_mask_cp3; | |
1415 | u32 ref_and_mask_cp4; | |
1416 | u32 ref_and_mask_cp5; | |
1417 | u32 ref_and_mask_cp6; | |
1418 | u32 ref_and_mask_cp7; | |
1419 | u32 ref_and_mask_cp8; | |
1420 | u32 ref_and_mask_cp9; | |
1421 | u32 ref_and_mask_sdma0; | |
1422 | u32 ref_and_mask_sdma1; | |
1423 | }; | |
946a4d5b SL |
1424 | |
1425 | struct amdgpu_nbio_funcs { | |
bf383fb6 AD |
1426 | const struct nbio_hdp_flush_reg *hdp_flush_reg; |
1427 | u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); | |
1428 | u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); | |
1429 | u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); | |
1430 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); | |
1431 | u32 (*get_rev_id)(struct amdgpu_device *adev); | |
bf383fb6 AD |
1432 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); |
1433 | void (*hdp_flush)(struct amdgpu_device *adev); | |
1434 | u32 (*get_memsize)(struct amdgpu_device *adev); | |
1435 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, | |
1436 | bool use_doorbell, int doorbell_index); | |
1437 | void (*enable_doorbell_aperture)(struct amdgpu_device *adev, | |
1438 | bool enable); | |
1439 | void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, | |
1440 | bool enable); | |
1441 | void (*ih_doorbell_range)(struct amdgpu_device *adev, | |
1442 | bool use_doorbell, int doorbell_index); | |
1443 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, | |
1444 | bool enable); | |
1445 | void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, | |
1446 | bool enable); | |
1447 | void (*get_clockgating_state)(struct amdgpu_device *adev, | |
1448 | u32 *flags); | |
1449 | void (*ih_control)(struct amdgpu_device *adev); | |
1450 | void (*init_registers)(struct amdgpu_device *adev); | |
1451 | void (*detect_hw_virt)(struct amdgpu_device *adev); | |
946a4d5b SL |
1452 | }; |
1453 | ||
1454 | ||
4522824c SL |
1455 | /* Define the HW IP blocks will be used in driver , add more if necessary */ |
1456 | enum amd_hw_ip_block_type { | |
1457 | GC_HWIP = 1, | |
1458 | HDP_HWIP, | |
1459 | SDMA0_HWIP, | |
1460 | SDMA1_HWIP, | |
1461 | MMHUB_HWIP, | |
1462 | ATHUB_HWIP, | |
1463 | NBIO_HWIP, | |
1464 | MP0_HWIP, | |
1465 | UVD_HWIP, | |
1466 | VCN_HWIP = UVD_HWIP, | |
1467 | VCE_HWIP, | |
1468 | DF_HWIP, | |
1469 | DCE_HWIP, | |
1470 | OSSSYS_HWIP, | |
1471 | SMUIO_HWIP, | |
1472 | PWR_HWIP, | |
1473 | NBIF_HWIP, | |
1474 | MAX_HWIP | |
1475 | }; | |
1476 | ||
1477 | #define HWIP_MAX_INSTANCE 6 | |
1478 | ||
11dc9364 RZ |
1479 | struct amd_powerplay { |
1480 | struct cgs_device *cgs_device; | |
1481 | void *pp_handle; | |
1482 | const struct amd_ip_funcs *ip_funcs; | |
1483 | const struct amd_pm_funcs *pp_funcs; | |
1484 | }; | |
1485 | ||
0c49e0b8 | 1486 | #define AMDGPU_RESET_MAGIC_NUM 64 |
97b2e202 AD |
1487 | struct amdgpu_device { |
1488 | struct device *dev; | |
1489 | struct drm_device *ddev; | |
1490 | struct pci_dev *pdev; | |
97b2e202 | 1491 | |
a8fe58ce MB |
1492 | #ifdef CONFIG_DRM_AMD_ACP |
1493 | struct amdgpu_acp acp; | |
1494 | #endif | |
1495 | ||
97b2e202 | 1496 | /* ASIC */ |
2f7d10b3 | 1497 | enum amd_asic_type asic_type; |
97b2e202 AD |
1498 | uint32_t family; |
1499 | uint32_t rev_id; | |
1500 | uint32_t external_rev_id; | |
1501 | unsigned long flags; | |
1502 | int usec_timeout; | |
1503 | const struct amdgpu_asic_funcs *asic_funcs; | |
1504 | bool shutdown; | |
97b2e202 AD |
1505 | bool need_dma32; |
1506 | bool accel_working; | |
edf600da | 1507 | struct work_struct reset_work; |
97b2e202 AD |
1508 | struct notifier_block acpi_nb; |
1509 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
1510 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
edf600da | 1511 | unsigned debugfs_count; |
97b2e202 | 1512 | #if defined(CONFIG_DEBUG_FS) |
adcec288 | 1513 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
97b2e202 AD |
1514 | #endif |
1515 | struct amdgpu_atif atif; | |
1516 | struct amdgpu_atcs atcs; | |
1517 | struct mutex srbm_mutex; | |
1518 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
1519 | struct mutex grbm_idx_mutex; | |
1520 | struct dev_pm_domain vga_pm_domain; | |
1521 | bool have_disp_power_ref; | |
1522 | ||
1523 | /* BIOS */ | |
0cdd5005 | 1524 | bool is_atom_fw; |
97b2e202 | 1525 | uint8_t *bios; |
a9f5db9c | 1526 | uint32_t bios_size; |
5af2c10d | 1527 | struct amdgpu_bo *stolen_vga_memory; |
a5bde2f9 | 1528 | uint32_t bios_scratch_reg_offset; |
97b2e202 AD |
1529 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
1530 | ||
1531 | /* Register/doorbell mmio */ | |
1532 | resource_size_t rmmio_base; | |
1533 | resource_size_t rmmio_size; | |
1534 | void __iomem *rmmio; | |
1535 | /* protects concurrent MM_INDEX/DATA based register access */ | |
1536 | spinlock_t mmio_idx_lock; | |
1537 | /* protects concurrent SMC based register access */ | |
1538 | spinlock_t smc_idx_lock; | |
1539 | amdgpu_rreg_t smc_rreg; | |
1540 | amdgpu_wreg_t smc_wreg; | |
1541 | /* protects concurrent PCIE register access */ | |
1542 | spinlock_t pcie_idx_lock; | |
1543 | amdgpu_rreg_t pcie_rreg; | |
1544 | amdgpu_wreg_t pcie_wreg; | |
36b9a952 HR |
1545 | amdgpu_rreg_t pciep_rreg; |
1546 | amdgpu_wreg_t pciep_wreg; | |
97b2e202 AD |
1547 | /* protects concurrent UVD register access */ |
1548 | spinlock_t uvd_ctx_idx_lock; | |
1549 | amdgpu_rreg_t uvd_ctx_rreg; | |
1550 | amdgpu_wreg_t uvd_ctx_wreg; | |
1551 | /* protects concurrent DIDT register access */ | |
1552 | spinlock_t didt_idx_lock; | |
1553 | amdgpu_rreg_t didt_rreg; | |
1554 | amdgpu_wreg_t didt_wreg; | |
ccdbb20a RZ |
1555 | /* protects concurrent gc_cac register access */ |
1556 | spinlock_t gc_cac_idx_lock; | |
1557 | amdgpu_rreg_t gc_cac_rreg; | |
1558 | amdgpu_wreg_t gc_cac_wreg; | |
16abb5d2 EQ |
1559 | /* protects concurrent se_cac register access */ |
1560 | spinlock_t se_cac_idx_lock; | |
1561 | amdgpu_rreg_t se_cac_rreg; | |
1562 | amdgpu_wreg_t se_cac_wreg; | |
97b2e202 AD |
1563 | /* protects concurrent ENDPOINT (audio) register access */ |
1564 | spinlock_t audio_endpt_idx_lock; | |
1565 | amdgpu_block_rreg_t audio_endpt_rreg; | |
1566 | amdgpu_block_wreg_t audio_endpt_wreg; | |
1567 | void __iomem *rio_mem; | |
1568 | resource_size_t rio_mem_size; | |
1569 | struct amdgpu_doorbell doorbell; | |
1570 | ||
1571 | /* clock/pll info */ | |
1572 | struct amdgpu_clock clock; | |
1573 | ||
1574 | /* MC */ | |
1575 | struct amdgpu_mc mc; | |
1576 | struct amdgpu_gart gart; | |
1577 | struct amdgpu_dummy_page dummy_page; | |
1578 | struct amdgpu_vm_manager vm_manager; | |
e60f8db5 | 1579 | struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; |
97b2e202 AD |
1580 | |
1581 | /* memory management */ | |
1582 | struct amdgpu_mman mman; | |
97b2e202 AD |
1583 | struct amdgpu_vram_scratch vram_scratch; |
1584 | struct amdgpu_wb wb; | |
97b2e202 | 1585 | atomic64_t num_bytes_moved; |
dbd5ed60 | 1586 | atomic64_t num_evictions; |
68e2c5ff | 1587 | atomic64_t num_vram_cpu_page_faults; |
d94aed5a | 1588 | atomic_t gpu_reset_counter; |
f1892138 | 1589 | atomic_t vram_lost_counter; |
97b2e202 | 1590 | |
95844d20 MO |
1591 | /* data for buffer migration throttling */ |
1592 | struct { | |
1593 | spinlock_t lock; | |
1594 | s64 last_update_us; | |
1595 | s64 accum_us; /* accumulated microseconds */ | |
00f06b24 | 1596 | s64 accum_us_vis; /* for visible VRAM */ |
95844d20 MO |
1597 | u32 log2_max_MBps; |
1598 | } mm_stats; | |
1599 | ||
97b2e202 | 1600 | /* display */ |
9accf2fd | 1601 | bool enable_virtual_display; |
97b2e202 | 1602 | struct amdgpu_mode_info mode_info; |
4562236b | 1603 | /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ |
97b2e202 AD |
1604 | struct work_struct hotplug_work; |
1605 | struct amdgpu_irq_src crtc_irq; | |
1606 | struct amdgpu_irq_src pageflip_irq; | |
1607 | struct amdgpu_irq_src hpd_irq; | |
1608 | ||
1609 | /* rings */ | |
76bf0db5 | 1610 | u64 fence_context; |
97b2e202 AD |
1611 | unsigned num_rings; |
1612 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
1613 | bool ib_pool_ready; | |
1614 | struct amdgpu_sa_manager ring_tmp_bo; | |
1615 | ||
1616 | /* interrupts */ | |
1617 | struct amdgpu_irq irq; | |
1618 | ||
1f7371b2 AD |
1619 | /* powerplay */ |
1620 | struct amd_powerplay powerplay; | |
f3898ea1 | 1621 | bool pp_force_state_enabled; |
1f7371b2 | 1622 | |
97b2e202 AD |
1623 | /* dpm */ |
1624 | struct amdgpu_pm pm; | |
1625 | u32 cg_flags; | |
1626 | u32 pg_flags; | |
1627 | ||
1628 | /* amdgpu smumgr */ | |
1629 | struct amdgpu_smumgr smu; | |
1630 | ||
1631 | /* gfx */ | |
1632 | struct amdgpu_gfx gfx; | |
1633 | ||
1634 | /* sdma */ | |
c113ea1c | 1635 | struct amdgpu_sdma sdma; |
97b2e202 | 1636 | |
b43aaee6 LL |
1637 | /* uvd */ |
1638 | struct amdgpu_uvd uvd; | |
1639 | ||
1640 | /* vce */ | |
1641 | struct amdgpu_vce vce; | |
1642 | ||
1643 | /* vcn */ | |
1644 | struct amdgpu_vcn vcn; | |
97b2e202 AD |
1645 | |
1646 | /* firmwares */ | |
1647 | struct amdgpu_firmware firmware; | |
1648 | ||
0e5ca0d1 HR |
1649 | /* PSP */ |
1650 | struct psp_context psp; | |
1651 | ||
97b2e202 AD |
1652 | /* GDS */ |
1653 | struct amdgpu_gds gds; | |
1654 | ||
4562236b HW |
1655 | /* display related functionality */ |
1656 | struct amdgpu_display_manager dm; | |
1657 | ||
a1255107 | 1658 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
97b2e202 | 1659 | int num_ip_blocks; |
97b2e202 AD |
1660 | struct mutex mn_lock; |
1661 | DECLARE_HASHTABLE(mn_hash, 7); | |
1662 | ||
1663 | /* tracking pinned memory */ | |
1664 | u64 vram_pin_size; | |
e131b914 | 1665 | u64 invisible_pin_size; |
97b2e202 | 1666 | u64 gart_pin_size; |
130e0371 OG |
1667 | |
1668 | /* amdkfd interface */ | |
1669 | struct kfd_dev *kfd; | |
23ca0e4e | 1670 | |
4522824c SL |
1671 | /* soc15 register offset based on ip, instance and segment */ |
1672 | uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; | |
1673 | ||
946a4d5b SL |
1674 | const struct amdgpu_nbio_funcs *nbio_funcs; |
1675 | ||
2dc80b00 S |
1676 | /* delayed work_func for deferring clockgating during resume */ |
1677 | struct delayed_work late_init_work; | |
1678 | ||
5a5099cb | 1679 | struct amdgpu_virt virt; |
a05502e5 HC |
1680 | /* firmware VRAM reservation */ |
1681 | struct amdgpu_fw_vram_usage fw_vram_usage; | |
0c4e7fa5 CZ |
1682 | |
1683 | /* link all shadow bo */ | |
1684 | struct list_head shadow_list; | |
1685 | struct mutex shadow_list_lock; | |
795f2813 AR |
1686 | /* keep an lru list of rings by HW IP */ |
1687 | struct list_head ring_lru_list; | |
1688 | spinlock_t ring_lru_list_lock; | |
5c1354bd | 1689 | |
c836fec5 JQ |
1690 | /* record hw reset is performed */ |
1691 | bool has_hw_reset; | |
0c49e0b8 | 1692 | u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; |
c836fec5 | 1693 | |
47ed4e1c KW |
1694 | /* record last mm index being written through WREG32*/ |
1695 | unsigned long last_mm_index; | |
13a752e3 ML |
1696 | bool in_gpu_reset; |
1697 | struct mutex lock_reset; | |
97b2e202 AD |
1698 | }; |
1699 | ||
a7d64de6 CK |
1700 | static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) |
1701 | { | |
1702 | return container_of(bdev, struct amdgpu_device, mman.bdev); | |
1703 | } | |
1704 | ||
97b2e202 AD |
1705 | int amdgpu_device_init(struct amdgpu_device *adev, |
1706 | struct drm_device *ddev, | |
1707 | struct pci_dev *pdev, | |
1708 | uint32_t flags); | |
1709 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
1710 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
1711 | ||
1712 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 1713 | uint32_t acc_flags); |
97b2e202 | 1714 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 1715 | uint32_t acc_flags); |
97b2e202 AD |
1716 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
1717 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
1718 | ||
1719 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
1720 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
832be404 KW |
1721 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); |
1722 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); | |
97b2e202 | 1723 | |
4562236b HW |
1724 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); |
1725 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); | |
1726 | ||
97b2e202 AD |
1727 | /* |
1728 | * Registers read & write functions. | |
1729 | */ | |
15d72fd7 ML |
1730 | |
1731 | #define AMDGPU_REGS_IDX (1<<0) | |
1732 | #define AMDGPU_REGS_NO_KIQ (1<<1) | |
1733 | ||
1734 | #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) | |
1735 | #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) | |
1736 | ||
1737 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) | |
1738 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) | |
1739 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) | |
1740 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) | |
1741 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) | |
97b2e202 AD |
1742 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1743 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1744 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
1745 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
36b9a952 HR |
1746 | #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) |
1747 | #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1748 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
1749 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
1750 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
1751 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
1752 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
1753 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
ccdbb20a RZ |
1754 | #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) |
1755 | #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) | |
16abb5d2 EQ |
1756 | #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) |
1757 | #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1758 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
1759 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
1760 | #define WREG32_P(reg, val, mask) \ | |
1761 | do { \ | |
1762 | uint32_t tmp_ = RREG32(reg); \ | |
1763 | tmp_ &= (mask); \ | |
1764 | tmp_ |= ((val) & ~(mask)); \ | |
1765 | WREG32(reg, tmp_); \ | |
1766 | } while (0) | |
1767 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
1768 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
1769 | #define WREG32_PLL_P(reg, val, mask) \ | |
1770 | do { \ | |
1771 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1772 | tmp_ &= (mask); \ | |
1773 | tmp_ |= ((val) & ~(mask)); \ | |
1774 | WREG32_PLL(reg, tmp_); \ | |
1775 | } while (0) | |
1776 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
1777 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
1778 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
1779 | ||
1780 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
1781 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
832be404 KW |
1782 | #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) |
1783 | #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) | |
97b2e202 AD |
1784 | |
1785 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT | |
1786 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
1787 | ||
1788 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
1789 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
1790 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
1791 | ||
1792 | #define REG_GET_FIELD(value, reg, field) \ | |
1793 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
61cb8cef TSD |
1794 | |
1795 | #define WREG32_FIELD(reg, field, val) \ | |
1796 | WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
97b2e202 | 1797 | |
ccaf3574 TSD |
1798 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
1799 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
1800 | ||
97b2e202 AD |
1801 | /* |
1802 | * BIOS helpers. | |
1803 | */ | |
1804 | #define RBIOS8(i) (adev->bios[i]) | |
1805 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1806 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1807 | ||
c113ea1c AD |
1808 | static inline struct amdgpu_sdma_instance * |
1809 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |
4b2f7e2c JZ |
1810 | { |
1811 | struct amdgpu_device *adev = ring->adev; | |
1812 | int i; | |
1813 | ||
c113ea1c AD |
1814 | for (i = 0; i < adev->sdma.num_instances; i++) |
1815 | if (&adev->sdma.instance[i].ring == ring) | |
4b2f7e2c JZ |
1816 | break; |
1817 | ||
1818 | if (i < AMDGPU_MAX_SDMA_INSTANCES) | |
c113ea1c | 1819 | return &adev->sdma.instance[i]; |
4b2f7e2c JZ |
1820 | else |
1821 | return NULL; | |
1822 | } | |
1823 | ||
97b2e202 AD |
1824 | /* |
1825 | * ASICs macro. | |
1826 | */ | |
1827 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
1828 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
97b2e202 AD |
1829 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
1830 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
1831 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
841686df MB |
1832 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
1833 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) | |
1834 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
97b2e202 | 1835 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
7946b878 | 1836 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 | 1837 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
bbf282d8 | 1838 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
97b2e202 AD |
1839 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) |
1840 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | |
3de676d8 | 1841 | #define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags)) |
97b2e202 | 1842 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) |
de9ea7bd | 1843 | #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) |
97b2e202 | 1844 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) |
5463545b | 1845 | #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) |
97b2e202 AD |
1846 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) |
1847 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) | |
bbec97aa | 1848 | #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) |
97b2e202 AD |
1849 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
1850 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
1851 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
d88bf583 | 1852 | #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) |
b8c7b39e | 1853 | #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) |
97b2e202 | 1854 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) |
890ee23f | 1855 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
97b2e202 | 1856 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) |
d2edb07b | 1857 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
11afbde8 | 1858 | #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) |
c2167a65 | 1859 | #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) |
753ad49c | 1860 | #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) |
b6091c12 XY |
1861 | #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) |
1862 | #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) | |
3b4d68e9 | 1863 | #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) |
9e5d5309 | 1864 | #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) |
03ccf481 ML |
1865 | #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) |
1866 | #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) | |
97b2e202 | 1867 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
00ecd8a2 | 1868 | #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) |
97b2e202 AD |
1869 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) |
1870 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) | |
97b2e202 AD |
1871 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) |
1872 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) | |
97b2e202 AD |
1873 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) |
1874 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) | |
1875 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) | |
1876 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) | |
1877 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) | |
1878 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) | |
cb9e59d7 | 1879 | #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) |
97b2e202 AD |
1880 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) |
1881 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) | |
1882 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) | |
c7ae72c0 | 1883 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
6e7a3840 | 1884 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
b95e31fd | 1885 | #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) |
9559ef5b | 1886 | #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) |
97b2e202 | 1887 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) |
0e5ca0d1 | 1888 | #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) |
97b2e202 AD |
1889 | |
1890 | /* Common functions */ | |
dcebf026 | 1891 | int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force); |
3ad81f16 | 1892 | bool amdgpu_need_backup(struct amdgpu_device *adev); |
8111c387 | 1893 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); |
c836fec5 | 1894 | bool amdgpu_need_post(struct amdgpu_device *adev); |
97b2e202 | 1895 | void amdgpu_update_display_priority(struct amdgpu_device *adev); |
d5fc5e82 | 1896 | |
00f06b24 JB |
1897 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
1898 | u64 num_vis_bytes); | |
765e7fbf | 1899 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); |
97b2e202 | 1900 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); |
2543e28a AD |
1901 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
1902 | struct amdgpu_mc *mc, u64 base); | |
1903 | void amdgpu_device_gart_location(struct amdgpu_device *adev, | |
1904 | struct amdgpu_mc *mc); | |
d6895ad3 | 1905 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); |
97b2e202 | 1906 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); |
9f31a0b0 BX |
1907 | int amdgpu_ttm_init(struct amdgpu_device *adev); |
1908 | void amdgpu_ttm_fini(struct amdgpu_device *adev); | |
9c3f2b54 | 1909 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
97b2e202 AD |
1910 | const u32 *registers, |
1911 | const u32 array_size); | |
1912 | ||
1913 | bool amdgpu_device_is_px(struct drm_device *dev); | |
1914 | /* atpx handler */ | |
1915 | #if defined(CONFIG_VGA_SWITCHEROO) | |
1916 | void amdgpu_register_atpx_handler(void); | |
1917 | void amdgpu_unregister_atpx_handler(void); | |
a78fe133 | 1918 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
2f5af82e | 1919 | bool amdgpu_is_atpx_hybrid(void); |
efc83cf4 | 1920 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); |
714f88e0 | 1921 | bool amdgpu_has_atpx(void); |
97b2e202 AD |
1922 | #else |
1923 | static inline void amdgpu_register_atpx_handler(void) {} | |
1924 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
a78fe133 | 1925 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
2f5af82e | 1926 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
efc83cf4 | 1927 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } |
714f88e0 | 1928 | static inline bool amdgpu_has_atpx(void) { return false; } |
97b2e202 AD |
1929 | #endif |
1930 | ||
1931 | /* | |
1932 | * KMS | |
1933 | */ | |
1934 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
f498d9ed | 1935 | extern const int amdgpu_max_kms_ioctl; |
97b2e202 AD |
1936 | |
1937 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
11b3c20b | 1938 | void amdgpu_driver_unload_kms(struct drm_device *dev); |
97b2e202 AD |
1939 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
1940 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
1941 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
1942 | struct drm_file *file_priv); | |
cdd61df6 | 1943 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev); |
810ddc3a AD |
1944 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); |
1945 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
1946 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
1947 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
1948 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
97b2e202 AD |
1949 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
1950 | unsigned long arg); | |
1951 | ||
97b2e202 AD |
1952 | /* |
1953 | * functions used by amdgpu_encoder.c | |
1954 | */ | |
1955 | struct amdgpu_afmt_acr { | |
1956 | u32 clock; | |
1957 | ||
1958 | int n_32khz; | |
1959 | int cts_32khz; | |
1960 | ||
1961 | int n_44_1khz; | |
1962 | int cts_44_1khz; | |
1963 | ||
1964 | int n_48khz; | |
1965 | int cts_48khz; | |
1966 | ||
1967 | }; | |
1968 | ||
1969 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
1970 | ||
1971 | /* amdgpu_acpi.c */ | |
1972 | #if defined(CONFIG_ACPI) | |
1973 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
1974 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
1975 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
1976 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
1977 | u8 perf_req, bool advertise); | |
1978 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
1979 | #else | |
1980 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
1981 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
1982 | #endif | |
1983 | ||
9cca0b8e CK |
1984 | int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
1985 | uint64_t addr, struct amdgpu_bo **bo, | |
1986 | struct amdgpu_bo_va_mapping **mapping); | |
97b2e202 | 1987 | |
4562236b HW |
1988 | #if defined(CONFIG_DRM_AMD_DC) |
1989 | int amdgpu_dm_display_resume(struct amdgpu_device *adev ); | |
1990 | #else | |
1991 | static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } | |
1992 | #endif | |
1993 | ||
97b2e202 | 1994 | #include "amdgpu_object.h" |
97b2e202 | 1995 | #endif |