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drm/ttm: allow mapping BOs while they are still on the swap list
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834
AR		 49#include <kgd_kfd_interface.h>
50
5fc3aeeb 51#include "amd_shared.h"
97b2e202
AD		 52#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
c632d799 56#include "amdgpu_ttm.h"
0e5ca0d1 57#include "amdgpu_psp.h"
97b2e202 58#include "amdgpu_gds.h"
56113504 59#include "amdgpu_sync.h"
78023016 60#include "amdgpu_ring.h"
073440d2 61#include "amdgpu_vm.h"
1f7371b2 62#include "amd_powerplay.h"
cf097881 63#include "amdgpu_dpm.h"
a8fe58ce 64#include "amdgpu_acp.h"
4df654d2 65#include "amdgpu_uvd.h"
5e568178 66#include "amdgpu_vce.h"
95aa13f6 67#include "amdgpu_vcn.h"
97b2e202 68
b80d8475 69#include "gpu_scheduler.h"
ceeb50ed 70#include "amdgpu_virt.h"
3490bdb5 71#include "amdgpu_gart.h"
b80d8475 72
97b2e202
AD		 73/*
74 * Modules parameters.
75 */
76extern int amdgpu_modeset;
77extern int amdgpu_vram_limit;
218b5dcd 78extern int amdgpu_vis_vram_limit;
83e74db6 79extern int amdgpu_gart_size;
36d38372 80extern int amdgpu_gtt_size;
95844d20 81extern int amdgpu_moverate;
97b2e202
AD		 82extern int amdgpu_benchmarking;
83extern int amdgpu_testing;
84extern int amdgpu_audio;
85extern int amdgpu_disp_priority;
86extern int amdgpu_hw_i2c;
87extern int amdgpu_pcie_gen2;
88extern int amdgpu_msi;
89extern int amdgpu_lockup_timeout;
90extern int amdgpu_dpm;
e635ee07 91extern int amdgpu_fw_load_type;
97b2e202
AD		 92extern int amdgpu_aspm;
93extern int amdgpu_runtime_pm;
97b2e202
AD		 94extern unsigned amdgpu_ip_block_mask;
95extern int amdgpu_bapm;
96extern int amdgpu_deep_color;
97extern int amdgpu_vm_size;
98extern int amdgpu_vm_block_size;
d07f14be 99extern int amdgpu_vm_fragment_size;
d9c13156 100extern int amdgpu_vm_fault_stop;
b495bd3a 101extern int amdgpu_vm_debug;
9a4b7d4c 102extern int amdgpu_vm_update_mode;
1333f723 103extern int amdgpu_sched_jobs;
4afcb303 104extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 105extern int amdgpu_no_evict;
106extern int amdgpu_direct_gma_size;
cd474ba0
AD		 107extern unsigned amdgpu_pcie_gen_cap;
108extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 109extern unsigned amdgpu_cg_mask;
110extern unsigned amdgpu_pg_mask;
a667386c 111extern unsigned amdgpu_sdma_phase_quantum;
6f8941a2 112extern char *amdgpu_disable_cu;
9accf2fd 113extern char *amdgpu_virtual_display;
5141e9d2 114extern unsigned amdgpu_pp_feature_mask;
6a7f76e7 115extern int amdgpu_vram_page_split;
bce23e00
AD		 116extern int amdgpu_ngg;
117extern int amdgpu_prim_buf_per_se;
118extern int amdgpu_pos_buf_per_se;
119extern int amdgpu_cntl_sb_buf_per_se;
120extern int amdgpu_param_buf_per_se;
65781c78 121extern int amdgpu_job_hang_limit;
e8835e0e 122extern int amdgpu_lbpw;
97b2e202 123
6dd13096
FK		 124#ifdef CONFIG_DRM_AMDGPU_SI
125extern int amdgpu_si_support;
126#endif
7df28986
FK		 127#ifdef CONFIG_DRM_AMDGPU_CIK
128extern int amdgpu_cik_support;
129#endif
97b2e202 130
55ed8caf 131#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 132#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 133#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
134#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
135/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
136#define AMDGPU_IB_POOL_SIZE 16
137#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
138#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 139#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 140
36f523a7
JZ		 141/* max number of IP instances */
142#define AMDGPU_MAX_SDMA_INSTANCES 2
143
97b2e202
AD		 144/* hard reset data */
145#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
146
147/* reset flags */
148#define AMDGPU_RESET_GFX (1 << 0)
149#define AMDGPU_RESET_COMPUTE (1 << 1)
150#define AMDGPU_RESET_DMA (1 << 2)
151#define AMDGPU_RESET_CP (1 << 3)
152#define AMDGPU_RESET_GRBM (1 << 4)
153#define AMDGPU_RESET_DMA1 (1 << 5)
154#define AMDGPU_RESET_RLC (1 << 6)
155#define AMDGPU_RESET_SEM (1 << 7)
156#define AMDGPU_RESET_IH (1 << 8)
157#define AMDGPU_RESET_VMC (1 << 9)
158#define AMDGPU_RESET_MC (1 << 10)
159#define AMDGPU_RESET_DISPLAY (1 << 11)
160#define AMDGPU_RESET_UVD (1 << 12)
161#define AMDGPU_RESET_VCE (1 << 13)
162#define AMDGPU_RESET_VCE1 (1 << 14)
163
97b2e202
AD		 164/* GFX current status */
165#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
166#define AMDGPU_GFX_SAFE_MODE 0x00000001L
167#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
168#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
169#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
170
171/* max cursor sizes (in pixels) */
172#define CIK_CURSOR_WIDTH 128
173#define CIK_CURSOR_HEIGHT 128
174
175struct amdgpu_device;
97b2e202 176struct amdgpu_ib;
97b2e202 177struct amdgpu_cs_parser;
bb977d37 178struct amdgpu_job;
97b2e202 179struct amdgpu_irq_src;
0b492a4c 180struct amdgpu_fpriv;
3fe89771 181struct amdgpu_mn;
97b2e202
AD		 182
183enum amdgpu_cp_irq {
184 AMDGPU_CP_IRQ_GFX_EOP = 0,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
193
194 AMDGPU_CP_IRQ_LAST
195};
196
197enum amdgpu_sdma_irq {
198 AMDGPU_SDMA_IRQ_TRAP0 = 0,
199 AMDGPU_SDMA_IRQ_TRAP1,
200
201 AMDGPU_SDMA_IRQ_LAST
202};
203
204enum amdgpu_thermal_irq {
205 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
206 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
207
208 AMDGPU_THERMAL_IRQ_LAST
209};
210
4e638ae9
XY		 211enum amdgpu_kiq_irq {
212 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
213 AMDGPU_CP_KIQ_IRQ_LAST
214};
215
97b2e202 216int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 217 enum amd_ip_block_type block_type,
218 enum amd_clockgating_state state);
97b2e202 219int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 220 enum amd_ip_block_type block_type,
221 enum amd_powergating_state state);
6cb2d4e4 222void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 223int amdgpu_wait_for_idle(struct amdgpu_device *adev,
224 enum amd_ip_block_type block_type);
225bool amdgpu_is_idle(struct amdgpu_device *adev,
226 enum amd_ip_block_type block_type);
97b2e202 227
a1255107
AD		 228#define AMDGPU_MAX_IP_NUM 16
229
230struct amdgpu_ip_block_status {
231 bool valid;
232 bool sw;
233 bool hw;
234 bool late_initialized;
235 bool hang;
236};
237
97b2e202 238struct amdgpu_ip_block_version {
a1255107
AD		 239 const enum amd_ip_block_type type;
240 const u32 major;
241 const u32 minor;
242 const u32 rev;
5fc3aeeb 243 const struct amd_ip_funcs *funcs;
97b2e202
AD		 244};
245
a1255107
AD		 246struct amdgpu_ip_block {
247 struct amdgpu_ip_block_status status;
248 const struct amdgpu_ip_block_version *version;
249};
250
97b2e202 251int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 252 enum amd_ip_block_type type,
97b2e202
AD		 253 u32 major, u32 minor);
254
a1255107
AD		 255struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
256 enum amd_ip_block_type type);
257
258int amdgpu_ip_block_add(struct amdgpu_device *adev,
259 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 260
261/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
262struct amdgpu_buffer_funcs {
263 /* maximum bytes in a single operation */
264 uint32_t copy_max_bytes;
265
266 /* number of dw to reserve per operation */
267 unsigned copy_num_dw;
268
269 /* used for buffer migration */
c7ae72c0 270 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 271 /* src addr in bytes */
272 uint64_t src_offset,
273 /* dst addr in bytes */
274 uint64_t dst_offset,
275 /* number of byte to transfer */
276 uint32_t byte_count);
277
278 /* maximum bytes in a single operation */
279 uint32_t fill_max_bytes;
280
281 /* number of dw to reserve per operation */
282 unsigned fill_num_dw;
283
284 /* used for buffer clearing */
6e7a3840 285 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 286 /* value to write to memory */
287 uint32_t src_data,
288 /* dst addr in bytes */
289 uint64_t dst_offset,
290 /* number of byte to fill */
291 uint32_t byte_count);
292};
293
294/* provided by hw blocks that can write ptes, e.g., sdma */
295struct amdgpu_vm_pte_funcs {
296 /* copy pte entries from GART */
297 void (*copy_pte)(struct amdgpu_ib *ib,
298 uint64_t pe, uint64_t src,
299 unsigned count);
300 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 301 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
302 uint64_t value, unsigned count,
303 uint32_t incr);
97b2e202
AD		 304 /* for linear pte/pde updates without addr mapping */
305 void (*set_pte_pde)(struct amdgpu_ib *ib,
306 uint64_t pe,
307 uint64_t addr, unsigned count,
6b777607 308 uint32_t incr, uint64_t flags);
97b2e202
AD		 309};
310
311/* provided by the gmc block */
312struct amdgpu_gart_funcs {
313 /* flush the vm tlb via mmio */
314 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
315 uint32_t vmid);
316 /* write pte/pde updates using the cpu */
317 int (*set_pte_pde)(struct amdgpu_device *adev,
318 void *cpu_pt_addr, /* cpu addr of page table */
319 uint32_t gpu_page_idx, /* pte/pde to update */
320 uint64_t addr, /* addr to write into pte/pde */
6b777607 321 uint64_t flags); /* access flags */
284710fa
CK		 322 /* enable/disable PRT support */
323 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 324 /* set pte flags based per asic */
325 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
326 uint32_t flags);
b1166325
CK		 327 /* get the pde for a given mc addr */
328 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 329 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 330};
331
97b2e202
AD		 332/* provided by the ih block */
333struct amdgpu_ih_funcs {
334 /* ring read/write ptr handling, called from interrupt context */
335 u32 (*get_wptr)(struct amdgpu_device *adev);
336 void (*decode_iv)(struct amdgpu_device *adev,
337 struct amdgpu_iv_entry *entry);
338 void (*set_rptr)(struct amdgpu_device *adev);
339};
340
97b2e202
AD		 341/*
342 * BIOS.
343 */
344bool amdgpu_get_bios(struct amdgpu_device *adev);
345bool amdgpu_read_bios(struct amdgpu_device *adev);
346
347/*
348 * Dummy page
349 */
350struct amdgpu_dummy_page {
351 struct page *page;
352 dma_addr_t addr;
353};
354int amdgpu_dummy_page_init(struct amdgpu_device *adev);
355void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
356
357
358/*
359 * Clocks
360 */
361
362#define AMDGPU_MAX_PPLL 3
363
364struct amdgpu_clock {
365 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
366 struct amdgpu_pll spll;
367 struct amdgpu_pll mpll;
368 /* 10 Khz units */
369 uint32_t default_mclk;
370 uint32_t default_sclk;
371 uint32_t default_dispclk;
372 uint32_t current_dispclk;
373 uint32_t dp_extclk;
374 uint32_t max_pixel_clock;
375};
376
97b2e202 377/*
9124a398 378 * GEM.
97b2e202 379 */
97b2e202 380
7e5a547f 381#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 382#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
383
384void amdgpu_gem_object_free(struct drm_gem_object *obj);
385int amdgpu_gem_object_open(struct drm_gem_object *obj,
386 struct drm_file *file_priv);
387void amdgpu_gem_object_close(struct drm_gem_object *obj,
388 struct drm_file *file_priv);
389unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
390struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 391struct drm_gem_object *
392amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
393 struct dma_buf_attachment *attach,
394 struct sg_table *sg);
97b2e202
AD		 395struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
396 struct drm_gem_object *gobj,
397 int flags);
398int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
399void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
400struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
401void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
402void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
403int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
404
405/* sub-allocation manager, it has to be protected by another lock.
406 * By conception this is an helper for other part of the driver
407 * like the indirect buffer or semaphore, which both have their
408 * locking.
409 *
410 * Principe is simple, we keep a list of sub allocation in offset
411 * order (first entry has offset == 0, last entry has the highest
412 * offset).
413 *
414 * When allocating new object we first check if there is room at
415 * the end total_size - (last_object_offset + last_object_size) >=
416 * alloc_size. If so we allocate new object there.
417 *
418 * When there is not enough room at the end, we start waiting for
419 * each sub object until we reach object_offset+object_size >=
420 * alloc_size, this object then become the sub object we return.
421 *
422 * Alignment can't be bigger than page size.
423 *
424 * Hole are not considered for allocation to keep things simple.
425 * Assumption is that there won't be hole (all object on same
426 * alignment).
427 */
6ba60b89
CK		 428
429#define AMDGPU_SA_NUM_FENCE_LISTS 32
430
97b2e202
AD		 431struct amdgpu_sa_manager {
432 wait_queue_head_t wq;
433 struct amdgpu_bo *bo;
434 struct list_head *hole;
6ba60b89 435 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 436 struct list_head olist;
437 unsigned size;
438 uint64_t gpu_addr;
439 void *cpu_ptr;
440 uint32_t domain;
441 uint32_t align;
442};
443
97b2e202
AD		 444/* sub-allocation buffer */
445struct amdgpu_sa_bo {
446 struct list_head olist;
447 struct list_head flist;
448 struct amdgpu_sa_manager *manager;
449 unsigned soffset;
450 unsigned eoffset;
f54d1867 451 struct dma_fence *fence;
97b2e202
AD		 452};
453
454/*
455 * GEM objects.
456 */
418aa0c2 457void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 458int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 459 int alignment, u32 initial_domain,
460 u64 flags, bool kernel,
461 struct reservation_object *resv,
462 struct drm_gem_object **obj);
97b2e202
AD		 463
464int amdgpu_mode_dumb_create(struct drm_file *file_priv,
465 struct drm_device *dev,
466 struct drm_mode_create_dumb *args);
467int amdgpu_mode_dumb_mmap(struct drm_file *filp,
468 struct drm_device *dev,
469 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 470int amdgpu_fence_slab_init(void);
471void amdgpu_fence_slab_fini(void);
97b2e202 472
e60f8db5
AX		 473/*
474 * VMHUB structures, functions & helpers
475 */
476struct amdgpu_vmhub {
477 uint32_t ctx0_ptb_addr_lo32;
478 uint32_t ctx0_ptb_addr_hi32;
479 uint32_t vm_inv_eng0_req;
480 uint32_t vm_inv_eng0_ack;
481 uint32_t vm_context0_cntl;
482 uint32_t vm_l2_pro_fault_status;
483 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 484};
485
97b2e202
AD		 486/*
487 * GPU MC structures, functions & helpers
488 */
489struct amdgpu_mc {
490 resource_size_t aper_size;
491 resource_size_t aper_base;
492 resource_size_t agp_base;
493 /* for some chips with <= 32MB we need to lie
494 * about vram size near mc fb location */
495 u64 mc_vram_size;
496 u64 visible_vram_size;
6f02a696
CK		 497 u64 gart_size;
498 u64 gart_start;
499 u64 gart_end;
97b2e202
AD		 500 u64 vram_start;
501 u64 vram_end;
502 unsigned vram_width;
503 u64 real_vram_size;
504 int vram_mtrr;
97b2e202
AD		 505 u64 mc_mask;
506 const struct firmware *fw; /* MC firmware */
507 uint32_t fw_version;
508 struct amdgpu_irq_src vm_fault;
81c59f54 509 uint32_t vram_type;
50b0197a 510 uint32_t srbm_soft_reset;
f7c35abe 511 bool prt_warning;
916910ad 512 uint64_t stolen_size;
8fe73328
JZ		 513 /* apertures */
514 u64 shared_aperture_start;
515 u64 shared_aperture_end;
516 u64 private_aperture_start;
517 u64 private_aperture_end;
e60f8db5
AX		 518 /* protects concurrent invalidation */
519 spinlock_t invalidate_lock;
97b2e202
AD		 520};
521
522/*
523 * GPU doorbell structures, functions & helpers
524 */
525typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
526{
527 AMDGPU_DOORBELL_KIQ = 0x000,
528 AMDGPU_DOORBELL_HIQ = 0x001,
529 AMDGPU_DOORBELL_DIQ = 0x002,
530 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
531 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
532 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
533 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
534 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
535 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
536 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
537 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
538 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
539 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
540 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
541 AMDGPU_DOORBELL_IH = 0x1E8,
542 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
543 AMDGPU_DOORBELL_INVALID = 0xFFFF
544} AMDGPU_DOORBELL_ASSIGNMENT;
545
546struct amdgpu_doorbell {
547 /* doorbell mmio */
548 resource_size_t base;
549 resource_size_t size;
550 u32 __iomem *ptr;
551 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
552};
553
39807b93
KW		 554/*
555 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
556 */
557typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
558{
559 /*
560 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
561 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
562 * Compute related doorbells are allocated from 0x00 to 0x8a
563 */
564
565
566 /* kernel scheduling */
567 AMDGPU_DOORBELL64_KIQ = 0x00,
568
569 /* HSA interface queue and debug queue */
570 AMDGPU_DOORBELL64_HIQ = 0x01,
571 AMDGPU_DOORBELL64_DIQ = 0x02,
572
573 /* Compute engines */
574 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
575 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
576 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
577 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
578 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
579 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
580 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
581 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
582
583 /* User queue doorbell range (128 doorbells) */
584 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
585 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
586
587 /* Graphics engine */
588 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
589
590 /*
591 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
592 * Graphics voltage island aperture 1
593 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
594 */
595
596 /* sDMA engines */
597 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
598 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
599 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
600 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
601
602 /* Interrupt handler */
603 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
604 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
605 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
606
e6b3ecb4
ML		 607 /* VCN engine use 32 bits doorbell */
608 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
609 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
610 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
611 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
612
613 /* overlap the doorbell assignment with VCN as they are mutually exclusive
614 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
615 */
4ed11d79
FM		 616 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
617 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
618 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
619 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
620
621 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
622 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
623 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
624 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 625
626 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
627 AMDGPU_DOORBELL64_INVALID = 0xFFFF
628} AMDGPU_DOORBELL64_ASSIGNMENT;
629
630
97b2e202
AD		 631void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
632 phys_addr_t *aperture_base,
633 size_t *aperture_size,
634 size_t *start_offset);
635
636/*
637 * IRQS.
638 */
639
640struct amdgpu_flip_work {
325cbba1 641 struct delayed_work flip_work;
97b2e202
AD		 642 struct work_struct unpin_work;
643 struct amdgpu_device *adev;
644 int crtc_id;
325cbba1 645 u32 target_vblank;
97b2e202
AD		 646 uint64_t base;
647 struct drm_pending_vblank_event *event;
765e7fbf 648 struct amdgpu_bo *old_abo;
f54d1867 649 struct dma_fence *excl;
1ffd2652 650 unsigned shared_count;
f54d1867
CW		 651 struct dma_fence **shared;
652 struct dma_fence_cb cb;
cb9e59d7 653 bool async;
97b2e202
AD		 654};
655
656
657/*
658 * CP & rings.
659 */
660
661struct amdgpu_ib {
662 struct amdgpu_sa_bo *sa_bo;
663 uint32_t length_dw;
664 uint64_t gpu_addr;
665 uint32_t *ptr;
de807f81 666 uint32_t flags;
97b2e202
AD		 667};
668
62250a91 669extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 670
50838c8c 671int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 672 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 673int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
674 struct amdgpu_job **job);
b6723c8d 675
a5fb4ec2 676void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 677void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 678int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 679 struct amd_sched_entity *entity, void *owner,
f54d1867 680 struct dma_fence **f);
8b4fb00b 681
effd924d
AR		 682/*
683 * Queue manager
684 */
685struct amdgpu_queue_mapper {
686 int hw_ip;
687 struct mutex lock;
688 /* protected by lock */
689 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
690};
691
692struct amdgpu_queue_mgr {
693 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
694};
695
696int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
697 struct amdgpu_queue_mgr *mgr);
698int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
699 struct amdgpu_queue_mgr *mgr);
700int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
701 struct amdgpu_queue_mgr *mgr,
702 int hw_ip, int instance, int ring,
703 struct amdgpu_ring **out_ring);
704
97b2e202
AD		 705/*
706 * context related structures
707 */
708
21c16bf6 709struct amdgpu_ctx_ring {
91404fb2 710 uint64_t sequence;
f54d1867 711 struct dma_fence **fences;
91404fb2 712 struct amd_sched_entity entity;
21c16bf6
CK		 713};
714
97b2e202 715struct amdgpu_ctx {
0b492a4c 716 struct kref refcount;
9cb7e5a9 717 struct amdgpu_device *adev;
effd924d 718 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 719 unsigned reset_counter;
21c16bf6 720 spinlock_t ring_lock;
f54d1867 721 struct dma_fence **fences;
21c16bf6 722 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 723 bool preamble_presented;
97b2e202
AD		 724};
725
726struct amdgpu_ctx_mgr {
0b492a4c
AD		 727 struct amdgpu_device *adev;
728 struct mutex lock;
729 /* protected by lock */
730 struct idr ctx_handles;
97b2e202
AD		 731};
732
0b492a4c
AD		 733struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
734int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
735
21c16bf6 736uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
f54d1867
CW		 737 struct dma_fence *fence);
738struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6
CK		 739 struct amdgpu_ring *ring, uint64_t seq);
740
0b492a4c
AD		 741int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
742 struct drm_file *filp);
743
efd4ccb5
CK		 744void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
745void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 746
97b2e202
AD		 747/*
748 * file private structure
749 */
750
751struct amdgpu_fpriv {
752 struct amdgpu_vm vm;
b85891bd 753 struct amdgpu_bo_va *prt_va;
0f4b3c68 754 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 755 struct mutex bo_list_lock;
756 struct idr bo_list_handles;
0b492a4c 757 struct amdgpu_ctx_mgr ctx_mgr;
f1892138 758 u32 vram_lost_counter;
97b2e202
AD		 759};
760
761/*
762 * residency list
763 */
9124a398
CK		 764struct amdgpu_bo_list_entry {
765 struct amdgpu_bo *robj;
766 struct ttm_validate_buffer tv;
767 struct amdgpu_bo_va *bo_va;
768 uint32_t priority;
769 struct page **user_pages;
770 int user_invalidated;
771};
97b2e202
AD		 772
773struct amdgpu_bo_list {
774 struct mutex lock;
5ac55629
AX		 775 struct rcu_head rhead;
776 struct kref refcount;
97b2e202
AD		 777 struct amdgpu_bo *gds_obj;
778 struct amdgpu_bo *gws_obj;
779 struct amdgpu_bo *oa_obj;
211dff55 780 unsigned first_userptr;
97b2e202
AD		 781 unsigned num_entries;
782 struct amdgpu_bo_list_entry *array;
783};
784
785struct amdgpu_bo_list *
786amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 787void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
788 struct list_head *validated);
97b2e202
AD		 789void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
790void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
791
792/*
793 * GFX stuff
794 */
795#include "clearstate_defs.h"
796
79e5412c
AD		 797struct amdgpu_rlc_funcs {
798 void (*enter_safe_mode)(struct amdgpu_device *adev);
799 void (*exit_safe_mode)(struct amdgpu_device *adev);
800};
801
97b2e202
AD		 802struct amdgpu_rlc {
803 /* for power gating */
804 struct amdgpu_bo *save_restore_obj;
805 uint64_t save_restore_gpu_addr;
806 volatile uint32_t *sr_ptr;
807 const u32 *reg_list;
808 u32 reg_list_size;
809 /* for clear state */
810 struct amdgpu_bo *clear_state_obj;
811 uint64_t clear_state_gpu_addr;
812 volatile uint32_t *cs_ptr;
813 const struct cs_section_def *cs_data;
814 u32 clear_state_size;
815 /* for cp tables */
816 struct amdgpu_bo *cp_table_obj;
817 uint64_t cp_table_gpu_addr;
818 volatile uint32_t *cp_table_ptr;
819 u32 cp_table_size;
79e5412c
AD		 820
821 /* safe mode for updating CG/PG state */
822 bool in_safe_mode;
823 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 824
825 /* for firmware data */
826 u32 save_and_restore_offset;
827 u32 clear_state_descriptor_offset;
828 u32 avail_scratch_ram_locations;
829 u32 reg_restore_list_size;
830 u32 reg_list_format_start;
831 u32 reg_list_format_separate_start;
832 u32 starting_offsets_start;
833 u32 reg_list_format_size_bytes;
834 u32 reg_list_size_bytes;
835
836 u32 *register_list_format;
837 u32 *register_restore;
97b2e202
AD		 838};
839
78c16834
AR		 840#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
841
97b2e202
AD		 842struct amdgpu_mec {
843 struct amdgpu_bo *hpd_eop_obj;
844 u64 hpd_eop_gpu_addr;
b1023571
KW		 845 struct amdgpu_bo *mec_fw_obj;
846 u64 mec_fw_gpu_addr;
97b2e202 847 u32 num_mec;
42794b27
AR		 848 u32 num_pipe_per_mec;
849 u32 num_queue_per_pipe;
59a82d7d 850 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 851
852 /* These are the resources for which amdgpu takes ownership */
853 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 854};
855
4e638ae9
XY		 856struct amdgpu_kiq {
857 u64 eop_gpu_addr;
858 struct amdgpu_bo *eop_obj;
cdf6adb2 859 struct mutex ring_mutex;
4e638ae9
XY		 860 struct amdgpu_ring ring;
861 struct amdgpu_irq_src irq;
862};
863
97b2e202
AD		 864/*
865 * GPU scratch registers structures, functions & helpers
866 */
867struct amdgpu_scratch {
868 unsigned num_reg;
869 uint32_t reg_base;
50261151 870 uint32_t free_mask;
97b2e202
AD		 871};
872
873/*
874 * GFX configurations
875 */
e3fa7630
AD		 876#define AMDGPU_GFX_MAX_SE 4
877#define AMDGPU_GFX_MAX_SH_PER_SE 2
878
879struct amdgpu_rb_config {
880 uint32_t rb_backend_disable;
881 uint32_t user_rb_backend_disable;
882 uint32_t raster_config;
883 uint32_t raster_config_1;
884};
885
d0e95758
AG		 886struct gb_addr_config {
887 uint16_t pipe_interleave_size;
888 uint8_t num_pipes;
889 uint8_t max_compress_frags;
890 uint8_t num_banks;
891 uint8_t num_se;
892 uint8_t num_rb_per_se;
893};
894
ea323f88 895struct amdgpu_gfx_config {
97b2e202
AD		 896 unsigned max_shader_engines;
897 unsigned max_tile_pipes;
898 unsigned max_cu_per_sh;
899 unsigned max_sh_per_se;
900 unsigned max_backends_per_se;
901 unsigned max_texture_channel_caches;
902 unsigned max_gprs;
903 unsigned max_gs_threads;
904 unsigned max_hw_contexts;
905 unsigned sc_prim_fifo_size_frontend;
906 unsigned sc_prim_fifo_size_backend;
907 unsigned sc_hiz_tile_fifo_size;
908 unsigned sc_earlyz_tile_fifo_size;
909
910 unsigned num_tile_pipes;
911 unsigned backend_enable_mask;
912 unsigned mem_max_burst_length_bytes;
913 unsigned mem_row_size_in_kb;
914 unsigned shader_engine_tile_size;
915 unsigned num_gpus;
916 unsigned multi_gpu_tile_size;
917 unsigned mc_arb_ramcfg;
918 unsigned gb_addr_config;
8f8e00c1 919 unsigned num_rbs;
408bfe7c
JZ		 920 unsigned gs_vgt_table_depth;
921 unsigned gs_prim_buffer_depth;
97b2e202
AD		 922
923 uint32_t tile_mode_array[32];
924 uint32_t macrotile_mode_array[16];
e3fa7630 925
d0e95758 926 struct gb_addr_config gb_addr_config_fields;
e3fa7630 927 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 928
929 /* gfx configure feature */
930 uint32_t double_offchip_lds_buf;
97b2e202
AD		 931};
932
7dae69a2 933struct amdgpu_cu_info {
51fd0370 934 uint32_t max_waves_per_simd;
408bfe7c 935 uint32_t wave_front_size;
51fd0370
HZ		 936 uint32_t max_scratch_slots_per_cu;
937 uint32_t lds_size;
dbfe85ea
FC		 938
939 /* total active CU number */
940 uint32_t number;
941 uint32_t ao_cu_mask;
942 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 943 uint32_t bitmap[4][4];
944};
945
b95e31fd
AD		 946struct amdgpu_gfx_funcs {
947 /* get the gpu clock counter */
948 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 949 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 950 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 951 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
952 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 953};
954
bce23e00
AD		 955struct amdgpu_ngg_buf {
956 struct amdgpu_bo *bo;
957 uint64_t gpu_addr;
958 uint32_t size;
959 uint32_t bo_size;
960};
961
962enum {
af8baf15
GR		 963 NGG_PRIM = 0,
964 NGG_POS,
965 NGG_CNTL,
966 NGG_PARAM,
bce23e00
AD		 967 NGG_BUF_MAX
968};
969
970struct amdgpu_ngg {
971 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
972 uint32_t gds_reserve_addr;
973 uint32_t gds_reserve_size;
974 bool init;
975};
976
97b2e202
AD		 977struct amdgpu_gfx {
978 struct mutex gpu_clock_mutex;
ea323f88 979 struct amdgpu_gfx_config config;
97b2e202
AD		 980 struct amdgpu_rlc rlc;
981 struct amdgpu_mec mec;
4e638ae9 982 struct amdgpu_kiq kiq;
97b2e202
AD		 983 struct amdgpu_scratch scratch;
984 const struct firmware *me_fw; /* ME firmware */
985 uint32_t me_fw_version;
986 const struct firmware *pfp_fw; /* PFP firmware */
987 uint32_t pfp_fw_version;
988 const struct firmware *ce_fw; /* CE firmware */
989 uint32_t ce_fw_version;
990 const struct firmware *rlc_fw; /* RLC firmware */
991 uint32_t rlc_fw_version;
992 const struct firmware *mec_fw; /* MEC firmware */
993 uint32_t mec_fw_version;
994 const struct firmware *mec2_fw; /* MEC2 firmware */
995 uint32_t mec2_fw_version;
02558a00
KW		 996 uint32_t me_feature_version;
997 uint32_t ce_feature_version;
998 uint32_t pfp_feature_version;
351643d7
JZ		 999 uint32_t rlc_feature_version;
1000 uint32_t mec_feature_version;
1001 uint32_t mec2_feature_version;
97b2e202
AD		 1002 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1003 unsigned num_gfx_rings;
1004 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1005 unsigned num_compute_rings;
1006 struct amdgpu_irq_src eop_irq;
1007 struct amdgpu_irq_src priv_reg_irq;
1008 struct amdgpu_irq_src priv_inst_irq;
1009 /* gfx status */
7dae69a2 1010 uint32_t gfx_current_status;
a101a899 1011 /* ce ram size*/
7dae69a2
AD		 1012 unsigned ce_ram_size;
1013 struct amdgpu_cu_info cu_info;
b95e31fd 1014 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1015
1016 /* reset mask */
1017 uint32_t grbm_soft_reset;
1018 uint32_t srbm_soft_reset;
223049cd 1019 bool in_reset;
b4e40676
DP		 1020 /* s3/s4 mask */
1021 bool in_suspend;
bce23e00
AD		 1022 /* NGG */
1023 struct amdgpu_ngg ngg;
97b2e202
AD		 1024};
1025
b07c60c0 1026int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1027 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1028void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1029 struct dma_fence *f);
b07c60c0 1030int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1031 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1032 struct dma_fence **f);
97b2e202
AD		 1033int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1034void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1035int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1036
1037/*
1038 * CS.
1039 */
1040struct amdgpu_cs_chunk {
1041 uint32_t chunk_id;
1042 uint32_t length_dw;
758ac17f 1043 void *kdata;
97b2e202
AD		 1044};
1045
1046struct amdgpu_cs_parser {
1047 struct amdgpu_device *adev;
1048 struct drm_file *filp;
3cb485f3 1049 struct amdgpu_ctx *ctx;
c3cca41e 1050
97b2e202
AD		 1051 /* chunks */
1052 unsigned nchunks;
1053 struct amdgpu_cs_chunk *chunks;
97b2e202 1054
50838c8c
CK		 1055 /* scheduler job object */
1056 struct amdgpu_job *job;
97b2e202 1057
c3cca41e
CK		 1058 /* buffer objects */
1059 struct ww_acquire_ctx ticket;
1060 struct amdgpu_bo_list *bo_list;
3fe89771 1061 struct amdgpu_mn *mn;
c3cca41e
CK		 1062 struct amdgpu_bo_list_entry vm_pd;
1063 struct list_head validated;
f54d1867 1064 struct dma_fence *fence;
c3cca41e 1065 uint64_t bytes_moved_threshold;
00f06b24 1066 uint64_t bytes_moved_vis_threshold;
c3cca41e 1067 uint64_t bytes_moved;
00f06b24 1068 uint64_t bytes_moved_vis;
662bfa61 1069 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1070
1071 /* user fence */
91acbeb6 1072 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1073
1074 unsigned num_post_dep_syncobjs;
1075 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1076};
1077
753ad49c
ML		 1078#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1079#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1080#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1081
bb977d37
CZ		 1082struct amdgpu_job {
1083 struct amd_sched_job base;
1084 struct amdgpu_device *adev;
edf600da 1085 struct amdgpu_vm *vm;
b07c60c0 1086 struct amdgpu_ring *ring;
e86f9cee 1087 struct amdgpu_sync sync;
a340c7bc 1088 struct amdgpu_sync dep_sync;
df83d1eb 1089 struct amdgpu_sync sched_sync;
bb977d37 1090 struct amdgpu_ib *ibs;
f54d1867 1091 struct dma_fence *fence; /* the hw fence */
753ad49c 1092 uint32_t preamble_status;
bb977d37 1093 uint32_t num_ibs;
e2840221 1094 void *owner;
3aecd24c 1095 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1096 bool vm_needs_flush;
d88bf583
CK		 1097 unsigned vm_id;
1098 uint64_t vm_pd_addr;
1099 uint32_t gds_base, gds_size;
1100 uint32_t gws_base, gws_size;
1101 uint32_t oa_base, oa_size;
758ac17f
CK		 1102
1103 /* user fence handling */
b5f5acbc 1104 uint64_t uf_addr;
758ac17f
CK		 1105 uint64_t uf_sequence;
1106
bb977d37 1107};
a6db8a33
JZ		 1108#define to_amdgpu_job(sched_job) \
1109 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1110
7270f839
CK		 1111static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1112 uint32_t ib_idx, int idx)
97b2e202 1113{
50838c8c 1114 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1115}
1116
7270f839
CK		 1117static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1118 uint32_t ib_idx, int idx,
1119 uint32_t value)
1120{
50838c8c 1121 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1122}
1123
97b2e202
AD		 1124/*
1125 * Writeback
1126 */
1127#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1128
1129struct amdgpu_wb {
1130 struct amdgpu_bo *wb_obj;
1131 volatile uint32_t *wb;
1132 uint64_t gpu_addr;
1133 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1134 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1135};
1136
1137int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1138void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1139
d0dd7f0c
AD		 1140void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1141
97b2e202
AD		 1142/*
1143 * SDMA
1144 */
c113ea1c 1145struct amdgpu_sdma_instance {
97b2e202
AD		 1146 /* SDMA firmware */
1147 const struct firmware *fw;
1148 uint32_t fw_version;
cfa2104f 1149 uint32_t feature_version;
97b2e202
AD		 1150
1151 struct amdgpu_ring ring;
18111de0 1152 bool burst_nop;
97b2e202
AD		 1153};
1154
c113ea1c
AD		 1155struct amdgpu_sdma {
1156 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1157#ifdef CONFIG_DRM_AMDGPU_SI
1158 //SI DMA has a difference trap irq number for the second engine
1159 struct amdgpu_irq_src trap_irq_1;
1160#endif
c113ea1c
AD		 1161 struct amdgpu_irq_src trap_irq;
1162 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1163 int num_instances;
e702a680 1164 uint32_t srbm_soft_reset;
c113ea1c
AD		 1165};
1166
97b2e202
AD		 1167/*
1168 * Firmware
1169 */
e635ee07
HR		 1170enum amdgpu_firmware_load_type {
1171 AMDGPU_FW_LOAD_DIRECT = 0,
1172 AMDGPU_FW_LOAD_SMU,
1173 AMDGPU_FW_LOAD_PSP,
1174};
1175
97b2e202
AD		 1176struct amdgpu_firmware {
1177 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1178 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1179 struct amdgpu_bo *fw_buf;
1180 unsigned int fw_size;
2445b227 1181 unsigned int max_ucodes;
0e5ca0d1
HR		 1182 /* firmwares are loaded by psp instead of smu from vega10 */
1183 const struct amdgpu_psp_funcs *funcs;
1184 struct amdgpu_bo *rbuf;
1185 struct mutex mutex;
ab4fe3e1
HR		 1186
1187 /* gpu info firmware data pointer */
1188 const struct firmware *gpu_info_fw;
97b2e202
AD		 1189};
1190
1191/*
1192 * Benchmarking
1193 */
1194void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1195
1196
1197/*
1198 * Testing
1199 */
1200void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202
AD		 1201
1202/*
1203 * MMU Notifier
1204 */
1205#if defined(CONFIG_MMU_NOTIFIER)
3fe89771 1206struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev);
97b2e202
AD		 1207int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1208void amdgpu_mn_unregister(struct amdgpu_bo *bo);
3fe89771
CK		 1209void amdgpu_mn_lock(struct amdgpu_mn *mn);
1210void amdgpu_mn_unlock(struct amdgpu_mn *mn);
97b2e202 1211#else
3fe89771
CK		 1212static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {}
1213static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {}
1214static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
1215{
1216 return NULL;
1217}
1d1106b0 1218static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1219{
1220 return -ENODEV;
1221}
1d1106b0 1222static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1223#endif
1224
1225/*
1226 * Debugfs
1227 */
1228struct amdgpu_debugfs {
06ab6832 1229 const struct drm_info_list *files;
97b2e202
AD		 1230 unsigned num_files;
1231};
1232
1233int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1234 const struct drm_info_list *files,
97b2e202
AD		 1235 unsigned nfiles);
1236int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1237
1238#if defined(CONFIG_DEBUG_FS)
1239int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1240#endif
1241
50ab2533
HR		 1242int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1243
97b2e202
AD		 1244/*
1245 * amdgpu smumgr functions
1246 */
1247struct amdgpu_smumgr_funcs {
1248 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1249 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1250 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1251};
1252
1253/*
1254 * amdgpu smumgr
1255 */
1256struct amdgpu_smumgr {
1257 struct amdgpu_bo *toc_buf;
1258 struct amdgpu_bo *smu_buf;
1259 /* asic priv smu data */
1260 void *priv;
1261 spinlock_t smu_lock;
1262 /* smumgr functions */
1263 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1264 /* ucode loading complete flag */
1265 uint32_t fw_flags;
1266};
1267
1268/*
1269 * ASIC specific register table accessible by UMD
1270 */
1271struct amdgpu_allowed_register_entry {
1272 uint32_t reg_offset;
97b2e202
AD		 1273 bool grbm_indexed;
1274};
1275
97b2e202
AD		 1276/*
1277 * ASIC specific functions.
1278 */
1279struct amdgpu_asic_funcs {
1280 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1281 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1282 u8 *bios, u32 length_bytes);
97b2e202
AD		 1283 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1284 u32 sh_num, u32 reg_offset, u32 *value);
1285 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1286 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1287 /* get the reference clock */
1288 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1289 /* MM block clocks */
1290 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1291 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1292 /* static power management */
1293 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1294 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1295 /* get config memsize register */
1296 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1297};
1298
1299/*
1300 * IOCTL.
1301 */
1302int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1303 struct drm_file *filp);
1304int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1305 struct drm_file *filp);
1306
1307int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1308 struct drm_file *filp);
1309int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1310 struct drm_file *filp);
1311int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1312 struct drm_file *filp);
1313int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1314 struct drm_file *filp);
1315int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *filp);
1317int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1318 struct drm_file *filp);
1319int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1320int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1321int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
97b2e202
AD		 1323
1324int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1325 struct drm_file *filp);
1326
1327/* VRAM scratch page for HDP bug, default vram page */
1328struct amdgpu_vram_scratch {
1329 struct amdgpu_bo *robj;
1330 volatile uint32_t *ptr;
1331 u64 gpu_addr;
1332};
1333
1334/*
1335 * ACPI
1336 */
1337struct amdgpu_atif_notification_cfg {
1338 bool enabled;
1339 int command_code;
1340};
1341
1342struct amdgpu_atif_notifications {
1343 bool display_switch;
1344 bool expansion_mode_change;
1345 bool thermal_state;
1346 bool forced_power_state;
1347 bool system_power_state;
1348 bool display_conf_change;
1349 bool px_gfx_switch;
1350 bool brightness_change;
1351 bool dgpu_display_event;
1352};
1353
1354struct amdgpu_atif_functions {
1355 bool system_params;
1356 bool sbios_requests;
1357 bool select_active_disp;
1358 bool lid_state;
1359 bool get_tv_standard;
1360 bool set_tv_standard;
1361 bool get_panel_expansion_mode;
1362 bool set_panel_expansion_mode;
1363 bool temperature_change;
1364 bool graphics_device_types;
1365};
1366
1367struct amdgpu_atif {
1368 struct amdgpu_atif_notifications notifications;
1369 struct amdgpu_atif_functions functions;
1370 struct amdgpu_atif_notification_cfg notification_cfg;
1371 struct amdgpu_encoder *encoder_for_bl;
1372};
1373
1374struct amdgpu_atcs_functions {
1375 bool get_ext_state;
1376 bool pcie_perf_req;
1377 bool pcie_dev_rdy;
1378 bool pcie_bus_width;
1379};
1380
1381struct amdgpu_atcs {
1382 struct amdgpu_atcs_functions functions;
1383};
1384
d03846af
CZ		 1385/*
1386 * CGS
1387 */
110e6f26
DA		 1388struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1389void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1390
97b2e202
AD		 1391/*
1392 * Core structure, functions and helpers.
1393 */
1394typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1395typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1396
1397typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1398typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1399
0c49e0b8 1400#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1401struct amdgpu_device {
1402 struct device *dev;
1403 struct drm_device *ddev;
1404 struct pci_dev *pdev;
97b2e202 1405
a8fe58ce
MB		 1406#ifdef CONFIG_DRM_AMD_ACP
1407 struct amdgpu_acp acp;
1408#endif
1409
97b2e202 1410 /* ASIC */
2f7d10b3 1411 enum amd_asic_type asic_type;
97b2e202
AD		 1412 uint32_t family;
1413 uint32_t rev_id;
1414 uint32_t external_rev_id;
1415 unsigned long flags;
1416 int usec_timeout;
1417 const struct amdgpu_asic_funcs *asic_funcs;
1418 bool shutdown;
97b2e202
AD		 1419 bool need_dma32;
1420 bool accel_working;
edf600da 1421 struct work_struct reset_work;
97b2e202
AD		 1422 struct notifier_block acpi_nb;
1423 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1424 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1425 unsigned debugfs_count;
97b2e202 1426#if defined(CONFIG_DEBUG_FS)
adcec288 1427 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1428#endif
1429 struct amdgpu_atif atif;
1430 struct amdgpu_atcs atcs;
1431 struct mutex srbm_mutex;
1432 /* GRBM index mutex. Protects concurrent access to GRBM index */
1433 struct mutex grbm_idx_mutex;
1434 struct dev_pm_domain vga_pm_domain;
1435 bool have_disp_power_ref;
1436
1437 /* BIOS */
0cdd5005 1438 bool is_atom_fw;
97b2e202 1439 uint8_t *bios;
a9f5db9c 1440 uint32_t bios_size;
5af2c10d 1441 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1442 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1443 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1444
1445 /* Register/doorbell mmio */
1446 resource_size_t rmmio_base;
1447 resource_size_t rmmio_size;
1448 void __iomem *rmmio;
1449 /* protects concurrent MM_INDEX/DATA based register access */
1450 spinlock_t mmio_idx_lock;
1451 /* protects concurrent SMC based register access */
1452 spinlock_t smc_idx_lock;
1453 amdgpu_rreg_t smc_rreg;
1454 amdgpu_wreg_t smc_wreg;
1455 /* protects concurrent PCIE register access */
1456 spinlock_t pcie_idx_lock;
1457 amdgpu_rreg_t pcie_rreg;
1458 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1459 amdgpu_rreg_t pciep_rreg;
1460 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1461 /* protects concurrent UVD register access */
1462 spinlock_t uvd_ctx_idx_lock;
1463 amdgpu_rreg_t uvd_ctx_rreg;
1464 amdgpu_wreg_t uvd_ctx_wreg;
1465 /* protects concurrent DIDT register access */
1466 spinlock_t didt_idx_lock;
1467 amdgpu_rreg_t didt_rreg;
1468 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1469 /* protects concurrent gc_cac register access */
1470 spinlock_t gc_cac_idx_lock;
1471 amdgpu_rreg_t gc_cac_rreg;
1472 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1473 /* protects concurrent se_cac register access */
1474 spinlock_t se_cac_idx_lock;
1475 amdgpu_rreg_t se_cac_rreg;
1476 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1477 /* protects concurrent ENDPOINT (audio) register access */
1478 spinlock_t audio_endpt_idx_lock;
1479 amdgpu_block_rreg_t audio_endpt_rreg;
1480 amdgpu_block_wreg_t audio_endpt_wreg;
1481 void __iomem *rio_mem;
1482 resource_size_t rio_mem_size;
1483 struct amdgpu_doorbell doorbell;
1484
1485 /* clock/pll info */
1486 struct amdgpu_clock clock;
1487
1488 /* MC */
1489 struct amdgpu_mc mc;
1490 struct amdgpu_gart gart;
1491 struct amdgpu_dummy_page dummy_page;
1492 struct amdgpu_vm_manager vm_manager;
e60f8db5 1493 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1494
1495 /* memory management */
1496 struct amdgpu_mman mman;
97b2e202
AD		 1497 struct amdgpu_vram_scratch vram_scratch;
1498 struct amdgpu_wb wb;
97b2e202 1499 atomic64_t num_bytes_moved;
dbd5ed60 1500 atomic64_t num_evictions;
68e2c5ff 1501 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1502 atomic_t gpu_reset_counter;
f1892138 1503 atomic_t vram_lost_counter;
97b2e202 1504
95844d20
MO		 1505 /* data for buffer migration throttling */
1506 struct {
1507 spinlock_t lock;
1508 s64 last_update_us;
1509 s64 accum_us; /* accumulated microseconds */
00f06b24 1510 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1511 u32 log2_max_MBps;
1512 } mm_stats;
1513
97b2e202 1514 /* display */
9accf2fd 1515 bool enable_virtual_display;
97b2e202
AD		 1516 struct amdgpu_mode_info mode_info;
1517 struct work_struct hotplug_work;
1518 struct amdgpu_irq_src crtc_irq;
1519 struct amdgpu_irq_src pageflip_irq;
1520 struct amdgpu_irq_src hpd_irq;
1521
1522 /* rings */
76bf0db5 1523 u64 fence_context;
97b2e202
AD		 1524 unsigned num_rings;
1525 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1526 bool ib_pool_ready;
1527 struct amdgpu_sa_manager ring_tmp_bo;
1528
1529 /* interrupts */
1530 struct amdgpu_irq irq;
1531
1f7371b2
AD		 1532 /* powerplay */
1533 struct amd_powerplay powerplay;
e61710c5 1534 bool pp_enabled;
f3898ea1 1535 bool pp_force_state_enabled;
1f7371b2 1536
97b2e202
AD		 1537 /* dpm */
1538 struct amdgpu_pm pm;
1539 u32 cg_flags;
1540 u32 pg_flags;
1541
1542 /* amdgpu smumgr */
1543 struct amdgpu_smumgr smu;
1544
1545 /* gfx */
1546 struct amdgpu_gfx gfx;
1547
1548 /* sdma */
c113ea1c 1549 struct amdgpu_sdma sdma;
97b2e202 1550
95d0906f
LL		 1551 union {
1552 struct {
1553 /* uvd */
1554 struct amdgpu_uvd uvd;
1555
1556 /* vce */
1557 struct amdgpu_vce vce;
1558 };
97b2e202 1559
95d0906f
LL		 1560 /* vcn */
1561 struct amdgpu_vcn vcn;
1562 };
97b2e202
AD		 1563
1564 /* firmwares */
1565 struct amdgpu_firmware firmware;
1566
0e5ca0d1
HR		 1567 /* PSP */
1568 struct psp_context psp;
1569
97b2e202
AD		 1570 /* GDS */
1571 struct amdgpu_gds gds;
1572
a1255107 1573 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1574 int num_ip_blocks;
97b2e202
AD		 1575 struct mutex mn_lock;
1576 DECLARE_HASHTABLE(mn_hash, 7);
1577
1578 /* tracking pinned memory */
1579 u64 vram_pin_size;
e131b914 1580 u64 invisible_pin_size;
97b2e202 1581 u64 gart_pin_size;
130e0371
OG		 1582
1583 /* amdkfd interface */
1584 struct kfd_dev *kfd;
23ca0e4e 1585
2dc80b00
S		 1586 /* delayed work_func for deferring clockgating during resume */
1587 struct delayed_work late_init_work;
1588
5a5099cb 1589 struct amdgpu_virt virt;
0c4e7fa5
CZ		 1590
1591 /* link all shadow bo */
1592 struct list_head shadow_list;
1593 struct mutex shadow_list_lock;
5c1354bd
CZ		 1594 /* link all gtt */
1595 spinlock_t gtt_list_lock;
1596 struct list_head gtt_list;
795f2813
AR		 1597 /* keep an lru list of rings by HW IP */
1598 struct list_head ring_lru_list;
1599 spinlock_t ring_lru_list_lock;
5c1354bd 1600
c836fec5
JQ		 1601 /* record hw reset is performed */
1602 bool has_hw_reset;
0c49e0b8 1603 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1604
47ed4e1c
KW		 1605 /* record last mm index being written through WREG32*/
1606 unsigned long last_mm_index;
97b2e202
AD		 1607};
1608
a7d64de6
CK		 1609static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1610{
1611 return container_of(bdev, struct amdgpu_device, mman.bdev);
1612}
1613
97b2e202
AD		 1614int amdgpu_device_init(struct amdgpu_device *adev,
1615 struct drm_device *ddev,
1616 struct pci_dev *pdev,
1617 uint32_t flags);
1618void amdgpu_device_fini(struct amdgpu_device *adev);
1619int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1620
1621uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1622 uint32_t acc_flags);
97b2e202 1623void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1624 uint32_t acc_flags);
97b2e202
AD		 1625u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1626void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1627
1628u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1629void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1630u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1631void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1632
97b2e202
AD		 1633/*
1634 * Registers read & write functions.
1635 */
15d72fd7
ML		 1636
1637#define AMDGPU_REGS_IDX (1<<0)
1638#define AMDGPU_REGS_NO_KIQ (1<<1)
1639
1640#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1641#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1642
1643#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1644#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1645#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1646#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1647#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1648#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1649#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1650#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1651#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1652#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1653#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1654#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1655#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1656#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1657#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1658#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1659#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1660#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1661#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1662#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1663#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1664#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1665#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1666#define WREG32_P(reg, val, mask) \
1667 do { \
1668 uint32_t tmp_ = RREG32(reg); \
1669 tmp_ &= (mask); \
1670 tmp_ |= ((val) & ~(mask)); \
1671 WREG32(reg, tmp_); \
1672 } while (0)
1673#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1674#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1675#define WREG32_PLL_P(reg, val, mask) \
1676 do { \
1677 uint32_t tmp_ = RREG32_PLL(reg); \
1678 tmp_ &= (mask); \
1679 tmp_ |= ((val) & ~(mask)); \
1680 WREG32_PLL(reg, tmp_); \
1681 } while (0)
1682#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1683#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1684#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1685
1686#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1687#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1688#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1689#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1690
1691#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1692#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1693
1694#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1695 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1696 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1697
1698#define REG_GET_FIELD(value, reg, field) \
1699 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1700
1701#define WREG32_FIELD(reg, field, val) \
1702 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1703
ccaf3574
TSD		 1704#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1705 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1706
97b2e202
AD		 1707/*
1708 * BIOS helpers.
1709 */
1710#define RBIOS8(i) (adev->bios[i])
1711#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1712#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1713
c113ea1c
AD		 1714static inline struct amdgpu_sdma_instance *
1715amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1716{
1717 struct amdgpu_device *adev = ring->adev;
1718 int i;
1719
c113ea1c
AD		 1720 for (i = 0; i < adev->sdma.num_instances; i++)
1721 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1722 break;
1723
1724 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1725 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1726 else
1727 return NULL;
1728}
1729
97b2e202
AD		 1730/*
1731 * ASICs macro.
1732 */
1733#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1734#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1735#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1736#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1737#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1738#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1739#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1740#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1741#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1742#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1743#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1744#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1745#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1746#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1747#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1748#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1749#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1750#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1751#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1752#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1753#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1754#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1755#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1756#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1757#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1758#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1759#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1760#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1761#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1762#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1763#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1764#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1765#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1766#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1767#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1768#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1769#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1770#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1771#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1772#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 1773#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1774#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1775#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1776#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1777#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1778#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1779#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1780#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1781#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1782#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1783#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1784#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1785#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1786#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1787#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1788#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1789#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1790#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1791#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1792#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1793#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1794
1795/* Common functions */
1796int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1797bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1798void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1799bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1800void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1801
00f06b24
JB		 1802void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1803 u64 num_vis_bytes);
765e7fbf 1804void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1805bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 1806int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
a216ab09 1807void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
1b0c0f9d 1808void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm);
97b2e202
AD		 1809int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1810 uint32_t flags);
1811bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 1812struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 1813bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1814 unsigned long end);
2f568dbd
CK		 1815bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1816 int *last_invalidated);
ca666a3c 1817bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
97b2e202 1818bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
6b777607 1819uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
97b2e202
AD		 1820 struct ttm_mem_reg *mem);
1821void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1822void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
97b2e202 1823void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1824int amdgpu_ttm_init(struct amdgpu_device *adev);
1825void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1826void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1827 const u32 *registers,
1828 const u32 array_size);
1829
1830bool amdgpu_device_is_px(struct drm_device *dev);
1831/* atpx handler */
1832#if defined(CONFIG_VGA_SWITCHEROO)
1833void amdgpu_register_atpx_handler(void);
1834void amdgpu_unregister_atpx_handler(void);
a78fe133 1835bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1836bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1837bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1838bool amdgpu_has_atpx(void);
97b2e202
AD		 1839#else
1840static inline void amdgpu_register_atpx_handler(void) {}
1841static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1842static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1843static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1844static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1845static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1846#endif
1847
1848/*
1849 * KMS
1850 */
1851extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1852extern const int amdgpu_max_kms_ioctl;
97b2e202 1853
f1892138
CZ		 1854bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1855 struct amdgpu_fpriv *fpriv);
97b2e202 1856int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1857void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1858void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1859int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1860void amdgpu_driver_postclose_kms(struct drm_device *dev,
1861 struct drm_file *file_priv);
faefba95 1862int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1863int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1864int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1865u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1866int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1867void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1868long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1869 unsigned long arg);
1870
97b2e202
AD		 1871/*
1872 * functions used by amdgpu_encoder.c
1873 */
1874struct amdgpu_afmt_acr {
1875 u32 clock;
1876
1877 int n_32khz;
1878 int cts_32khz;
1879
1880 int n_44_1khz;
1881 int cts_44_1khz;
1882
1883 int n_48khz;
1884 int cts_48khz;
1885
1886};
1887
1888struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1889
1890/* amdgpu_acpi.c */
1891#if defined(CONFIG_ACPI)
1892int amdgpu_acpi_init(struct amdgpu_device *adev);
1893void amdgpu_acpi_fini(struct amdgpu_device *adev);
1894bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1895int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1896 u8 perf_req, bool advertise);
1897int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1898#else
1899static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1900static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1901#endif
1902
1903struct amdgpu_bo_va_mapping *
1904amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1905 uint64_t addr, struct amdgpu_bo **bo);
c855e250 1906int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
97b2e202
AD		 1907
1908#include "amdgpu_object.h"
97b2e202 1909#endif
Linux 6.x block layer and io_uring tree(s)