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drm/amdgpu: stop waiting on UVD messages before mapping them
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
97b2e202 88
4b559c90 89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
97b2e202
AD		 98/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
36f523a7
JZ		 104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
97b2e202
AD		 107/* hardcode that limit for now */
108#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
109
110/* hard reset data */
111#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
112
113/* reset flags */
114#define AMDGPU_RESET_GFX (1 << 0)
115#define AMDGPU_RESET_COMPUTE (1 << 1)
116#define AMDGPU_RESET_DMA (1 << 2)
117#define AMDGPU_RESET_CP (1 << 3)
118#define AMDGPU_RESET_GRBM (1 << 4)
119#define AMDGPU_RESET_DMA1 (1 << 5)
120#define AMDGPU_RESET_RLC (1 << 6)
121#define AMDGPU_RESET_SEM (1 << 7)
122#define AMDGPU_RESET_IH (1 << 8)
123#define AMDGPU_RESET_VMC (1 << 9)
124#define AMDGPU_RESET_MC (1 << 10)
125#define AMDGPU_RESET_DISPLAY (1 << 11)
126#define AMDGPU_RESET_UVD (1 << 12)
127#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14)
129
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
182struct amdgpu_device;
183struct amdgpu_fence;
184struct amdgpu_ib;
185struct amdgpu_vm;
186struct amdgpu_ring;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
97b2e202
AD		 191
192enum amdgpu_cp_irq {
193 AMDGPU_CP_IRQ_GFX_EOP = 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202
203 AMDGPU_CP_IRQ_LAST
204};
205
206enum amdgpu_sdma_irq {
207 AMDGPU_SDMA_IRQ_TRAP0 = 0,
208 AMDGPU_SDMA_IRQ_TRAP1,
209
210 AMDGPU_SDMA_IRQ_LAST
211};
212
213enum amdgpu_thermal_irq {
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
216
217 AMDGPU_THERMAL_IRQ_LAST
218};
219
97b2e202 220int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_clockgating_state state);
97b2e202 223int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_powergating_state state);
97b2e202
AD		 226
227struct amdgpu_ip_block_version {
5fc3aeeb 228 enum amd_ip_block_type type;
97b2e202
AD		 229 u32 major;
230 u32 minor;
231 u32 rev;
5fc3aeeb 232 const struct amd_ip_funcs *funcs;
97b2e202
AD		 233};
234
235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 236 enum amd_ip_block_type type,
97b2e202
AD		 237 u32 major, u32 minor);
238
239const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
240 struct amdgpu_device *adev,
5fc3aeeb 241 enum amd_ip_block_type type);
97b2e202
AD		 242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
c7ae72c0 252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
6e7a3840 267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 284 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 285 uint64_t addr, unsigned count,
286 uint32_t incr, uint32_t flags);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
97b2e202
AD		 292};
293
294/* provided by the gmc block */
295struct amdgpu_gart_funcs {
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
298 uint32_t vmid);
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde)(struct amdgpu_device *adev,
301 void *cpu_pt_addr, /* cpu addr of page table */
302 uint32_t gpu_page_idx, /* pte/pde to update */
303 uint64_t addr, /* addr to write into pte/pde */
304 uint32_t flags); /* access flags */
305};
306
307/* provided by the ih block */
308struct amdgpu_ih_funcs {
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr)(struct amdgpu_device *adev);
311 void (*decode_iv)(struct amdgpu_device *adev,
312 struct amdgpu_iv_entry *entry);
313 void (*set_rptr)(struct amdgpu_device *adev);
314};
315
316/* provided by hw blocks that expose a ring buffer for commands */
317struct amdgpu_ring_funcs {
318 /* ring read/write ptr handling */
319 u32 (*get_rptr)(struct amdgpu_ring *ring);
320 u32 (*get_wptr)(struct amdgpu_ring *ring);
321 void (*set_wptr)(struct amdgpu_ring *ring);
322 /* validating and patching of IBs */
323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
324 /* command emit functions */
325 void (*emit_ib)(struct amdgpu_ring *ring,
326 struct amdgpu_ib *ib);
327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 328 uint64_t seq, unsigned flags);
b8c7b39e 329 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 330 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
331 uint64_t pd_addr);
d2edb07b 332 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 333 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 334 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
335 uint32_t gds_base, uint32_t gds_size,
336 uint32_t gws_base, uint32_t gws_size,
337 uint32_t oa_base, uint32_t oa_size);
338 /* testing functions */
339 int (*test_ring)(struct amdgpu_ring *ring);
340 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 341 /* insert NOP packets */
342 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 343 /* pad the indirect buffer to the necessary number of dw */
344 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202
AD		 345};
346
347/*
348 * BIOS.
349 */
350bool amdgpu_get_bios(struct amdgpu_device *adev);
351bool amdgpu_read_bios(struct amdgpu_device *adev);
352
353/*
354 * Dummy page
355 */
356struct amdgpu_dummy_page {
357 struct page *page;
358 dma_addr_t addr;
359};
360int amdgpu_dummy_page_init(struct amdgpu_device *adev);
361void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
362
363
364/*
365 * Clocks
366 */
367
368#define AMDGPU_MAX_PPLL 3
369
370struct amdgpu_clock {
371 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
372 struct amdgpu_pll spll;
373 struct amdgpu_pll mpll;
374 /* 10 Khz units */
375 uint32_t default_mclk;
376 uint32_t default_sclk;
377 uint32_t default_dispclk;
378 uint32_t current_dispclk;
379 uint32_t dp_extclk;
380 uint32_t max_pixel_clock;
381};
382
383/*
384 * Fences.
385 */
386struct amdgpu_fence_driver {
97b2e202
AD		 387 uint64_t gpu_addr;
388 volatile uint32_t *cpu_addr;
389 /* sync_seq is protected by ring emission lock */
5907a0d8 390 uint64_t sync_seq;
97b2e202
AD		 391 atomic64_t last_seq;
392 bool initialized;
97b2e202
AD		 393 struct amdgpu_irq_src *irq_src;
394 unsigned irq_type;
c2776afe 395 struct timer_list fallback_timer;
7f06c236 396 wait_queue_head_t fence_queue;
97b2e202
AD		 397};
398
399/* some special values for the owner field */
400#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
401#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 402
890ee23f
CZ		 403#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
404#define AMDGPU_FENCE_FLAG_INT (1 << 1)
405
97b2e202
AD		 406struct amdgpu_fence {
407 struct fence base;
4cef9267 408
97b2e202
AD		 409 /* RB, DMA, etc. */
410 struct amdgpu_ring *ring;
411 uint64_t seq;
412
97b2e202
AD		 413 wait_queue_t fence_wake;
414};
415
416struct amdgpu_user_fence {
417 /* write-back bo */
418 struct amdgpu_bo *bo;
419 /* write-back address offset to bo start */
420 uint32_t offset;
421};
422
423int amdgpu_fence_driver_init(struct amdgpu_device *adev);
424void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
425void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
426
4f839a24 427int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 428int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
429 struct amdgpu_irq_src *irq_src,
430 unsigned irq_type);
5ceb54c6
AD		 431void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
432void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 433int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202
AD		 434void amdgpu_fence_process(struct amdgpu_ring *ring);
435int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
436int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
437unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
438
97b2e202
AD		 439/*
440 * TTM.
441 */
442struct amdgpu_mman {
443 struct ttm_bo_global_ref bo_global_ref;
444 struct drm_global_reference mem_global_ref;
445 struct ttm_bo_device bdev;
446 bool mem_global_referenced;
447 bool initialized;
448
449#if defined(CONFIG_DEBUG_FS)
450 struct dentry *vram;
451 struct dentry *gtt;
452#endif
453
454 /* buffer handling */
455 const struct amdgpu_buffer_funcs *buffer_funcs;
456 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 457 /* Scheduler entity for buffer moves */
458 struct amd_sched_entity entity;
97b2e202
AD		 459};
460
461int amdgpu_copy_buffer(struct amdgpu_ring *ring,
462 uint64_t src_offset,
463 uint64_t dst_offset,
464 uint32_t byte_count,
465 struct reservation_object *resv,
c7ae72c0 466 struct fence **fence);
97b2e202
AD		 467int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
468
469struct amdgpu_bo_list_entry {
470 struct amdgpu_bo *robj;
471 struct ttm_validate_buffer tv;
472 struct amdgpu_bo_va *bo_va;
97b2e202 473 uint32_t priority;
2f568dbd
CK		 474 struct page **user_pages;
475 int user_invalidated;
97b2e202
AD		 476};
477
478struct amdgpu_bo_va_mapping {
479 struct list_head list;
480 struct interval_tree_node it;
481 uint64_t offset;
482 uint32_t flags;
483};
484
485/* bo virtual addresses in a specific vm */
486struct amdgpu_bo_va {
487 /* protected by bo being reserved */
488 struct list_head bo_list;
bb1e38a4 489 struct fence *last_pt_update;
97b2e202
AD		 490 unsigned ref_count;
491
7fc11959 492 /* protected by vm mutex and spinlock */
97b2e202
AD		 493 struct list_head vm_status;
494
7fc11959
CK		 495 /* mappings for this bo_va */
496 struct list_head invalids;
497 struct list_head valids;
498
97b2e202
AD		 499 /* constant after initialization */
500 struct amdgpu_vm *vm;
501 struct amdgpu_bo *bo;
502};
503
7e5a547f
CZ		 504#define AMDGPU_GEM_DOMAIN_MAX 0x3
505
97b2e202
AD		 506struct amdgpu_bo {
507 /* Protected by gem.mutex */
508 struct list_head list;
509 /* Protected by tbo.reserved */
1ea863fd
CK		 510 u32 prefered_domains;
511 u32 allowed_domains;
7e5a547f 512 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 513 struct ttm_placement placement;
514 struct ttm_buffer_object tbo;
515 struct ttm_bo_kmap_obj kmap;
516 u64 flags;
517 unsigned pin_count;
518 void *kptr;
519 u64 tiling_flags;
520 u64 metadata_flags;
521 void *metadata;
522 u32 metadata_size;
523 /* list of all virtual address to which this bo
524 * is associated to
525 */
526 struct list_head va;
527 /* Constant after initialization */
528 struct amdgpu_device *adev;
529 struct drm_gem_object gem_base;
82b9c55b 530 struct amdgpu_bo *parent;
97b2e202
AD		 531
532 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 533 struct amdgpu_mn *mn;
534 struct list_head mn_list;
535};
536#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
537
538void amdgpu_gem_object_free(struct drm_gem_object *obj);
539int amdgpu_gem_object_open(struct drm_gem_object *obj,
540 struct drm_file *file_priv);
541void amdgpu_gem_object_close(struct drm_gem_object *obj,
542 struct drm_file *file_priv);
543unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
544struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
545struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
546 struct dma_buf_attachment *attach,
547 struct sg_table *sg);
548struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
549 struct drm_gem_object *gobj,
550 int flags);
551int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
552void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
553struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
554void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
555void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
556int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
557
558/* sub-allocation manager, it has to be protected by another lock.
559 * By conception this is an helper for other part of the driver
560 * like the indirect buffer or semaphore, which both have their
561 * locking.
562 *
563 * Principe is simple, we keep a list of sub allocation in offset
564 * order (first entry has offset == 0, last entry has the highest
565 * offset).
566 *
567 * When allocating new object we first check if there is room at
568 * the end total_size - (last_object_offset + last_object_size) >=
569 * alloc_size. If so we allocate new object there.
570 *
571 * When there is not enough room at the end, we start waiting for
572 * each sub object until we reach object_offset+object_size >=
573 * alloc_size, this object then become the sub object we return.
574 *
575 * Alignment can't be bigger than page size.
576 *
577 * Hole are not considered for allocation to keep things simple.
578 * Assumption is that there won't be hole (all object on same
579 * alignment).
580 */
581struct amdgpu_sa_manager {
582 wait_queue_head_t wq;
583 struct amdgpu_bo *bo;
584 struct list_head *hole;
585 struct list_head flist[AMDGPU_MAX_RINGS];
586 struct list_head olist;
587 unsigned size;
588 uint64_t gpu_addr;
589 void *cpu_ptr;
590 uint32_t domain;
591 uint32_t align;
592};
593
594struct amdgpu_sa_bo;
595
596/* sub-allocation buffer */
597struct amdgpu_sa_bo {
598 struct list_head olist;
599 struct list_head flist;
600 struct amdgpu_sa_manager *manager;
601 unsigned soffset;
602 unsigned eoffset;
4ce9891e 603 struct fence *fence;
97b2e202
AD		 604};
605
606/*
607 * GEM objects.
608 */
418aa0c2 609void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 610int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
611 int alignment, u32 initial_domain,
612 u64 flags, bool kernel,
613 struct drm_gem_object **obj);
614
615int amdgpu_mode_dumb_create(struct drm_file *file_priv,
616 struct drm_device *dev,
617 struct drm_mode_create_dumb *args);
618int amdgpu_mode_dumb_mmap(struct drm_file *filp,
619 struct drm_device *dev,
620 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 621/*
622 * Synchronization
623 */
624struct amdgpu_sync {
f91b3a69 625 DECLARE_HASHTABLE(fences, 4);
3c62338c 626 struct fence *last_vm_update;
97b2e202
AD		 627};
628
629void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 630int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
631 struct fence *f);
97b2e202
AD		 632int amdgpu_sync_resv(struct amdgpu_device *adev,
633 struct amdgpu_sync *sync,
634 struct reservation_object *resv,
635 void *owner);
e61235db 636struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 637int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 638void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 639int amdgpu_sync_init(void);
640void amdgpu_sync_fini(void);
97b2e202
AD		 641
642/*
643 * GART structures, functions & helpers
644 */
645struct amdgpu_mc;
646
647#define AMDGPU_GPU_PAGE_SIZE 4096
648#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
649#define AMDGPU_GPU_PAGE_SHIFT 12
650#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
651
652struct amdgpu_gart {
653 dma_addr_t table_addr;
654 struct amdgpu_bo *robj;
655 void *ptr;
656 unsigned num_gpu_pages;
657 unsigned num_cpu_pages;
658 unsigned table_size;
659 struct page **pages;
660 dma_addr_t *pages_addr;
661 bool ready;
662 const struct amdgpu_gart_funcs *gart_funcs;
663};
664
665int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
666void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
667int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
668void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
669int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
670void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
671int amdgpu_gart_init(struct amdgpu_device *adev);
672void amdgpu_gart_fini(struct amdgpu_device *adev);
673void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
674 int pages);
675int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
676 int pages, struct page **pagelist,
677 dma_addr_t *dma_addr, uint32_t flags);
678
679/*
680 * GPU MC structures, functions & helpers
681 */
682struct amdgpu_mc {
683 resource_size_t aper_size;
684 resource_size_t aper_base;
685 resource_size_t agp_base;
686 /* for some chips with <= 32MB we need to lie
687 * about vram size near mc fb location */
688 u64 mc_vram_size;
689 u64 visible_vram_size;
690 u64 gtt_size;
691 u64 gtt_start;
692 u64 gtt_end;
693 u64 vram_start;
694 u64 vram_end;
695 unsigned vram_width;
696 u64 real_vram_size;
697 int vram_mtrr;
698 u64 gtt_base_align;
699 u64 mc_mask;
700 const struct firmware *fw; /* MC firmware */
701 uint32_t fw_version;
702 struct amdgpu_irq_src vm_fault;
81c59f54 703 uint32_t vram_type;
97b2e202
AD		 704};
705
706/*
707 * GPU doorbell structures, functions & helpers
708 */
709typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
710{
711 AMDGPU_DOORBELL_KIQ = 0x000,
712 AMDGPU_DOORBELL_HIQ = 0x001,
713 AMDGPU_DOORBELL_DIQ = 0x002,
714 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
715 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
716 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
717 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
718 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
719 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
720 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
721 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
722 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
723 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
724 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
725 AMDGPU_DOORBELL_IH = 0x1E8,
726 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
727 AMDGPU_DOORBELL_INVALID = 0xFFFF
728} AMDGPU_DOORBELL_ASSIGNMENT;
729
730struct amdgpu_doorbell {
731 /* doorbell mmio */
732 resource_size_t base;
733 resource_size_t size;
734 u32 __iomem *ptr;
735 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
736};
737
738void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
739 phys_addr_t *aperture_base,
740 size_t *aperture_size,
741 size_t *start_offset);
742
743/*
744 * IRQS.
745 */
746
747struct amdgpu_flip_work {
748 struct work_struct flip_work;
749 struct work_struct unpin_work;
750 struct amdgpu_device *adev;
751 int crtc_id;
752 uint64_t base;
753 struct drm_pending_vblank_event *event;
754 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 755 struct fence *excl;
756 unsigned shared_count;
757 struct fence **shared;
c3874b75 758 struct fence_cb cb;
97b2e202
AD		 759};
760
761
762/*
763 * CP & rings.
764 */
765
766struct amdgpu_ib {
767 struct amdgpu_sa_bo *sa_bo;
768 uint32_t length_dw;
769 uint64_t gpu_addr;
770 uint32_t *ptr;
364beb2c 771 struct fence *fence;
97b2e202
AD		 772 struct amdgpu_user_fence *user;
773 struct amdgpu_vm *vm;
4ff37a83
CK		 774 unsigned vm_id;
775 uint64_t vm_pd_addr;
3cb485f3 776 struct amdgpu_ctx *ctx;
97b2e202
AD		 777 uint32_t gds_base, gds_size;
778 uint32_t gws_base, gws_size;
779 uint32_t oa_base, oa_size;
de807f81 780 uint32_t flags;
5430a3ff
CK		 781 /* resulting sequence number */
782 uint64_t sequence;
97b2e202
AD		 783};
784
785enum amdgpu_ring_type {
786 AMDGPU_RING_TYPE_GFX,
787 AMDGPU_RING_TYPE_COMPUTE,
788 AMDGPU_RING_TYPE_SDMA,
789 AMDGPU_RING_TYPE_UVD,
790 AMDGPU_RING_TYPE_VCE
791};
792
c1b69ed0
CZ		 793extern struct amd_sched_backend_ops amdgpu_sched_ops;
794
50838c8c
CK		 795int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
796 struct amdgpu_job **job);
d71518b5
CK		 797int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
798 struct amdgpu_job **job);
50838c8c 799void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 800int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 801 struct amd_sched_entity *entity, void *owner,
802 struct fence **f);
3c704e93 803
97b2e202
AD		 804struct amdgpu_ring {
805 struct amdgpu_device *adev;
806 const struct amdgpu_ring_funcs *funcs;
807 struct amdgpu_fence_driver fence_drv;
4f839a24 808 struct amd_gpu_scheduler sched;
97b2e202 809
176e1ab1 810 spinlock_t fence_lock;
97b2e202
AD		 811 struct amdgpu_bo *ring_obj;
812 volatile uint32_t *ring;
813 unsigned rptr_offs;
814 u64 next_rptr_gpu_addr;
815 volatile u32 *next_rptr_cpu_addr;
816 unsigned wptr;
817 unsigned wptr_old;
818 unsigned ring_size;
c7e6be23 819 unsigned max_dw;
97b2e202 820 int count_dw;
97b2e202
AD		 821 uint64_t gpu_addr;
822 uint32_t align_mask;
823 uint32_t ptr_mask;
824 bool ready;
825 u32 nop;
826 u32 idx;
97b2e202
AD		 827 u32 me;
828 u32 pipe;
829 u32 queue;
830 struct amdgpu_bo *mqd_obj;
831 u32 doorbell_index;
832 bool use_doorbell;
833 unsigned wptr_offs;
834 unsigned next_rptr_offs;
835 unsigned fence_offs;
3cb485f3 836 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 837 enum amdgpu_ring_type type;
838 char name[16];
839};
840
841/*
842 * VM
843 */
844
845/* maximum number of VMIDs */
846#define AMDGPU_NUM_VM 16
847
848/* number of entries in page table */
849#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
850
851/* PTBs (Page Table Blocks) need to be aligned to 32K */
852#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
853#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
854#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
855
856#define AMDGPU_PTE_VALID (1 << 0)
857#define AMDGPU_PTE_SYSTEM (1 << 1)
858#define AMDGPU_PTE_SNOOPED (1 << 2)
859
860/* VI only */
861#define AMDGPU_PTE_EXECUTABLE (1 << 4)
862
863#define AMDGPU_PTE_READABLE (1 << 5)
864#define AMDGPU_PTE_WRITEABLE (1 << 6)
865
866/* PTE (Page Table Entry) fragment field for different page sizes */
867#define AMDGPU_PTE_FRAG_4KB (0 << 7)
868#define AMDGPU_PTE_FRAG_64KB (4 << 7)
869#define AMDGPU_LOG2_PAGES_PER_FRAG 4
870
d9c13156
CK		 871/* How to programm VM fault handling */
872#define AMDGPU_VM_FAULT_STOP_NEVER 0
873#define AMDGPU_VM_FAULT_STOP_FIRST 1
874#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
875
97b2e202 876struct amdgpu_vm_pt {
ee1782c3
CK		 877 struct amdgpu_bo_list_entry entry;
878 uint64_t addr;
97b2e202
AD		 879};
880
881struct amdgpu_vm_id {
4ff37a83
CK		 882 struct amdgpu_vm_manager_id *mgr_id;
883 uint64_t pd_gpu_addr;
97b2e202 884 /* last flushed PD/PT update */
4ff37a83 885 struct fence *flushed_updates;
97b2e202
AD		 886};
887
888struct amdgpu_vm {
25cfc3c2 889 /* tree of virtual addresses mapped */
97b2e202
AD		 890 struct rb_root va;
891
7fc11959 892 /* protecting invalidated */
97b2e202
AD		 893 spinlock_t status_lock;
894
895 /* BOs moved, but not yet updated in the PT */
896 struct list_head invalidated;
897
7fc11959
CK		 898 /* BOs cleared in the PT because of a move */
899 struct list_head cleared;
900
901 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 902 struct list_head freed;
903
904 /* contains the page directory */
905 struct amdgpu_bo *page_directory;
906 unsigned max_pde_used;
05906dec 907 struct fence *page_directory_fence;
97b2e202
AD		 908
909 /* array of page tables, one for each page directory entry */
910 struct amdgpu_vm_pt *page_tables;
911
912 /* for id and flush management per ring */
913 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 914
81d75a30 915 /* protecting freed */
916 spinlock_t freed_lock;
2bd9ccfa
CK		 917
918 /* Scheduler entity for page table updates */
919 struct amd_sched_entity entity;
97b2e202
AD		 920};
921
a9a78b32
CK		 922struct amdgpu_vm_manager_id {
923 struct list_head list;
924 struct fence *active;
925 atomic_long_t owner;
971fe9a9
CK		 926
927 uint32_t gds_base;
928 uint32_t gds_size;
929 uint32_t gws_base;
930 uint32_t gws_size;
931 uint32_t oa_base;
932 uint32_t oa_size;
a9a78b32
CK		 933};
934
97b2e202 935struct amdgpu_vm_manager {
a9a78b32 936 /* Handling of VMIDs */
8d0a7cea 937 struct mutex lock;
a9a78b32
CK		 938 unsigned num_ids;
939 struct list_head ids_lru;
940 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
1c16c0a7 941
8b4fb00b 942 uint32_t max_pfn;
97b2e202 943 /* vram base address for page table entry */
8b4fb00b 944 u64 vram_base_offset;
97b2e202 945 /* is vm enabled? */
8b4fb00b 946 bool enabled;
97b2e202
AD		 947 /* vm pte handling */
948 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 949 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
950 unsigned vm_pte_num_rings;
951 atomic_t vm_pte_next_ring;
97b2e202
AD		 952};
953
a9a78b32 954void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 955void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 956int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
957void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 958void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
959 struct list_head *validated,
960 struct amdgpu_bo_list_entry *entry);
ee1782c3 961void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 962void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
963 struct amdgpu_vm *vm);
8b4fb00b 964int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83
CK		 965 struct amdgpu_sync *sync, struct fence *fence,
966 unsigned *vm_id, uint64_t *vm_pd_addr);
8b4fb00b 967void amdgpu_vm_flush(struct amdgpu_ring *ring,
cffadc83
CK		 968 unsigned vm_id, uint64_t pd_addr,
969 uint32_t gds_base, uint32_t gds_size,
970 uint32_t gws_base, uint32_t gws_size,
971 uint32_t oa_base, uint32_t oa_size);
971fe9a9 972void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
b07c9d2a 973uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 974int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
975 struct amdgpu_vm *vm);
976int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
977 struct amdgpu_vm *vm);
978int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
979 struct amdgpu_sync *sync);
980int amdgpu_vm_bo_update(struct amdgpu_device *adev,
981 struct amdgpu_bo_va *bo_va,
982 struct ttm_mem_reg *mem);
983void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
984 struct amdgpu_bo *bo);
985struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
986 struct amdgpu_bo *bo);
987struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
988 struct amdgpu_vm *vm,
989 struct amdgpu_bo *bo);
990int amdgpu_vm_bo_map(struct amdgpu_device *adev,
991 struct amdgpu_bo_va *bo_va,
992 uint64_t addr, uint64_t offset,
993 uint64_t size, uint32_t flags);
994int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
995 struct amdgpu_bo_va *bo_va,
996 uint64_t addr);
997void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
998 struct amdgpu_bo_va *bo_va);
8b4fb00b 999
97b2e202
AD		 1000/*
1001 * context related structures
1002 */
1003
21c16bf6 1004struct amdgpu_ctx_ring {
91404fb2 1005 uint64_t sequence;
37cd0ca2 1006 struct fence **fences;
91404fb2 1007 struct amd_sched_entity entity;
21c16bf6
CK		 1008};
1009
97b2e202 1010struct amdgpu_ctx {
0b492a4c 1011 struct kref refcount;
9cb7e5a9 1012 struct amdgpu_device *adev;
0b492a4c 1013 unsigned reset_counter;
21c16bf6 1014 spinlock_t ring_lock;
37cd0ca2 1015 struct fence **fences;
21c16bf6 1016 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1017};
1018
1019struct amdgpu_ctx_mgr {
0b492a4c
AD		 1020 struct amdgpu_device *adev;
1021 struct mutex lock;
1022 /* protected by lock */
1023 struct idr ctx_handles;
97b2e202
AD		 1024};
1025
0b492a4c
AD		 1026struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1027int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1028
21c16bf6 1029uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1030 struct fence *fence);
21c16bf6
CK		 1031struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1032 struct amdgpu_ring *ring, uint64_t seq);
1033
0b492a4c
AD		 1034int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1035 struct drm_file *filp);
1036
efd4ccb5
CK		 1037void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1038void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1039
97b2e202
AD		 1040/*
1041 * file private structure
1042 */
1043
1044struct amdgpu_fpriv {
1045 struct amdgpu_vm vm;
1046 struct mutex bo_list_lock;
1047 struct idr bo_list_handles;
0b492a4c 1048 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1049};
1050
1051/*
1052 * residency list
1053 */
1054
1055struct amdgpu_bo_list {
1056 struct mutex lock;
1057 struct amdgpu_bo *gds_obj;
1058 struct amdgpu_bo *gws_obj;
1059 struct amdgpu_bo *oa_obj;
211dff55 1060 unsigned first_userptr;
97b2e202
AD		 1061 unsigned num_entries;
1062 struct amdgpu_bo_list_entry *array;
1063};
1064
1065struct amdgpu_bo_list *
1066amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1067void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1068 struct list_head *validated);
97b2e202
AD		 1069void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1070void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1071
1072/*
1073 * GFX stuff
1074 */
1075#include "clearstate_defs.h"
1076
1077struct amdgpu_rlc {
1078 /* for power gating */
1079 struct amdgpu_bo *save_restore_obj;
1080 uint64_t save_restore_gpu_addr;
1081 volatile uint32_t *sr_ptr;
1082 const u32 *reg_list;
1083 u32 reg_list_size;
1084 /* for clear state */
1085 struct amdgpu_bo *clear_state_obj;
1086 uint64_t clear_state_gpu_addr;
1087 volatile uint32_t *cs_ptr;
1088 const struct cs_section_def *cs_data;
1089 u32 clear_state_size;
1090 /* for cp tables */
1091 struct amdgpu_bo *cp_table_obj;
1092 uint64_t cp_table_gpu_addr;
1093 volatile uint32_t *cp_table_ptr;
1094 u32 cp_table_size;
1095};
1096
1097struct amdgpu_mec {
1098 struct amdgpu_bo *hpd_eop_obj;
1099 u64 hpd_eop_gpu_addr;
1100 u32 num_pipe;
1101 u32 num_mec;
1102 u32 num_queue;
1103};
1104
1105/*
1106 * GPU scratch registers structures, functions & helpers
1107 */
1108struct amdgpu_scratch {
1109 unsigned num_reg;
1110 uint32_t reg_base;
1111 bool free[32];
1112 uint32_t reg[32];
1113};
1114
1115/*
1116 * GFX configurations
1117 */
1118struct amdgpu_gca_config {
1119 unsigned max_shader_engines;
1120 unsigned max_tile_pipes;
1121 unsigned max_cu_per_sh;
1122 unsigned max_sh_per_se;
1123 unsigned max_backends_per_se;
1124 unsigned max_texture_channel_caches;
1125 unsigned max_gprs;
1126 unsigned max_gs_threads;
1127 unsigned max_hw_contexts;
1128 unsigned sc_prim_fifo_size_frontend;
1129 unsigned sc_prim_fifo_size_backend;
1130 unsigned sc_hiz_tile_fifo_size;
1131 unsigned sc_earlyz_tile_fifo_size;
1132
1133 unsigned num_tile_pipes;
1134 unsigned backend_enable_mask;
1135 unsigned mem_max_burst_length_bytes;
1136 unsigned mem_row_size_in_kb;
1137 unsigned shader_engine_tile_size;
1138 unsigned num_gpus;
1139 unsigned multi_gpu_tile_size;
1140 unsigned mc_arb_ramcfg;
1141 unsigned gb_addr_config;
8f8e00c1 1142 unsigned num_rbs;
97b2e202
AD		 1143
1144 uint32_t tile_mode_array[32];
1145 uint32_t macrotile_mode_array[16];
1146};
1147
1148struct amdgpu_gfx {
1149 struct mutex gpu_clock_mutex;
1150 struct amdgpu_gca_config config;
1151 struct amdgpu_rlc rlc;
1152 struct amdgpu_mec mec;
1153 struct amdgpu_scratch scratch;
1154 const struct firmware *me_fw; /* ME firmware */
1155 uint32_t me_fw_version;
1156 const struct firmware *pfp_fw; /* PFP firmware */
1157 uint32_t pfp_fw_version;
1158 const struct firmware *ce_fw; /* CE firmware */
1159 uint32_t ce_fw_version;
1160 const struct firmware *rlc_fw; /* RLC firmware */
1161 uint32_t rlc_fw_version;
1162 const struct firmware *mec_fw; /* MEC firmware */
1163 uint32_t mec_fw_version;
1164 const struct firmware *mec2_fw; /* MEC2 firmware */
1165 uint32_t mec2_fw_version;
02558a00
KW		 1166 uint32_t me_feature_version;
1167 uint32_t ce_feature_version;
1168 uint32_t pfp_feature_version;
351643d7
JZ		 1169 uint32_t rlc_feature_version;
1170 uint32_t mec_feature_version;
1171 uint32_t mec2_feature_version;
97b2e202
AD		 1172 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1173 unsigned num_gfx_rings;
1174 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1175 unsigned num_compute_rings;
1176 struct amdgpu_irq_src eop_irq;
1177 struct amdgpu_irq_src priv_reg_irq;
1178 struct amdgpu_irq_src priv_inst_irq;
1179 /* gfx status */
1180 uint32_t gfx_current_status;
a101a899
KW		 1181 /* ce ram size*/
1182 unsigned ce_ram_size;
97b2e202
AD		 1183};
1184
b07c60c0 1185int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202
AD		 1186 unsigned size, struct amdgpu_ib *ib);
1187void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
b07c60c0 1188int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1189 struct amdgpu_ib *ib, struct fence *last_vm_update,
ec72b800 1190 struct fence **f);
97b2e202
AD		 1191int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1192void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1193int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1194int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1195void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1196void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1197void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1198void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1199unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1200 uint32_t **data);
1201int amdgpu_ring_restore(struct amdgpu_ring *ring,
1202 unsigned size, uint32_t *data);
1203int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1204 unsigned ring_size, u32 nop, u32 align_mask,
1205 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1206 enum amdgpu_ring_type ring_type);
1207void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1208struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1209
1210/*
1211 * CS.
1212 */
1213struct amdgpu_cs_chunk {
1214 uint32_t chunk_id;
1215 uint32_t length_dw;
1216 uint32_t *kdata;
97b2e202
AD		 1217};
1218
1219struct amdgpu_cs_parser {
1220 struct amdgpu_device *adev;
1221 struct drm_file *filp;
3cb485f3 1222 struct amdgpu_ctx *ctx;
c3cca41e 1223
97b2e202
AD		 1224 /* chunks */
1225 unsigned nchunks;
1226 struct amdgpu_cs_chunk *chunks;
97b2e202 1227
50838c8c
CK		 1228 /* scheduler job object */
1229 struct amdgpu_job *job;
97b2e202 1230
c3cca41e
CK		 1231 /* buffer objects */
1232 struct ww_acquire_ctx ticket;
1233 struct amdgpu_bo_list *bo_list;
1234 struct amdgpu_bo_list_entry vm_pd;
1235 struct list_head validated;
1236 struct fence *fence;
1237 uint64_t bytes_moved_threshold;
1238 uint64_t bytes_moved;
97b2e202
AD		 1239
1240 /* user fence */
91acbeb6 1241 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1242};
1243
bb977d37
CZ		 1244struct amdgpu_job {
1245 struct amd_sched_job base;
1246 struct amdgpu_device *adev;
b07c60c0 1247 struct amdgpu_ring *ring;
e86f9cee 1248 struct amdgpu_sync sync;
bb977d37
CZ		 1249 struct amdgpu_ib *ibs;
1250 uint32_t num_ibs;
e2840221 1251 void *owner;
bb977d37 1252 struct amdgpu_user_fence uf;
bb977d37 1253};
a6db8a33
JZ		 1254#define to_amdgpu_job(sched_job) \
1255 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1256
7270f839
CK		 1257static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1258 uint32_t ib_idx, int idx)
97b2e202 1259{
50838c8c 1260 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1261}
1262
7270f839
CK		 1263static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1264 uint32_t ib_idx, int idx,
1265 uint32_t value)
1266{
50838c8c 1267 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1268}
1269
97b2e202
AD		 1270/*
1271 * Writeback
1272 */
1273#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1274
1275struct amdgpu_wb {
1276 struct amdgpu_bo *wb_obj;
1277 volatile uint32_t *wb;
1278 uint64_t gpu_addr;
1279 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1280 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1281};
1282
1283int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1284void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1285
97b2e202 1286
97b2e202
AD		 1287
1288enum amdgpu_int_thermal_type {
1289 THERMAL_TYPE_NONE,
1290 THERMAL_TYPE_EXTERNAL,
1291 THERMAL_TYPE_EXTERNAL_GPIO,
1292 THERMAL_TYPE_RV6XX,
1293 THERMAL_TYPE_RV770,
1294 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1295 THERMAL_TYPE_EVERGREEN,
1296 THERMAL_TYPE_SUMO,
1297 THERMAL_TYPE_NI,
1298 THERMAL_TYPE_SI,
1299 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1300 THERMAL_TYPE_CI,
1301 THERMAL_TYPE_KV,
1302};
1303
1304enum amdgpu_dpm_auto_throttle_src {
1305 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1306 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1307};
1308
1309enum amdgpu_dpm_event_src {
1310 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1311 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1312 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1313 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1314 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1315};
1316
1317#define AMDGPU_MAX_VCE_LEVELS 6
1318
1319enum amdgpu_vce_level {
1320 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1321 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1322 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1323 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1324 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1325 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1326};
1327
1328struct amdgpu_ps {
1329 u32 caps; /* vbios flags */
1330 u32 class; /* vbios flags */
1331 u32 class2; /* vbios flags */
1332 /* UVD clocks */
1333 u32 vclk;
1334 u32 dclk;
1335 /* VCE clocks */
1336 u32 evclk;
1337 u32 ecclk;
1338 bool vce_active;
1339 enum amdgpu_vce_level vce_level;
1340 /* asic priv */
1341 void *ps_priv;
1342};
1343
1344struct amdgpu_dpm_thermal {
1345 /* thermal interrupt work */
1346 struct work_struct work;
1347 /* low temperature threshold */
1348 int min_temp;
1349 /* high temperature threshold */
1350 int max_temp;
1351 /* was last interrupt low to high or high to low */
1352 bool high_to_low;
1353 /* interrupt source */
1354 struct amdgpu_irq_src irq;
1355};
1356
1357enum amdgpu_clk_action
1358{
1359 AMDGPU_SCLK_UP = 1,
1360 AMDGPU_SCLK_DOWN
1361};
1362
1363struct amdgpu_blacklist_clocks
1364{
1365 u32 sclk;
1366 u32 mclk;
1367 enum amdgpu_clk_action action;
1368};
1369
1370struct amdgpu_clock_and_voltage_limits {
1371 u32 sclk;
1372 u32 mclk;
1373 u16 vddc;
1374 u16 vddci;
1375};
1376
1377struct amdgpu_clock_array {
1378 u32 count;
1379 u32 *values;
1380};
1381
1382struct amdgpu_clock_voltage_dependency_entry {
1383 u32 clk;
1384 u16 v;
1385};
1386
1387struct amdgpu_clock_voltage_dependency_table {
1388 u32 count;
1389 struct amdgpu_clock_voltage_dependency_entry *entries;
1390};
1391
1392union amdgpu_cac_leakage_entry {
1393 struct {
1394 u16 vddc;
1395 u32 leakage;
1396 };
1397 struct {
1398 u16 vddc1;
1399 u16 vddc2;
1400 u16 vddc3;
1401 };
1402};
1403
1404struct amdgpu_cac_leakage_table {
1405 u32 count;
1406 union amdgpu_cac_leakage_entry *entries;
1407};
1408
1409struct amdgpu_phase_shedding_limits_entry {
1410 u16 voltage;
1411 u32 sclk;
1412 u32 mclk;
1413};
1414
1415struct amdgpu_phase_shedding_limits_table {
1416 u32 count;
1417 struct amdgpu_phase_shedding_limits_entry *entries;
1418};
1419
1420struct amdgpu_uvd_clock_voltage_dependency_entry {
1421 u32 vclk;
1422 u32 dclk;
1423 u16 v;
1424};
1425
1426struct amdgpu_uvd_clock_voltage_dependency_table {
1427 u8 count;
1428 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1429};
1430
1431struct amdgpu_vce_clock_voltage_dependency_entry {
1432 u32 ecclk;
1433 u32 evclk;
1434 u16 v;
1435};
1436
1437struct amdgpu_vce_clock_voltage_dependency_table {
1438 u8 count;
1439 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1440};
1441
1442struct amdgpu_ppm_table {
1443 u8 ppm_design;
1444 u16 cpu_core_number;
1445 u32 platform_tdp;
1446 u32 small_ac_platform_tdp;
1447 u32 platform_tdc;
1448 u32 small_ac_platform_tdc;
1449 u32 apu_tdp;
1450 u32 dgpu_tdp;
1451 u32 dgpu_ulv_power;
1452 u32 tj_max;
1453};
1454
1455struct amdgpu_cac_tdp_table {
1456 u16 tdp;
1457 u16 configurable_tdp;
1458 u16 tdc;
1459 u16 battery_power_limit;
1460 u16 small_power_limit;
1461 u16 low_cac_leakage;
1462 u16 high_cac_leakage;
1463 u16 maximum_power_delivery_limit;
1464};
1465
1466struct amdgpu_dpm_dynamic_state {
1467 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1468 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1469 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1470 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1471 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1472 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1473 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1474 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1475 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1476 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1477 struct amdgpu_clock_array valid_sclk_values;
1478 struct amdgpu_clock_array valid_mclk_values;
1479 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1480 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1481 u32 mclk_sclk_ratio;
1482 u32 sclk_mclk_delta;
1483 u16 vddc_vddci_delta;
1484 u16 min_vddc_for_pcie_gen2;
1485 struct amdgpu_cac_leakage_table cac_leakage_table;
1486 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1487 struct amdgpu_ppm_table *ppm_table;
1488 struct amdgpu_cac_tdp_table *cac_tdp_table;
1489};
1490
1491struct amdgpu_dpm_fan {
1492 u16 t_min;
1493 u16 t_med;
1494 u16 t_high;
1495 u16 pwm_min;
1496 u16 pwm_med;
1497 u16 pwm_high;
1498 u8 t_hyst;
1499 u32 cycle_delay;
1500 u16 t_max;
1501 u8 control_mode;
1502 u16 default_max_fan_pwm;
1503 u16 default_fan_output_sensitivity;
1504 u16 fan_output_sensitivity;
1505 bool ucode_fan_control;
1506};
1507
1508enum amdgpu_pcie_gen {
1509 AMDGPU_PCIE_GEN1 = 0,
1510 AMDGPU_PCIE_GEN2 = 1,
1511 AMDGPU_PCIE_GEN3 = 2,
1512 AMDGPU_PCIE_GEN_INVALID = 0xffff
1513};
1514
1515enum amdgpu_dpm_forced_level {
1516 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1517 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1518 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1519 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1520};
1521
1522struct amdgpu_vce_state {
1523 /* vce clocks */
1524 u32 evclk;
1525 u32 ecclk;
1526 /* gpu clocks */
1527 u32 sclk;
1528 u32 mclk;
1529 u8 clk_idx;
1530 u8 pstate;
1531};
1532
1533struct amdgpu_dpm_funcs {
1534 int (*get_temperature)(struct amdgpu_device *adev);
1535 int (*pre_set_power_state)(struct amdgpu_device *adev);
1536 int (*set_power_state)(struct amdgpu_device *adev);
1537 void (*post_set_power_state)(struct amdgpu_device *adev);
1538 void (*display_configuration_changed)(struct amdgpu_device *adev);
1539 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1540 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1541 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1542 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1543 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1544 bool (*vblank_too_short)(struct amdgpu_device *adev);
1545 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1546 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1547 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1548 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1549 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1550 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1551 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1552};
1553
1554struct amdgpu_dpm {
1555 struct amdgpu_ps *ps;
1556 /* number of valid power states */
1557 int num_ps;
1558 /* current power state that is active */
1559 struct amdgpu_ps *current_ps;
1560 /* requested power state */
1561 struct amdgpu_ps *requested_ps;
1562 /* boot up power state */
1563 struct amdgpu_ps *boot_ps;
1564 /* default uvd power state */
1565 struct amdgpu_ps *uvd_ps;
1566 /* vce requirements */
1567 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1568 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1569 enum amd_pm_state_type state;
1570 enum amd_pm_state_type user_state;
97b2e202
AD		 1571 u32 platform_caps;
1572 u32 voltage_response_time;
1573 u32 backbias_response_time;
1574 void *priv;
1575 u32 new_active_crtcs;
1576 int new_active_crtc_count;
1577 u32 current_active_crtcs;
1578 int current_active_crtc_count;
1579 struct amdgpu_dpm_dynamic_state dyn_state;
1580 struct amdgpu_dpm_fan fan;
1581 u32 tdp_limit;
1582 u32 near_tdp_limit;
1583 u32 near_tdp_limit_adjusted;
1584 u32 sq_ramping_threshold;
1585 u32 cac_leakage;
1586 u16 tdp_od_limit;
1587 u32 tdp_adjustment;
1588 u16 load_line_slope;
1589 bool power_control;
1590 bool ac_power;
1591 /* special states active */
1592 bool thermal_active;
1593 bool uvd_active;
1594 bool vce_active;
1595 /* thermal handling */
1596 struct amdgpu_dpm_thermal thermal;
1597 /* forced levels */
1598 enum amdgpu_dpm_forced_level forced_level;
1599};
1600
1601struct amdgpu_pm {
1602 struct mutex mutex;
97b2e202
AD		 1603 u32 current_sclk;
1604 u32 current_mclk;
1605 u32 default_sclk;
1606 u32 default_mclk;
1607 struct amdgpu_i2c_chan *i2c_bus;
1608 /* internal thermal controller on rv6xx+ */
1609 enum amdgpu_int_thermal_type int_thermal_type;
1610 struct device *int_hwmon_dev;
1611 /* fan control parameters */
1612 bool no_fan;
1613 u8 fan_pulses_per_revolution;
1614 u8 fan_min_rpm;
1615 u8 fan_max_rpm;
1616 /* dpm */
1617 bool dpm_enabled;
c86f5ebf 1618 bool sysfs_initialized;
97b2e202
AD		 1619 struct amdgpu_dpm dpm;
1620 const struct firmware *fw; /* SMC firmware */
1621 uint32_t fw_version;
1622 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1623 uint32_t pcie_gen_mask;
1624 uint32_t pcie_mlw_mask;
7fb72a1f 1625 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1626};
1627
d0dd7f0c
AD		 1628void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1629
97b2e202
AD		 1630/*
1631 * UVD
1632 */
1633#define AMDGPU_MAX_UVD_HANDLES 10
1634#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1635#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1636#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1637
1638struct amdgpu_uvd {
1639 struct amdgpu_bo *vcpu_bo;
1640 void *cpu_addr;
1641 uint64_t gpu_addr;
97b2e202
AD		 1642 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1643 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1644 struct delayed_work idle_work;
1645 const struct firmware *fw; /* UVD firmware */
1646 struct amdgpu_ring ring;
1647 struct amdgpu_irq_src irq;
1648 bool address_64_bit;
ead833ec 1649 struct amd_sched_entity entity;
97b2e202
AD		 1650};
1651
1652/*
1653 * VCE
1654 */
1655#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1656#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1657
6a585777
AD		 1658#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1659#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1660
97b2e202
AD		 1661struct amdgpu_vce {
1662 struct amdgpu_bo *vcpu_bo;
1663 uint64_t gpu_addr;
1664 unsigned fw_version;
1665 unsigned fb_version;
1666 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1667 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1668 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1669 struct delayed_work idle_work;
1670 const struct firmware *fw; /* VCE firmware */
1671 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1672 struct amdgpu_irq_src irq;
6a585777 1673 unsigned harvest_config;
c594989c 1674 struct amd_sched_entity entity;
97b2e202
AD		 1675};
1676
1677/*
1678 * SDMA
1679 */
c113ea1c 1680struct amdgpu_sdma_instance {
97b2e202
AD		 1681 /* SDMA firmware */
1682 const struct firmware *fw;
1683 uint32_t fw_version;
cfa2104f 1684 uint32_t feature_version;
97b2e202
AD		 1685
1686 struct amdgpu_ring ring;
18111de0 1687 bool burst_nop;
97b2e202
AD		 1688};
1689
c113ea1c
AD		 1690struct amdgpu_sdma {
1691 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1692 struct amdgpu_irq_src trap_irq;
1693 struct amdgpu_irq_src illegal_inst_irq;
1694 int num_instances;
1695};
1696
97b2e202
AD		 1697/*
1698 * Firmware
1699 */
1700struct amdgpu_firmware {
1701 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1702 bool smu_load;
1703 struct amdgpu_bo *fw_buf;
1704 unsigned int fw_size;
1705};
1706
1707/*
1708 * Benchmarking
1709 */
1710void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1711
1712
1713/*
1714 * Testing
1715 */
1716void amdgpu_test_moves(struct amdgpu_device *adev);
1717void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1718 struct amdgpu_ring *cpA,
1719 struct amdgpu_ring *cpB);
1720void amdgpu_test_syncing(struct amdgpu_device *adev);
1721
1722/*
1723 * MMU Notifier
1724 */
1725#if defined(CONFIG_MMU_NOTIFIER)
1726int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1727void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1728#else
1d1106b0 1729static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1730{
1731 return -ENODEV;
1732}
1d1106b0 1733static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1734#endif
1735
1736/*
1737 * Debugfs
1738 */
1739struct amdgpu_debugfs {
1740 struct drm_info_list *files;
1741 unsigned num_files;
1742};
1743
1744int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1745 struct drm_info_list *files,
1746 unsigned nfiles);
1747int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1748
1749#if defined(CONFIG_DEBUG_FS)
1750int amdgpu_debugfs_init(struct drm_minor *minor);
1751void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1752#endif
1753
1754/*
1755 * amdgpu smumgr functions
1756 */
1757struct amdgpu_smumgr_funcs {
1758 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1759 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1760 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1761};
1762
1763/*
1764 * amdgpu smumgr
1765 */
1766struct amdgpu_smumgr {
1767 struct amdgpu_bo *toc_buf;
1768 struct amdgpu_bo *smu_buf;
1769 /* asic priv smu data */
1770 void *priv;
1771 spinlock_t smu_lock;
1772 /* smumgr functions */
1773 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1774 /* ucode loading complete flag */
1775 uint32_t fw_flags;
1776};
1777
1778/*
1779 * ASIC specific register table accessible by UMD
1780 */
1781struct amdgpu_allowed_register_entry {
1782 uint32_t reg_offset;
1783 bool untouched;
1784 bool grbm_indexed;
1785};
1786
1787struct amdgpu_cu_info {
1788 uint32_t number; /* total active CU number */
1789 uint32_t ao_cu_mask;
1790 uint32_t bitmap[4][4];
1791};
1792
1793
1794/*
1795 * ASIC specific functions.
1796 */
1797struct amdgpu_asic_funcs {
1798 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1799 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1800 u8 *bios, u32 length_bytes);
97b2e202
AD		 1801 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1802 u32 sh_num, u32 reg_offset, u32 *value);
1803 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1804 int (*reset)(struct amdgpu_device *adev);
1805 /* wait for mc_idle */
1806 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1807 /* get the reference clock */
1808 u32 (*get_xclk)(struct amdgpu_device *adev);
1809 /* get the gpu clock counter */
1810 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1811 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1812 /* MM block clocks */
1813 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1814 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1815};
1816
1817/*
1818 * IOCTL.
1819 */
1820int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824
1825int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1828 struct drm_file *filp);
1829int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1833int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1834 struct drm_file *filp);
1835int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1838int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1839
1840int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842
1843/* VRAM scratch page for HDP bug, default vram page */
1844struct amdgpu_vram_scratch {
1845 struct amdgpu_bo *robj;
1846 volatile uint32_t *ptr;
1847 u64 gpu_addr;
1848};
1849
1850/*
1851 * ACPI
1852 */
1853struct amdgpu_atif_notification_cfg {
1854 bool enabled;
1855 int command_code;
1856};
1857
1858struct amdgpu_atif_notifications {
1859 bool display_switch;
1860 bool expansion_mode_change;
1861 bool thermal_state;
1862 bool forced_power_state;
1863 bool system_power_state;
1864 bool display_conf_change;
1865 bool px_gfx_switch;
1866 bool brightness_change;
1867 bool dgpu_display_event;
1868};
1869
1870struct amdgpu_atif_functions {
1871 bool system_params;
1872 bool sbios_requests;
1873 bool select_active_disp;
1874 bool lid_state;
1875 bool get_tv_standard;
1876 bool set_tv_standard;
1877 bool get_panel_expansion_mode;
1878 bool set_panel_expansion_mode;
1879 bool temperature_change;
1880 bool graphics_device_types;
1881};
1882
1883struct amdgpu_atif {
1884 struct amdgpu_atif_notifications notifications;
1885 struct amdgpu_atif_functions functions;
1886 struct amdgpu_atif_notification_cfg notification_cfg;
1887 struct amdgpu_encoder *encoder_for_bl;
1888};
1889
1890struct amdgpu_atcs_functions {
1891 bool get_ext_state;
1892 bool pcie_perf_req;
1893 bool pcie_dev_rdy;
1894 bool pcie_bus_width;
1895};
1896
1897struct amdgpu_atcs {
1898 struct amdgpu_atcs_functions functions;
1899};
1900
d03846af
CZ		 1901/*
1902 * CGS
1903 */
1904void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1905void amdgpu_cgs_destroy_device(void *cgs_device);
1906
1907
a8fe58ce
MB		 1908/*
1909 * CGS
1910 */
1911void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1912void amdgpu_cgs_destroy_device(void *cgs_device);
1913
1914
7e471e6f
AD		 1915/* GPU virtualization */
1916struct amdgpu_virtualization {
1917 bool supports_sr_iov;
1918};
1919
97b2e202
AD		 1920/*
1921 * Core structure, functions and helpers.
1922 */
1923typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1924typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1925
1926typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1927typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1928
8faf0e08
AD		 1929struct amdgpu_ip_block_status {
1930 bool valid;
1931 bool sw;
1932 bool hw;
1933};
1934
97b2e202
AD		 1935struct amdgpu_device {
1936 struct device *dev;
1937 struct drm_device *ddev;
1938 struct pci_dev *pdev;
97b2e202 1939
a8fe58ce
MB		 1940#ifdef CONFIG_DRM_AMD_ACP
1941 struct amdgpu_acp acp;
1942#endif
1943
97b2e202 1944 /* ASIC */
2f7d10b3 1945 enum amd_asic_type asic_type;
97b2e202
AD		 1946 uint32_t family;
1947 uint32_t rev_id;
1948 uint32_t external_rev_id;
1949 unsigned long flags;
1950 int usec_timeout;
1951 const struct amdgpu_asic_funcs *asic_funcs;
1952 bool shutdown;
1953 bool suspend;
1954 bool need_dma32;
1955 bool accel_working;
97b2e202
AD		 1956 struct work_struct reset_work;
1957 struct notifier_block acpi_nb;
1958 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1959 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1960 unsigned debugfs_count;
1961#if defined(CONFIG_DEBUG_FS)
1962 struct dentry *debugfs_regs;
1963#endif
1964 struct amdgpu_atif atif;
1965 struct amdgpu_atcs atcs;
1966 struct mutex srbm_mutex;
1967 /* GRBM index mutex. Protects concurrent access to GRBM index */
1968 struct mutex grbm_idx_mutex;
1969 struct dev_pm_domain vga_pm_domain;
1970 bool have_disp_power_ref;
1971
1972 /* BIOS */
1973 uint8_t *bios;
1974 bool is_atom_bios;
1975 uint16_t bios_header_start;
1976 struct amdgpu_bo *stollen_vga_memory;
1977 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1978
1979 /* Register/doorbell mmio */
1980 resource_size_t rmmio_base;
1981 resource_size_t rmmio_size;
1982 void __iomem *rmmio;
1983 /* protects concurrent MM_INDEX/DATA based register access */
1984 spinlock_t mmio_idx_lock;
1985 /* protects concurrent SMC based register access */
1986 spinlock_t smc_idx_lock;
1987 amdgpu_rreg_t smc_rreg;
1988 amdgpu_wreg_t smc_wreg;
1989 /* protects concurrent PCIE register access */
1990 spinlock_t pcie_idx_lock;
1991 amdgpu_rreg_t pcie_rreg;
1992 amdgpu_wreg_t pcie_wreg;
1993 /* protects concurrent UVD register access */
1994 spinlock_t uvd_ctx_idx_lock;
1995 amdgpu_rreg_t uvd_ctx_rreg;
1996 amdgpu_wreg_t uvd_ctx_wreg;
1997 /* protects concurrent DIDT register access */
1998 spinlock_t didt_idx_lock;
1999 amdgpu_rreg_t didt_rreg;
2000 amdgpu_wreg_t didt_wreg;
2001 /* protects concurrent ENDPOINT (audio) register access */
2002 spinlock_t audio_endpt_idx_lock;
2003 amdgpu_block_rreg_t audio_endpt_rreg;
2004 amdgpu_block_wreg_t audio_endpt_wreg;
2005 void __iomem *rio_mem;
2006 resource_size_t rio_mem_size;
2007 struct amdgpu_doorbell doorbell;
2008
2009 /* clock/pll info */
2010 struct amdgpu_clock clock;
2011
2012 /* MC */
2013 struct amdgpu_mc mc;
2014 struct amdgpu_gart gart;
2015 struct amdgpu_dummy_page dummy_page;
2016 struct amdgpu_vm_manager vm_manager;
2017
2018 /* memory management */
2019 struct amdgpu_mman mman;
97b2e202
AD		 2020 struct amdgpu_vram_scratch vram_scratch;
2021 struct amdgpu_wb wb;
2022 atomic64_t vram_usage;
2023 atomic64_t vram_vis_usage;
2024 atomic64_t gtt_usage;
2025 atomic64_t num_bytes_moved;
d94aed5a 2026 atomic_t gpu_reset_counter;
97b2e202
AD		 2027
2028 /* display */
2029 struct amdgpu_mode_info mode_info;
2030 struct work_struct hotplug_work;
2031 struct amdgpu_irq_src crtc_irq;
2032 struct amdgpu_irq_src pageflip_irq;
2033 struct amdgpu_irq_src hpd_irq;
2034
2035 /* rings */
97b2e202 2036 unsigned fence_context;
97b2e202
AD		 2037 unsigned num_rings;
2038 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2039 bool ib_pool_ready;
2040 struct amdgpu_sa_manager ring_tmp_bo;
2041
2042 /* interrupts */
2043 struct amdgpu_irq irq;
2044
1f7371b2
AD		 2045 /* powerplay */
2046 struct amd_powerplay powerplay;
e61710c5 2047 bool pp_enabled;
f3898ea1 2048 bool pp_force_state_enabled;
1f7371b2 2049
97b2e202
AD		 2050 /* dpm */
2051 struct amdgpu_pm pm;
2052 u32 cg_flags;
2053 u32 pg_flags;
2054
2055 /* amdgpu smumgr */
2056 struct amdgpu_smumgr smu;
2057
2058 /* gfx */
2059 struct amdgpu_gfx gfx;
2060
2061 /* sdma */
c113ea1c 2062 struct amdgpu_sdma sdma;
97b2e202
AD		 2063
2064 /* uvd */
97b2e202
AD		 2065 struct amdgpu_uvd uvd;
2066
2067 /* vce */
2068 struct amdgpu_vce vce;
2069
2070 /* firmwares */
2071 struct amdgpu_firmware firmware;
2072
2073 /* GDS */
2074 struct amdgpu_gds gds;
2075
2076 const struct amdgpu_ip_block_version *ip_blocks;
2077 int num_ip_blocks;
8faf0e08 2078 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2079 struct mutex mn_lock;
2080 DECLARE_HASHTABLE(mn_hash, 7);
2081
2082 /* tracking pinned memory */
2083 u64 vram_pin_size;
2084 u64 gart_pin_size;
130e0371
OG		 2085
2086 /* amdkfd interface */
2087 struct kfd_dev *kfd;
23ca0e4e 2088
7e471e6f 2089 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2090};
2091
2092bool amdgpu_device_is_px(struct drm_device *dev);
2093int amdgpu_device_init(struct amdgpu_device *adev,
2094 struct drm_device *ddev,
2095 struct pci_dev *pdev,
2096 uint32_t flags);
2097void amdgpu_device_fini(struct amdgpu_device *adev);
2098int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2099
2100uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2101 bool always_indirect);
2102void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2103 bool always_indirect);
2104u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2105void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2106
2107u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2108void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2109
2110/*
2111 * Cast helper
2112 */
2113extern const struct fence_ops amdgpu_fence_ops;
2114static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2115{
2116 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2117
2118 if (__f->base.ops == &amdgpu_fence_ops)
2119 return __f;
2120
2121 return NULL;
2122}
2123
2124/*
2125 * Registers read & write functions.
2126 */
2127#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2128#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2129#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2130#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2131#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2132#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2133#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2134#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2135#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2136#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2137#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2138#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2139#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2140#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2141#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2142#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2143#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2144#define WREG32_P(reg, val, mask) \
2145 do { \
2146 uint32_t tmp_ = RREG32(reg); \
2147 tmp_ &= (mask); \
2148 tmp_ |= ((val) & ~(mask)); \
2149 WREG32(reg, tmp_); \
2150 } while (0)
2151#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2152#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2153#define WREG32_PLL_P(reg, val, mask) \
2154 do { \
2155 uint32_t tmp_ = RREG32_PLL(reg); \
2156 tmp_ &= (mask); \
2157 tmp_ |= ((val) & ~(mask)); \
2158 WREG32_PLL(reg, tmp_); \
2159 } while (0)
2160#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2161#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2162#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2163
2164#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2165#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2166
2167#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2168#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2169
2170#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2171 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2172 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2173
2174#define REG_GET_FIELD(value, reg, field) \
2175 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2176
2177/*
2178 * BIOS helpers.
2179 */
2180#define RBIOS8(i) (adev->bios[i])
2181#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2182#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2183
2184/*
2185 * RING helpers.
2186 */
2187static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2188{
2189 if (ring->count_dw <= 0)
86c2b790 2190 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2191 ring->ring[ring->wptr++] = v;
2192 ring->wptr &= ring->ptr_mask;
2193 ring->count_dw--;
97b2e202
AD		 2194}
2195
c113ea1c
AD		 2196static inline struct amdgpu_sdma_instance *
2197amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2198{
2199 struct amdgpu_device *adev = ring->adev;
2200 int i;
2201
c113ea1c
AD		 2202 for (i = 0; i < adev->sdma.num_instances; i++)
2203 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2204 break;
2205
2206 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2207 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2208 else
2209 return NULL;
2210}
2211
97b2e202
AD		 2212/*
2213 * ASICs macro.
2214 */
2215#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2216#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2217#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2218#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2219#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2220#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2221#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2222#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2223#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2224#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2225#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2226#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2227#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2228#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2229#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2230#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2231#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2232#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2233#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2234#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2235#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2236#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2237#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
b8c7b39e 2238#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2239#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2240#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2241#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2242#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2243#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2244#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
97b2e202
AD		 2245#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2246#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2247#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2248#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2249#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2250#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2251#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2252#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2253#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2254#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2255#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2256#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2257#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2258#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2259#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2260#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2261#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2262#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2263#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2264#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2265#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2266#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2267#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2268#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2269#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2270#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2271#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2272#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2273
2274#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2275 ((adev)->pp_enabled ? \
e61710c5 2276 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2277 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2278
2279#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2280 ((adev)->pp_enabled ? \
e61710c5 2281 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2282 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2283
2284#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2285 ((adev)->pp_enabled ? \
e61710c5 2286 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2287 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2288
2289#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2290 ((adev)->pp_enabled ? \
e61710c5 2291 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2292 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2293
2294#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2295 ((adev)->pp_enabled ? \
e61710c5 2296 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2297 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2298
1b5708ff 2299#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2300 ((adev)->pp_enabled ? \
e61710c5 2301 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2302 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2303
2304#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2305 ((adev)->pp_enabled ? \
e61710c5 2306 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2307 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2308
2309
2310#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2311 ((adev)->pp_enabled ? \
e61710c5 2312 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2313 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2314
2315#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2316 ((adev)->pp_enabled ? \
e61710c5 2317 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2318 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2319
2320#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2321 ((adev)->pp_enabled ? \
e61710c5 2322 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2323 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2324
2325#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2326 ((adev)->pp_enabled ? \
e61710c5 2327 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2328 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2329
2330#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2331 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2332
2333#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2334 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2335
f3898ea1
EH		 2336#define amdgpu_dpm_get_pp_num_states(adev, data) \
2337 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2338
2339#define amdgpu_dpm_get_pp_table(adev, table) \
2340 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2341
2342#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2343 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2344
2345#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2346 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2347
2348#define amdgpu_dpm_force_clock_level(adev, type, level) \
2349 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2350
e61710c5 2351#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2352 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2353
2354#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2355
2356/* Common functions */
2357int amdgpu_gpu_reset(struct amdgpu_device *adev);
2358void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2359bool amdgpu_card_posted(struct amdgpu_device *adev);
2360void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2361
97b2e202
AD		 2362int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2363int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2364 u32 ip_instance, u32 ring,
2365 struct amdgpu_ring **out_ring);
2366void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2367bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2368int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2369int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2370 uint32_t flags);
cc325d19 2371struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2372bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2373 unsigned long end);
2f568dbd
CK		 2374bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2375 int *last_invalidated);
97b2e202
AD		 2376bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2377uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2378 struct ttm_mem_reg *mem);
2379void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2380void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2381void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2382void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2383 const u32 *registers,
2384 const u32 array_size);
2385
2386bool amdgpu_device_is_px(struct drm_device *dev);
2387/* atpx handler */
2388#if defined(CONFIG_VGA_SWITCHEROO)
2389void amdgpu_register_atpx_handler(void);
2390void amdgpu_unregister_atpx_handler(void);
2391#else
2392static inline void amdgpu_register_atpx_handler(void) {}
2393static inline void amdgpu_unregister_atpx_handler(void) {}
2394#endif
2395
2396/*
2397 * KMS
2398 */
2399extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2400extern int amdgpu_max_kms_ioctl;
2401
2402int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2403int amdgpu_driver_unload_kms(struct drm_device *dev);
2404void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2405int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2406void amdgpu_driver_postclose_kms(struct drm_device *dev,
2407 struct drm_file *file_priv);
2408void amdgpu_driver_preclose_kms(struct drm_device *dev,
2409 struct drm_file *file_priv);
2410int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2411int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2412u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2413int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2414void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2415int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2416 int *max_error,
2417 struct timeval *vblank_time,
2418 unsigned flags);
2419long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2420 unsigned long arg);
2421
97b2e202
AD		 2422/*
2423 * functions used by amdgpu_encoder.c
2424 */
2425struct amdgpu_afmt_acr {
2426 u32 clock;
2427
2428 int n_32khz;
2429 int cts_32khz;
2430
2431 int n_44_1khz;
2432 int cts_44_1khz;
2433
2434 int n_48khz;
2435 int cts_48khz;
2436
2437};
2438
2439struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2440
2441/* amdgpu_acpi.c */
2442#if defined(CONFIG_ACPI)
2443int amdgpu_acpi_init(struct amdgpu_device *adev);
2444void amdgpu_acpi_fini(struct amdgpu_device *adev);
2445bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2446int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2447 u8 perf_req, bool advertise);
2448int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2449#else
2450static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2451static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2452#endif
2453
2454struct amdgpu_bo_va_mapping *
2455amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2456 uint64_t addr, struct amdgpu_bo **bo);
2457
2458#include "amdgpu_object.h"
2459
2460#endif
Linux 6.x block layer and io_uring tree(s)