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drm/amdgpu:make ctx_add_fence interruptible(v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834
AR		 49#include <kgd_kfd_interface.h>
50
5fc3aeeb 51#include "amd_shared.h"
97b2e202
AD		 52#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
c632d799 56#include "amdgpu_ttm.h"
0e5ca0d1 57#include "amdgpu_psp.h"
97b2e202 58#include "amdgpu_gds.h"
56113504 59#include "amdgpu_sync.h"
78023016 60#include "amdgpu_ring.h"
073440d2 61#include "amdgpu_vm.h"
1f7371b2 62#include "amd_powerplay.h"
cf097881 63#include "amdgpu_dpm.h"
a8fe58ce 64#include "amdgpu_acp.h"
4df654d2 65#include "amdgpu_uvd.h"
5e568178 66#include "amdgpu_vce.h"
95aa13f6 67#include "amdgpu_vcn.h"
9a189996 68#include "amdgpu_mn.h"
97b2e202 69
b80d8475 70#include "gpu_scheduler.h"
ceeb50ed 71#include "amdgpu_virt.h"
3490bdb5 72#include "amdgpu_gart.h"
b80d8475 73
97b2e202
AD		 74/*
75 * Modules parameters.
76 */
77extern int amdgpu_modeset;
78extern int amdgpu_vram_limit;
218b5dcd 79extern int amdgpu_vis_vram_limit;
83e74db6 80extern int amdgpu_gart_size;
36d38372 81extern int amdgpu_gtt_size;
95844d20 82extern int amdgpu_moverate;
97b2e202
AD		 83extern int amdgpu_benchmarking;
84extern int amdgpu_testing;
85extern int amdgpu_audio;
86extern int amdgpu_disp_priority;
87extern int amdgpu_hw_i2c;
88extern int amdgpu_pcie_gen2;
89extern int amdgpu_msi;
90extern int amdgpu_lockup_timeout;
91extern int amdgpu_dpm;
e635ee07 92extern int amdgpu_fw_load_type;
97b2e202
AD		 93extern int amdgpu_aspm;
94extern int amdgpu_runtime_pm;
0b693f0b 95extern uint amdgpu_ip_block_mask;
97b2e202
AD		 96extern int amdgpu_bapm;
97extern int amdgpu_deep_color;
98extern int amdgpu_vm_size;
99extern int amdgpu_vm_block_size;
d07f14be 100extern int amdgpu_vm_fragment_size;
d9c13156 101extern int amdgpu_vm_fault_stop;
b495bd3a 102extern int amdgpu_vm_debug;
9a4b7d4c 103extern int amdgpu_vm_update_mode;
1333f723 104extern int amdgpu_sched_jobs;
4afcb303 105extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 106extern int amdgpu_no_evict;
107extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 108extern uint amdgpu_pcie_gen_cap;
109extern uint amdgpu_pcie_lane_cap;
110extern uint amdgpu_cg_mask;
111extern uint amdgpu_pg_mask;
112extern uint amdgpu_sdma_phase_quantum;
6f8941a2 113extern char *amdgpu_disable_cu;
9accf2fd 114extern char *amdgpu_virtual_display;
0b693f0b 115extern uint amdgpu_pp_feature_mask;
6a7f76e7 116extern int amdgpu_vram_page_split;
bce23e00
AD		 117extern int amdgpu_ngg;
118extern int amdgpu_prim_buf_per_se;
119extern int amdgpu_pos_buf_per_se;
120extern int amdgpu_cntl_sb_buf_per_se;
121extern int amdgpu_param_buf_per_se;
65781c78 122extern int amdgpu_job_hang_limit;
e8835e0e 123extern int amdgpu_lbpw;
97b2e202 124
6dd13096
FK		 125#ifdef CONFIG_DRM_AMDGPU_SI
126extern int amdgpu_si_support;
127#endif
7df28986
FK		 128#ifdef CONFIG_DRM_AMDGPU_CIK
129extern int amdgpu_cik_support;
130#endif
97b2e202 131
55ed8caf 132#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 133#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 134#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
135#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
136/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
137#define AMDGPU_IB_POOL_SIZE 16
138#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
139#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 140#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 141
36f523a7
JZ		 142/* max number of IP instances */
143#define AMDGPU_MAX_SDMA_INSTANCES 2
144
97b2e202
AD		 145/* hard reset data */
146#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
147
148/* reset flags */
149#define AMDGPU_RESET_GFX (1 << 0)
150#define AMDGPU_RESET_COMPUTE (1 << 1)
151#define AMDGPU_RESET_DMA (1 << 2)
152#define AMDGPU_RESET_CP (1 << 3)
153#define AMDGPU_RESET_GRBM (1 << 4)
154#define AMDGPU_RESET_DMA1 (1 << 5)
155#define AMDGPU_RESET_RLC (1 << 6)
156#define AMDGPU_RESET_SEM (1 << 7)
157#define AMDGPU_RESET_IH (1 << 8)
158#define AMDGPU_RESET_VMC (1 << 9)
159#define AMDGPU_RESET_MC (1 << 10)
160#define AMDGPU_RESET_DISPLAY (1 << 11)
161#define AMDGPU_RESET_UVD (1 << 12)
162#define AMDGPU_RESET_VCE (1 << 13)
163#define AMDGPU_RESET_VCE1 (1 << 14)
164
97b2e202
AD		 165/* GFX current status */
166#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
167#define AMDGPU_GFX_SAFE_MODE 0x00000001L
168#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
169#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
170#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
171
172/* max cursor sizes (in pixels) */
173#define CIK_CURSOR_WIDTH 128
174#define CIK_CURSOR_HEIGHT 128
175
176struct amdgpu_device;
97b2e202 177struct amdgpu_ib;
97b2e202 178struct amdgpu_cs_parser;
bb977d37 179struct amdgpu_job;
97b2e202 180struct amdgpu_irq_src;
0b492a4c 181struct amdgpu_fpriv;
9cca0b8e 182struct amdgpu_bo_va_mapping;
97b2e202
AD		 183
184enum amdgpu_cp_irq {
185 AMDGPU_CP_IRQ_GFX_EOP = 0,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
194
195 AMDGPU_CP_IRQ_LAST
196};
197
198enum amdgpu_sdma_irq {
199 AMDGPU_SDMA_IRQ_TRAP0 = 0,
200 AMDGPU_SDMA_IRQ_TRAP1,
201
202 AMDGPU_SDMA_IRQ_LAST
203};
204
205enum amdgpu_thermal_irq {
206 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
207 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
208
209 AMDGPU_THERMAL_IRQ_LAST
210};
211
4e638ae9
XY		 212enum amdgpu_kiq_irq {
213 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
214 AMDGPU_CP_KIQ_IRQ_LAST
215};
216
97b2e202 217int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 218 enum amd_ip_block_type block_type,
219 enum amd_clockgating_state state);
97b2e202 220int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_powergating_state state);
6cb2d4e4 223void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 224int amdgpu_wait_for_idle(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type);
226bool amdgpu_is_idle(struct amdgpu_device *adev,
227 enum amd_ip_block_type block_type);
97b2e202 228
a1255107
AD		 229#define AMDGPU_MAX_IP_NUM 16
230
231struct amdgpu_ip_block_status {
232 bool valid;
233 bool sw;
234 bool hw;
235 bool late_initialized;
236 bool hang;
237};
238
97b2e202 239struct amdgpu_ip_block_version {
a1255107
AD		 240 const enum amd_ip_block_type type;
241 const u32 major;
242 const u32 minor;
243 const u32 rev;
5fc3aeeb 244 const struct amd_ip_funcs *funcs;
97b2e202
AD		 245};
246
a1255107
AD		 247struct amdgpu_ip_block {
248 struct amdgpu_ip_block_status status;
249 const struct amdgpu_ip_block_version *version;
250};
251
97b2e202 252int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 253 enum amd_ip_block_type type,
97b2e202
AD		 254 u32 major, u32 minor);
255
a1255107
AD		 256struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
257 enum amd_ip_block_type type);
258
259int amdgpu_ip_block_add(struct amdgpu_device *adev,
260 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 261
262/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
263struct amdgpu_buffer_funcs {
264 /* maximum bytes in a single operation */
265 uint32_t copy_max_bytes;
266
267 /* number of dw to reserve per operation */
268 unsigned copy_num_dw;
269
270 /* used for buffer migration */
c7ae72c0 271 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 272 /* src addr in bytes */
273 uint64_t src_offset,
274 /* dst addr in bytes */
275 uint64_t dst_offset,
276 /* number of byte to transfer */
277 uint32_t byte_count);
278
279 /* maximum bytes in a single operation */
280 uint32_t fill_max_bytes;
281
282 /* number of dw to reserve per operation */
283 unsigned fill_num_dw;
284
285 /* used for buffer clearing */
6e7a3840 286 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 287 /* value to write to memory */
288 uint32_t src_data,
289 /* dst addr in bytes */
290 uint64_t dst_offset,
291 /* number of byte to fill */
292 uint32_t byte_count);
293};
294
295/* provided by hw blocks that can write ptes, e.g., sdma */
296struct amdgpu_vm_pte_funcs {
297 /* copy pte entries from GART */
298 void (*copy_pte)(struct amdgpu_ib *ib,
299 uint64_t pe, uint64_t src,
300 unsigned count);
301 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 302 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
303 uint64_t value, unsigned count,
304 uint32_t incr);
97b2e202
AD		 305 /* for linear pte/pde updates without addr mapping */
306 void (*set_pte_pde)(struct amdgpu_ib *ib,
307 uint64_t pe,
308 uint64_t addr, unsigned count,
6b777607 309 uint32_t incr, uint64_t flags);
97b2e202
AD		 310};
311
312/* provided by the gmc block */
313struct amdgpu_gart_funcs {
314 /* flush the vm tlb via mmio */
315 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
316 uint32_t vmid);
317 /* write pte/pde updates using the cpu */
318 int (*set_pte_pde)(struct amdgpu_device *adev,
319 void *cpu_pt_addr, /* cpu addr of page table */
320 uint32_t gpu_page_idx, /* pte/pde to update */
321 uint64_t addr, /* addr to write into pte/pde */
6b777607 322 uint64_t flags); /* access flags */
284710fa
CK		 323 /* enable/disable PRT support */
324 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 325 /* set pte flags based per asic */
326 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
327 uint32_t flags);
b1166325
CK		 328 /* get the pde for a given mc addr */
329 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 330 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 331};
332
97b2e202
AD		 333/* provided by the ih block */
334struct amdgpu_ih_funcs {
335 /* ring read/write ptr handling, called from interrupt context */
336 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 337 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 338 void (*decode_iv)(struct amdgpu_device *adev,
339 struct amdgpu_iv_entry *entry);
340 void (*set_rptr)(struct amdgpu_device *adev);
341};
342
97b2e202
AD		 343/*
344 * BIOS.
345 */
346bool amdgpu_get_bios(struct amdgpu_device *adev);
347bool amdgpu_read_bios(struct amdgpu_device *adev);
348
349/*
350 * Dummy page
351 */
352struct amdgpu_dummy_page {
353 struct page *page;
354 dma_addr_t addr;
355};
356int amdgpu_dummy_page_init(struct amdgpu_device *adev);
357void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
358
359
360/*
361 * Clocks
362 */
363
364#define AMDGPU_MAX_PPLL 3
365
366struct amdgpu_clock {
367 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
368 struct amdgpu_pll spll;
369 struct amdgpu_pll mpll;
370 /* 10 Khz units */
371 uint32_t default_mclk;
372 uint32_t default_sclk;
373 uint32_t default_dispclk;
374 uint32_t current_dispclk;
375 uint32_t dp_extclk;
376 uint32_t max_pixel_clock;
377};
378
97b2e202 379/*
9124a398 380 * GEM.
97b2e202 381 */
97b2e202 382
7e5a547f 383#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 384#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
385
386void amdgpu_gem_object_free(struct drm_gem_object *obj);
387int amdgpu_gem_object_open(struct drm_gem_object *obj,
388 struct drm_file *file_priv);
389void amdgpu_gem_object_close(struct drm_gem_object *obj,
390 struct drm_file *file_priv);
391unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
392struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 393struct drm_gem_object *
394amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
395 struct dma_buf_attachment *attach,
396 struct sg_table *sg);
97b2e202
AD		 397struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
398 struct drm_gem_object *gobj,
399 int flags);
400int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
401void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
402struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
403void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
404void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
405int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
406
407/* sub-allocation manager, it has to be protected by another lock.
408 * By conception this is an helper for other part of the driver
409 * like the indirect buffer or semaphore, which both have their
410 * locking.
411 *
412 * Principe is simple, we keep a list of sub allocation in offset
413 * order (first entry has offset == 0, last entry has the highest
414 * offset).
415 *
416 * When allocating new object we first check if there is room at
417 * the end total_size - (last_object_offset + last_object_size) >=
418 * alloc_size. If so we allocate new object there.
419 *
420 * When there is not enough room at the end, we start waiting for
421 * each sub object until we reach object_offset+object_size >=
422 * alloc_size, this object then become the sub object we return.
423 *
424 * Alignment can't be bigger than page size.
425 *
426 * Hole are not considered for allocation to keep things simple.
427 * Assumption is that there won't be hole (all object on same
428 * alignment).
429 */
6ba60b89
CK		 430
431#define AMDGPU_SA_NUM_FENCE_LISTS 32
432
97b2e202
AD		 433struct amdgpu_sa_manager {
434 wait_queue_head_t wq;
435 struct amdgpu_bo *bo;
436 struct list_head *hole;
6ba60b89 437 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 438 struct list_head olist;
439 unsigned size;
440 uint64_t gpu_addr;
441 void *cpu_ptr;
442 uint32_t domain;
443 uint32_t align;
444};
445
97b2e202
AD		 446/* sub-allocation buffer */
447struct amdgpu_sa_bo {
448 struct list_head olist;
449 struct list_head flist;
450 struct amdgpu_sa_manager *manager;
451 unsigned soffset;
452 unsigned eoffset;
f54d1867 453 struct dma_fence *fence;
97b2e202
AD		 454};
455
456/*
457 * GEM objects.
458 */
418aa0c2 459void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 460int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 461 int alignment, u32 initial_domain,
462 u64 flags, bool kernel,
463 struct reservation_object *resv,
464 struct drm_gem_object **obj);
97b2e202
AD		 465
466int amdgpu_mode_dumb_create(struct drm_file *file_priv,
467 struct drm_device *dev,
468 struct drm_mode_create_dumb *args);
469int amdgpu_mode_dumb_mmap(struct drm_file *filp,
470 struct drm_device *dev,
471 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 472int amdgpu_fence_slab_init(void);
473void amdgpu_fence_slab_fini(void);
97b2e202 474
e60f8db5
AX		 475/*
476 * VMHUB structures, functions & helpers
477 */
478struct amdgpu_vmhub {
479 uint32_t ctx0_ptb_addr_lo32;
480 uint32_t ctx0_ptb_addr_hi32;
481 uint32_t vm_inv_eng0_req;
482 uint32_t vm_inv_eng0_ack;
483 uint32_t vm_context0_cntl;
484 uint32_t vm_l2_pro_fault_status;
485 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 486};
487
97b2e202
AD		 488/*
489 * GPU MC structures, functions & helpers
490 */
491struct amdgpu_mc {
492 resource_size_t aper_size;
493 resource_size_t aper_base;
494 resource_size_t agp_base;
495 /* for some chips with <= 32MB we need to lie
496 * about vram size near mc fb location */
497 u64 mc_vram_size;
498 u64 visible_vram_size;
6f02a696
CK		 499 u64 gart_size;
500 u64 gart_start;
501 u64 gart_end;
97b2e202
AD		 502 u64 vram_start;
503 u64 vram_end;
504 unsigned vram_width;
505 u64 real_vram_size;
506 int vram_mtrr;
97b2e202
AD		 507 u64 mc_mask;
508 const struct firmware *fw; /* MC firmware */
509 uint32_t fw_version;
510 struct amdgpu_irq_src vm_fault;
81c59f54 511 uint32_t vram_type;
50b0197a 512 uint32_t srbm_soft_reset;
f7c35abe 513 bool prt_warning;
916910ad 514 uint64_t stolen_size;
8fe73328
JZ		 515 /* apertures */
516 u64 shared_aperture_start;
517 u64 shared_aperture_end;
518 u64 private_aperture_start;
519 u64 private_aperture_end;
e60f8db5
AX		 520 /* protects concurrent invalidation */
521 spinlock_t invalidate_lock;
97b2e202
AD		 522};
523
524/*
525 * GPU doorbell structures, functions & helpers
526 */
527typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
528{
529 AMDGPU_DOORBELL_KIQ = 0x000,
530 AMDGPU_DOORBELL_HIQ = 0x001,
531 AMDGPU_DOORBELL_DIQ = 0x002,
532 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
533 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
534 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
535 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
536 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
537 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
538 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
539 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
540 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
541 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
542 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
543 AMDGPU_DOORBELL_IH = 0x1E8,
544 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
545 AMDGPU_DOORBELL_INVALID = 0xFFFF
546} AMDGPU_DOORBELL_ASSIGNMENT;
547
548struct amdgpu_doorbell {
549 /* doorbell mmio */
550 resource_size_t base;
551 resource_size_t size;
552 u32 __iomem *ptr;
553 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
554};
555
39807b93
KW		 556/*
557 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
558 */
559typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
560{
561 /*
562 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
563 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
564 * Compute related doorbells are allocated from 0x00 to 0x8a
565 */
566
567
568 /* kernel scheduling */
569 AMDGPU_DOORBELL64_KIQ = 0x00,
570
571 /* HSA interface queue and debug queue */
572 AMDGPU_DOORBELL64_HIQ = 0x01,
573 AMDGPU_DOORBELL64_DIQ = 0x02,
574
575 /* Compute engines */
576 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
577 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
578 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
579 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
580 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
581 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
582 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
583 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
584
585 /* User queue doorbell range (128 doorbells) */
586 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
587 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
588
589 /* Graphics engine */
590 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
591
592 /*
593 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
594 * Graphics voltage island aperture 1
595 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
596 */
597
598 /* sDMA engines */
599 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
600 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
601 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
602 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
603
604 /* Interrupt handler */
605 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
606 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
607 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
608
e6b3ecb4
ML		 609 /* VCN engine use 32 bits doorbell */
610 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
611 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
612 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
613 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
614
615 /* overlap the doorbell assignment with VCN as they are mutually exclusive
616 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
617 */
4ed11d79
FM		 618 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
619 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
620 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
621 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
622
623 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
624 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
625 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
626 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 627
628 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
629 AMDGPU_DOORBELL64_INVALID = 0xFFFF
630} AMDGPU_DOORBELL64_ASSIGNMENT;
631
632
97b2e202
AD		 633void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
634 phys_addr_t *aperture_base,
635 size_t *aperture_size,
636 size_t *start_offset);
637
638/*
639 * IRQS.
640 */
641
642struct amdgpu_flip_work {
325cbba1 643 struct delayed_work flip_work;
97b2e202
AD		 644 struct work_struct unpin_work;
645 struct amdgpu_device *adev;
646 int crtc_id;
325cbba1 647 u32 target_vblank;
97b2e202
AD		 648 uint64_t base;
649 struct drm_pending_vblank_event *event;
765e7fbf 650 struct amdgpu_bo *old_abo;
f54d1867 651 struct dma_fence *excl;
1ffd2652 652 unsigned shared_count;
f54d1867
CW		 653 struct dma_fence **shared;
654 struct dma_fence_cb cb;
cb9e59d7 655 bool async;
97b2e202
AD		 656};
657
658
659/*
660 * CP & rings.
661 */
662
663struct amdgpu_ib {
664 struct amdgpu_sa_bo *sa_bo;
665 uint32_t length_dw;
666 uint64_t gpu_addr;
667 uint32_t *ptr;
de807f81 668 uint32_t flags;
97b2e202
AD		 669};
670
62250a91 671extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 672
50838c8c 673int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 674 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 675int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
676 struct amdgpu_job **job);
b6723c8d 677
a5fb4ec2 678void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 679void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 680int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 681 struct amd_sched_entity *entity, void *owner,
f54d1867 682 struct dma_fence **f);
8b4fb00b 683
effd924d
AR		 684/*
685 * Queue manager
686 */
687struct amdgpu_queue_mapper {
688 int hw_ip;
689 struct mutex lock;
690 /* protected by lock */
691 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
692};
693
694struct amdgpu_queue_mgr {
695 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
696};
697
698int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
699 struct amdgpu_queue_mgr *mgr);
700int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
701 struct amdgpu_queue_mgr *mgr);
702int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
703 struct amdgpu_queue_mgr *mgr,
704 int hw_ip, int instance, int ring,
705 struct amdgpu_ring **out_ring);
706
97b2e202
AD		 707/*
708 * context related structures
709 */
710
21c16bf6 711struct amdgpu_ctx_ring {
91404fb2 712 uint64_t sequence;
f54d1867 713 struct dma_fence **fences;
91404fb2 714 struct amd_sched_entity entity;
21c16bf6
CK		 715};
716
97b2e202 717struct amdgpu_ctx {
0b492a4c 718 struct kref refcount;
9cb7e5a9 719 struct amdgpu_device *adev;
effd924d 720 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 721 unsigned reset_counter;
21c16bf6 722 spinlock_t ring_lock;
f54d1867 723 struct dma_fence **fences;
21c16bf6 724 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 725 bool preamble_presented;
97b2e202
AD		 726};
727
728struct amdgpu_ctx_mgr {
0b492a4c
AD		 729 struct amdgpu_device *adev;
730 struct mutex lock;
731 /* protected by lock */
732 struct idr ctx_handles;
97b2e202
AD		 733};
734
0b492a4c
AD		 735struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
736int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
737
eb01abc7
ML		 738int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
739 struct dma_fence *fence, uint64_t *seq);
f54d1867 740struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6
CK		 741 struct amdgpu_ring *ring, uint64_t seq);
742
0b492a4c
AD		 743int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
745
efd4ccb5
CK		 746void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
747void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 748
97b2e202
AD		 749/*
750 * file private structure
751 */
752
753struct amdgpu_fpriv {
754 struct amdgpu_vm vm;
b85891bd 755 struct amdgpu_bo_va *prt_va;
0f4b3c68 756 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 757 struct mutex bo_list_lock;
758 struct idr bo_list_handles;
0b492a4c 759 struct amdgpu_ctx_mgr ctx_mgr;
f1892138 760 u32 vram_lost_counter;
97b2e202
AD		 761};
762
763/*
764 * residency list
765 */
9124a398
CK		 766struct amdgpu_bo_list_entry {
767 struct amdgpu_bo *robj;
768 struct ttm_validate_buffer tv;
769 struct amdgpu_bo_va *bo_va;
770 uint32_t priority;
771 struct page **user_pages;
772 int user_invalidated;
773};
97b2e202
AD		 774
775struct amdgpu_bo_list {
776 struct mutex lock;
5ac55629
AX		 777 struct rcu_head rhead;
778 struct kref refcount;
97b2e202
AD		 779 struct amdgpu_bo *gds_obj;
780 struct amdgpu_bo *gws_obj;
781 struct amdgpu_bo *oa_obj;
211dff55 782 unsigned first_userptr;
97b2e202
AD		 783 unsigned num_entries;
784 struct amdgpu_bo_list_entry *array;
785};
786
787struct amdgpu_bo_list *
788amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 789void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
790 struct list_head *validated);
97b2e202
AD		 791void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
792void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
793
794/*
795 * GFX stuff
796 */
797#include "clearstate_defs.h"
798
79e5412c
AD		 799struct amdgpu_rlc_funcs {
800 void (*enter_safe_mode)(struct amdgpu_device *adev);
801 void (*exit_safe_mode)(struct amdgpu_device *adev);
802};
803
97b2e202
AD		 804struct amdgpu_rlc {
805 /* for power gating */
806 struct amdgpu_bo *save_restore_obj;
807 uint64_t save_restore_gpu_addr;
808 volatile uint32_t *sr_ptr;
809 const u32 *reg_list;
810 u32 reg_list_size;
811 /* for clear state */
812 struct amdgpu_bo *clear_state_obj;
813 uint64_t clear_state_gpu_addr;
814 volatile uint32_t *cs_ptr;
815 const struct cs_section_def *cs_data;
816 u32 clear_state_size;
817 /* for cp tables */
818 struct amdgpu_bo *cp_table_obj;
819 uint64_t cp_table_gpu_addr;
820 volatile uint32_t *cp_table_ptr;
821 u32 cp_table_size;
79e5412c
AD		 822
823 /* safe mode for updating CG/PG state */
824 bool in_safe_mode;
825 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 826
827 /* for firmware data */
828 u32 save_and_restore_offset;
829 u32 clear_state_descriptor_offset;
830 u32 avail_scratch_ram_locations;
831 u32 reg_restore_list_size;
832 u32 reg_list_format_start;
833 u32 reg_list_format_separate_start;
834 u32 starting_offsets_start;
835 u32 reg_list_format_size_bytes;
836 u32 reg_list_size_bytes;
837
838 u32 *register_list_format;
839 u32 *register_restore;
97b2e202
AD		 840};
841
78c16834
AR		 842#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
843
97b2e202
AD		 844struct amdgpu_mec {
845 struct amdgpu_bo *hpd_eop_obj;
846 u64 hpd_eop_gpu_addr;
b1023571
KW		 847 struct amdgpu_bo *mec_fw_obj;
848 u64 mec_fw_gpu_addr;
97b2e202 849 u32 num_mec;
42794b27
AR		 850 u32 num_pipe_per_mec;
851 u32 num_queue_per_pipe;
59a82d7d 852 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 853
854 /* These are the resources for which amdgpu takes ownership */
855 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 856};
857
4e638ae9
XY		 858struct amdgpu_kiq {
859 u64 eop_gpu_addr;
860 struct amdgpu_bo *eop_obj;
cdf6adb2 861 struct mutex ring_mutex;
4e638ae9
XY		 862 struct amdgpu_ring ring;
863 struct amdgpu_irq_src irq;
864};
865
97b2e202
AD		 866/*
867 * GPU scratch registers structures, functions & helpers
868 */
869struct amdgpu_scratch {
870 unsigned num_reg;
871 uint32_t reg_base;
50261151 872 uint32_t free_mask;
97b2e202
AD		 873};
874
875/*
876 * GFX configurations
877 */
e3fa7630
AD		 878#define AMDGPU_GFX_MAX_SE 4
879#define AMDGPU_GFX_MAX_SH_PER_SE 2
880
881struct amdgpu_rb_config {
882 uint32_t rb_backend_disable;
883 uint32_t user_rb_backend_disable;
884 uint32_t raster_config;
885 uint32_t raster_config_1;
886};
887
d0e95758
AG		 888struct gb_addr_config {
889 uint16_t pipe_interleave_size;
890 uint8_t num_pipes;
891 uint8_t max_compress_frags;
892 uint8_t num_banks;
893 uint8_t num_se;
894 uint8_t num_rb_per_se;
895};
896
ea323f88 897struct amdgpu_gfx_config {
97b2e202
AD		 898 unsigned max_shader_engines;
899 unsigned max_tile_pipes;
900 unsigned max_cu_per_sh;
901 unsigned max_sh_per_se;
902 unsigned max_backends_per_se;
903 unsigned max_texture_channel_caches;
904 unsigned max_gprs;
905 unsigned max_gs_threads;
906 unsigned max_hw_contexts;
907 unsigned sc_prim_fifo_size_frontend;
908 unsigned sc_prim_fifo_size_backend;
909 unsigned sc_hiz_tile_fifo_size;
910 unsigned sc_earlyz_tile_fifo_size;
911
912 unsigned num_tile_pipes;
913 unsigned backend_enable_mask;
914 unsigned mem_max_burst_length_bytes;
915 unsigned mem_row_size_in_kb;
916 unsigned shader_engine_tile_size;
917 unsigned num_gpus;
918 unsigned multi_gpu_tile_size;
919 unsigned mc_arb_ramcfg;
920 unsigned gb_addr_config;
8f8e00c1 921 unsigned num_rbs;
408bfe7c
JZ		 922 unsigned gs_vgt_table_depth;
923 unsigned gs_prim_buffer_depth;
97b2e202
AD		 924
925 uint32_t tile_mode_array[32];
926 uint32_t macrotile_mode_array[16];
e3fa7630 927
d0e95758 928 struct gb_addr_config gb_addr_config_fields;
e3fa7630 929 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 930
931 /* gfx configure feature */
932 uint32_t double_offchip_lds_buf;
97b2e202
AD		 933};
934
7dae69a2 935struct amdgpu_cu_info {
51fd0370 936 uint32_t max_waves_per_simd;
408bfe7c 937 uint32_t wave_front_size;
51fd0370
HZ		 938 uint32_t max_scratch_slots_per_cu;
939 uint32_t lds_size;
dbfe85ea
FC		 940
941 /* total active CU number */
942 uint32_t number;
943 uint32_t ao_cu_mask;
944 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 945 uint32_t bitmap[4][4];
946};
947
b95e31fd
AD		 948struct amdgpu_gfx_funcs {
949 /* get the gpu clock counter */
950 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 951 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 952 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 953 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
954 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 955};
956
bce23e00
AD		 957struct amdgpu_ngg_buf {
958 struct amdgpu_bo *bo;
959 uint64_t gpu_addr;
960 uint32_t size;
961 uint32_t bo_size;
962};
963
964enum {
af8baf15
GR		 965 NGG_PRIM = 0,
966 NGG_POS,
967 NGG_CNTL,
968 NGG_PARAM,
bce23e00
AD		 969 NGG_BUF_MAX
970};
971
972struct amdgpu_ngg {
973 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
974 uint32_t gds_reserve_addr;
975 uint32_t gds_reserve_size;
976 bool init;
977};
978
97b2e202
AD		 979struct amdgpu_gfx {
980 struct mutex gpu_clock_mutex;
ea323f88 981 struct amdgpu_gfx_config config;
97b2e202
AD		 982 struct amdgpu_rlc rlc;
983 struct amdgpu_mec mec;
4e638ae9 984 struct amdgpu_kiq kiq;
97b2e202
AD		 985 struct amdgpu_scratch scratch;
986 const struct firmware *me_fw; /* ME firmware */
987 uint32_t me_fw_version;
988 const struct firmware *pfp_fw; /* PFP firmware */
989 uint32_t pfp_fw_version;
990 const struct firmware *ce_fw; /* CE firmware */
991 uint32_t ce_fw_version;
992 const struct firmware *rlc_fw; /* RLC firmware */
993 uint32_t rlc_fw_version;
994 const struct firmware *mec_fw; /* MEC firmware */
995 uint32_t mec_fw_version;
996 const struct firmware *mec2_fw; /* MEC2 firmware */
997 uint32_t mec2_fw_version;
02558a00
KW		 998 uint32_t me_feature_version;
999 uint32_t ce_feature_version;
1000 uint32_t pfp_feature_version;
351643d7
JZ		 1001 uint32_t rlc_feature_version;
1002 uint32_t mec_feature_version;
1003 uint32_t mec2_feature_version;
97b2e202
AD		 1004 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1005 unsigned num_gfx_rings;
1006 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1007 unsigned num_compute_rings;
1008 struct amdgpu_irq_src eop_irq;
1009 struct amdgpu_irq_src priv_reg_irq;
1010 struct amdgpu_irq_src priv_inst_irq;
1011 /* gfx status */
7dae69a2 1012 uint32_t gfx_current_status;
a101a899 1013 /* ce ram size*/
7dae69a2
AD		 1014 unsigned ce_ram_size;
1015 struct amdgpu_cu_info cu_info;
b95e31fd 1016 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1017
1018 /* reset mask */
1019 uint32_t grbm_soft_reset;
1020 uint32_t srbm_soft_reset;
b4e40676
DP		 1021 /* s3/s4 mask */
1022 bool in_suspend;
bce23e00
AD		 1023 /* NGG */
1024 struct amdgpu_ngg ngg;
97b2e202
AD		 1025};
1026
b07c60c0 1027int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1028 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1029void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1030 struct dma_fence *f);
b07c60c0 1031int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1032 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1033 struct dma_fence **f);
97b2e202
AD		 1034int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1035void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1036int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1037
1038/*
1039 * CS.
1040 */
1041struct amdgpu_cs_chunk {
1042 uint32_t chunk_id;
1043 uint32_t length_dw;
758ac17f 1044 void *kdata;
97b2e202
AD		 1045};
1046
1047struct amdgpu_cs_parser {
1048 struct amdgpu_device *adev;
1049 struct drm_file *filp;
3cb485f3 1050 struct amdgpu_ctx *ctx;
c3cca41e 1051
97b2e202
AD		 1052 /* chunks */
1053 unsigned nchunks;
1054 struct amdgpu_cs_chunk *chunks;
97b2e202 1055
50838c8c
CK		 1056 /* scheduler job object */
1057 struct amdgpu_job *job;
97b2e202 1058
c3cca41e
CK		 1059 /* buffer objects */
1060 struct ww_acquire_ctx ticket;
1061 struct amdgpu_bo_list *bo_list;
3fe89771 1062 struct amdgpu_mn *mn;
c3cca41e
CK		 1063 struct amdgpu_bo_list_entry vm_pd;
1064 struct list_head validated;
f54d1867 1065 struct dma_fence *fence;
c3cca41e 1066 uint64_t bytes_moved_threshold;
00f06b24 1067 uint64_t bytes_moved_vis_threshold;
c3cca41e 1068 uint64_t bytes_moved;
00f06b24 1069 uint64_t bytes_moved_vis;
662bfa61 1070 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1071
1072 /* user fence */
91acbeb6 1073 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1074
1075 unsigned num_post_dep_syncobjs;
1076 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1077};
1078
753ad49c
ML		 1079#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1080#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1081#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1082
bb977d37
CZ		 1083struct amdgpu_job {
1084 struct amd_sched_job base;
1085 struct amdgpu_device *adev;
edf600da 1086 struct amdgpu_vm *vm;
b07c60c0 1087 struct amdgpu_ring *ring;
e86f9cee 1088 struct amdgpu_sync sync;
a340c7bc 1089 struct amdgpu_sync dep_sync;
df83d1eb 1090 struct amdgpu_sync sched_sync;
bb977d37 1091 struct amdgpu_ib *ibs;
f54d1867 1092 struct dma_fence *fence; /* the hw fence */
753ad49c 1093 uint32_t preamble_status;
bb977d37 1094 uint32_t num_ibs;
e2840221 1095 void *owner;
3aecd24c 1096 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1097 bool vm_needs_flush;
d88bf583
CK		 1098 unsigned vm_id;
1099 uint64_t vm_pd_addr;
1100 uint32_t gds_base, gds_size;
1101 uint32_t gws_base, gws_size;
1102 uint32_t oa_base, oa_size;
758ac17f
CK		 1103
1104 /* user fence handling */
b5f5acbc 1105 uint64_t uf_addr;
758ac17f
CK		 1106 uint64_t uf_sequence;
1107
bb977d37 1108};
a6db8a33
JZ		 1109#define to_amdgpu_job(sched_job) \
1110 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1111
7270f839
CK		 1112static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1113 uint32_t ib_idx, int idx)
97b2e202 1114{
50838c8c 1115 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1116}
1117
7270f839
CK		 1118static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1119 uint32_t ib_idx, int idx,
1120 uint32_t value)
1121{
50838c8c 1122 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1123}
1124
97b2e202
AD		 1125/*
1126 * Writeback
1127 */
1128#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1129
1130struct amdgpu_wb {
1131 struct amdgpu_bo *wb_obj;
1132 volatile uint32_t *wb;
1133 uint64_t gpu_addr;
1134 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1135 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1136};
1137
1138int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1139void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1140
d0dd7f0c
AD		 1141void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1142
97b2e202
AD		 1143/*
1144 * SDMA
1145 */
c113ea1c 1146struct amdgpu_sdma_instance {
97b2e202
AD		 1147 /* SDMA firmware */
1148 const struct firmware *fw;
1149 uint32_t fw_version;
cfa2104f 1150 uint32_t feature_version;
97b2e202
AD		 1151
1152 struct amdgpu_ring ring;
18111de0 1153 bool burst_nop;
97b2e202
AD		 1154};
1155
c113ea1c
AD		 1156struct amdgpu_sdma {
1157 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1158#ifdef CONFIG_DRM_AMDGPU_SI
1159 //SI DMA has a difference trap irq number for the second engine
1160 struct amdgpu_irq_src trap_irq_1;
1161#endif
c113ea1c
AD		 1162 struct amdgpu_irq_src trap_irq;
1163 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1164 int num_instances;
e702a680 1165 uint32_t srbm_soft_reset;
c113ea1c
AD		 1166};
1167
97b2e202
AD		 1168/*
1169 * Firmware
1170 */
e635ee07
HR		 1171enum amdgpu_firmware_load_type {
1172 AMDGPU_FW_LOAD_DIRECT = 0,
1173 AMDGPU_FW_LOAD_SMU,
1174 AMDGPU_FW_LOAD_PSP,
1175};
1176
97b2e202
AD		 1177struct amdgpu_firmware {
1178 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1179 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1180 struct amdgpu_bo *fw_buf;
1181 unsigned int fw_size;
2445b227 1182 unsigned int max_ucodes;
0e5ca0d1
HR		 1183 /* firmwares are loaded by psp instead of smu from vega10 */
1184 const struct amdgpu_psp_funcs *funcs;
1185 struct amdgpu_bo *rbuf;
1186 struct mutex mutex;
ab4fe3e1
HR		 1187
1188 /* gpu info firmware data pointer */
1189 const struct firmware *gpu_info_fw;
97b2e202
AD		 1190};
1191
1192/*
1193 * Benchmarking
1194 */
1195void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1196
1197
1198/*
1199 * Testing
1200 */
1201void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1202
97b2e202
AD		 1203/*
1204 * Debugfs
1205 */
1206struct amdgpu_debugfs {
06ab6832 1207 const struct drm_info_list *files;
97b2e202
AD		 1208 unsigned num_files;
1209};
1210
1211int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1212 const struct drm_info_list *files,
97b2e202
AD		 1213 unsigned nfiles);
1214int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1215
1216#if defined(CONFIG_DEBUG_FS)
1217int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1218#endif
1219
50ab2533
HR		 1220int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1221
97b2e202
AD		 1222/*
1223 * amdgpu smumgr functions
1224 */
1225struct amdgpu_smumgr_funcs {
1226 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1227 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1228 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1229};
1230
1231/*
1232 * amdgpu smumgr
1233 */
1234struct amdgpu_smumgr {
1235 struct amdgpu_bo *toc_buf;
1236 struct amdgpu_bo *smu_buf;
1237 /* asic priv smu data */
1238 void *priv;
1239 spinlock_t smu_lock;
1240 /* smumgr functions */
1241 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1242 /* ucode loading complete flag */
1243 uint32_t fw_flags;
1244};
1245
1246/*
1247 * ASIC specific register table accessible by UMD
1248 */
1249struct amdgpu_allowed_register_entry {
1250 uint32_t reg_offset;
97b2e202
AD		 1251 bool grbm_indexed;
1252};
1253
97b2e202
AD		 1254/*
1255 * ASIC specific functions.
1256 */
1257struct amdgpu_asic_funcs {
1258 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1259 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1260 u8 *bios, u32 length_bytes);
97b2e202
AD		 1261 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1262 u32 sh_num, u32 reg_offset, u32 *value);
1263 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1264 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1265 /* get the reference clock */
1266 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1267 /* MM block clocks */
1268 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1269 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1270 /* static power management */
1271 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1272 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1273 /* get config memsize register */
1274 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1275};
1276
1277/*
1278 * IOCTL.
1279 */
1280int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1281 struct drm_file *filp);
1282int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1283 struct drm_file *filp);
1284
1285int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1286 struct drm_file *filp);
1287int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1288 struct drm_file *filp);
1289int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1290 struct drm_file *filp);
1291int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1292 struct drm_file *filp);
1293int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1294 struct drm_file *filp);
1295int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1296 struct drm_file *filp);
1297int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1298int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1299int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1300 struct drm_file *filp);
97b2e202
AD		 1301
1302int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1303 struct drm_file *filp);
1304
1305/* VRAM scratch page for HDP bug, default vram page */
1306struct amdgpu_vram_scratch {
1307 struct amdgpu_bo *robj;
1308 volatile uint32_t *ptr;
1309 u64 gpu_addr;
1310};
1311
1312/*
1313 * ACPI
1314 */
1315struct amdgpu_atif_notification_cfg {
1316 bool enabled;
1317 int command_code;
1318};
1319
1320struct amdgpu_atif_notifications {
1321 bool display_switch;
1322 bool expansion_mode_change;
1323 bool thermal_state;
1324 bool forced_power_state;
1325 bool system_power_state;
1326 bool display_conf_change;
1327 bool px_gfx_switch;
1328 bool brightness_change;
1329 bool dgpu_display_event;
1330};
1331
1332struct amdgpu_atif_functions {
1333 bool system_params;
1334 bool sbios_requests;
1335 bool select_active_disp;
1336 bool lid_state;
1337 bool get_tv_standard;
1338 bool set_tv_standard;
1339 bool get_panel_expansion_mode;
1340 bool set_panel_expansion_mode;
1341 bool temperature_change;
1342 bool graphics_device_types;
1343};
1344
1345struct amdgpu_atif {
1346 struct amdgpu_atif_notifications notifications;
1347 struct amdgpu_atif_functions functions;
1348 struct amdgpu_atif_notification_cfg notification_cfg;
1349 struct amdgpu_encoder *encoder_for_bl;
1350};
1351
1352struct amdgpu_atcs_functions {
1353 bool get_ext_state;
1354 bool pcie_perf_req;
1355 bool pcie_dev_rdy;
1356 bool pcie_bus_width;
1357};
1358
1359struct amdgpu_atcs {
1360 struct amdgpu_atcs_functions functions;
1361};
1362
d03846af
CZ		 1363/*
1364 * CGS
1365 */
110e6f26
DA		 1366struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1367void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1368
97b2e202
AD		 1369/*
1370 * Core structure, functions and helpers.
1371 */
1372typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1373typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1374
1375typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1376typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1377
0c49e0b8 1378#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1379struct amdgpu_device {
1380 struct device *dev;
1381 struct drm_device *ddev;
1382 struct pci_dev *pdev;
97b2e202 1383
a8fe58ce
MB		 1384#ifdef CONFIG_DRM_AMD_ACP
1385 struct amdgpu_acp acp;
1386#endif
1387
97b2e202 1388 /* ASIC */
2f7d10b3 1389 enum amd_asic_type asic_type;
97b2e202
AD		 1390 uint32_t family;
1391 uint32_t rev_id;
1392 uint32_t external_rev_id;
1393 unsigned long flags;
1394 int usec_timeout;
1395 const struct amdgpu_asic_funcs *asic_funcs;
1396 bool shutdown;
97b2e202
AD		 1397 bool need_dma32;
1398 bool accel_working;
edf600da 1399 struct work_struct reset_work;
97b2e202
AD		 1400 struct notifier_block acpi_nb;
1401 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1402 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1403 unsigned debugfs_count;
97b2e202 1404#if defined(CONFIG_DEBUG_FS)
adcec288 1405 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1406#endif
1407 struct amdgpu_atif atif;
1408 struct amdgpu_atcs atcs;
1409 struct mutex srbm_mutex;
1410 /* GRBM index mutex. Protects concurrent access to GRBM index */
1411 struct mutex grbm_idx_mutex;
1412 struct dev_pm_domain vga_pm_domain;
1413 bool have_disp_power_ref;
1414
1415 /* BIOS */
0cdd5005 1416 bool is_atom_fw;
97b2e202 1417 uint8_t *bios;
a9f5db9c 1418 uint32_t bios_size;
5af2c10d 1419 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1420 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1421 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1422
1423 /* Register/doorbell mmio */
1424 resource_size_t rmmio_base;
1425 resource_size_t rmmio_size;
1426 void __iomem *rmmio;
1427 /* protects concurrent MM_INDEX/DATA based register access */
1428 spinlock_t mmio_idx_lock;
1429 /* protects concurrent SMC based register access */
1430 spinlock_t smc_idx_lock;
1431 amdgpu_rreg_t smc_rreg;
1432 amdgpu_wreg_t smc_wreg;
1433 /* protects concurrent PCIE register access */
1434 spinlock_t pcie_idx_lock;
1435 amdgpu_rreg_t pcie_rreg;
1436 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1437 amdgpu_rreg_t pciep_rreg;
1438 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1439 /* protects concurrent UVD register access */
1440 spinlock_t uvd_ctx_idx_lock;
1441 amdgpu_rreg_t uvd_ctx_rreg;
1442 amdgpu_wreg_t uvd_ctx_wreg;
1443 /* protects concurrent DIDT register access */
1444 spinlock_t didt_idx_lock;
1445 amdgpu_rreg_t didt_rreg;
1446 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1447 /* protects concurrent gc_cac register access */
1448 spinlock_t gc_cac_idx_lock;
1449 amdgpu_rreg_t gc_cac_rreg;
1450 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1451 /* protects concurrent se_cac register access */
1452 spinlock_t se_cac_idx_lock;
1453 amdgpu_rreg_t se_cac_rreg;
1454 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1455 /* protects concurrent ENDPOINT (audio) register access */
1456 spinlock_t audio_endpt_idx_lock;
1457 amdgpu_block_rreg_t audio_endpt_rreg;
1458 amdgpu_block_wreg_t audio_endpt_wreg;
1459 void __iomem *rio_mem;
1460 resource_size_t rio_mem_size;
1461 struct amdgpu_doorbell doorbell;
1462
1463 /* clock/pll info */
1464 struct amdgpu_clock clock;
1465
1466 /* MC */
1467 struct amdgpu_mc mc;
1468 struct amdgpu_gart gart;
1469 struct amdgpu_dummy_page dummy_page;
1470 struct amdgpu_vm_manager vm_manager;
e60f8db5 1471 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1472
1473 /* memory management */
1474 struct amdgpu_mman mman;
97b2e202
AD		 1475 struct amdgpu_vram_scratch vram_scratch;
1476 struct amdgpu_wb wb;
97b2e202 1477 atomic64_t num_bytes_moved;
dbd5ed60 1478 atomic64_t num_evictions;
68e2c5ff 1479 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1480 atomic_t gpu_reset_counter;
f1892138 1481 atomic_t vram_lost_counter;
97b2e202 1482
95844d20
MO		 1483 /* data for buffer migration throttling */
1484 struct {
1485 spinlock_t lock;
1486 s64 last_update_us;
1487 s64 accum_us; /* accumulated microseconds */
00f06b24 1488 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1489 u32 log2_max_MBps;
1490 } mm_stats;
1491
97b2e202 1492 /* display */
9accf2fd 1493 bool enable_virtual_display;
97b2e202
AD		 1494 struct amdgpu_mode_info mode_info;
1495 struct work_struct hotplug_work;
1496 struct amdgpu_irq_src crtc_irq;
1497 struct amdgpu_irq_src pageflip_irq;
1498 struct amdgpu_irq_src hpd_irq;
1499
1500 /* rings */
76bf0db5 1501 u64 fence_context;
97b2e202
AD		 1502 unsigned num_rings;
1503 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1504 bool ib_pool_ready;
1505 struct amdgpu_sa_manager ring_tmp_bo;
1506
1507 /* interrupts */
1508 struct amdgpu_irq irq;
1509
1f7371b2
AD		 1510 /* powerplay */
1511 struct amd_powerplay powerplay;
e61710c5 1512 bool pp_enabled;
f3898ea1 1513 bool pp_force_state_enabled;
1f7371b2 1514
97b2e202
AD		 1515 /* dpm */
1516 struct amdgpu_pm pm;
1517 u32 cg_flags;
1518 u32 pg_flags;
1519
1520 /* amdgpu smumgr */
1521 struct amdgpu_smumgr smu;
1522
1523 /* gfx */
1524 struct amdgpu_gfx gfx;
1525
1526 /* sdma */
c113ea1c 1527 struct amdgpu_sdma sdma;
97b2e202 1528
95d0906f
LL		 1529 union {
1530 struct {
1531 /* uvd */
1532 struct amdgpu_uvd uvd;
1533
1534 /* vce */
1535 struct amdgpu_vce vce;
1536 };
97b2e202 1537
95d0906f
LL		 1538 /* vcn */
1539 struct amdgpu_vcn vcn;
1540 };
97b2e202
AD		 1541
1542 /* firmwares */
1543 struct amdgpu_firmware firmware;
1544
0e5ca0d1
HR		 1545 /* PSP */
1546 struct psp_context psp;
1547
97b2e202
AD		 1548 /* GDS */
1549 struct amdgpu_gds gds;
1550
a1255107 1551 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1552 int num_ip_blocks;
97b2e202
AD		 1553 struct mutex mn_lock;
1554 DECLARE_HASHTABLE(mn_hash, 7);
1555
1556 /* tracking pinned memory */
1557 u64 vram_pin_size;
e131b914 1558 u64 invisible_pin_size;
97b2e202 1559 u64 gart_pin_size;
130e0371
OG		 1560
1561 /* amdkfd interface */
1562 struct kfd_dev *kfd;
23ca0e4e 1563
2dc80b00
S		 1564 /* delayed work_func for deferring clockgating during resume */
1565 struct delayed_work late_init_work;
1566
5a5099cb 1567 struct amdgpu_virt virt;
0c4e7fa5
CZ		 1568
1569 /* link all shadow bo */
1570 struct list_head shadow_list;
1571 struct mutex shadow_list_lock;
5c1354bd
CZ		 1572 /* link all gtt */
1573 spinlock_t gtt_list_lock;
1574 struct list_head gtt_list;
795f2813
AR		 1575 /* keep an lru list of rings by HW IP */
1576 struct list_head ring_lru_list;
1577 spinlock_t ring_lru_list_lock;
5c1354bd 1578
c836fec5
JQ		 1579 /* record hw reset is performed */
1580 bool has_hw_reset;
0c49e0b8 1581 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1582
47ed4e1c
KW		 1583 /* record last mm index being written through WREG32*/
1584 unsigned long last_mm_index;
3224a12b 1585 bool in_sriov_reset;
97b2e202
AD		 1586};
1587
a7d64de6
CK		 1588static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1589{
1590 return container_of(bdev, struct amdgpu_device, mman.bdev);
1591}
1592
97b2e202
AD		 1593int amdgpu_device_init(struct amdgpu_device *adev,
1594 struct drm_device *ddev,
1595 struct pci_dev *pdev,
1596 uint32_t flags);
1597void amdgpu_device_fini(struct amdgpu_device *adev);
1598int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1599
1600uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1601 uint32_t acc_flags);
97b2e202 1602void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1603 uint32_t acc_flags);
97b2e202
AD		 1604u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1605void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1606
1607u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1608void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1609u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1610void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1611
97b2e202
AD		 1612/*
1613 * Registers read & write functions.
1614 */
15d72fd7
ML		 1615
1616#define AMDGPU_REGS_IDX (1<<0)
1617#define AMDGPU_REGS_NO_KIQ (1<<1)
1618
1619#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1620#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1621
1622#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1623#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1624#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1625#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1626#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1627#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1628#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1629#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1630#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1631#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1632#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1633#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1634#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1635#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1636#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1637#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1638#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1639#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1640#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1641#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1642#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1643#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1644#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1645#define WREG32_P(reg, val, mask) \
1646 do { \
1647 uint32_t tmp_ = RREG32(reg); \
1648 tmp_ &= (mask); \
1649 tmp_ |= ((val) & ~(mask)); \
1650 WREG32(reg, tmp_); \
1651 } while (0)
1652#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1653#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1654#define WREG32_PLL_P(reg, val, mask) \
1655 do { \
1656 uint32_t tmp_ = RREG32_PLL(reg); \
1657 tmp_ &= (mask); \
1658 tmp_ |= ((val) & ~(mask)); \
1659 WREG32_PLL(reg, tmp_); \
1660 } while (0)
1661#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1662#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1663#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1664
1665#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1666#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1667#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1668#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1669
1670#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1671#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1672
1673#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1674 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1675 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1676
1677#define REG_GET_FIELD(value, reg, field) \
1678 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1679
1680#define WREG32_FIELD(reg, field, val) \
1681 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1682
ccaf3574
TSD		 1683#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1684 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1685
97b2e202
AD		 1686/*
1687 * BIOS helpers.
1688 */
1689#define RBIOS8(i) (adev->bios[i])
1690#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1691#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1692
c113ea1c
AD		 1693static inline struct amdgpu_sdma_instance *
1694amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1695{
1696 struct amdgpu_device *adev = ring->adev;
1697 int i;
1698
c113ea1c
AD		 1699 for (i = 0; i < adev->sdma.num_instances; i++)
1700 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1701 break;
1702
1703 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1704 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1705 else
1706 return NULL;
1707}
1708
97b2e202
AD		 1709/*
1710 * ASICs macro.
1711 */
1712#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1713#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1714#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1715#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1716#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1717#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1718#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1719#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1720#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1721#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1722#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1723#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1724#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1725#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1726#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1727#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1728#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1729#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1730#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1731#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1732#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1733#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1734#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1735#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1736#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1737#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1738#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1739#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1740#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1741#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1742#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1743#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1744#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1745#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1746#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1747#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1748#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1749#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1750#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1751#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1752#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1753#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1754#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1755#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1756#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1757#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1758#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1759#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1760#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1761#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1762#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1763#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1764#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1765#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1766#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1767#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1768#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1769#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1770#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1771#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1772#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1773#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1774
1775/* Common functions */
1776int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1777bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1778void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1779bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1780void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1781
00f06b24
JB		 1782void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1783 u64 num_vis_bytes);
765e7fbf 1784void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1785bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1786void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1787void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
97b2e202 1788void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1789int amdgpu_ttm_init(struct amdgpu_device *adev);
1790void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1791void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1792 const u32 *registers,
1793 const u32 array_size);
1794
1795bool amdgpu_device_is_px(struct drm_device *dev);
1796/* atpx handler */
1797#if defined(CONFIG_VGA_SWITCHEROO)
1798void amdgpu_register_atpx_handler(void);
1799void amdgpu_unregister_atpx_handler(void);
a78fe133 1800bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1801bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1802bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1803bool amdgpu_has_atpx(void);
97b2e202
AD		 1804#else
1805static inline void amdgpu_register_atpx_handler(void) {}
1806static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1807static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1808static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1809static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1810static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1811#endif
1812
1813/*
1814 * KMS
1815 */
1816extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1817extern const int amdgpu_max_kms_ioctl;
97b2e202 1818
f1892138
CZ		 1819bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1820 struct amdgpu_fpriv *fpriv);
97b2e202 1821int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1822void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1823void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1824int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1825void amdgpu_driver_postclose_kms(struct drm_device *dev,
1826 struct drm_file *file_priv);
faefba95 1827int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1828int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1829int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1830u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1831int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1832void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1833long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1834 unsigned long arg);
1835
97b2e202
AD		 1836/*
1837 * functions used by amdgpu_encoder.c
1838 */
1839struct amdgpu_afmt_acr {
1840 u32 clock;
1841
1842 int n_32khz;
1843 int cts_32khz;
1844
1845 int n_44_1khz;
1846 int cts_44_1khz;
1847
1848 int n_48khz;
1849 int cts_48khz;
1850
1851};
1852
1853struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1854
1855/* amdgpu_acpi.c */
1856#if defined(CONFIG_ACPI)
1857int amdgpu_acpi_init(struct amdgpu_device *adev);
1858void amdgpu_acpi_fini(struct amdgpu_device *adev);
1859bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1860int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1861 u8 perf_req, bool advertise);
1862int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1863#else
1864static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1865static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1866#endif
1867
9cca0b8e
CK		 1868int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1869 uint64_t addr, struct amdgpu_bo **bo,
1870 struct amdgpu_bo_va_mapping **mapping);
97b2e202
AD		 1871
1872#include "amdgpu_object.h"
97b2e202 1873#endif
Linux 6.x block layer and io_uring tree(s)