Commit | Line | Data |
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97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
31 | #include <linux/atomic.h> | |
32 | #include <linux/wait.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
a9f87f64 | 35 | #include <linux/rbtree.h> |
97b2e202 | 36 | #include <linux/hashtable.h> |
f54d1867 | 37 | #include <linux/dma-fence.h> |
97b2e202 | 38 | |
248a1d6f MY |
39 | #include <drm/ttm/ttm_bo_api.h> |
40 | #include <drm/ttm/ttm_bo_driver.h> | |
41 | #include <drm/ttm/ttm_placement.h> | |
42 | #include <drm/ttm/ttm_module.h> | |
43 | #include <drm/ttm/ttm_execbuf_util.h> | |
97b2e202 | 44 | |
d03846af | 45 | #include <drm/drmP.h> |
97b2e202 | 46 | #include <drm/drm_gem.h> |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
1b1f42d8 | 48 | #include <drm/gpu_scheduler.h> |
97b2e202 | 49 | |
78c16834 | 50 | #include <kgd_kfd_interface.h> |
c79563a3 RZ |
51 | #include "dm_pp_interface.h" |
52 | #include "kgd_pp_interface.h" | |
78c16834 | 53 | |
5fc3aeeb | 54 | #include "amd_shared.h" |
97b2e202 AD |
55 | #include "amdgpu_mode.h" |
56 | #include "amdgpu_ih.h" | |
57 | #include "amdgpu_irq.h" | |
58 | #include "amdgpu_ucode.h" | |
c632d799 | 59 | #include "amdgpu_ttm.h" |
0e5ca0d1 | 60 | #include "amdgpu_psp.h" |
97b2e202 | 61 | #include "amdgpu_gds.h" |
56113504 | 62 | #include "amdgpu_sync.h" |
78023016 | 63 | #include "amdgpu_ring.h" |
073440d2 | 64 | #include "amdgpu_vm.h" |
cf097881 | 65 | #include "amdgpu_dpm.h" |
a8fe58ce | 66 | #include "amdgpu_acp.h" |
4df654d2 | 67 | #include "amdgpu_uvd.h" |
5e568178 | 68 | #include "amdgpu_vce.h" |
95aa13f6 | 69 | #include "amdgpu_vcn.h" |
9a189996 | 70 | #include "amdgpu_mn.h" |
4562236b | 71 | #include "amdgpu_dm.h" |
ceeb50ed | 72 | #include "amdgpu_virt.h" |
3490bdb5 | 73 | #include "amdgpu_gart.h" |
75758255 | 74 | #include "amdgpu_debugfs.h" |
c79563a3 | 75 | |
97b2e202 AD |
76 | /* |
77 | * Modules parameters. | |
78 | */ | |
79 | extern int amdgpu_modeset; | |
80 | extern int amdgpu_vram_limit; | |
218b5dcd | 81 | extern int amdgpu_vis_vram_limit; |
83e74db6 | 82 | extern int amdgpu_gart_size; |
36d38372 | 83 | extern int amdgpu_gtt_size; |
95844d20 | 84 | extern int amdgpu_moverate; |
97b2e202 AD |
85 | extern int amdgpu_benchmarking; |
86 | extern int amdgpu_testing; | |
87 | extern int amdgpu_audio; | |
88 | extern int amdgpu_disp_priority; | |
89 | extern int amdgpu_hw_i2c; | |
90 | extern int amdgpu_pcie_gen2; | |
91 | extern int amdgpu_msi; | |
92 | extern int amdgpu_lockup_timeout; | |
93 | extern int amdgpu_dpm; | |
e635ee07 | 94 | extern int amdgpu_fw_load_type; |
97b2e202 AD |
95 | extern int amdgpu_aspm; |
96 | extern int amdgpu_runtime_pm; | |
0b693f0b | 97 | extern uint amdgpu_ip_block_mask; |
97b2e202 AD |
98 | extern int amdgpu_bapm; |
99 | extern int amdgpu_deep_color; | |
100 | extern int amdgpu_vm_size; | |
101 | extern int amdgpu_vm_block_size; | |
d07f14be | 102 | extern int amdgpu_vm_fragment_size; |
d9c13156 | 103 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 104 | extern int amdgpu_vm_debug; |
9a4b7d4c | 105 | extern int amdgpu_vm_update_mode; |
4562236b | 106 | extern int amdgpu_dc; |
02e749dc | 107 | extern int amdgpu_dc_log; |
1333f723 | 108 | extern int amdgpu_sched_jobs; |
4afcb303 | 109 | extern int amdgpu_sched_hw_submission; |
3ca67300 RZ |
110 | extern int amdgpu_no_evict; |
111 | extern int amdgpu_direct_gma_size; | |
0b693f0b RZ |
112 | extern uint amdgpu_pcie_gen_cap; |
113 | extern uint amdgpu_pcie_lane_cap; | |
114 | extern uint amdgpu_cg_mask; | |
115 | extern uint amdgpu_pg_mask; | |
116 | extern uint amdgpu_sdma_phase_quantum; | |
6f8941a2 | 117 | extern char *amdgpu_disable_cu; |
9accf2fd | 118 | extern char *amdgpu_virtual_display; |
0b693f0b | 119 | extern uint amdgpu_pp_feature_mask; |
6a7f76e7 | 120 | extern int amdgpu_vram_page_split; |
bce23e00 AD |
121 | extern int amdgpu_ngg; |
122 | extern int amdgpu_prim_buf_per_se; | |
123 | extern int amdgpu_pos_buf_per_se; | |
124 | extern int amdgpu_cntl_sb_buf_per_se; | |
125 | extern int amdgpu_param_buf_per_se; | |
65781c78 | 126 | extern int amdgpu_job_hang_limit; |
e8835e0e | 127 | extern int amdgpu_lbpw; |
4a75aefe | 128 | extern int amdgpu_compute_multipipe; |
dcebf026 | 129 | extern int amdgpu_gpu_recovery; |
97b2e202 | 130 | |
6dd13096 FK |
131 | #ifdef CONFIG_DRM_AMDGPU_SI |
132 | extern int amdgpu_si_support; | |
133 | #endif | |
7df28986 FK |
134 | #ifdef CONFIG_DRM_AMDGPU_CIK |
135 | extern int amdgpu_cik_support; | |
136 | #endif | |
97b2e202 | 137 | |
55ed8caf | 138 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
4b559c90 | 139 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 AD |
140 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
141 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
142 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | |
143 | #define AMDGPU_IB_POOL_SIZE 16 | |
144 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
145 | #define AMDGPUFB_CONN_LIMIT 4 | |
a5bde2f9 | 146 | #define AMDGPU_BIOS_NUM_SCRATCH 16 |
97b2e202 | 147 | |
36f523a7 JZ |
148 | /* max number of IP instances */ |
149 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | |
150 | ||
97b2e202 AD |
151 | /* hard reset data */ |
152 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
153 | ||
154 | /* reset flags */ | |
155 | #define AMDGPU_RESET_GFX (1 << 0) | |
156 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
157 | #define AMDGPU_RESET_DMA (1 << 2) | |
158 | #define AMDGPU_RESET_CP (1 << 3) | |
159 | #define AMDGPU_RESET_GRBM (1 << 4) | |
160 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
161 | #define AMDGPU_RESET_RLC (1 << 6) | |
162 | #define AMDGPU_RESET_SEM (1 << 7) | |
163 | #define AMDGPU_RESET_IH (1 << 8) | |
164 | #define AMDGPU_RESET_VMC (1 << 9) | |
165 | #define AMDGPU_RESET_MC (1 << 10) | |
166 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
167 | #define AMDGPU_RESET_UVD (1 << 12) | |
168 | #define AMDGPU_RESET_VCE (1 << 13) | |
169 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
170 | ||
97b2e202 AD |
171 | /* GFX current status */ |
172 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L | |
173 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L | |
174 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L | |
175 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L | |
176 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L | |
177 | ||
178 | /* max cursor sizes (in pixels) */ | |
179 | #define CIK_CURSOR_WIDTH 128 | |
180 | #define CIK_CURSOR_HEIGHT 128 | |
181 | ||
5740682e ML |
182 | /* GPU RESET flags */ |
183 | #define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0) | |
184 | #define AMDGPU_RESET_INFO_FULLRESET (1 << 1) | |
185 | ||
97b2e202 | 186 | struct amdgpu_device; |
97b2e202 | 187 | struct amdgpu_ib; |
97b2e202 | 188 | struct amdgpu_cs_parser; |
bb977d37 | 189 | struct amdgpu_job; |
97b2e202 | 190 | struct amdgpu_irq_src; |
0b492a4c | 191 | struct amdgpu_fpriv; |
9cca0b8e | 192 | struct amdgpu_bo_va_mapping; |
97b2e202 AD |
193 | |
194 | enum amdgpu_cp_irq { | |
195 | AMDGPU_CP_IRQ_GFX_EOP = 0, | |
196 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, | |
197 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
198 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
199 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
200 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
201 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
202 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
203 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
204 | ||
205 | AMDGPU_CP_IRQ_LAST | |
206 | }; | |
207 | ||
208 | enum amdgpu_sdma_irq { | |
209 | AMDGPU_SDMA_IRQ_TRAP0 = 0, | |
210 | AMDGPU_SDMA_IRQ_TRAP1, | |
211 | ||
212 | AMDGPU_SDMA_IRQ_LAST | |
213 | }; | |
214 | ||
215 | enum amdgpu_thermal_irq { | |
216 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
217 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
218 | ||
219 | AMDGPU_THERMAL_IRQ_LAST | |
220 | }; | |
221 | ||
4e638ae9 XY |
222 | enum amdgpu_kiq_irq { |
223 | AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, | |
224 | AMDGPU_CP_KIQ_IRQ_LAST | |
225 | }; | |
226 | ||
2990a1fc AD |
227 | int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, |
228 | enum amd_ip_block_type block_type, | |
229 | enum amd_clockgating_state state); | |
230 | int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, | |
231 | enum amd_ip_block_type block_type, | |
232 | enum amd_powergating_state state); | |
233 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, | |
234 | u32 *flags); | |
235 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, | |
236 | enum amd_ip_block_type block_type); | |
237 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, | |
238 | enum amd_ip_block_type block_type); | |
97b2e202 | 239 | |
a1255107 AD |
240 | #define AMDGPU_MAX_IP_NUM 16 |
241 | ||
242 | struct amdgpu_ip_block_status { | |
243 | bool valid; | |
244 | bool sw; | |
245 | bool hw; | |
246 | bool late_initialized; | |
247 | bool hang; | |
248 | }; | |
249 | ||
97b2e202 | 250 | struct amdgpu_ip_block_version { |
a1255107 AD |
251 | const enum amd_ip_block_type type; |
252 | const u32 major; | |
253 | const u32 minor; | |
254 | const u32 rev; | |
5fc3aeeb | 255 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
256 | }; |
257 | ||
a1255107 AD |
258 | struct amdgpu_ip_block { |
259 | struct amdgpu_ip_block_status status; | |
260 | const struct amdgpu_ip_block_version *version; | |
261 | }; | |
262 | ||
2990a1fc AD |
263 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
264 | enum amd_ip_block_type type, | |
265 | u32 major, u32 minor); | |
97b2e202 | 266 | |
2990a1fc AD |
267 | struct amdgpu_ip_block * |
268 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
269 | enum amd_ip_block_type type); | |
a1255107 | 270 | |
2990a1fc AD |
271 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
272 | const struct amdgpu_ip_block_version *ip_block_version); | |
97b2e202 AD |
273 | |
274 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ | |
275 | struct amdgpu_buffer_funcs { | |
276 | /* maximum bytes in a single operation */ | |
277 | uint32_t copy_max_bytes; | |
278 | ||
279 | /* number of dw to reserve per operation */ | |
280 | unsigned copy_num_dw; | |
281 | ||
282 | /* used for buffer migration */ | |
c7ae72c0 | 283 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
284 | /* src addr in bytes */ |
285 | uint64_t src_offset, | |
286 | /* dst addr in bytes */ | |
287 | uint64_t dst_offset, | |
288 | /* number of byte to transfer */ | |
289 | uint32_t byte_count); | |
290 | ||
291 | /* maximum bytes in a single operation */ | |
292 | uint32_t fill_max_bytes; | |
293 | ||
294 | /* number of dw to reserve per operation */ | |
295 | unsigned fill_num_dw; | |
296 | ||
297 | /* used for buffer clearing */ | |
6e7a3840 | 298 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
299 | /* value to write to memory */ |
300 | uint32_t src_data, | |
301 | /* dst addr in bytes */ | |
302 | uint64_t dst_offset, | |
303 | /* number of byte to fill */ | |
304 | uint32_t byte_count); | |
305 | }; | |
306 | ||
307 | /* provided by hw blocks that can write ptes, e.g., sdma */ | |
308 | struct amdgpu_vm_pte_funcs { | |
e6d92197 YZ |
309 | /* number of dw to reserve per operation */ |
310 | unsigned copy_pte_num_dw; | |
311 | ||
97b2e202 AD |
312 | /* copy pte entries from GART */ |
313 | void (*copy_pte)(struct amdgpu_ib *ib, | |
314 | uint64_t pe, uint64_t src, | |
315 | unsigned count); | |
e6d92197 | 316 | |
97b2e202 | 317 | /* write pte one entry at a time with addr mapping */ |
de9ea7bd CK |
318 | void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, |
319 | uint64_t value, unsigned count, | |
320 | uint32_t incr); | |
7bdc53f9 YZ |
321 | |
322 | /* maximum nums of PTEs/PDEs in a single operation */ | |
323 | uint32_t set_max_nums_pte_pde; | |
324 | ||
325 | /* number of dw to reserve per operation */ | |
326 | unsigned set_pte_pde_num_dw; | |
327 | ||
97b2e202 AD |
328 | /* for linear pte/pde updates without addr mapping */ |
329 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
330 | uint64_t pe, | |
331 | uint64_t addr, unsigned count, | |
6b777607 | 332 | uint32_t incr, uint64_t flags); |
97b2e202 AD |
333 | }; |
334 | ||
335 | /* provided by the gmc block */ | |
336 | struct amdgpu_gart_funcs { | |
337 | /* flush the vm tlb via mmio */ | |
338 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, | |
339 | uint32_t vmid); | |
340 | /* write pte/pde updates using the cpu */ | |
341 | int (*set_pte_pde)(struct amdgpu_device *adev, | |
342 | void *cpu_pt_addr, /* cpu addr of page table */ | |
343 | uint32_t gpu_page_idx, /* pte/pde to update */ | |
344 | uint64_t addr, /* addr to write into pte/pde */ | |
6b777607 | 345 | uint64_t flags); /* access flags */ |
284710fa CK |
346 | /* enable/disable PRT support */ |
347 | void (*set_prt)(struct amdgpu_device *adev, bool enable); | |
5463545b AX |
348 | /* set pte flags based per asic */ |
349 | uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, | |
350 | uint32_t flags); | |
b1166325 | 351 | /* get the pde for a given mc addr */ |
3de676d8 CK |
352 | void (*get_vm_pde)(struct amdgpu_device *adev, int level, |
353 | u64 *dst, u64 *flags); | |
c4f46f22 | 354 | uint32_t (*get_invalidate_req)(unsigned int vmid); |
e60f8db5 AX |
355 | }; |
356 | ||
97b2e202 AD |
357 | /* provided by the ih block */ |
358 | struct amdgpu_ih_funcs { | |
359 | /* ring read/write ptr handling, called from interrupt context */ | |
360 | u32 (*get_wptr)(struct amdgpu_device *adev); | |
00ecd8a2 | 361 | bool (*prescreen_iv)(struct amdgpu_device *adev); |
97b2e202 AD |
362 | void (*decode_iv)(struct amdgpu_device *adev, |
363 | struct amdgpu_iv_entry *entry); | |
364 | void (*set_rptr)(struct amdgpu_device *adev); | |
365 | }; | |
366 | ||
97b2e202 AD |
367 | /* |
368 | * BIOS. | |
369 | */ | |
370 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
371 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
372 | ||
373 | /* | |
374 | * Dummy page | |
375 | */ | |
376 | struct amdgpu_dummy_page { | |
377 | struct page *page; | |
378 | dma_addr_t addr; | |
379 | }; | |
97b2e202 AD |
380 | |
381 | /* | |
382 | * Clocks | |
383 | */ | |
384 | ||
385 | #define AMDGPU_MAX_PPLL 3 | |
386 | ||
387 | struct amdgpu_clock { | |
388 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
389 | struct amdgpu_pll spll; | |
390 | struct amdgpu_pll mpll; | |
391 | /* 10 Khz units */ | |
392 | uint32_t default_mclk; | |
393 | uint32_t default_sclk; | |
394 | uint32_t default_dispclk; | |
395 | uint32_t current_dispclk; | |
396 | uint32_t dp_extclk; | |
397 | uint32_t max_pixel_clock; | |
398 | }; | |
399 | ||
97b2e202 | 400 | /* |
9124a398 | 401 | * GEM. |
97b2e202 | 402 | */ |
97b2e202 | 403 | |
7e5a547f | 404 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
97b2e202 AD |
405 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) |
406 | ||
407 | void amdgpu_gem_object_free(struct drm_gem_object *obj); | |
408 | int amdgpu_gem_object_open(struct drm_gem_object *obj, | |
409 | struct drm_file *file_priv); | |
410 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
411 | struct drm_file *file_priv); | |
412 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); | |
413 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); | |
4d9c514d CK |
414 | struct drm_gem_object * |
415 | amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
416 | struct dma_buf_attachment *attach, | |
417 | struct sg_table *sg); | |
97b2e202 AD |
418 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, |
419 | struct drm_gem_object *gobj, | |
420 | int flags); | |
09052fc3 SL |
421 | struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, |
422 | struct dma_buf *dma_buf); | |
97b2e202 AD |
423 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); |
424 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); | |
425 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); | |
426 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); | |
427 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
dfced2e4 | 428 | int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
97b2e202 AD |
429 | |
430 | /* sub-allocation manager, it has to be protected by another lock. | |
431 | * By conception this is an helper for other part of the driver | |
432 | * like the indirect buffer or semaphore, which both have their | |
433 | * locking. | |
434 | * | |
435 | * Principe is simple, we keep a list of sub allocation in offset | |
436 | * order (first entry has offset == 0, last entry has the highest | |
437 | * offset). | |
438 | * | |
439 | * When allocating new object we first check if there is room at | |
440 | * the end total_size - (last_object_offset + last_object_size) >= | |
441 | * alloc_size. If so we allocate new object there. | |
442 | * | |
443 | * When there is not enough room at the end, we start waiting for | |
444 | * each sub object until we reach object_offset+object_size >= | |
445 | * alloc_size, this object then become the sub object we return. | |
446 | * | |
447 | * Alignment can't be bigger than page size. | |
448 | * | |
449 | * Hole are not considered for allocation to keep things simple. | |
450 | * Assumption is that there won't be hole (all object on same | |
451 | * alignment). | |
452 | */ | |
6ba60b89 CK |
453 | |
454 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 | |
455 | ||
97b2e202 AD |
456 | struct amdgpu_sa_manager { |
457 | wait_queue_head_t wq; | |
458 | struct amdgpu_bo *bo; | |
459 | struct list_head *hole; | |
6ba60b89 | 460 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
97b2e202 AD |
461 | struct list_head olist; |
462 | unsigned size; | |
463 | uint64_t gpu_addr; | |
464 | void *cpu_ptr; | |
465 | uint32_t domain; | |
466 | uint32_t align; | |
467 | }; | |
468 | ||
97b2e202 AD |
469 | /* sub-allocation buffer */ |
470 | struct amdgpu_sa_bo { | |
471 | struct list_head olist; | |
472 | struct list_head flist; | |
473 | struct amdgpu_sa_manager *manager; | |
474 | unsigned soffset; | |
475 | unsigned eoffset; | |
f54d1867 | 476 | struct dma_fence *fence; |
97b2e202 AD |
477 | }; |
478 | ||
479 | /* | |
480 | * GEM objects. | |
481 | */ | |
418aa0c2 | 482 | void amdgpu_gem_force_release(struct amdgpu_device *adev); |
97b2e202 | 483 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, |
e1eb899b CK |
484 | int alignment, u32 initial_domain, |
485 | u64 flags, bool kernel, | |
486 | struct reservation_object *resv, | |
487 | struct drm_gem_object **obj); | |
97b2e202 AD |
488 | |
489 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
490 | struct drm_device *dev, | |
491 | struct drm_mode_create_dumb *args); | |
492 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
493 | struct drm_device *dev, | |
494 | uint32_t handle, uint64_t *offset_p); | |
d573de2d RZ |
495 | int amdgpu_fence_slab_init(void); |
496 | void amdgpu_fence_slab_fini(void); | |
97b2e202 | 497 | |
e60f8db5 AX |
498 | /* |
499 | * VMHUB structures, functions & helpers | |
500 | */ | |
501 | struct amdgpu_vmhub { | |
502 | uint32_t ctx0_ptb_addr_lo32; | |
503 | uint32_t ctx0_ptb_addr_hi32; | |
504 | uint32_t vm_inv_eng0_req; | |
505 | uint32_t vm_inv_eng0_ack; | |
506 | uint32_t vm_context0_cntl; | |
507 | uint32_t vm_l2_pro_fault_status; | |
508 | uint32_t vm_l2_pro_fault_cntl; | |
e60f8db5 AX |
509 | }; |
510 | ||
97b2e202 AD |
511 | /* |
512 | * GPU MC structures, functions & helpers | |
513 | */ | |
514 | struct amdgpu_mc { | |
515 | resource_size_t aper_size; | |
516 | resource_size_t aper_base; | |
97b2e202 AD |
517 | /* for some chips with <= 32MB we need to lie |
518 | * about vram size near mc fb location */ | |
519 | u64 mc_vram_size; | |
520 | u64 visible_vram_size; | |
6f02a696 CK |
521 | u64 gart_size; |
522 | u64 gart_start; | |
523 | u64 gart_end; | |
97b2e202 AD |
524 | u64 vram_start; |
525 | u64 vram_end; | |
526 | unsigned vram_width; | |
527 | u64 real_vram_size; | |
528 | int vram_mtrr; | |
97b2e202 AD |
529 | u64 mc_mask; |
530 | const struct firmware *fw; /* MC firmware */ | |
531 | uint32_t fw_version; | |
532 | struct amdgpu_irq_src vm_fault; | |
81c59f54 | 533 | uint32_t vram_type; |
50b0197a | 534 | uint32_t srbm_soft_reset; |
f7c35abe | 535 | bool prt_warning; |
916910ad | 536 | uint64_t stolen_size; |
8fe73328 JZ |
537 | /* apertures */ |
538 | u64 shared_aperture_start; | |
539 | u64 shared_aperture_end; | |
540 | u64 private_aperture_start; | |
541 | u64 private_aperture_end; | |
e60f8db5 AX |
542 | /* protects concurrent invalidation */ |
543 | spinlock_t invalidate_lock; | |
6a42fd6f | 544 | bool translate_further; |
97b2e202 AD |
545 | }; |
546 | ||
547 | /* | |
548 | * GPU doorbell structures, functions & helpers | |
549 | */ | |
550 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
551 | { | |
552 | AMDGPU_DOORBELL_KIQ = 0x000, | |
553 | AMDGPU_DOORBELL_HIQ = 0x001, | |
554 | AMDGPU_DOORBELL_DIQ = 0x002, | |
555 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
556 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
557 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
558 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
559 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
560 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
561 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
562 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
563 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
564 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
565 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
566 | AMDGPU_DOORBELL_IH = 0x1E8, | |
567 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
568 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
569 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
570 | ||
571 | struct amdgpu_doorbell { | |
572 | /* doorbell mmio */ | |
573 | resource_size_t base; | |
574 | resource_size_t size; | |
575 | u32 __iomem *ptr; | |
576 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
577 | }; | |
578 | ||
39807b93 KW |
579 | /* |
580 | * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space | |
581 | */ | |
582 | typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT | |
583 | { | |
584 | /* | |
585 | * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in | |
586 | * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. | |
587 | * Compute related doorbells are allocated from 0x00 to 0x8a | |
588 | */ | |
589 | ||
590 | ||
591 | /* kernel scheduling */ | |
592 | AMDGPU_DOORBELL64_KIQ = 0x00, | |
593 | ||
594 | /* HSA interface queue and debug queue */ | |
595 | AMDGPU_DOORBELL64_HIQ = 0x01, | |
596 | AMDGPU_DOORBELL64_DIQ = 0x02, | |
597 | ||
598 | /* Compute engines */ | |
599 | AMDGPU_DOORBELL64_MEC_RING0 = 0x03, | |
600 | AMDGPU_DOORBELL64_MEC_RING1 = 0x04, | |
601 | AMDGPU_DOORBELL64_MEC_RING2 = 0x05, | |
602 | AMDGPU_DOORBELL64_MEC_RING3 = 0x06, | |
603 | AMDGPU_DOORBELL64_MEC_RING4 = 0x07, | |
604 | AMDGPU_DOORBELL64_MEC_RING5 = 0x08, | |
605 | AMDGPU_DOORBELL64_MEC_RING6 = 0x09, | |
606 | AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, | |
607 | ||
608 | /* User queue doorbell range (128 doorbells) */ | |
609 | AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, | |
610 | AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, | |
611 | ||
612 | /* Graphics engine */ | |
613 | AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, | |
614 | ||
615 | /* | |
616 | * Other graphics doorbells can be allocated here: from 0x8c to 0xef | |
617 | * Graphics voltage island aperture 1 | |
618 | * default non-graphics QWORD index is 0xF0 - 0xFF inclusive | |
619 | */ | |
620 | ||
621 | /* sDMA engines */ | |
622 | AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, | |
623 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, | |
624 | AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, | |
625 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, | |
626 | ||
627 | /* Interrupt handler */ | |
628 | AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ | |
629 | AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ | |
630 | AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ | |
631 | ||
e6b3ecb4 ML |
632 | /* VCN engine use 32 bits doorbell */ |
633 | AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ | |
634 | AMDGPU_DOORBELL64_VCN2_3 = 0xF9, | |
635 | AMDGPU_DOORBELL64_VCN4_5 = 0xFA, | |
636 | AMDGPU_DOORBELL64_VCN6_7 = 0xFB, | |
637 | ||
638 | /* overlap the doorbell assignment with VCN as they are mutually exclusive | |
639 | * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD | |
640 | */ | |
4ed11d79 FM |
641 | AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, |
642 | AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, | |
643 | AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, | |
644 | AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, | |
645 | ||
646 | AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, | |
647 | AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, | |
648 | AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, | |
649 | AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, | |
39807b93 KW |
650 | |
651 | AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, | |
652 | AMDGPU_DOORBELL64_INVALID = 0xFFFF | |
653 | } AMDGPU_DOORBELL64_ASSIGNMENT; | |
654 | ||
97b2e202 AD |
655 | /* |
656 | * IRQS. | |
657 | */ | |
658 | ||
659 | struct amdgpu_flip_work { | |
325cbba1 | 660 | struct delayed_work flip_work; |
97b2e202 AD |
661 | struct work_struct unpin_work; |
662 | struct amdgpu_device *adev; | |
663 | int crtc_id; | |
325cbba1 | 664 | u32 target_vblank; |
97b2e202 AD |
665 | uint64_t base; |
666 | struct drm_pending_vblank_event *event; | |
765e7fbf | 667 | struct amdgpu_bo *old_abo; |
f54d1867 | 668 | struct dma_fence *excl; |
1ffd2652 | 669 | unsigned shared_count; |
f54d1867 CW |
670 | struct dma_fence **shared; |
671 | struct dma_fence_cb cb; | |
cb9e59d7 | 672 | bool async; |
97b2e202 AD |
673 | }; |
674 | ||
675 | ||
676 | /* | |
677 | * CP & rings. | |
678 | */ | |
679 | ||
680 | struct amdgpu_ib { | |
681 | struct amdgpu_sa_bo *sa_bo; | |
682 | uint32_t length_dw; | |
683 | uint64_t gpu_addr; | |
684 | uint32_t *ptr; | |
de807f81 | 685 | uint32_t flags; |
97b2e202 AD |
686 | }; |
687 | ||
1b1f42d8 | 688 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
c1b69ed0 | 689 | |
50838c8c | 690 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
c5637837 | 691 | struct amdgpu_job **job, struct amdgpu_vm *vm); |
d71518b5 CK |
692 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
693 | struct amdgpu_job **job); | |
b6723c8d | 694 | |
a5fb4ec2 | 695 | void amdgpu_job_free_resources(struct amdgpu_job *job); |
50838c8c | 696 | void amdgpu_job_free(struct amdgpu_job *job); |
d71518b5 | 697 | int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, |
1b1f42d8 | 698 | struct drm_sched_entity *entity, void *owner, |
f54d1867 | 699 | struct dma_fence **f); |
8b4fb00b | 700 | |
effd924d AR |
701 | /* |
702 | * Queue manager | |
703 | */ | |
704 | struct amdgpu_queue_mapper { | |
705 | int hw_ip; | |
706 | struct mutex lock; | |
707 | /* protected by lock */ | |
708 | struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; | |
709 | }; | |
710 | ||
711 | struct amdgpu_queue_mgr { | |
712 | struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; | |
713 | }; | |
714 | ||
715 | int amdgpu_queue_mgr_init(struct amdgpu_device *adev, | |
716 | struct amdgpu_queue_mgr *mgr); | |
717 | int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, | |
718 | struct amdgpu_queue_mgr *mgr); | |
719 | int amdgpu_queue_mgr_map(struct amdgpu_device *adev, | |
720 | struct amdgpu_queue_mgr *mgr, | |
fa7c7939 | 721 | u32 hw_ip, u32 instance, u32 ring, |
effd924d AR |
722 | struct amdgpu_ring **out_ring); |
723 | ||
97b2e202 AD |
724 | /* |
725 | * context related structures | |
726 | */ | |
727 | ||
21c16bf6 | 728 | struct amdgpu_ctx_ring { |
91404fb2 | 729 | uint64_t sequence; |
f54d1867 | 730 | struct dma_fence **fences; |
1b1f42d8 | 731 | struct drm_sched_entity entity; |
21c16bf6 CK |
732 | }; |
733 | ||
97b2e202 | 734 | struct amdgpu_ctx { |
0b492a4c | 735 | struct kref refcount; |
9cb7e5a9 | 736 | struct amdgpu_device *adev; |
effd924d | 737 | struct amdgpu_queue_mgr queue_mgr; |
0b492a4c | 738 | unsigned reset_counter; |
668ca1b4 | 739 | unsigned reset_counter_query; |
e55f2b64 | 740 | uint32_t vram_lost_counter; |
21c16bf6 | 741 | spinlock_t ring_lock; |
f54d1867 | 742 | struct dma_fence **fences; |
21c16bf6 | 743 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; |
e55f2b64 | 744 | bool preamble_presented; |
1b1f42d8 LS |
745 | enum drm_sched_priority init_priority; |
746 | enum drm_sched_priority override_priority; | |
0ae94444 | 747 | struct mutex lock; |
1102900d | 748 | atomic_t guilty; |
97b2e202 AD |
749 | }; |
750 | ||
751 | struct amdgpu_ctx_mgr { | |
0b492a4c AD |
752 | struct amdgpu_device *adev; |
753 | struct mutex lock; | |
754 | /* protected by lock */ | |
755 | struct idr ctx_handles; | |
97b2e202 AD |
756 | }; |
757 | ||
0b492a4c AD |
758 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
759 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); | |
760 | ||
eb01abc7 ML |
761 | int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
762 | struct dma_fence *fence, uint64_t *seq); | |
f54d1867 | 763 | struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
21c16bf6 | 764 | struct amdgpu_ring *ring, uint64_t seq); |
c23be4ae | 765 | void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, |
1b1f42d8 | 766 | enum drm_sched_priority priority); |
21c16bf6 | 767 | |
0b492a4c AD |
768 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
769 | struct drm_file *filp); | |
770 | ||
0ae94444 AG |
771 | int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); |
772 | ||
efd4ccb5 CK |
773 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
774 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); | |
0b492a4c | 775 | |
0ae94444 | 776 | |
97b2e202 AD |
777 | /* |
778 | * file private structure | |
779 | */ | |
780 | ||
781 | struct amdgpu_fpriv { | |
782 | struct amdgpu_vm vm; | |
b85891bd | 783 | struct amdgpu_bo_va *prt_va; |
0f4b3c68 | 784 | struct amdgpu_bo_va *csa_va; |
97b2e202 AD |
785 | struct mutex bo_list_lock; |
786 | struct idr bo_list_handles; | |
0b492a4c | 787 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
788 | }; |
789 | ||
790 | /* | |
791 | * residency list | |
792 | */ | |
9124a398 CK |
793 | struct amdgpu_bo_list_entry { |
794 | struct amdgpu_bo *robj; | |
795 | struct ttm_validate_buffer tv; | |
796 | struct amdgpu_bo_va *bo_va; | |
797 | uint32_t priority; | |
798 | struct page **user_pages; | |
799 | int user_invalidated; | |
800 | }; | |
97b2e202 AD |
801 | |
802 | struct amdgpu_bo_list { | |
803 | struct mutex lock; | |
5ac55629 AX |
804 | struct rcu_head rhead; |
805 | struct kref refcount; | |
97b2e202 AD |
806 | struct amdgpu_bo *gds_obj; |
807 | struct amdgpu_bo *gws_obj; | |
808 | struct amdgpu_bo *oa_obj; | |
211dff55 | 809 | unsigned first_userptr; |
97b2e202 AD |
810 | unsigned num_entries; |
811 | struct amdgpu_bo_list_entry *array; | |
812 | }; | |
813 | ||
814 | struct amdgpu_bo_list * | |
815 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); | |
636ce25c CK |
816 | void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, |
817 | struct list_head *validated); | |
97b2e202 AD |
818 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); |
819 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); | |
820 | ||
821 | /* | |
822 | * GFX stuff | |
823 | */ | |
824 | #include "clearstate_defs.h" | |
825 | ||
79e5412c AD |
826 | struct amdgpu_rlc_funcs { |
827 | void (*enter_safe_mode)(struct amdgpu_device *adev); | |
828 | void (*exit_safe_mode)(struct amdgpu_device *adev); | |
829 | }; | |
830 | ||
97b2e202 AD |
831 | struct amdgpu_rlc { |
832 | /* for power gating */ | |
833 | struct amdgpu_bo *save_restore_obj; | |
834 | uint64_t save_restore_gpu_addr; | |
835 | volatile uint32_t *sr_ptr; | |
836 | const u32 *reg_list; | |
837 | u32 reg_list_size; | |
838 | /* for clear state */ | |
839 | struct amdgpu_bo *clear_state_obj; | |
840 | uint64_t clear_state_gpu_addr; | |
841 | volatile uint32_t *cs_ptr; | |
842 | const struct cs_section_def *cs_data; | |
843 | u32 clear_state_size; | |
844 | /* for cp tables */ | |
845 | struct amdgpu_bo *cp_table_obj; | |
846 | uint64_t cp_table_gpu_addr; | |
847 | volatile uint32_t *cp_table_ptr; | |
848 | u32 cp_table_size; | |
79e5412c AD |
849 | |
850 | /* safe mode for updating CG/PG state */ | |
851 | bool in_safe_mode; | |
852 | const struct amdgpu_rlc_funcs *funcs; | |
2b6cd977 EH |
853 | |
854 | /* for firmware data */ | |
855 | u32 save_and_restore_offset; | |
856 | u32 clear_state_descriptor_offset; | |
857 | u32 avail_scratch_ram_locations; | |
858 | u32 reg_restore_list_size; | |
859 | u32 reg_list_format_start; | |
860 | u32 reg_list_format_separate_start; | |
861 | u32 starting_offsets_start; | |
862 | u32 reg_list_format_size_bytes; | |
863 | u32 reg_list_size_bytes; | |
864 | ||
865 | u32 *register_list_format; | |
866 | u32 *register_restore; | |
97b2e202 AD |
867 | }; |
868 | ||
78c16834 AR |
869 | #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES |
870 | ||
97b2e202 AD |
871 | struct amdgpu_mec { |
872 | struct amdgpu_bo *hpd_eop_obj; | |
873 | u64 hpd_eop_gpu_addr; | |
b1023571 KW |
874 | struct amdgpu_bo *mec_fw_obj; |
875 | u64 mec_fw_gpu_addr; | |
97b2e202 | 876 | u32 num_mec; |
42794b27 AR |
877 | u32 num_pipe_per_mec; |
878 | u32 num_queue_per_pipe; | |
59a82d7d | 879 | void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; |
78c16834 AR |
880 | |
881 | /* These are the resources for which amdgpu takes ownership */ | |
882 | DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); | |
97b2e202 AD |
883 | }; |
884 | ||
4e638ae9 XY |
885 | struct amdgpu_kiq { |
886 | u64 eop_gpu_addr; | |
887 | struct amdgpu_bo *eop_obj; | |
43ca8efa | 888 | spinlock_t ring_lock; |
4e638ae9 XY |
889 | struct amdgpu_ring ring; |
890 | struct amdgpu_irq_src irq; | |
891 | }; | |
892 | ||
97b2e202 AD |
893 | /* |
894 | * GPU scratch registers structures, functions & helpers | |
895 | */ | |
896 | struct amdgpu_scratch { | |
897 | unsigned num_reg; | |
898 | uint32_t reg_base; | |
50261151 | 899 | uint32_t free_mask; |
97b2e202 AD |
900 | }; |
901 | ||
902 | /* | |
903 | * GFX configurations | |
904 | */ | |
e3fa7630 AD |
905 | #define AMDGPU_GFX_MAX_SE 4 |
906 | #define AMDGPU_GFX_MAX_SH_PER_SE 2 | |
907 | ||
908 | struct amdgpu_rb_config { | |
909 | uint32_t rb_backend_disable; | |
910 | uint32_t user_rb_backend_disable; | |
911 | uint32_t raster_config; | |
912 | uint32_t raster_config_1; | |
913 | }; | |
914 | ||
d0e95758 AG |
915 | struct gb_addr_config { |
916 | uint16_t pipe_interleave_size; | |
917 | uint8_t num_pipes; | |
918 | uint8_t max_compress_frags; | |
919 | uint8_t num_banks; | |
920 | uint8_t num_se; | |
921 | uint8_t num_rb_per_se; | |
922 | }; | |
923 | ||
ea323f88 | 924 | struct amdgpu_gfx_config { |
97b2e202 AD |
925 | unsigned max_shader_engines; |
926 | unsigned max_tile_pipes; | |
927 | unsigned max_cu_per_sh; | |
928 | unsigned max_sh_per_se; | |
929 | unsigned max_backends_per_se; | |
930 | unsigned max_texture_channel_caches; | |
931 | unsigned max_gprs; | |
932 | unsigned max_gs_threads; | |
933 | unsigned max_hw_contexts; | |
934 | unsigned sc_prim_fifo_size_frontend; | |
935 | unsigned sc_prim_fifo_size_backend; | |
936 | unsigned sc_hiz_tile_fifo_size; | |
937 | unsigned sc_earlyz_tile_fifo_size; | |
938 | ||
939 | unsigned num_tile_pipes; | |
940 | unsigned backend_enable_mask; | |
941 | unsigned mem_max_burst_length_bytes; | |
942 | unsigned mem_row_size_in_kb; | |
943 | unsigned shader_engine_tile_size; | |
944 | unsigned num_gpus; | |
945 | unsigned multi_gpu_tile_size; | |
946 | unsigned mc_arb_ramcfg; | |
947 | unsigned gb_addr_config; | |
8f8e00c1 | 948 | unsigned num_rbs; |
408bfe7c JZ |
949 | unsigned gs_vgt_table_depth; |
950 | unsigned gs_prim_buffer_depth; | |
97b2e202 AD |
951 | |
952 | uint32_t tile_mode_array[32]; | |
953 | uint32_t macrotile_mode_array[16]; | |
e3fa7630 | 954 | |
d0e95758 | 955 | struct gb_addr_config gb_addr_config_fields; |
e3fa7630 | 956 | struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; |
df6e2c4a JZ |
957 | |
958 | /* gfx configure feature */ | |
959 | uint32_t double_offchip_lds_buf; | |
97b2e202 AD |
960 | }; |
961 | ||
7dae69a2 | 962 | struct amdgpu_cu_info { |
ebdebf42 | 963 | uint32_t simd_per_cu; |
51fd0370 | 964 | uint32_t max_waves_per_simd; |
408bfe7c | 965 | uint32_t wave_front_size; |
51fd0370 HZ |
966 | uint32_t max_scratch_slots_per_cu; |
967 | uint32_t lds_size; | |
dbfe85ea FC |
968 | |
969 | /* total active CU number */ | |
970 | uint32_t number; | |
971 | uint32_t ao_cu_mask; | |
972 | uint32_t ao_cu_bitmap[4][4]; | |
7dae69a2 AD |
973 | uint32_t bitmap[4][4]; |
974 | }; | |
975 | ||
b95e31fd AD |
976 | struct amdgpu_gfx_funcs { |
977 | /* get the gpu clock counter */ | |
978 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); | |
9559ef5b | 979 | void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); |
472259f0 | 980 | void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); |
c5a60ce8 TSD |
981 | void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); |
982 | void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); | |
b95e31fd AD |
983 | }; |
984 | ||
bce23e00 AD |
985 | struct amdgpu_ngg_buf { |
986 | struct amdgpu_bo *bo; | |
987 | uint64_t gpu_addr; | |
988 | uint32_t size; | |
989 | uint32_t bo_size; | |
990 | }; | |
991 | ||
992 | enum { | |
af8baf15 GR |
993 | NGG_PRIM = 0, |
994 | NGG_POS, | |
995 | NGG_CNTL, | |
996 | NGG_PARAM, | |
bce23e00 AD |
997 | NGG_BUF_MAX |
998 | }; | |
999 | ||
1000 | struct amdgpu_ngg { | |
1001 | struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; | |
1002 | uint32_t gds_reserve_addr; | |
1003 | uint32_t gds_reserve_size; | |
1004 | bool init; | |
1005 | }; | |
1006 | ||
97b2e202 AD |
1007 | struct amdgpu_gfx { |
1008 | struct mutex gpu_clock_mutex; | |
ea323f88 | 1009 | struct amdgpu_gfx_config config; |
97b2e202 AD |
1010 | struct amdgpu_rlc rlc; |
1011 | struct amdgpu_mec mec; | |
4e638ae9 | 1012 | struct amdgpu_kiq kiq; |
97b2e202 AD |
1013 | struct amdgpu_scratch scratch; |
1014 | const struct firmware *me_fw; /* ME firmware */ | |
1015 | uint32_t me_fw_version; | |
1016 | const struct firmware *pfp_fw; /* PFP firmware */ | |
1017 | uint32_t pfp_fw_version; | |
1018 | const struct firmware *ce_fw; /* CE firmware */ | |
1019 | uint32_t ce_fw_version; | |
1020 | const struct firmware *rlc_fw; /* RLC firmware */ | |
1021 | uint32_t rlc_fw_version; | |
1022 | const struct firmware *mec_fw; /* MEC firmware */ | |
1023 | uint32_t mec_fw_version; | |
1024 | const struct firmware *mec2_fw; /* MEC2 firmware */ | |
1025 | uint32_t mec2_fw_version; | |
02558a00 KW |
1026 | uint32_t me_feature_version; |
1027 | uint32_t ce_feature_version; | |
1028 | uint32_t pfp_feature_version; | |
351643d7 JZ |
1029 | uint32_t rlc_feature_version; |
1030 | uint32_t mec_feature_version; | |
1031 | uint32_t mec2_feature_version; | |
97b2e202 AD |
1032 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
1033 | unsigned num_gfx_rings; | |
1034 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; | |
1035 | unsigned num_compute_rings; | |
1036 | struct amdgpu_irq_src eop_irq; | |
1037 | struct amdgpu_irq_src priv_reg_irq; | |
1038 | struct amdgpu_irq_src priv_inst_irq; | |
1039 | /* gfx status */ | |
7dae69a2 | 1040 | uint32_t gfx_current_status; |
a101a899 | 1041 | /* ce ram size*/ |
7dae69a2 AD |
1042 | unsigned ce_ram_size; |
1043 | struct amdgpu_cu_info cu_info; | |
b95e31fd | 1044 | const struct amdgpu_gfx_funcs *funcs; |
3d7c6384 CZ |
1045 | |
1046 | /* reset mask */ | |
1047 | uint32_t grbm_soft_reset; | |
1048 | uint32_t srbm_soft_reset; | |
b4e40676 DP |
1049 | /* s3/s4 mask */ |
1050 | bool in_suspend; | |
bce23e00 AD |
1051 | /* NGG */ |
1052 | struct amdgpu_ngg ngg; | |
b8866c26 AR |
1053 | |
1054 | /* pipe reservation */ | |
1055 | struct mutex pipe_reserve_mutex; | |
1056 | DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); | |
97b2e202 AD |
1057 | }; |
1058 | ||
b07c60c0 | 1059 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
97b2e202 | 1060 | unsigned size, struct amdgpu_ib *ib); |
4d9c514d | 1061 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, |
f54d1867 | 1062 | struct dma_fence *f); |
b07c60c0 | 1063 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
50ddc75e JZ |
1064 | struct amdgpu_ib *ibs, struct amdgpu_job *job, |
1065 | struct dma_fence **f); | |
97b2e202 AD |
1066 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
1067 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
1068 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
97b2e202 AD |
1069 | |
1070 | /* | |
1071 | * CS. | |
1072 | */ | |
1073 | struct amdgpu_cs_chunk { | |
1074 | uint32_t chunk_id; | |
1075 | uint32_t length_dw; | |
758ac17f | 1076 | void *kdata; |
97b2e202 AD |
1077 | }; |
1078 | ||
1079 | struct amdgpu_cs_parser { | |
1080 | struct amdgpu_device *adev; | |
1081 | struct drm_file *filp; | |
3cb485f3 | 1082 | struct amdgpu_ctx *ctx; |
c3cca41e | 1083 | |
97b2e202 AD |
1084 | /* chunks */ |
1085 | unsigned nchunks; | |
1086 | struct amdgpu_cs_chunk *chunks; | |
97b2e202 | 1087 | |
50838c8c CK |
1088 | /* scheduler job object */ |
1089 | struct amdgpu_job *job; | |
97b2e202 | 1090 | |
c3cca41e CK |
1091 | /* buffer objects */ |
1092 | struct ww_acquire_ctx ticket; | |
1093 | struct amdgpu_bo_list *bo_list; | |
3fe89771 | 1094 | struct amdgpu_mn *mn; |
c3cca41e CK |
1095 | struct amdgpu_bo_list_entry vm_pd; |
1096 | struct list_head validated; | |
f54d1867 | 1097 | struct dma_fence *fence; |
c3cca41e | 1098 | uint64_t bytes_moved_threshold; |
00f06b24 | 1099 | uint64_t bytes_moved_vis_threshold; |
c3cca41e | 1100 | uint64_t bytes_moved; |
00f06b24 | 1101 | uint64_t bytes_moved_vis; |
662bfa61 | 1102 | struct amdgpu_bo_list_entry *evictable; |
97b2e202 AD |
1103 | |
1104 | /* user fence */ | |
91acbeb6 | 1105 | struct amdgpu_bo_list_entry uf_entry; |
660e8558 DA |
1106 | |
1107 | unsigned num_post_dep_syncobjs; | |
1108 | struct drm_syncobj **post_dep_syncobjs; | |
97b2e202 AD |
1109 | }; |
1110 | ||
753ad49c ML |
1111 | #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ |
1112 | #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ | |
1113 | #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ | |
1114 | ||
bb977d37 | 1115 | struct amdgpu_job { |
1b1f42d8 | 1116 | struct drm_sched_job base; |
bb977d37 | 1117 | struct amdgpu_device *adev; |
edf600da | 1118 | struct amdgpu_vm *vm; |
b07c60c0 | 1119 | struct amdgpu_ring *ring; |
e86f9cee | 1120 | struct amdgpu_sync sync; |
df83d1eb | 1121 | struct amdgpu_sync sched_sync; |
bb977d37 | 1122 | struct amdgpu_ib *ibs; |
f54d1867 | 1123 | struct dma_fence *fence; /* the hw fence */ |
753ad49c | 1124 | uint32_t preamble_status; |
bb977d37 | 1125 | uint32_t num_ibs; |
e2840221 | 1126 | void *owner; |
3aecd24c | 1127 | uint64_t fence_ctx; /* the fence_context this job uses */ |
fd53be30 | 1128 | bool vm_needs_flush; |
c4f46f22 | 1129 | unsigned vmid; |
d88bf583 CK |
1130 | uint64_t vm_pd_addr; |
1131 | uint32_t gds_base, gds_size; | |
1132 | uint32_t gws_base, gws_size; | |
1133 | uint32_t oa_base, oa_size; | |
14e47f93 | 1134 | uint32_t vram_lost_counter; |
758ac17f CK |
1135 | |
1136 | /* user fence handling */ | |
b5f5acbc | 1137 | uint64_t uf_addr; |
758ac17f CK |
1138 | uint64_t uf_sequence; |
1139 | ||
bb977d37 | 1140 | }; |
a6db8a33 JZ |
1141 | #define to_amdgpu_job(sched_job) \ |
1142 | container_of((sched_job), struct amdgpu_job, base) | |
bb977d37 | 1143 | |
7270f839 CK |
1144 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
1145 | uint32_t ib_idx, int idx) | |
97b2e202 | 1146 | { |
50838c8c | 1147 | return p->job->ibs[ib_idx].ptr[idx]; |
97b2e202 AD |
1148 | } |
1149 | ||
7270f839 CK |
1150 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
1151 | uint32_t ib_idx, int idx, | |
1152 | uint32_t value) | |
1153 | { | |
50838c8c | 1154 | p->job->ibs[ib_idx].ptr[idx] = value; |
7270f839 CK |
1155 | } |
1156 | ||
97b2e202 AD |
1157 | /* |
1158 | * Writeback | |
1159 | */ | |
896a664c | 1160 | #define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ |
97b2e202 AD |
1161 | |
1162 | struct amdgpu_wb { | |
1163 | struct amdgpu_bo *wb_obj; | |
1164 | volatile uint32_t *wb; | |
1165 | uint64_t gpu_addr; | |
1166 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
1167 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
1168 | }; | |
1169 | ||
131b4b36 AD |
1170 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); |
1171 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); | |
97b2e202 | 1172 | |
041d9d93 | 1173 | void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
d0dd7f0c | 1174 | |
97b2e202 AD |
1175 | /* |
1176 | * SDMA | |
1177 | */ | |
c113ea1c | 1178 | struct amdgpu_sdma_instance { |
97b2e202 AD |
1179 | /* SDMA firmware */ |
1180 | const struct firmware *fw; | |
1181 | uint32_t fw_version; | |
cfa2104f | 1182 | uint32_t feature_version; |
97b2e202 AD |
1183 | |
1184 | struct amdgpu_ring ring; | |
18111de0 | 1185 | bool burst_nop; |
97b2e202 AD |
1186 | }; |
1187 | ||
c113ea1c AD |
1188 | struct amdgpu_sdma { |
1189 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; | |
30d1574f KW |
1190 | #ifdef CONFIG_DRM_AMDGPU_SI |
1191 | //SI DMA has a difference trap irq number for the second engine | |
1192 | struct amdgpu_irq_src trap_irq_1; | |
1193 | #endif | |
c113ea1c AD |
1194 | struct amdgpu_irq_src trap_irq; |
1195 | struct amdgpu_irq_src illegal_inst_irq; | |
edf600da | 1196 | int num_instances; |
e702a680 | 1197 | uint32_t srbm_soft_reset; |
c113ea1c AD |
1198 | }; |
1199 | ||
97b2e202 AD |
1200 | /* |
1201 | * Firmware | |
1202 | */ | |
e635ee07 HR |
1203 | enum amdgpu_firmware_load_type { |
1204 | AMDGPU_FW_LOAD_DIRECT = 0, | |
1205 | AMDGPU_FW_LOAD_SMU, | |
1206 | AMDGPU_FW_LOAD_PSP, | |
1207 | }; | |
1208 | ||
97b2e202 AD |
1209 | struct amdgpu_firmware { |
1210 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; | |
e635ee07 | 1211 | enum amdgpu_firmware_load_type load_type; |
97b2e202 AD |
1212 | struct amdgpu_bo *fw_buf; |
1213 | unsigned int fw_size; | |
2445b227 | 1214 | unsigned int max_ucodes; |
0e5ca0d1 HR |
1215 | /* firmwares are loaded by psp instead of smu from vega10 */ |
1216 | const struct amdgpu_psp_funcs *funcs; | |
1217 | struct amdgpu_bo *rbuf; | |
1218 | struct mutex mutex; | |
ab4fe3e1 HR |
1219 | |
1220 | /* gpu info firmware data pointer */ | |
1221 | const struct firmware *gpu_info_fw; | |
d59c026b ML |
1222 | |
1223 | void *fw_buf_ptr; | |
1224 | uint64_t fw_buf_mc; | |
97b2e202 AD |
1225 | }; |
1226 | ||
1227 | /* | |
1228 | * Benchmarking | |
1229 | */ | |
1230 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
1231 | ||
1232 | ||
1233 | /* | |
1234 | * Testing | |
1235 | */ | |
1236 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
97b2e202 | 1237 | |
50ab2533 | 1238 | |
97b2e202 AD |
1239 | /* |
1240 | * amdgpu smumgr functions | |
1241 | */ | |
1242 | struct amdgpu_smumgr_funcs { | |
1243 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); | |
1244 | int (*request_smu_load_fw)(struct amdgpu_device *adev); | |
1245 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); | |
1246 | }; | |
1247 | ||
1248 | /* | |
1249 | * amdgpu smumgr | |
1250 | */ | |
1251 | struct amdgpu_smumgr { | |
1252 | struct amdgpu_bo *toc_buf; | |
1253 | struct amdgpu_bo *smu_buf; | |
1254 | /* asic priv smu data */ | |
1255 | void *priv; | |
1256 | spinlock_t smu_lock; | |
1257 | /* smumgr functions */ | |
1258 | const struct amdgpu_smumgr_funcs *smumgr_funcs; | |
1259 | /* ucode loading complete flag */ | |
1260 | uint32_t fw_flags; | |
1261 | }; | |
1262 | ||
1263 | /* | |
1264 | * ASIC specific register table accessible by UMD | |
1265 | */ | |
1266 | struct amdgpu_allowed_register_entry { | |
1267 | uint32_t reg_offset; | |
97b2e202 AD |
1268 | bool grbm_indexed; |
1269 | }; | |
1270 | ||
97b2e202 AD |
1271 | /* |
1272 | * ASIC specific functions. | |
1273 | */ | |
1274 | struct amdgpu_asic_funcs { | |
1275 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
1276 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
1277 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
1278 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
1279 | u32 sh_num, u32 reg_offset, u32 *value); | |
1280 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
1281 | int (*reset)(struct amdgpu_device *adev); | |
97b2e202 AD |
1282 | /* get the reference clock */ |
1283 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
97b2e202 AD |
1284 | /* MM block clocks */ |
1285 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
1286 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
841686df MB |
1287 | /* static power management */ |
1288 | int (*get_pcie_lanes)(struct amdgpu_device *adev); | |
1289 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); | |
bbf282d8 AD |
1290 | /* get config memsize register */ |
1291 | u32 (*get_config_memsize)(struct amdgpu_device *adev); | |
2df1b8b6 AD |
1292 | /* flush hdp write queue */ |
1293 | void (*flush_hdp)(struct amdgpu_device *adev); | |
1294 | /* invalidate hdp read cache */ | |
1295 | void (*invalidate_hdp)(struct amdgpu_device *adev); | |
97b2e202 AD |
1296 | }; |
1297 | ||
1298 | /* | |
1299 | * IOCTL. | |
1300 | */ | |
1301 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
1302 | struct drm_file *filp); | |
1303 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, | |
1304 | struct drm_file *filp); | |
1305 | ||
1306 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, | |
1307 | struct drm_file *filp); | |
1308 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
1309 | struct drm_file *filp); | |
1310 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1311 | struct drm_file *filp); | |
1312 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1313 | struct drm_file *filp); | |
1314 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
1315 | struct drm_file *filp); | |
1316 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
1317 | struct drm_file *filp); | |
1318 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
7ca24cf2 MO |
1319 | int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, |
1320 | struct drm_file *filp); | |
97b2e202 | 1321 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
eef18a82 JZ |
1322 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, |
1323 | struct drm_file *filp); | |
97b2e202 AD |
1324 | |
1325 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
1326 | struct drm_file *filp); | |
1327 | ||
1328 | /* VRAM scratch page for HDP bug, default vram page */ | |
1329 | struct amdgpu_vram_scratch { | |
1330 | struct amdgpu_bo *robj; | |
1331 | volatile uint32_t *ptr; | |
1332 | u64 gpu_addr; | |
1333 | }; | |
1334 | ||
1335 | /* | |
1336 | * ACPI | |
1337 | */ | |
1338 | struct amdgpu_atif_notification_cfg { | |
1339 | bool enabled; | |
1340 | int command_code; | |
1341 | }; | |
1342 | ||
1343 | struct amdgpu_atif_notifications { | |
1344 | bool display_switch; | |
1345 | bool expansion_mode_change; | |
1346 | bool thermal_state; | |
1347 | bool forced_power_state; | |
1348 | bool system_power_state; | |
1349 | bool display_conf_change; | |
1350 | bool px_gfx_switch; | |
1351 | bool brightness_change; | |
1352 | bool dgpu_display_event; | |
1353 | }; | |
1354 | ||
1355 | struct amdgpu_atif_functions { | |
1356 | bool system_params; | |
1357 | bool sbios_requests; | |
1358 | bool select_active_disp; | |
1359 | bool lid_state; | |
1360 | bool get_tv_standard; | |
1361 | bool set_tv_standard; | |
1362 | bool get_panel_expansion_mode; | |
1363 | bool set_panel_expansion_mode; | |
1364 | bool temperature_change; | |
1365 | bool graphics_device_types; | |
1366 | }; | |
1367 | ||
1368 | struct amdgpu_atif { | |
1369 | struct amdgpu_atif_notifications notifications; | |
1370 | struct amdgpu_atif_functions functions; | |
1371 | struct amdgpu_atif_notification_cfg notification_cfg; | |
1372 | struct amdgpu_encoder *encoder_for_bl; | |
1373 | }; | |
1374 | ||
1375 | struct amdgpu_atcs_functions { | |
1376 | bool get_ext_state; | |
1377 | bool pcie_perf_req; | |
1378 | bool pcie_dev_rdy; | |
1379 | bool pcie_bus_width; | |
1380 | }; | |
1381 | ||
1382 | struct amdgpu_atcs { | |
1383 | struct amdgpu_atcs_functions functions; | |
1384 | }; | |
1385 | ||
a05502e5 HC |
1386 | /* |
1387 | * Firmware VRAM reservation | |
1388 | */ | |
1389 | struct amdgpu_fw_vram_usage { | |
1390 | u64 start_offset; | |
1391 | u64 size; | |
1392 | struct amdgpu_bo *reserved_bo; | |
1393 | void *va; | |
1394 | }; | |
1395 | ||
d03846af CZ |
1396 | /* |
1397 | * CGS | |
1398 | */ | |
110e6f26 DA |
1399 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
1400 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); | |
a8fe58ce | 1401 | |
97b2e202 AD |
1402 | /* |
1403 | * Core structure, functions and helpers. | |
1404 | */ | |
1405 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
1406 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1407 | ||
1408 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1409 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
1410 | ||
946a4d5b SL |
1411 | |
1412 | /* | |
1413 | * amdgpu nbio functions | |
1414 | * | |
946a4d5b | 1415 | */ |
bf383fb6 AD |
1416 | struct nbio_hdp_flush_reg { |
1417 | u32 ref_and_mask_cp0; | |
1418 | u32 ref_and_mask_cp1; | |
1419 | u32 ref_and_mask_cp2; | |
1420 | u32 ref_and_mask_cp3; | |
1421 | u32 ref_and_mask_cp4; | |
1422 | u32 ref_and_mask_cp5; | |
1423 | u32 ref_and_mask_cp6; | |
1424 | u32 ref_and_mask_cp7; | |
1425 | u32 ref_and_mask_cp8; | |
1426 | u32 ref_and_mask_cp9; | |
1427 | u32 ref_and_mask_sdma0; | |
1428 | u32 ref_and_mask_sdma1; | |
1429 | }; | |
946a4d5b SL |
1430 | |
1431 | struct amdgpu_nbio_funcs { | |
bf383fb6 AD |
1432 | const struct nbio_hdp_flush_reg *hdp_flush_reg; |
1433 | u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); | |
1434 | u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); | |
1435 | u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); | |
1436 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); | |
1437 | u32 (*get_rev_id)(struct amdgpu_device *adev); | |
bf383fb6 AD |
1438 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); |
1439 | void (*hdp_flush)(struct amdgpu_device *adev); | |
1440 | u32 (*get_memsize)(struct amdgpu_device *adev); | |
1441 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, | |
1442 | bool use_doorbell, int doorbell_index); | |
1443 | void (*enable_doorbell_aperture)(struct amdgpu_device *adev, | |
1444 | bool enable); | |
1445 | void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, | |
1446 | bool enable); | |
1447 | void (*ih_doorbell_range)(struct amdgpu_device *adev, | |
1448 | bool use_doorbell, int doorbell_index); | |
1449 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, | |
1450 | bool enable); | |
1451 | void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, | |
1452 | bool enable); | |
1453 | void (*get_clockgating_state)(struct amdgpu_device *adev, | |
1454 | u32 *flags); | |
1455 | void (*ih_control)(struct amdgpu_device *adev); | |
1456 | void (*init_registers)(struct amdgpu_device *adev); | |
1457 | void (*detect_hw_virt)(struct amdgpu_device *adev); | |
946a4d5b SL |
1458 | }; |
1459 | ||
1460 | ||
4522824c SL |
1461 | /* Define the HW IP blocks will be used in driver , add more if necessary */ |
1462 | enum amd_hw_ip_block_type { | |
1463 | GC_HWIP = 1, | |
1464 | HDP_HWIP, | |
1465 | SDMA0_HWIP, | |
1466 | SDMA1_HWIP, | |
1467 | MMHUB_HWIP, | |
1468 | ATHUB_HWIP, | |
1469 | NBIO_HWIP, | |
1470 | MP0_HWIP, | |
1471 | UVD_HWIP, | |
1472 | VCN_HWIP = UVD_HWIP, | |
1473 | VCE_HWIP, | |
1474 | DF_HWIP, | |
1475 | DCE_HWIP, | |
1476 | OSSSYS_HWIP, | |
1477 | SMUIO_HWIP, | |
1478 | PWR_HWIP, | |
1479 | NBIF_HWIP, | |
1480 | MAX_HWIP | |
1481 | }; | |
1482 | ||
1483 | #define HWIP_MAX_INSTANCE 6 | |
1484 | ||
11dc9364 RZ |
1485 | struct amd_powerplay { |
1486 | struct cgs_device *cgs_device; | |
1487 | void *pp_handle; | |
1488 | const struct amd_ip_funcs *ip_funcs; | |
1489 | const struct amd_pm_funcs *pp_funcs; | |
1490 | }; | |
1491 | ||
0c49e0b8 | 1492 | #define AMDGPU_RESET_MAGIC_NUM 64 |
97b2e202 AD |
1493 | struct amdgpu_device { |
1494 | struct device *dev; | |
1495 | struct drm_device *ddev; | |
1496 | struct pci_dev *pdev; | |
97b2e202 | 1497 | |
a8fe58ce MB |
1498 | #ifdef CONFIG_DRM_AMD_ACP |
1499 | struct amdgpu_acp acp; | |
1500 | #endif | |
1501 | ||
97b2e202 | 1502 | /* ASIC */ |
2f7d10b3 | 1503 | enum amd_asic_type asic_type; |
97b2e202 AD |
1504 | uint32_t family; |
1505 | uint32_t rev_id; | |
1506 | uint32_t external_rev_id; | |
1507 | unsigned long flags; | |
1508 | int usec_timeout; | |
1509 | const struct amdgpu_asic_funcs *asic_funcs; | |
1510 | bool shutdown; | |
97b2e202 | 1511 | bool need_dma32; |
fd5fd480 | 1512 | bool need_swiotlb; |
97b2e202 | 1513 | bool accel_working; |
edf600da | 1514 | struct work_struct reset_work; |
97b2e202 AD |
1515 | struct notifier_block acpi_nb; |
1516 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
1517 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
edf600da | 1518 | unsigned debugfs_count; |
97b2e202 | 1519 | #if defined(CONFIG_DEBUG_FS) |
adcec288 | 1520 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
97b2e202 AD |
1521 | #endif |
1522 | struct amdgpu_atif atif; | |
1523 | struct amdgpu_atcs atcs; | |
1524 | struct mutex srbm_mutex; | |
1525 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
1526 | struct mutex grbm_idx_mutex; | |
1527 | struct dev_pm_domain vga_pm_domain; | |
1528 | bool have_disp_power_ref; | |
1529 | ||
1530 | /* BIOS */ | |
0cdd5005 | 1531 | bool is_atom_fw; |
97b2e202 | 1532 | uint8_t *bios; |
a9f5db9c | 1533 | uint32_t bios_size; |
5af2c10d | 1534 | struct amdgpu_bo *stolen_vga_memory; |
a5bde2f9 | 1535 | uint32_t bios_scratch_reg_offset; |
97b2e202 AD |
1536 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
1537 | ||
1538 | /* Register/doorbell mmio */ | |
1539 | resource_size_t rmmio_base; | |
1540 | resource_size_t rmmio_size; | |
1541 | void __iomem *rmmio; | |
1542 | /* protects concurrent MM_INDEX/DATA based register access */ | |
1543 | spinlock_t mmio_idx_lock; | |
1544 | /* protects concurrent SMC based register access */ | |
1545 | spinlock_t smc_idx_lock; | |
1546 | amdgpu_rreg_t smc_rreg; | |
1547 | amdgpu_wreg_t smc_wreg; | |
1548 | /* protects concurrent PCIE register access */ | |
1549 | spinlock_t pcie_idx_lock; | |
1550 | amdgpu_rreg_t pcie_rreg; | |
1551 | amdgpu_wreg_t pcie_wreg; | |
36b9a952 HR |
1552 | amdgpu_rreg_t pciep_rreg; |
1553 | amdgpu_wreg_t pciep_wreg; | |
97b2e202 AD |
1554 | /* protects concurrent UVD register access */ |
1555 | spinlock_t uvd_ctx_idx_lock; | |
1556 | amdgpu_rreg_t uvd_ctx_rreg; | |
1557 | amdgpu_wreg_t uvd_ctx_wreg; | |
1558 | /* protects concurrent DIDT register access */ | |
1559 | spinlock_t didt_idx_lock; | |
1560 | amdgpu_rreg_t didt_rreg; | |
1561 | amdgpu_wreg_t didt_wreg; | |
ccdbb20a RZ |
1562 | /* protects concurrent gc_cac register access */ |
1563 | spinlock_t gc_cac_idx_lock; | |
1564 | amdgpu_rreg_t gc_cac_rreg; | |
1565 | amdgpu_wreg_t gc_cac_wreg; | |
16abb5d2 EQ |
1566 | /* protects concurrent se_cac register access */ |
1567 | spinlock_t se_cac_idx_lock; | |
1568 | amdgpu_rreg_t se_cac_rreg; | |
1569 | amdgpu_wreg_t se_cac_wreg; | |
97b2e202 AD |
1570 | /* protects concurrent ENDPOINT (audio) register access */ |
1571 | spinlock_t audio_endpt_idx_lock; | |
1572 | amdgpu_block_rreg_t audio_endpt_rreg; | |
1573 | amdgpu_block_wreg_t audio_endpt_wreg; | |
1574 | void __iomem *rio_mem; | |
1575 | resource_size_t rio_mem_size; | |
1576 | struct amdgpu_doorbell doorbell; | |
1577 | ||
1578 | /* clock/pll info */ | |
1579 | struct amdgpu_clock clock; | |
1580 | ||
1581 | /* MC */ | |
1582 | struct amdgpu_mc mc; | |
1583 | struct amdgpu_gart gart; | |
1584 | struct amdgpu_dummy_page dummy_page; | |
1585 | struct amdgpu_vm_manager vm_manager; | |
e60f8db5 | 1586 | struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; |
97b2e202 AD |
1587 | |
1588 | /* memory management */ | |
1589 | struct amdgpu_mman mman; | |
97b2e202 AD |
1590 | struct amdgpu_vram_scratch vram_scratch; |
1591 | struct amdgpu_wb wb; | |
97b2e202 | 1592 | atomic64_t num_bytes_moved; |
dbd5ed60 | 1593 | atomic64_t num_evictions; |
68e2c5ff | 1594 | atomic64_t num_vram_cpu_page_faults; |
d94aed5a | 1595 | atomic_t gpu_reset_counter; |
f1892138 | 1596 | atomic_t vram_lost_counter; |
97b2e202 | 1597 | |
95844d20 MO |
1598 | /* data for buffer migration throttling */ |
1599 | struct { | |
1600 | spinlock_t lock; | |
1601 | s64 last_update_us; | |
1602 | s64 accum_us; /* accumulated microseconds */ | |
00f06b24 | 1603 | s64 accum_us_vis; /* for visible VRAM */ |
95844d20 MO |
1604 | u32 log2_max_MBps; |
1605 | } mm_stats; | |
1606 | ||
97b2e202 | 1607 | /* display */ |
9accf2fd | 1608 | bool enable_virtual_display; |
97b2e202 | 1609 | struct amdgpu_mode_info mode_info; |
4562236b | 1610 | /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ |
97b2e202 AD |
1611 | struct work_struct hotplug_work; |
1612 | struct amdgpu_irq_src crtc_irq; | |
1613 | struct amdgpu_irq_src pageflip_irq; | |
1614 | struct amdgpu_irq_src hpd_irq; | |
1615 | ||
1616 | /* rings */ | |
76bf0db5 | 1617 | u64 fence_context; |
97b2e202 AD |
1618 | unsigned num_rings; |
1619 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
1620 | bool ib_pool_ready; | |
1621 | struct amdgpu_sa_manager ring_tmp_bo; | |
1622 | ||
1623 | /* interrupts */ | |
1624 | struct amdgpu_irq irq; | |
1625 | ||
1f7371b2 AD |
1626 | /* powerplay */ |
1627 | struct amd_powerplay powerplay; | |
f3898ea1 | 1628 | bool pp_force_state_enabled; |
1f7371b2 | 1629 | |
97b2e202 AD |
1630 | /* dpm */ |
1631 | struct amdgpu_pm pm; | |
1632 | u32 cg_flags; | |
1633 | u32 pg_flags; | |
1634 | ||
1635 | /* amdgpu smumgr */ | |
1636 | struct amdgpu_smumgr smu; | |
1637 | ||
1638 | /* gfx */ | |
1639 | struct amdgpu_gfx gfx; | |
1640 | ||
1641 | /* sdma */ | |
c113ea1c | 1642 | struct amdgpu_sdma sdma; |
97b2e202 | 1643 | |
b43aaee6 LL |
1644 | /* uvd */ |
1645 | struct amdgpu_uvd uvd; | |
1646 | ||
1647 | /* vce */ | |
1648 | struct amdgpu_vce vce; | |
1649 | ||
1650 | /* vcn */ | |
1651 | struct amdgpu_vcn vcn; | |
97b2e202 AD |
1652 | |
1653 | /* firmwares */ | |
1654 | struct amdgpu_firmware firmware; | |
1655 | ||
0e5ca0d1 HR |
1656 | /* PSP */ |
1657 | struct psp_context psp; | |
1658 | ||
97b2e202 AD |
1659 | /* GDS */ |
1660 | struct amdgpu_gds gds; | |
1661 | ||
4562236b HW |
1662 | /* display related functionality */ |
1663 | struct amdgpu_display_manager dm; | |
1664 | ||
a1255107 | 1665 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
97b2e202 | 1666 | int num_ip_blocks; |
97b2e202 AD |
1667 | struct mutex mn_lock; |
1668 | DECLARE_HASHTABLE(mn_hash, 7); | |
1669 | ||
1670 | /* tracking pinned memory */ | |
1671 | u64 vram_pin_size; | |
e131b914 | 1672 | u64 invisible_pin_size; |
97b2e202 | 1673 | u64 gart_pin_size; |
130e0371 OG |
1674 | |
1675 | /* amdkfd interface */ | |
1676 | struct kfd_dev *kfd; | |
23ca0e4e | 1677 | |
4522824c SL |
1678 | /* soc15 register offset based on ip, instance and segment */ |
1679 | uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; | |
1680 | ||
946a4d5b SL |
1681 | const struct amdgpu_nbio_funcs *nbio_funcs; |
1682 | ||
2dc80b00 S |
1683 | /* delayed work_func for deferring clockgating during resume */ |
1684 | struct delayed_work late_init_work; | |
1685 | ||
5a5099cb | 1686 | struct amdgpu_virt virt; |
a05502e5 HC |
1687 | /* firmware VRAM reservation */ |
1688 | struct amdgpu_fw_vram_usage fw_vram_usage; | |
0c4e7fa5 CZ |
1689 | |
1690 | /* link all shadow bo */ | |
1691 | struct list_head shadow_list; | |
1692 | struct mutex shadow_list_lock; | |
795f2813 AR |
1693 | /* keep an lru list of rings by HW IP */ |
1694 | struct list_head ring_lru_list; | |
1695 | spinlock_t ring_lru_list_lock; | |
5c1354bd | 1696 | |
c836fec5 JQ |
1697 | /* record hw reset is performed */ |
1698 | bool has_hw_reset; | |
0c49e0b8 | 1699 | u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; |
c836fec5 | 1700 | |
47ed4e1c KW |
1701 | /* record last mm index being written through WREG32*/ |
1702 | unsigned long last_mm_index; | |
13a752e3 ML |
1703 | bool in_gpu_reset; |
1704 | struct mutex lock_reset; | |
97b2e202 AD |
1705 | }; |
1706 | ||
a7d64de6 CK |
1707 | static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) |
1708 | { | |
1709 | return container_of(bdev, struct amdgpu_device, mman.bdev); | |
1710 | } | |
1711 | ||
97b2e202 AD |
1712 | int amdgpu_device_init(struct amdgpu_device *adev, |
1713 | struct drm_device *ddev, | |
1714 | struct pci_dev *pdev, | |
1715 | uint32_t flags); | |
1716 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
1717 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
1718 | ||
1719 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 1720 | uint32_t acc_flags); |
97b2e202 | 1721 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 1722 | uint32_t acc_flags); |
97b2e202 AD |
1723 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
1724 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
1725 | ||
1726 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
1727 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
832be404 KW |
1728 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); |
1729 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); | |
97b2e202 | 1730 | |
4562236b HW |
1731 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); |
1732 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); | |
1733 | ||
97b2e202 AD |
1734 | /* |
1735 | * Registers read & write functions. | |
1736 | */ | |
15d72fd7 ML |
1737 | |
1738 | #define AMDGPU_REGS_IDX (1<<0) | |
1739 | #define AMDGPU_REGS_NO_KIQ (1<<1) | |
1740 | ||
1741 | #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) | |
1742 | #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) | |
1743 | ||
1744 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) | |
1745 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) | |
1746 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) | |
1747 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) | |
1748 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) | |
97b2e202 AD |
1749 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1750 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1751 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
1752 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
36b9a952 HR |
1753 | #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) |
1754 | #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1755 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
1756 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
1757 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
1758 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
1759 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
1760 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
ccdbb20a RZ |
1761 | #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) |
1762 | #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) | |
16abb5d2 EQ |
1763 | #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) |
1764 | #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1765 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
1766 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
1767 | #define WREG32_P(reg, val, mask) \ | |
1768 | do { \ | |
1769 | uint32_t tmp_ = RREG32(reg); \ | |
1770 | tmp_ &= (mask); \ | |
1771 | tmp_ |= ((val) & ~(mask)); \ | |
1772 | WREG32(reg, tmp_); \ | |
1773 | } while (0) | |
1774 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
1775 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
1776 | #define WREG32_PLL_P(reg, val, mask) \ | |
1777 | do { \ | |
1778 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1779 | tmp_ &= (mask); \ | |
1780 | tmp_ |= ((val) & ~(mask)); \ | |
1781 | WREG32_PLL(reg, tmp_); \ | |
1782 | } while (0) | |
1783 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
1784 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
1785 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
1786 | ||
1787 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
1788 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
832be404 KW |
1789 | #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) |
1790 | #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) | |
97b2e202 AD |
1791 | |
1792 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT | |
1793 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
1794 | ||
1795 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
1796 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
1797 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
1798 | ||
1799 | #define REG_GET_FIELD(value, reg, field) \ | |
1800 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
61cb8cef TSD |
1801 | |
1802 | #define WREG32_FIELD(reg, field, val) \ | |
1803 | WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
97b2e202 | 1804 | |
ccaf3574 TSD |
1805 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
1806 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
1807 | ||
97b2e202 AD |
1808 | /* |
1809 | * BIOS helpers. | |
1810 | */ | |
1811 | #define RBIOS8(i) (adev->bios[i]) | |
1812 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1813 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1814 | ||
c113ea1c AD |
1815 | static inline struct amdgpu_sdma_instance * |
1816 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |
4b2f7e2c JZ |
1817 | { |
1818 | struct amdgpu_device *adev = ring->adev; | |
1819 | int i; | |
1820 | ||
c113ea1c AD |
1821 | for (i = 0; i < adev->sdma.num_instances; i++) |
1822 | if (&adev->sdma.instance[i].ring == ring) | |
4b2f7e2c JZ |
1823 | break; |
1824 | ||
1825 | if (i < AMDGPU_MAX_SDMA_INSTANCES) | |
c113ea1c | 1826 | return &adev->sdma.instance[i]; |
4b2f7e2c JZ |
1827 | else |
1828 | return NULL; | |
1829 | } | |
1830 | ||
97b2e202 AD |
1831 | /* |
1832 | * ASICs macro. | |
1833 | */ | |
1834 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
1835 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
97b2e202 AD |
1836 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
1837 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
1838 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
841686df MB |
1839 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
1840 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) | |
1841 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
97b2e202 | 1842 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
7946b878 | 1843 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 | 1844 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
bbf282d8 | 1845 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
2df1b8b6 AD |
1846 | #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev)) |
1847 | #define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev)) | |
97b2e202 AD |
1848 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) |
1849 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | |
3de676d8 | 1850 | #define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags)) |
97b2e202 | 1851 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) |
de9ea7bd | 1852 | #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) |
97b2e202 | 1853 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) |
5463545b | 1854 | #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) |
97b2e202 AD |
1855 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) |
1856 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) | |
bbec97aa | 1857 | #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) |
97b2e202 AD |
1858 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
1859 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
1860 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
c4f46f22 | 1861 | #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c)) |
b8c7b39e | 1862 | #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) |
97b2e202 | 1863 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) |
890ee23f | 1864 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
97b2e202 | 1865 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) |
d2edb07b | 1866 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
11afbde8 | 1867 | #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) |
c2167a65 | 1868 | #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) |
753ad49c | 1869 | #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) |
b6091c12 XY |
1870 | #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) |
1871 | #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) | |
3b4d68e9 | 1872 | #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) |
9e5d5309 | 1873 | #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) |
03ccf481 ML |
1874 | #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) |
1875 | #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) | |
97b2e202 | 1876 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
00ecd8a2 | 1877 | #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) |
97b2e202 AD |
1878 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) |
1879 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) | |
97b2e202 AD |
1880 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) |
1881 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) | |
97b2e202 AD |
1882 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) |
1883 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) | |
1884 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) | |
1885 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) | |
1886 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) | |
1887 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) | |
cb9e59d7 | 1888 | #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) |
97b2e202 AD |
1889 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) |
1890 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) | |
1891 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) | |
c7ae72c0 | 1892 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
6e7a3840 | 1893 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
b95e31fd | 1894 | #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) |
9559ef5b | 1895 | #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) |
97b2e202 | 1896 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) |
0e5ca0d1 | 1897 | #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) |
97b2e202 AD |
1898 | |
1899 | /* Common functions */ | |
5f152b5e AD |
1900 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
1901 | struct amdgpu_job* job, bool force); | |
8111c387 | 1902 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); |
39c640c0 | 1903 | bool amdgpu_device_need_post(struct amdgpu_device *adev); |
97b2e202 | 1904 | void amdgpu_update_display_priority(struct amdgpu_device *adev); |
d5fc5e82 | 1905 | |
00f06b24 JB |
1906 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
1907 | u64 num_vis_bytes); | |
765e7fbf | 1908 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); |
97b2e202 | 1909 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); |
2543e28a AD |
1910 | void amdgpu_device_vram_location(struct amdgpu_device *adev, |
1911 | struct amdgpu_mc *mc, u64 base); | |
1912 | void amdgpu_device_gart_location(struct amdgpu_device *adev, | |
1913 | struct amdgpu_mc *mc); | |
d6895ad3 | 1914 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); |
97b2e202 | 1915 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); |
9f31a0b0 BX |
1916 | int amdgpu_ttm_init(struct amdgpu_device *adev); |
1917 | void amdgpu_ttm_fini(struct amdgpu_device *adev); | |
9c3f2b54 | 1918 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
97b2e202 AD |
1919 | const u32 *registers, |
1920 | const u32 array_size); | |
1921 | ||
1922 | bool amdgpu_device_is_px(struct drm_device *dev); | |
1923 | /* atpx handler */ | |
1924 | #if defined(CONFIG_VGA_SWITCHEROO) | |
1925 | void amdgpu_register_atpx_handler(void); | |
1926 | void amdgpu_unregister_atpx_handler(void); | |
a78fe133 | 1927 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
2f5af82e | 1928 | bool amdgpu_is_atpx_hybrid(void); |
efc83cf4 | 1929 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); |
714f88e0 | 1930 | bool amdgpu_has_atpx(void); |
97b2e202 AD |
1931 | #else |
1932 | static inline void amdgpu_register_atpx_handler(void) {} | |
1933 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
a78fe133 | 1934 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
2f5af82e | 1935 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
efc83cf4 | 1936 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } |
714f88e0 | 1937 | static inline bool amdgpu_has_atpx(void) { return false; } |
97b2e202 AD |
1938 | #endif |
1939 | ||
1940 | /* | |
1941 | * KMS | |
1942 | */ | |
1943 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
f498d9ed | 1944 | extern const int amdgpu_max_kms_ioctl; |
97b2e202 AD |
1945 | |
1946 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
11b3c20b | 1947 | void amdgpu_driver_unload_kms(struct drm_device *dev); |
97b2e202 AD |
1948 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
1949 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
1950 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
1951 | struct drm_file *file_priv); | |
cdd61df6 | 1952 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev); |
810ddc3a AD |
1953 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); |
1954 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
1955 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
1956 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
1957 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
97b2e202 AD |
1958 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
1959 | unsigned long arg); | |
1960 | ||
97b2e202 AD |
1961 | /* |
1962 | * functions used by amdgpu_encoder.c | |
1963 | */ | |
1964 | struct amdgpu_afmt_acr { | |
1965 | u32 clock; | |
1966 | ||
1967 | int n_32khz; | |
1968 | int cts_32khz; | |
1969 | ||
1970 | int n_44_1khz; | |
1971 | int cts_44_1khz; | |
1972 | ||
1973 | int n_48khz; | |
1974 | int cts_48khz; | |
1975 | ||
1976 | }; | |
1977 | ||
1978 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
1979 | ||
1980 | /* amdgpu_acpi.c */ | |
1981 | #if defined(CONFIG_ACPI) | |
1982 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
1983 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
1984 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
1985 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
1986 | u8 perf_req, bool advertise); | |
1987 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
1988 | #else | |
1989 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
1990 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
1991 | #endif | |
1992 | ||
9cca0b8e CK |
1993 | int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
1994 | uint64_t addr, struct amdgpu_bo **bo, | |
1995 | struct amdgpu_bo_va_mapping **mapping); | |
97b2e202 | 1996 | |
4562236b HW |
1997 | #if defined(CONFIG_DRM_AMD_DC) |
1998 | int amdgpu_dm_display_resume(struct amdgpu_device *adev ); | |
1999 | #else | |
2000 | static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } | |
2001 | #endif | |
2002 | ||
97b2e202 | 2003 | #include "amdgpu_object.h" |
97b2e202 | 2004 | #endif |