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drm/amdgpu: add option to stop on VM fault
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
55
b80d8475
AD		 56#include "gpu_scheduler.h"
57
97b2e202
AD		 58/*
59 * Modules parameters.
60 */
61extern int amdgpu_modeset;
62extern int amdgpu_vram_limit;
63extern int amdgpu_gart_size;
64extern int amdgpu_benchmarking;
65extern int amdgpu_testing;
66extern int amdgpu_audio;
67extern int amdgpu_disp_priority;
68extern int amdgpu_hw_i2c;
69extern int amdgpu_pcie_gen2;
70extern int amdgpu_msi;
71extern int amdgpu_lockup_timeout;
72extern int amdgpu_dpm;
73extern int amdgpu_smc_load_fw;
74extern int amdgpu_aspm;
75extern int amdgpu_runtime_pm;
76extern int amdgpu_hard_reset;
77extern unsigned amdgpu_ip_block_mask;
78extern int amdgpu_bapm;
79extern int amdgpu_deep_color;
80extern int amdgpu_vm_size;
81extern int amdgpu_vm_block_size;
d9c13156 82extern int amdgpu_vm_fault_stop;
b80d8475 83extern int amdgpu_enable_scheduler;
1333f723 84extern int amdgpu_sched_jobs;
4afcb303 85extern int amdgpu_sched_hw_submission;
3daea9e3 86extern int amdgpu_enable_semaphores;
97b2e202 87
4b559c90 88#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 89#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
90#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
91/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
92#define AMDGPU_IB_POOL_SIZE 16
93#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
94#define AMDGPUFB_CONN_LIMIT 4
95#define AMDGPU_BIOS_NUM_SCRATCH 8
96
97b2e202
AD		 97/* max number of rings */
98#define AMDGPU_MAX_RINGS 16
99#define AMDGPU_MAX_GFX_RINGS 1
100#define AMDGPU_MAX_COMPUTE_RINGS 8
101#define AMDGPU_MAX_VCE_RINGS 2
102
36f523a7
JZ		 103/* max number of IP instances */
104#define AMDGPU_MAX_SDMA_INSTANCES 2
105
97b2e202
AD		 106/* number of hw syncs before falling back on blocking */
107#define AMDGPU_NUM_SYNCS 4
108
109/* hardcode that limit for now */
110#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112/* hard reset data */
113#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115/* reset flags */
116#define AMDGPU_RESET_GFX (1 << 0)
117#define AMDGPU_RESET_COMPUTE (1 << 1)
118#define AMDGPU_RESET_DMA (1 << 2)
119#define AMDGPU_RESET_CP (1 << 3)
120#define AMDGPU_RESET_GRBM (1 << 4)
121#define AMDGPU_RESET_DMA1 (1 << 5)
122#define AMDGPU_RESET_RLC (1 << 6)
123#define AMDGPU_RESET_SEM (1 << 7)
124#define AMDGPU_RESET_IH (1 << 8)
125#define AMDGPU_RESET_VMC (1 << 9)
126#define AMDGPU_RESET_MC (1 << 10)
127#define AMDGPU_RESET_DISPLAY (1 << 11)
128#define AMDGPU_RESET_UVD (1 << 12)
129#define AMDGPU_RESET_VCE (1 << 13)
130#define AMDGPU_RESET_VCE1 (1 << 14)
131
132/* CG block flags */
133#define AMDGPU_CG_BLOCK_GFX (1 << 0)
134#define AMDGPU_CG_BLOCK_MC (1 << 1)
135#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
136#define AMDGPU_CG_BLOCK_UVD (1 << 3)
137#define AMDGPU_CG_BLOCK_VCE (1 << 4)
138#define AMDGPU_CG_BLOCK_HDP (1 << 5)
139#define AMDGPU_CG_BLOCK_BIF (1 << 6)
140
141/* CG flags */
142#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
143#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
144#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
145#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
146#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
147#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
148#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
149#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
150#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
151#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
152#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
153#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
154#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
155#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
156#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
157#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
158#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
159
160/* PG flags */
161#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
162#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
163#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
164#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
165#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
166#define AMDGPU_PG_SUPPORT_CP (1 << 5)
167#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
168#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
169#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
170#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
171#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
172
173/* GFX current status */
174#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
175#define AMDGPU_GFX_SAFE_MODE 0x00000001L
176#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
177#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
178#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
179
180/* max cursor sizes (in pixels) */
181#define CIK_CURSOR_WIDTH 128
182#define CIK_CURSOR_HEIGHT 128
183
184struct amdgpu_device;
185struct amdgpu_fence;
186struct amdgpu_ib;
187struct amdgpu_vm;
188struct amdgpu_ring;
189struct amdgpu_semaphore;
190struct amdgpu_cs_parser;
bb977d37 191struct amdgpu_job;
97b2e202 192struct amdgpu_irq_src;
0b492a4c 193struct amdgpu_fpriv;
97b2e202
AD		 194
195enum amdgpu_cp_irq {
196 AMDGPU_CP_IRQ_GFX_EOP = 0,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
205
206 AMDGPU_CP_IRQ_LAST
207};
208
209enum amdgpu_sdma_irq {
210 AMDGPU_SDMA_IRQ_TRAP0 = 0,
211 AMDGPU_SDMA_IRQ_TRAP1,
212
213 AMDGPU_SDMA_IRQ_LAST
214};
215
216enum amdgpu_thermal_irq {
217 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
218 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
219
220 AMDGPU_THERMAL_IRQ_LAST
221};
222
97b2e202 223int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_clockgating_state state);
97b2e202 226int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_powergating_state state);
97b2e202
AD		 229
230struct amdgpu_ip_block_version {
5fc3aeeb 231 enum amd_ip_block_type type;
97b2e202
AD		 232 u32 major;
233 u32 minor;
234 u32 rev;
5fc3aeeb 235 const struct amd_ip_funcs *funcs;
97b2e202
AD		 236};
237
238int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 239 enum amd_ip_block_type type,
97b2e202
AD		 240 u32 major, u32 minor);
241
242const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
243 struct amdgpu_device *adev,
5fc3aeeb 244 enum amd_ip_block_type type);
97b2e202
AD		 245
246/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
247struct amdgpu_buffer_funcs {
248 /* maximum bytes in a single operation */
249 uint32_t copy_max_bytes;
250
251 /* number of dw to reserve per operation */
252 unsigned copy_num_dw;
253
254 /* used for buffer migration */
c7ae72c0 255 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 256 /* src addr in bytes */
257 uint64_t src_offset,
258 /* dst addr in bytes */
259 uint64_t dst_offset,
260 /* number of byte to transfer */
261 uint32_t byte_count);
262
263 /* maximum bytes in a single operation */
264 uint32_t fill_max_bytes;
265
266 /* number of dw to reserve per operation */
267 unsigned fill_num_dw;
268
269 /* used for buffer clearing */
6e7a3840 270 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 271 /* value to write to memory */
272 uint32_t src_data,
273 /* dst addr in bytes */
274 uint64_t dst_offset,
275 /* number of byte to fill */
276 uint32_t byte_count);
277};
278
279/* provided by hw blocks that can write ptes, e.g., sdma */
280struct amdgpu_vm_pte_funcs {
281 /* copy pte entries from GART */
282 void (*copy_pte)(struct amdgpu_ib *ib,
283 uint64_t pe, uint64_t src,
284 unsigned count);
285 /* write pte one entry at a time with addr mapping */
286 void (*write_pte)(struct amdgpu_ib *ib,
287 uint64_t pe,
288 uint64_t addr, unsigned count,
289 uint32_t incr, uint32_t flags);
290 /* for linear pte/pde updates without addr mapping */
291 void (*set_pte_pde)(struct amdgpu_ib *ib,
292 uint64_t pe,
293 uint64_t addr, unsigned count,
294 uint32_t incr, uint32_t flags);
295 /* pad the indirect buffer to the necessary number of dw */
296 void (*pad_ib)(struct amdgpu_ib *ib);
297};
298
299/* provided by the gmc block */
300struct amdgpu_gart_funcs {
301 /* flush the vm tlb via mmio */
302 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
303 uint32_t vmid);
304 /* write pte/pde updates using the cpu */
305 int (*set_pte_pde)(struct amdgpu_device *adev,
306 void *cpu_pt_addr, /* cpu addr of page table */
307 uint32_t gpu_page_idx, /* pte/pde to update */
308 uint64_t addr, /* addr to write into pte/pde */
309 uint32_t flags); /* access flags */
310};
311
312/* provided by the ih block */
313struct amdgpu_ih_funcs {
314 /* ring read/write ptr handling, called from interrupt context */
315 u32 (*get_wptr)(struct amdgpu_device *adev);
316 void (*decode_iv)(struct amdgpu_device *adev,
317 struct amdgpu_iv_entry *entry);
318 void (*set_rptr)(struct amdgpu_device *adev);
319};
320
321/* provided by hw blocks that expose a ring buffer for commands */
322struct amdgpu_ring_funcs {
323 /* ring read/write ptr handling */
324 u32 (*get_rptr)(struct amdgpu_ring *ring);
325 u32 (*get_wptr)(struct amdgpu_ring *ring);
326 void (*set_wptr)(struct amdgpu_ring *ring);
327 /* validating and patching of IBs */
328 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
329 /* command emit functions */
330 void (*emit_ib)(struct amdgpu_ring *ring,
331 struct amdgpu_ib *ib);
332 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 333 uint64_t seq, unsigned flags);
97b2e202
AD		 334 bool (*emit_semaphore)(struct amdgpu_ring *ring,
335 struct amdgpu_semaphore *semaphore,
336 bool emit_wait);
337 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
338 uint64_t pd_addr);
d2edb07b 339 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 340 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
341 uint32_t gds_base, uint32_t gds_size,
342 uint32_t gws_base, uint32_t gws_size,
343 uint32_t oa_base, uint32_t oa_size);
344 /* testing functions */
345 int (*test_ring)(struct amdgpu_ring *ring);
346 int (*test_ib)(struct amdgpu_ring *ring);
347 bool (*is_lockup)(struct amdgpu_ring *ring);
edff0e28
JZ		 348 /* insert NOP packets */
349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 350};
351
352/*
353 * BIOS.
354 */
355bool amdgpu_get_bios(struct amdgpu_device *adev);
356bool amdgpu_read_bios(struct amdgpu_device *adev);
357
358/*
359 * Dummy page
360 */
361struct amdgpu_dummy_page {
362 struct page *page;
363 dma_addr_t addr;
364};
365int amdgpu_dummy_page_init(struct amdgpu_device *adev);
366void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
367
368
369/*
370 * Clocks
371 */
372
373#define AMDGPU_MAX_PPLL 3
374
375struct amdgpu_clock {
376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
377 struct amdgpu_pll spll;
378 struct amdgpu_pll mpll;
379 /* 10 Khz units */
380 uint32_t default_mclk;
381 uint32_t default_sclk;
382 uint32_t default_dispclk;
383 uint32_t current_dispclk;
384 uint32_t dp_extclk;
385 uint32_t max_pixel_clock;
386};
387
388/*
389 * Fences.
390 */
391struct amdgpu_fence_driver {
392 struct amdgpu_ring *ring;
393 uint64_t gpu_addr;
394 volatile uint32_t *cpu_addr;
395 /* sync_seq is protected by ring emission lock */
396 uint64_t sync_seq[AMDGPU_MAX_RINGS];
397 atomic64_t last_seq;
398 bool initialized;
97b2e202
AD		 399 struct amdgpu_irq_src *irq_src;
400 unsigned irq_type;
401 struct delayed_work lockup_work;
7f06c236 402 wait_queue_head_t fence_queue;
97b2e202
AD		 403};
404
405/* some special values for the owner field */
406#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
407#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
408#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
409
890ee23f
CZ		 410#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411#define AMDGPU_FENCE_FLAG_INT (1 << 1)
412
97b2e202
AD		 413struct amdgpu_fence {
414 struct fence base;
4cef9267 415
97b2e202
AD		 416 /* RB, DMA, etc. */
417 struct amdgpu_ring *ring;
418 uint64_t seq;
419
420 /* filp or special value for fence creator */
421 void *owner;
422
423 wait_queue_t fence_wake;
424};
425
426struct amdgpu_user_fence {
427 /* write-back bo */
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
430 uint32_t offset;
431};
432
433int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
436
4f839a24 437int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 438int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
440 unsigned irq_type);
5ceb54c6
AD		 441void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 443int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445void amdgpu_fence_process(struct amdgpu_ring *ring);
446int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
449
8221d706
CK		 450signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
451 struct fence **array,
452 uint32_t count,
453 bool intr,
454 signed long t);
97b2e202
AD		 455struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
456void amdgpu_fence_unref(struct amdgpu_fence **fence);
457
458bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
459 struct amdgpu_ring *ring);
460void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
461 struct amdgpu_ring *ring);
462
463static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
464 struct amdgpu_fence *b)
465{
466 if (!a) {
467 return b;
468 }
469
470 if (!b) {
471 return a;
472 }
473
474 BUG_ON(a->ring != b->ring);
475
476 if (a->seq > b->seq) {
477 return a;
478 } else {
479 return b;
480 }
481}
482
483static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
484 struct amdgpu_fence *b)
485{
486 if (!a) {
487 return false;
488 }
489
490 if (!b) {
491 return true;
492 }
493
494 BUG_ON(a->ring != b->ring);
495
496 return a->seq < b->seq;
497}
498
332dfe90 499int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
97b2e202
AD		 500 void *owner, struct amdgpu_fence **fence);
501
502/*
503 * TTM.
504 */
505struct amdgpu_mman {
506 struct ttm_bo_global_ref bo_global_ref;
507 struct drm_global_reference mem_global_ref;
508 struct ttm_bo_device bdev;
509 bool mem_global_referenced;
510 bool initialized;
511
512#if defined(CONFIG_DEBUG_FS)
513 struct dentry *vram;
514 struct dentry *gtt;
515#endif
516
517 /* buffer handling */
518 const struct amdgpu_buffer_funcs *buffer_funcs;
519 struct amdgpu_ring *buffer_funcs_ring;
520};
521
522int amdgpu_copy_buffer(struct amdgpu_ring *ring,
523 uint64_t src_offset,
524 uint64_t dst_offset,
525 uint32_t byte_count,
526 struct reservation_object *resv,
c7ae72c0 527 struct fence **fence);
97b2e202
AD		 528int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
529
530struct amdgpu_bo_list_entry {
531 struct amdgpu_bo *robj;
532 struct ttm_validate_buffer tv;
533 struct amdgpu_bo_va *bo_va;
534 unsigned prefered_domains;
535 unsigned allowed_domains;
536 uint32_t priority;
537};
538
539struct amdgpu_bo_va_mapping {
540 struct list_head list;
541 struct interval_tree_node it;
542 uint64_t offset;
543 uint32_t flags;
544};
545
546/* bo virtual addresses in a specific vm */
547struct amdgpu_bo_va {
548 /* protected by bo being reserved */
549 struct list_head bo_list;
bb1e38a4 550 struct fence *last_pt_update;
97b2e202
AD		 551 unsigned ref_count;
552
7fc11959 553 /* protected by vm mutex and spinlock */
97b2e202
AD		 554 struct list_head vm_status;
555
7fc11959
CK		 556 /* mappings for this bo_va */
557 struct list_head invalids;
558 struct list_head valids;
559
97b2e202
AD		 560 /* constant after initialization */
561 struct amdgpu_vm *vm;
562 struct amdgpu_bo *bo;
563};
564
7e5a547f
CZ		 565#define AMDGPU_GEM_DOMAIN_MAX 0x3
566
97b2e202
AD		 567struct amdgpu_bo {
568 /* Protected by gem.mutex */
569 struct list_head list;
570 /* Protected by tbo.reserved */
571 u32 initial_domain;
7e5a547f 572 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 573 struct ttm_placement placement;
574 struct ttm_buffer_object tbo;
575 struct ttm_bo_kmap_obj kmap;
576 u64 flags;
577 unsigned pin_count;
578 void *kptr;
579 u64 tiling_flags;
580 u64 metadata_flags;
581 void *metadata;
582 u32 metadata_size;
583 /* list of all virtual address to which this bo
584 * is associated to
585 */
586 struct list_head va;
587 /* Constant after initialization */
588 struct amdgpu_device *adev;
589 struct drm_gem_object gem_base;
590
591 struct ttm_bo_kmap_obj dma_buf_vmap;
592 pid_t pid;
593 struct amdgpu_mn *mn;
594 struct list_head mn_list;
595};
596#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
597
598void amdgpu_gem_object_free(struct drm_gem_object *obj);
599int amdgpu_gem_object_open(struct drm_gem_object *obj,
600 struct drm_file *file_priv);
601void amdgpu_gem_object_close(struct drm_gem_object *obj,
602 struct drm_file *file_priv);
603unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
604struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
605struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
606 struct dma_buf_attachment *attach,
607 struct sg_table *sg);
608struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
609 struct drm_gem_object *gobj,
610 int flags);
611int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
612void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
613struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
614void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
615void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
616int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
617
618/* sub-allocation manager, it has to be protected by another lock.
619 * By conception this is an helper for other part of the driver
620 * like the indirect buffer or semaphore, which both have their
621 * locking.
622 *
623 * Principe is simple, we keep a list of sub allocation in offset
624 * order (first entry has offset == 0, last entry has the highest
625 * offset).
626 *
627 * When allocating new object we first check if there is room at
628 * the end total_size - (last_object_offset + last_object_size) >=
629 * alloc_size. If so we allocate new object there.
630 *
631 * When there is not enough room at the end, we start waiting for
632 * each sub object until we reach object_offset+object_size >=
633 * alloc_size, this object then become the sub object we return.
634 *
635 * Alignment can't be bigger than page size.
636 *
637 * Hole are not considered for allocation to keep things simple.
638 * Assumption is that there won't be hole (all object on same
639 * alignment).
640 */
641struct amdgpu_sa_manager {
642 wait_queue_head_t wq;
643 struct amdgpu_bo *bo;
644 struct list_head *hole;
645 struct list_head flist[AMDGPU_MAX_RINGS];
646 struct list_head olist;
647 unsigned size;
648 uint64_t gpu_addr;
649 void *cpu_ptr;
650 uint32_t domain;
651 uint32_t align;
652};
653
654struct amdgpu_sa_bo;
655
656/* sub-allocation buffer */
657struct amdgpu_sa_bo {
658 struct list_head olist;
659 struct list_head flist;
660 struct amdgpu_sa_manager *manager;
661 unsigned soffset;
662 unsigned eoffset;
4ce9891e 663 struct fence *fence;
97b2e202
AD		 664};
665
666/*
667 * GEM objects.
668 */
669struct amdgpu_gem {
670 struct mutex mutex;
671 struct list_head objects;
672};
673
674int amdgpu_gem_init(struct amdgpu_device *adev);
675void amdgpu_gem_fini(struct amdgpu_device *adev);
676int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
677 int alignment, u32 initial_domain,
678 u64 flags, bool kernel,
679 struct drm_gem_object **obj);
680
681int amdgpu_mode_dumb_create(struct drm_file *file_priv,
682 struct drm_device *dev,
683 struct drm_mode_create_dumb *args);
684int amdgpu_mode_dumb_mmap(struct drm_file *filp,
685 struct drm_device *dev,
686 uint32_t handle, uint64_t *offset_p);
687
688/*
689 * Semaphores.
690 */
691struct amdgpu_semaphore {
692 struct amdgpu_sa_bo *sa_bo;
693 signed waiters;
694 uint64_t gpu_addr;
695};
696
697int amdgpu_semaphore_create(struct amdgpu_device *adev,
698 struct amdgpu_semaphore **semaphore);
699bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
700 struct amdgpu_semaphore *semaphore);
701bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
702 struct amdgpu_semaphore *semaphore);
703void amdgpu_semaphore_free(struct amdgpu_device *adev,
704 struct amdgpu_semaphore **semaphore,
4ce9891e 705 struct fence *fence);
97b2e202
AD		 706
707/*
708 * Synchronization
709 */
710struct amdgpu_sync {
711 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
712 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
f91b3a69 713 DECLARE_HASHTABLE(fences, 4);
3c62338c 714 struct fence *last_vm_update;
97b2e202
AD		 715};
716
717void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 718int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
719 struct fence *f);
97b2e202
AD		 720int amdgpu_sync_resv(struct amdgpu_device *adev,
721 struct amdgpu_sync *sync,
722 struct reservation_object *resv,
723 void *owner);
724int amdgpu_sync_rings(struct amdgpu_sync *sync,
725 struct amdgpu_ring *ring);
e61235db 726struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 727int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 728void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 729 struct fence *fence);
97b2e202
AD		 730
731/*
732 * GART structures, functions & helpers
733 */
734struct amdgpu_mc;
735
736#define AMDGPU_GPU_PAGE_SIZE 4096
737#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
738#define AMDGPU_GPU_PAGE_SHIFT 12
739#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
740
741struct amdgpu_gart {
742 dma_addr_t table_addr;
743 struct amdgpu_bo *robj;
744 void *ptr;
745 unsigned num_gpu_pages;
746 unsigned num_cpu_pages;
747 unsigned table_size;
748 struct page **pages;
749 dma_addr_t *pages_addr;
750 bool ready;
751 const struct amdgpu_gart_funcs *gart_funcs;
752};
753
754int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
755void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
756int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
757void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
758int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
759void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
760int amdgpu_gart_init(struct amdgpu_device *adev);
761void amdgpu_gart_fini(struct amdgpu_device *adev);
762void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
763 int pages);
764int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
765 int pages, struct page **pagelist,
766 dma_addr_t *dma_addr, uint32_t flags);
767
768/*
769 * GPU MC structures, functions & helpers
770 */
771struct amdgpu_mc {
772 resource_size_t aper_size;
773 resource_size_t aper_base;
774 resource_size_t agp_base;
775 /* for some chips with <= 32MB we need to lie
776 * about vram size near mc fb location */
777 u64 mc_vram_size;
778 u64 visible_vram_size;
779 u64 gtt_size;
780 u64 gtt_start;
781 u64 gtt_end;
782 u64 vram_start;
783 u64 vram_end;
784 unsigned vram_width;
785 u64 real_vram_size;
786 int vram_mtrr;
787 u64 gtt_base_align;
788 u64 mc_mask;
789 const struct firmware *fw; /* MC firmware */
790 uint32_t fw_version;
791 struct amdgpu_irq_src vm_fault;
81c59f54 792 uint32_t vram_type;
97b2e202
AD		 793};
794
795/*
796 * GPU doorbell structures, functions & helpers
797 */
798typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
799{
800 AMDGPU_DOORBELL_KIQ = 0x000,
801 AMDGPU_DOORBELL_HIQ = 0x001,
802 AMDGPU_DOORBELL_DIQ = 0x002,
803 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
804 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
805 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
806 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
807 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
808 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
809 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
810 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
811 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
812 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
813 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
814 AMDGPU_DOORBELL_IH = 0x1E8,
815 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
816 AMDGPU_DOORBELL_INVALID = 0xFFFF
817} AMDGPU_DOORBELL_ASSIGNMENT;
818
819struct amdgpu_doorbell {
820 /* doorbell mmio */
821 resource_size_t base;
822 resource_size_t size;
823 u32 __iomem *ptr;
824 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
825};
826
827void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
828 phys_addr_t *aperture_base,
829 size_t *aperture_size,
830 size_t *start_offset);
831
832/*
833 * IRQS.
834 */
835
836struct amdgpu_flip_work {
837 struct work_struct flip_work;
838 struct work_struct unpin_work;
839 struct amdgpu_device *adev;
840 int crtc_id;
841 uint64_t base;
842 struct drm_pending_vblank_event *event;
843 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 844 struct fence *excl;
845 unsigned shared_count;
846 struct fence **shared;
97b2e202
AD		 847};
848
849
850/*
851 * CP & rings.
852 */
853
854struct amdgpu_ib {
855 struct amdgpu_sa_bo *sa_bo;
856 uint32_t length_dw;
857 uint64_t gpu_addr;
858 uint32_t *ptr;
859 struct amdgpu_ring *ring;
860 struct amdgpu_fence *fence;
861 struct amdgpu_user_fence *user;
862 struct amdgpu_vm *vm;
3cb485f3 863 struct amdgpu_ctx *ctx;
97b2e202 864 struct amdgpu_sync sync;
97b2e202
AD		 865 uint32_t gds_base, gds_size;
866 uint32_t gws_base, gws_size;
867 uint32_t oa_base, oa_size;
de807f81 868 uint32_t flags;
5430a3ff
CK		 869 /* resulting sequence number */
870 uint64_t sequence;
97b2e202
AD		 871};
872
873enum amdgpu_ring_type {
874 AMDGPU_RING_TYPE_GFX,
875 AMDGPU_RING_TYPE_COMPUTE,
876 AMDGPU_RING_TYPE_SDMA,
877 AMDGPU_RING_TYPE_UVD,
878 AMDGPU_RING_TYPE_VCE
879};
880
c1b69ed0
CZ		 881extern struct amd_sched_backend_ops amdgpu_sched_ops;
882
3c704e93
CZ		 883int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
884 struct amdgpu_ring *ring,
885 struct amdgpu_ib *ibs,
886 unsigned num_ibs,
bb977d37 887 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 888 void *owner,
889 struct fence **fence);
3c704e93 890
97b2e202
AD		 891struct amdgpu_ring {
892 struct amdgpu_device *adev;
893 const struct amdgpu_ring_funcs *funcs;
894 struct amdgpu_fence_driver fence_drv;
4f839a24 895 struct amd_gpu_scheduler sched;
97b2e202 896
176e1ab1 897 spinlock_t fence_lock;
97b2e202
AD		 898 struct mutex *ring_lock;
899 struct amdgpu_bo *ring_obj;
900 volatile uint32_t *ring;
901 unsigned rptr_offs;
902 u64 next_rptr_gpu_addr;
903 volatile u32 *next_rptr_cpu_addr;
904 unsigned wptr;
905 unsigned wptr_old;
906 unsigned ring_size;
907 unsigned ring_free_dw;
908 int count_dw;
909 atomic_t last_rptr;
910 atomic64_t last_activity;
911 uint64_t gpu_addr;
912 uint32_t align_mask;
913 uint32_t ptr_mask;
914 bool ready;
915 u32 nop;
916 u32 idx;
917 u64 last_semaphore_signal_addr;
918 u64 last_semaphore_wait_addr;
919 u32 me;
920 u32 pipe;
921 u32 queue;
922 struct amdgpu_bo *mqd_obj;
923 u32 doorbell_index;
924 bool use_doorbell;
925 unsigned wptr_offs;
926 unsigned next_rptr_offs;
927 unsigned fence_offs;
3cb485f3 928 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 929 enum amdgpu_ring_type type;
930 char name[16];
4274f5d4 931 bool is_pte_ring;
97b2e202
AD		 932};
933
934/*
935 * VM
936 */
937
938/* maximum number of VMIDs */
939#define AMDGPU_NUM_VM 16
940
941/* number of entries in page table */
942#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
943
944/* PTBs (Page Table Blocks) need to be aligned to 32K */
945#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
946#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
947#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
948
949#define AMDGPU_PTE_VALID (1 << 0)
950#define AMDGPU_PTE_SYSTEM (1 << 1)
951#define AMDGPU_PTE_SNOOPED (1 << 2)
952
953/* VI only */
954#define AMDGPU_PTE_EXECUTABLE (1 << 4)
955
956#define AMDGPU_PTE_READABLE (1 << 5)
957#define AMDGPU_PTE_WRITEABLE (1 << 6)
958
959/* PTE (Page Table Entry) fragment field for different page sizes */
960#define AMDGPU_PTE_FRAG_4KB (0 << 7)
961#define AMDGPU_PTE_FRAG_64KB (4 << 7)
962#define AMDGPU_LOG2_PAGES_PER_FRAG 4
963
d9c13156
CK		 964/* How to programm VM fault handling */
965#define AMDGPU_VM_FAULT_STOP_NEVER 0
966#define AMDGPU_VM_FAULT_STOP_FIRST 1
967#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
968
97b2e202
AD		 969struct amdgpu_vm_pt {
970 struct amdgpu_bo *bo;
971 uint64_t addr;
972};
973
974struct amdgpu_vm_id {
975 unsigned id;
976 uint64_t pd_gpu_addr;
977 /* last flushed PD/PT update */
3c62338c 978 struct fence *flushed_updates;
97b2e202
AD		 979 /* last use of vmid */
980 struct amdgpu_fence *last_id_use;
981};
982
983struct amdgpu_vm {
984 struct mutex mutex;
985
986 struct rb_root va;
987
7fc11959 988 /* protecting invalidated */
97b2e202
AD		 989 spinlock_t status_lock;
990
991 /* BOs moved, but not yet updated in the PT */
992 struct list_head invalidated;
993
7fc11959
CK		 994 /* BOs cleared in the PT because of a move */
995 struct list_head cleared;
996
997 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 998 struct list_head freed;
999
1000 /* contains the page directory */
1001 struct amdgpu_bo *page_directory;
1002 unsigned max_pde_used;
05906dec 1003 struct fence *page_directory_fence;
97b2e202
AD		 1004
1005 /* array of page tables, one for each page directory entry */
1006 struct amdgpu_vm_pt *page_tables;
1007
1008 /* for id and flush management per ring */
1009 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
1010};
1011
1012struct amdgpu_vm_manager {
1013 struct amdgpu_fence *active[AMDGPU_NUM_VM];
1014 uint32_t max_pfn;
1015 /* number of VMIDs */
1016 unsigned nvm;
1017 /* vram base address for page table entry */
1018 u64 vram_base_offset;
1019 /* is vm enabled? */
1020 bool enabled;
1021 /* for hw to save the PD addr on suspend/resume */
1022 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1023 /* vm pte handling */
1024 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1025 struct amdgpu_ring *vm_pte_funcs_ring;
1026};
1027
1028/*
1029 * context related structures
1030 */
1031
21c16bf6
CK		 1032#define AMDGPU_CTX_MAX_CS_PENDING 16
1033
1034struct amdgpu_ctx_ring {
91404fb2
CK		 1035 uint64_t sequence;
1036 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1037 struct amd_sched_entity entity;
21c16bf6
CK		 1038};
1039
97b2e202 1040struct amdgpu_ctx {
0b492a4c 1041 struct kref refcount;
9cb7e5a9 1042 struct amdgpu_device *adev;
0b492a4c 1043 unsigned reset_counter;
21c16bf6
CK		 1044 spinlock_t ring_lock;
1045 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1046};
1047
1048struct amdgpu_ctx_mgr {
0b492a4c
AD		 1049 struct amdgpu_device *adev;
1050 struct mutex lock;
1051 /* protected by lock */
1052 struct idr ctx_handles;
97b2e202
AD		 1053};
1054
47f38501
CK		 1055int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1056 struct amdgpu_ctx *ctx);
1057void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1058
0b492a4c
AD		 1059struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1060int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1061
21c16bf6 1062uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1063 struct fence *fence);
21c16bf6
CK		 1064struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1065 struct amdgpu_ring *ring, uint64_t seq);
1066
0b492a4c
AD		 1067int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *filp);
1069
efd4ccb5
CK		 1070void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1071void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1072
97b2e202
AD		 1073/*
1074 * file private structure
1075 */
1076
1077struct amdgpu_fpriv {
1078 struct amdgpu_vm vm;
1079 struct mutex bo_list_lock;
1080 struct idr bo_list_handles;
0b492a4c 1081 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1082};
1083
1084/*
1085 * residency list
1086 */
1087
1088struct amdgpu_bo_list {
1089 struct mutex lock;
1090 struct amdgpu_bo *gds_obj;
1091 struct amdgpu_bo *gws_obj;
1092 struct amdgpu_bo *oa_obj;
1093 bool has_userptr;
1094 unsigned num_entries;
1095 struct amdgpu_bo_list_entry *array;
1096};
1097
1098struct amdgpu_bo_list *
1099amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1100void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1101void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1102
1103/*
1104 * GFX stuff
1105 */
1106#include "clearstate_defs.h"
1107
1108struct amdgpu_rlc {
1109 /* for power gating */
1110 struct amdgpu_bo *save_restore_obj;
1111 uint64_t save_restore_gpu_addr;
1112 volatile uint32_t *sr_ptr;
1113 const u32 *reg_list;
1114 u32 reg_list_size;
1115 /* for clear state */
1116 struct amdgpu_bo *clear_state_obj;
1117 uint64_t clear_state_gpu_addr;
1118 volatile uint32_t *cs_ptr;
1119 const struct cs_section_def *cs_data;
1120 u32 clear_state_size;
1121 /* for cp tables */
1122 struct amdgpu_bo *cp_table_obj;
1123 uint64_t cp_table_gpu_addr;
1124 volatile uint32_t *cp_table_ptr;
1125 u32 cp_table_size;
1126};
1127
1128struct amdgpu_mec {
1129 struct amdgpu_bo *hpd_eop_obj;
1130 u64 hpd_eop_gpu_addr;
1131 u32 num_pipe;
1132 u32 num_mec;
1133 u32 num_queue;
1134};
1135
1136/*
1137 * GPU scratch registers structures, functions & helpers
1138 */
1139struct amdgpu_scratch {
1140 unsigned num_reg;
1141 uint32_t reg_base;
1142 bool free[32];
1143 uint32_t reg[32];
1144};
1145
1146/*
1147 * GFX configurations
1148 */
1149struct amdgpu_gca_config {
1150 unsigned max_shader_engines;
1151 unsigned max_tile_pipes;
1152 unsigned max_cu_per_sh;
1153 unsigned max_sh_per_se;
1154 unsigned max_backends_per_se;
1155 unsigned max_texture_channel_caches;
1156 unsigned max_gprs;
1157 unsigned max_gs_threads;
1158 unsigned max_hw_contexts;
1159 unsigned sc_prim_fifo_size_frontend;
1160 unsigned sc_prim_fifo_size_backend;
1161 unsigned sc_hiz_tile_fifo_size;
1162 unsigned sc_earlyz_tile_fifo_size;
1163
1164 unsigned num_tile_pipes;
1165 unsigned backend_enable_mask;
1166 unsigned mem_max_burst_length_bytes;
1167 unsigned mem_row_size_in_kb;
1168 unsigned shader_engine_tile_size;
1169 unsigned num_gpus;
1170 unsigned multi_gpu_tile_size;
1171 unsigned mc_arb_ramcfg;
1172 unsigned gb_addr_config;
1173
1174 uint32_t tile_mode_array[32];
1175 uint32_t macrotile_mode_array[16];
1176};
1177
1178struct amdgpu_gfx {
1179 struct mutex gpu_clock_mutex;
1180 struct amdgpu_gca_config config;
1181 struct amdgpu_rlc rlc;
1182 struct amdgpu_mec mec;
1183 struct amdgpu_scratch scratch;
1184 const struct firmware *me_fw; /* ME firmware */
1185 uint32_t me_fw_version;
1186 const struct firmware *pfp_fw; /* PFP firmware */
1187 uint32_t pfp_fw_version;
1188 const struct firmware *ce_fw; /* CE firmware */
1189 uint32_t ce_fw_version;
1190 const struct firmware *rlc_fw; /* RLC firmware */
1191 uint32_t rlc_fw_version;
1192 const struct firmware *mec_fw; /* MEC firmware */
1193 uint32_t mec_fw_version;
1194 const struct firmware *mec2_fw; /* MEC2 firmware */
1195 uint32_t mec2_fw_version;
02558a00
KW		 1196 uint32_t me_feature_version;
1197 uint32_t ce_feature_version;
1198 uint32_t pfp_feature_version;
351643d7
JZ		 1199 uint32_t rlc_feature_version;
1200 uint32_t mec_feature_version;
1201 uint32_t mec2_feature_version;
97b2e202
AD		 1202 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1203 unsigned num_gfx_rings;
1204 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1205 unsigned num_compute_rings;
1206 struct amdgpu_irq_src eop_irq;
1207 struct amdgpu_irq_src priv_reg_irq;
1208 struct amdgpu_irq_src priv_inst_irq;
1209 /* gfx status */
1210 uint32_t gfx_current_status;
a101a899
KW		 1211 /* ce ram size*/
1212 unsigned ce_ram_size;
97b2e202
AD		 1213};
1214
1215int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1216 unsigned size, struct amdgpu_ib *ib);
1217void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1218int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1219 struct amdgpu_ib *ib, void *owner);
1220int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1221void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1222int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1223/* Ring access between begin & end cannot sleep */
1224void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1225int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1226int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1227void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 1228void amdgpu_ring_commit(struct amdgpu_ring *ring);
1229void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1230void amdgpu_ring_undo(struct amdgpu_ring *ring);
1231void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1232void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1233bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1234unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1235 uint32_t **data);
1236int amdgpu_ring_restore(struct amdgpu_ring *ring,
1237 unsigned size, uint32_t *data);
1238int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1239 unsigned ring_size, u32 nop, u32 align_mask,
1240 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1241 enum amdgpu_ring_type ring_type);
1242void amdgpu_ring_fini(struct amdgpu_ring *ring);
1243
1244/*
1245 * CS.
1246 */
1247struct amdgpu_cs_chunk {
1248 uint32_t chunk_id;
1249 uint32_t length_dw;
1250 uint32_t *kdata;
1251 void __user *user_ptr;
1252};
1253
1254struct amdgpu_cs_parser {
1255 struct amdgpu_device *adev;
1256 struct drm_file *filp;
3cb485f3 1257 struct amdgpu_ctx *ctx;
97b2e202
AD		 1258 struct amdgpu_bo_list *bo_list;
1259 /* chunks */
1260 unsigned nchunks;
1261 struct amdgpu_cs_chunk *chunks;
1262 /* relocations */
1263 struct amdgpu_bo_list_entry *vm_bos;
97b2e202
AD		 1264 struct list_head validated;
1265
1266 struct amdgpu_ib *ibs;
1267 uint32_t num_ibs;
1268
1269 struct ww_acquire_ctx ticket;
1270
1271 /* user fence */
1272 struct amdgpu_user_fence uf;
1273};
1274
bb977d37
CZ		 1275struct amdgpu_job {
1276 struct amd_sched_job base;
1277 struct amdgpu_device *adev;
bb977d37
CZ		 1278 struct amdgpu_ib *ibs;
1279 uint32_t num_ibs;
1280 struct mutex job_lock;
1281 struct amdgpu_user_fence uf;
4c7eb91c 1282 int (*free_job)(struct amdgpu_job *job);
bb977d37 1283};
a6db8a33
JZ		 1284#define to_amdgpu_job(sched_job) \
1285 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1286
97b2e202
AD		 1287static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1288{
1289 return p->ibs[ib_idx].ptr[idx];
1290}
1291
1292/*
1293 * Writeback
1294 */
1295#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1296
1297struct amdgpu_wb {
1298 struct amdgpu_bo *wb_obj;
1299 volatile uint32_t *wb;
1300 uint64_t gpu_addr;
1301 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1302 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1303};
1304
1305int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1306void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1307
1308/**
1309 * struct amdgpu_pm - power management datas
1310 * It keeps track of various data needed to take powermanagement decision.
1311 */
1312
1313enum amdgpu_pm_state_type {
1314 /* not used for dpm */
1315 POWER_STATE_TYPE_DEFAULT,
1316 POWER_STATE_TYPE_POWERSAVE,
1317 /* user selectable states */
1318 POWER_STATE_TYPE_BATTERY,
1319 POWER_STATE_TYPE_BALANCED,
1320 POWER_STATE_TYPE_PERFORMANCE,
1321 /* internal states */
1322 POWER_STATE_TYPE_INTERNAL_UVD,
1323 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1324 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1325 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1326 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1327 POWER_STATE_TYPE_INTERNAL_BOOT,
1328 POWER_STATE_TYPE_INTERNAL_THERMAL,
1329 POWER_STATE_TYPE_INTERNAL_ACPI,
1330 POWER_STATE_TYPE_INTERNAL_ULV,
1331 POWER_STATE_TYPE_INTERNAL_3DPERF,
1332};
1333
1334enum amdgpu_int_thermal_type {
1335 THERMAL_TYPE_NONE,
1336 THERMAL_TYPE_EXTERNAL,
1337 THERMAL_TYPE_EXTERNAL_GPIO,
1338 THERMAL_TYPE_RV6XX,
1339 THERMAL_TYPE_RV770,
1340 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1341 THERMAL_TYPE_EVERGREEN,
1342 THERMAL_TYPE_SUMO,
1343 THERMAL_TYPE_NI,
1344 THERMAL_TYPE_SI,
1345 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1346 THERMAL_TYPE_CI,
1347 THERMAL_TYPE_KV,
1348};
1349
1350enum amdgpu_dpm_auto_throttle_src {
1351 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1352 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1353};
1354
1355enum amdgpu_dpm_event_src {
1356 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1357 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1358 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1359 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1360 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1361};
1362
1363#define AMDGPU_MAX_VCE_LEVELS 6
1364
1365enum amdgpu_vce_level {
1366 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1367 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1368 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1369 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1370 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1371 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1372};
1373
1374struct amdgpu_ps {
1375 u32 caps; /* vbios flags */
1376 u32 class; /* vbios flags */
1377 u32 class2; /* vbios flags */
1378 /* UVD clocks */
1379 u32 vclk;
1380 u32 dclk;
1381 /* VCE clocks */
1382 u32 evclk;
1383 u32 ecclk;
1384 bool vce_active;
1385 enum amdgpu_vce_level vce_level;
1386 /* asic priv */
1387 void *ps_priv;
1388};
1389
1390struct amdgpu_dpm_thermal {
1391 /* thermal interrupt work */
1392 struct work_struct work;
1393 /* low temperature threshold */
1394 int min_temp;
1395 /* high temperature threshold */
1396 int max_temp;
1397 /* was last interrupt low to high or high to low */
1398 bool high_to_low;
1399 /* interrupt source */
1400 struct amdgpu_irq_src irq;
1401};
1402
1403enum amdgpu_clk_action
1404{
1405 AMDGPU_SCLK_UP = 1,
1406 AMDGPU_SCLK_DOWN
1407};
1408
1409struct amdgpu_blacklist_clocks
1410{
1411 u32 sclk;
1412 u32 mclk;
1413 enum amdgpu_clk_action action;
1414};
1415
1416struct amdgpu_clock_and_voltage_limits {
1417 u32 sclk;
1418 u32 mclk;
1419 u16 vddc;
1420 u16 vddci;
1421};
1422
1423struct amdgpu_clock_array {
1424 u32 count;
1425 u32 *values;
1426};
1427
1428struct amdgpu_clock_voltage_dependency_entry {
1429 u32 clk;
1430 u16 v;
1431};
1432
1433struct amdgpu_clock_voltage_dependency_table {
1434 u32 count;
1435 struct amdgpu_clock_voltage_dependency_entry *entries;
1436};
1437
1438union amdgpu_cac_leakage_entry {
1439 struct {
1440 u16 vddc;
1441 u32 leakage;
1442 };
1443 struct {
1444 u16 vddc1;
1445 u16 vddc2;
1446 u16 vddc3;
1447 };
1448};
1449
1450struct amdgpu_cac_leakage_table {
1451 u32 count;
1452 union amdgpu_cac_leakage_entry *entries;
1453};
1454
1455struct amdgpu_phase_shedding_limits_entry {
1456 u16 voltage;
1457 u32 sclk;
1458 u32 mclk;
1459};
1460
1461struct amdgpu_phase_shedding_limits_table {
1462 u32 count;
1463 struct amdgpu_phase_shedding_limits_entry *entries;
1464};
1465
1466struct amdgpu_uvd_clock_voltage_dependency_entry {
1467 u32 vclk;
1468 u32 dclk;
1469 u16 v;
1470};
1471
1472struct amdgpu_uvd_clock_voltage_dependency_table {
1473 u8 count;
1474 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1475};
1476
1477struct amdgpu_vce_clock_voltage_dependency_entry {
1478 u32 ecclk;
1479 u32 evclk;
1480 u16 v;
1481};
1482
1483struct amdgpu_vce_clock_voltage_dependency_table {
1484 u8 count;
1485 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1486};
1487
1488struct amdgpu_ppm_table {
1489 u8 ppm_design;
1490 u16 cpu_core_number;
1491 u32 platform_tdp;
1492 u32 small_ac_platform_tdp;
1493 u32 platform_tdc;
1494 u32 small_ac_platform_tdc;
1495 u32 apu_tdp;
1496 u32 dgpu_tdp;
1497 u32 dgpu_ulv_power;
1498 u32 tj_max;
1499};
1500
1501struct amdgpu_cac_tdp_table {
1502 u16 tdp;
1503 u16 configurable_tdp;
1504 u16 tdc;
1505 u16 battery_power_limit;
1506 u16 small_power_limit;
1507 u16 low_cac_leakage;
1508 u16 high_cac_leakage;
1509 u16 maximum_power_delivery_limit;
1510};
1511
1512struct amdgpu_dpm_dynamic_state {
1513 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1514 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1515 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1516 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1517 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1518 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1519 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1520 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1521 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1522 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1523 struct amdgpu_clock_array valid_sclk_values;
1524 struct amdgpu_clock_array valid_mclk_values;
1525 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1526 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1527 u32 mclk_sclk_ratio;
1528 u32 sclk_mclk_delta;
1529 u16 vddc_vddci_delta;
1530 u16 min_vddc_for_pcie_gen2;
1531 struct amdgpu_cac_leakage_table cac_leakage_table;
1532 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1533 struct amdgpu_ppm_table *ppm_table;
1534 struct amdgpu_cac_tdp_table *cac_tdp_table;
1535};
1536
1537struct amdgpu_dpm_fan {
1538 u16 t_min;
1539 u16 t_med;
1540 u16 t_high;
1541 u16 pwm_min;
1542 u16 pwm_med;
1543 u16 pwm_high;
1544 u8 t_hyst;
1545 u32 cycle_delay;
1546 u16 t_max;
1547 u8 control_mode;
1548 u16 default_max_fan_pwm;
1549 u16 default_fan_output_sensitivity;
1550 u16 fan_output_sensitivity;
1551 bool ucode_fan_control;
1552};
1553
1554enum amdgpu_pcie_gen {
1555 AMDGPU_PCIE_GEN1 = 0,
1556 AMDGPU_PCIE_GEN2 = 1,
1557 AMDGPU_PCIE_GEN3 = 2,
1558 AMDGPU_PCIE_GEN_INVALID = 0xffff
1559};
1560
1561enum amdgpu_dpm_forced_level {
1562 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1563 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1564 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1565};
1566
1567struct amdgpu_vce_state {
1568 /* vce clocks */
1569 u32 evclk;
1570 u32 ecclk;
1571 /* gpu clocks */
1572 u32 sclk;
1573 u32 mclk;
1574 u8 clk_idx;
1575 u8 pstate;
1576};
1577
1578struct amdgpu_dpm_funcs {
1579 int (*get_temperature)(struct amdgpu_device *adev);
1580 int (*pre_set_power_state)(struct amdgpu_device *adev);
1581 int (*set_power_state)(struct amdgpu_device *adev);
1582 void (*post_set_power_state)(struct amdgpu_device *adev);
1583 void (*display_configuration_changed)(struct amdgpu_device *adev);
1584 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1585 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1586 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1587 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1588 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1589 bool (*vblank_too_short)(struct amdgpu_device *adev);
1590 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1591 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1592 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1593 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1594 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1595 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1596 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1597};
1598
1599struct amdgpu_dpm {
1600 struct amdgpu_ps *ps;
1601 /* number of valid power states */
1602 int num_ps;
1603 /* current power state that is active */
1604 struct amdgpu_ps *current_ps;
1605 /* requested power state */
1606 struct amdgpu_ps *requested_ps;
1607 /* boot up power state */
1608 struct amdgpu_ps *boot_ps;
1609 /* default uvd power state */
1610 struct amdgpu_ps *uvd_ps;
1611 /* vce requirements */
1612 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1613 enum amdgpu_vce_level vce_level;
1614 enum amdgpu_pm_state_type state;
1615 enum amdgpu_pm_state_type user_state;
1616 u32 platform_caps;
1617 u32 voltage_response_time;
1618 u32 backbias_response_time;
1619 void *priv;
1620 u32 new_active_crtcs;
1621 int new_active_crtc_count;
1622 u32 current_active_crtcs;
1623 int current_active_crtc_count;
1624 struct amdgpu_dpm_dynamic_state dyn_state;
1625 struct amdgpu_dpm_fan fan;
1626 u32 tdp_limit;
1627 u32 near_tdp_limit;
1628 u32 near_tdp_limit_adjusted;
1629 u32 sq_ramping_threshold;
1630 u32 cac_leakage;
1631 u16 tdp_od_limit;
1632 u32 tdp_adjustment;
1633 u16 load_line_slope;
1634 bool power_control;
1635 bool ac_power;
1636 /* special states active */
1637 bool thermal_active;
1638 bool uvd_active;
1639 bool vce_active;
1640 /* thermal handling */
1641 struct amdgpu_dpm_thermal thermal;
1642 /* forced levels */
1643 enum amdgpu_dpm_forced_level forced_level;
1644};
1645
1646struct amdgpu_pm {
1647 struct mutex mutex;
97b2e202
AD		 1648 u32 current_sclk;
1649 u32 current_mclk;
1650 u32 default_sclk;
1651 u32 default_mclk;
1652 struct amdgpu_i2c_chan *i2c_bus;
1653 /* internal thermal controller on rv6xx+ */
1654 enum amdgpu_int_thermal_type int_thermal_type;
1655 struct device *int_hwmon_dev;
1656 /* fan control parameters */
1657 bool no_fan;
1658 u8 fan_pulses_per_revolution;
1659 u8 fan_min_rpm;
1660 u8 fan_max_rpm;
1661 /* dpm */
1662 bool dpm_enabled;
1663 struct amdgpu_dpm dpm;
1664 const struct firmware *fw; /* SMC firmware */
1665 uint32_t fw_version;
1666 const struct amdgpu_dpm_funcs *funcs;
1667};
1668
1669/*
1670 * UVD
1671 */
1672#define AMDGPU_MAX_UVD_HANDLES 10
1673#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1674#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1675#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1676
1677struct amdgpu_uvd {
1678 struct amdgpu_bo *vcpu_bo;
1679 void *cpu_addr;
1680 uint64_t gpu_addr;
97b2e202
AD		 1681 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1682 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1683 struct delayed_work idle_work;
1684 const struct firmware *fw; /* UVD firmware */
1685 struct amdgpu_ring ring;
1686 struct amdgpu_irq_src irq;
1687 bool address_64_bit;
1688};
1689
1690/*
1691 * VCE
1692 */
1693#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1694#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1695
6a585777
AD		 1696#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1697#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1698
97b2e202
AD		 1699struct amdgpu_vce {
1700 struct amdgpu_bo *vcpu_bo;
1701 uint64_t gpu_addr;
1702 unsigned fw_version;
1703 unsigned fb_version;
1704 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1705 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1706 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1707 struct delayed_work idle_work;
1708 const struct firmware *fw; /* VCE firmware */
1709 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1710 struct amdgpu_irq_src irq;
6a585777 1711 unsigned harvest_config;
97b2e202
AD		 1712};
1713
1714/*
1715 * SDMA
1716 */
c113ea1c 1717struct amdgpu_sdma_instance {
97b2e202
AD		 1718 /* SDMA firmware */
1719 const struct firmware *fw;
1720 uint32_t fw_version;
cfa2104f 1721 uint32_t feature_version;
97b2e202
AD		 1722
1723 struct amdgpu_ring ring;
18111de0 1724 bool burst_nop;
97b2e202
AD		 1725};
1726
c113ea1c
AD		 1727struct amdgpu_sdma {
1728 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1729 struct amdgpu_irq_src trap_irq;
1730 struct amdgpu_irq_src illegal_inst_irq;
1731 int num_instances;
1732};
1733
97b2e202
AD		 1734/*
1735 * Firmware
1736 */
1737struct amdgpu_firmware {
1738 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1739 bool smu_load;
1740 struct amdgpu_bo *fw_buf;
1741 unsigned int fw_size;
1742};
1743
1744/*
1745 * Benchmarking
1746 */
1747void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1748
1749
1750/*
1751 * Testing
1752 */
1753void amdgpu_test_moves(struct amdgpu_device *adev);
1754void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1755 struct amdgpu_ring *cpA,
1756 struct amdgpu_ring *cpB);
1757void amdgpu_test_syncing(struct amdgpu_device *adev);
1758
1759/*
1760 * MMU Notifier
1761 */
1762#if defined(CONFIG_MMU_NOTIFIER)
1763int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1764void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1765#else
1766static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1767{
1768 return -ENODEV;
1769}
1770static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1771#endif
1772
1773/*
1774 * Debugfs
1775 */
1776struct amdgpu_debugfs {
1777 struct drm_info_list *files;
1778 unsigned num_files;
1779};
1780
1781int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1782 struct drm_info_list *files,
1783 unsigned nfiles);
1784int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1785
1786#if defined(CONFIG_DEBUG_FS)
1787int amdgpu_debugfs_init(struct drm_minor *minor);
1788void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1789#endif
1790
1791/*
1792 * amdgpu smumgr functions
1793 */
1794struct amdgpu_smumgr_funcs {
1795 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1796 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1797 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1798};
1799
1800/*
1801 * amdgpu smumgr
1802 */
1803struct amdgpu_smumgr {
1804 struct amdgpu_bo *toc_buf;
1805 struct amdgpu_bo *smu_buf;
1806 /* asic priv smu data */
1807 void *priv;
1808 spinlock_t smu_lock;
1809 /* smumgr functions */
1810 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1811 /* ucode loading complete flag */
1812 uint32_t fw_flags;
1813};
1814
1815/*
1816 * ASIC specific register table accessible by UMD
1817 */
1818struct amdgpu_allowed_register_entry {
1819 uint32_t reg_offset;
1820 bool untouched;
1821 bool grbm_indexed;
1822};
1823
1824struct amdgpu_cu_info {
1825 uint32_t number; /* total active CU number */
1826 uint32_t ao_cu_mask;
1827 uint32_t bitmap[4][4];
1828};
1829
1830
1831/*
1832 * ASIC specific functions.
1833 */
1834struct amdgpu_asic_funcs {
1835 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1836 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1837 u32 sh_num, u32 reg_offset, u32 *value);
1838 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1839 int (*reset)(struct amdgpu_device *adev);
1840 /* wait for mc_idle */
1841 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1842 /* get the reference clock */
1843 u32 (*get_xclk)(struct amdgpu_device *adev);
1844 /* get the gpu clock counter */
1845 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1846 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1847 /* MM block clocks */
1848 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1849 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1850};
1851
1852/*
1853 * IOCTL.
1854 */
1855int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859
1860int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *filp);
1866int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1867 struct drm_file *filp);
1868int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1869 struct drm_file *filp);
1870int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1871 struct drm_file *filp);
1872int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1873int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1874
1875int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1876 struct drm_file *filp);
1877
1878/* VRAM scratch page for HDP bug, default vram page */
1879struct amdgpu_vram_scratch {
1880 struct amdgpu_bo *robj;
1881 volatile uint32_t *ptr;
1882 u64 gpu_addr;
1883};
1884
1885/*
1886 * ACPI
1887 */
1888struct amdgpu_atif_notification_cfg {
1889 bool enabled;
1890 int command_code;
1891};
1892
1893struct amdgpu_atif_notifications {
1894 bool display_switch;
1895 bool expansion_mode_change;
1896 bool thermal_state;
1897 bool forced_power_state;
1898 bool system_power_state;
1899 bool display_conf_change;
1900 bool px_gfx_switch;
1901 bool brightness_change;
1902 bool dgpu_display_event;
1903};
1904
1905struct amdgpu_atif_functions {
1906 bool system_params;
1907 bool sbios_requests;
1908 bool select_active_disp;
1909 bool lid_state;
1910 bool get_tv_standard;
1911 bool set_tv_standard;
1912 bool get_panel_expansion_mode;
1913 bool set_panel_expansion_mode;
1914 bool temperature_change;
1915 bool graphics_device_types;
1916};
1917
1918struct amdgpu_atif {
1919 struct amdgpu_atif_notifications notifications;
1920 struct amdgpu_atif_functions functions;
1921 struct amdgpu_atif_notification_cfg notification_cfg;
1922 struct amdgpu_encoder *encoder_for_bl;
1923};
1924
1925struct amdgpu_atcs_functions {
1926 bool get_ext_state;
1927 bool pcie_perf_req;
1928 bool pcie_dev_rdy;
1929 bool pcie_bus_width;
1930};
1931
1932struct amdgpu_atcs {
1933 struct amdgpu_atcs_functions functions;
1934};
1935
d03846af
CZ		 1936/*
1937 * CGS
1938 */
1939void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1940void amdgpu_cgs_destroy_device(void *cgs_device);
1941
1942
97b2e202
AD		 1943/*
1944 * Core structure, functions and helpers.
1945 */
1946typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1947typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1948
1949typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1950typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1951
8faf0e08
AD		 1952struct amdgpu_ip_block_status {
1953 bool valid;
1954 bool sw;
1955 bool hw;
1956};
1957
97b2e202
AD		 1958struct amdgpu_device {
1959 struct device *dev;
1960 struct drm_device *ddev;
1961 struct pci_dev *pdev;
1962 struct rw_semaphore exclusive_lock;
1963
1964 /* ASIC */
2f7d10b3 1965 enum amd_asic_type asic_type;
97b2e202
AD		 1966 uint32_t family;
1967 uint32_t rev_id;
1968 uint32_t external_rev_id;
1969 unsigned long flags;
1970 int usec_timeout;
1971 const struct amdgpu_asic_funcs *asic_funcs;
1972 bool shutdown;
1973 bool suspend;
1974 bool need_dma32;
1975 bool accel_working;
1976 bool needs_reset;
1977 struct work_struct reset_work;
1978 struct notifier_block acpi_nb;
1979 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1980 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1981 unsigned debugfs_count;
1982#if defined(CONFIG_DEBUG_FS)
1983 struct dentry *debugfs_regs;
1984#endif
1985 struct amdgpu_atif atif;
1986 struct amdgpu_atcs atcs;
1987 struct mutex srbm_mutex;
1988 /* GRBM index mutex. Protects concurrent access to GRBM index */
1989 struct mutex grbm_idx_mutex;
1990 struct dev_pm_domain vga_pm_domain;
1991 bool have_disp_power_ref;
1992
1993 /* BIOS */
1994 uint8_t *bios;
1995 bool is_atom_bios;
1996 uint16_t bios_header_start;
1997 struct amdgpu_bo *stollen_vga_memory;
1998 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1999
2000 /* Register/doorbell mmio */
2001 resource_size_t rmmio_base;
2002 resource_size_t rmmio_size;
2003 void __iomem *rmmio;
2004 /* protects concurrent MM_INDEX/DATA based register access */
2005 spinlock_t mmio_idx_lock;
2006 /* protects concurrent SMC based register access */
2007 spinlock_t smc_idx_lock;
2008 amdgpu_rreg_t smc_rreg;
2009 amdgpu_wreg_t smc_wreg;
2010 /* protects concurrent PCIE register access */
2011 spinlock_t pcie_idx_lock;
2012 amdgpu_rreg_t pcie_rreg;
2013 amdgpu_wreg_t pcie_wreg;
2014 /* protects concurrent UVD register access */
2015 spinlock_t uvd_ctx_idx_lock;
2016 amdgpu_rreg_t uvd_ctx_rreg;
2017 amdgpu_wreg_t uvd_ctx_wreg;
2018 /* protects concurrent DIDT register access */
2019 spinlock_t didt_idx_lock;
2020 amdgpu_rreg_t didt_rreg;
2021 amdgpu_wreg_t didt_wreg;
2022 /* protects concurrent ENDPOINT (audio) register access */
2023 spinlock_t audio_endpt_idx_lock;
2024 amdgpu_block_rreg_t audio_endpt_rreg;
2025 amdgpu_block_wreg_t audio_endpt_wreg;
2026 void __iomem *rio_mem;
2027 resource_size_t rio_mem_size;
2028 struct amdgpu_doorbell doorbell;
2029
2030 /* clock/pll info */
2031 struct amdgpu_clock clock;
2032
2033 /* MC */
2034 struct amdgpu_mc mc;
2035 struct amdgpu_gart gart;
2036 struct amdgpu_dummy_page dummy_page;
2037 struct amdgpu_vm_manager vm_manager;
2038
2039 /* memory management */
2040 struct amdgpu_mman mman;
2041 struct amdgpu_gem gem;
2042 struct amdgpu_vram_scratch vram_scratch;
2043 struct amdgpu_wb wb;
2044 atomic64_t vram_usage;
2045 atomic64_t vram_vis_usage;
2046 atomic64_t gtt_usage;
2047 atomic64_t num_bytes_moved;
d94aed5a 2048 atomic_t gpu_reset_counter;
97b2e202
AD		 2049
2050 /* display */
2051 struct amdgpu_mode_info mode_info;
2052 struct work_struct hotplug_work;
2053 struct amdgpu_irq_src crtc_irq;
2054 struct amdgpu_irq_src pageflip_irq;
2055 struct amdgpu_irq_src hpd_irq;
2056
2057 /* rings */
97b2e202
AD		 2058 unsigned fence_context;
2059 struct mutex ring_lock;
2060 unsigned num_rings;
2061 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2062 bool ib_pool_ready;
2063 struct amdgpu_sa_manager ring_tmp_bo;
2064
2065 /* interrupts */
2066 struct amdgpu_irq irq;
2067
2068 /* dpm */
2069 struct amdgpu_pm pm;
2070 u32 cg_flags;
2071 u32 pg_flags;
2072
2073 /* amdgpu smumgr */
2074 struct amdgpu_smumgr smu;
2075
2076 /* gfx */
2077 struct amdgpu_gfx gfx;
2078
2079 /* sdma */
c113ea1c 2080 struct amdgpu_sdma sdma;
97b2e202
AD		 2081
2082 /* uvd */
2083 bool has_uvd;
2084 struct amdgpu_uvd uvd;
2085
2086 /* vce */
2087 struct amdgpu_vce vce;
2088
2089 /* firmwares */
2090 struct amdgpu_firmware firmware;
2091
2092 /* GDS */
2093 struct amdgpu_gds gds;
2094
2095 const struct amdgpu_ip_block_version *ip_blocks;
2096 int num_ip_blocks;
8faf0e08 2097 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2098 struct mutex mn_lock;
2099 DECLARE_HASHTABLE(mn_hash, 7);
2100
2101 /* tracking pinned memory */
2102 u64 vram_pin_size;
2103 u64 gart_pin_size;
130e0371
OG		 2104
2105 /* amdkfd interface */
2106 struct kfd_dev *kfd;
23ca0e4e
CZ		 2107
2108 /* kernel conext for IB submission */
47f38501 2109 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2110};
2111
2112bool amdgpu_device_is_px(struct drm_device *dev);
2113int amdgpu_device_init(struct amdgpu_device *adev,
2114 struct drm_device *ddev,
2115 struct pci_dev *pdev,
2116 uint32_t flags);
2117void amdgpu_device_fini(struct amdgpu_device *adev);
2118int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2119
2120uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2121 bool always_indirect);
2122void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2123 bool always_indirect);
2124u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2125void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2126
2127u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2128void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2129
2130/*
2131 * Cast helper
2132 */
2133extern const struct fence_ops amdgpu_fence_ops;
2134static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2135{
2136 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2137
2138 if (__f->base.ops == &amdgpu_fence_ops)
2139 return __f;
2140
2141 return NULL;
2142}
2143
2144/*
2145 * Registers read & write functions.
2146 */
2147#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2148#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2149#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2150#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2151#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2152#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2153#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2154#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2155#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2156#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2157#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2158#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2159#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2160#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2161#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2162#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2163#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2164#define WREG32_P(reg, val, mask) \
2165 do { \
2166 uint32_t tmp_ = RREG32(reg); \
2167 tmp_ &= (mask); \
2168 tmp_ |= ((val) & ~(mask)); \
2169 WREG32(reg, tmp_); \
2170 } while (0)
2171#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2172#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2173#define WREG32_PLL_P(reg, val, mask) \
2174 do { \
2175 uint32_t tmp_ = RREG32_PLL(reg); \
2176 tmp_ &= (mask); \
2177 tmp_ |= ((val) & ~(mask)); \
2178 WREG32_PLL(reg, tmp_); \
2179 } while (0)
2180#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2181#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2182#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2183
2184#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2185#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2186
2187#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2188#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2189
2190#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2191 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2192 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2193
2194#define REG_GET_FIELD(value, reg, field) \
2195 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2196
2197/*
2198 * BIOS helpers.
2199 */
2200#define RBIOS8(i) (adev->bios[i])
2201#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2202#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2203
2204/*
2205 * RING helpers.
2206 */
2207static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2208{
2209 if (ring->count_dw <= 0)
86c2b790 2210 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2211 ring->ring[ring->wptr++] = v;
2212 ring->wptr &= ring->ptr_mask;
2213 ring->count_dw--;
2214 ring->ring_free_dw--;
2215}
2216
c113ea1c
AD		 2217static inline struct amdgpu_sdma_instance *
2218amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2219{
2220 struct amdgpu_device *adev = ring->adev;
2221 int i;
2222
c113ea1c
AD		 2223 for (i = 0; i < adev->sdma.num_instances; i++)
2224 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2225 break;
2226
2227 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2228 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2229 else
2230 return NULL;
2231}
2232
97b2e202
AD		 2233/*
2234 * ASICs macro.
2235 */
2236#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2237#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2238#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2239#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2240#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2241#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2242#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2243#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2244#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2245#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2246#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2247#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2248#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2249#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2250#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2251#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2252#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2253#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2254#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2255#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2256#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2257#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2258#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2259#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2260#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2261#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2262#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2263#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2264#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2265#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2266#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2267#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2268#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2269#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2270#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2271#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2272#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2273#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2274#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2275#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2276#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2277#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2278#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2279#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2280#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2281#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2282#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2283#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2284#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2285#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2286#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2287#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2288#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2289#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2290#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2291#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2292#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2293#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2294#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2295#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2296#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2297#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
b7a07769 2298#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
97b2e202
AD		 2299#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2300#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2301#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2302#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2303#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2304
2305#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2306
2307/* Common functions */
2308int amdgpu_gpu_reset(struct amdgpu_device *adev);
2309void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2310bool amdgpu_card_posted(struct amdgpu_device *adev);
2311void amdgpu_update_display_priority(struct amdgpu_device *adev);
2312bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82
CZ		 2313struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2314 struct drm_file *filp,
2315 struct amdgpu_ctx *ctx,
2316 struct amdgpu_ib *ibs,
2317 uint32_t num_ibs);
2318
97b2e202
AD		 2319int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2320int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2321 u32 ip_instance, u32 ring,
2322 struct amdgpu_ring **out_ring);
2323void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2324bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2325int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2326 uint32_t flags);
2327bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2328bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2329uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2330 struct ttm_mem_reg *mem);
2331void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2332void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2333void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2334void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2335 const u32 *registers,
2336 const u32 array_size);
2337
2338bool amdgpu_device_is_px(struct drm_device *dev);
2339/* atpx handler */
2340#if defined(CONFIG_VGA_SWITCHEROO)
2341void amdgpu_register_atpx_handler(void);
2342void amdgpu_unregister_atpx_handler(void);
2343#else
2344static inline void amdgpu_register_atpx_handler(void) {}
2345static inline void amdgpu_unregister_atpx_handler(void) {}
2346#endif
2347
2348/*
2349 * KMS
2350 */
2351extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2352extern int amdgpu_max_kms_ioctl;
2353
2354int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2355int amdgpu_driver_unload_kms(struct drm_device *dev);
2356void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2357int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2358void amdgpu_driver_postclose_kms(struct drm_device *dev,
2359 struct drm_file *file_priv);
2360void amdgpu_driver_preclose_kms(struct drm_device *dev,
2361 struct drm_file *file_priv);
2362int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2363int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2364u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2365int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2366void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2367int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2368 int *max_error,
2369 struct timeval *vblank_time,
2370 unsigned flags);
2371long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2372 unsigned long arg);
2373
2374/*
2375 * vm
2376 */
2377int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2378void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2379struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2380 struct amdgpu_vm *vm,
2381 struct list_head *head);
7f8a5290
CK		 2382int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2383 struct amdgpu_sync *sync);
97b2e202
AD		 2384void amdgpu_vm_flush(struct amdgpu_ring *ring,
2385 struct amdgpu_vm *vm,
3c62338c 2386 struct fence *updates);
97b2e202
AD		 2387void amdgpu_vm_fence(struct amdgpu_device *adev,
2388 struct amdgpu_vm *vm,
2389 struct amdgpu_fence *fence);
2390uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2391int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2392 struct amdgpu_vm *vm);
2393int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2394 struct amdgpu_vm *vm);
2395int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
cfe2c978 2396 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
97b2e202
AD		 2397int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2398 struct amdgpu_bo_va *bo_va,
2399 struct ttm_mem_reg *mem);
2400void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2401 struct amdgpu_bo *bo);
2402struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2403 struct amdgpu_bo *bo);
2404struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2405 struct amdgpu_vm *vm,
2406 struct amdgpu_bo *bo);
2407int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2408 struct amdgpu_bo_va *bo_va,
2409 uint64_t addr, uint64_t offset,
2410 uint64_t size, uint32_t flags);
2411int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2412 struct amdgpu_bo_va *bo_va,
2413 uint64_t addr);
2414void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2415 struct amdgpu_bo_va *bo_va);
c7ae72c0 2416int amdgpu_vm_free_job(struct amdgpu_job *job);
97b2e202
AD		 2417/*
2418 * functions used by amdgpu_encoder.c
2419 */
2420struct amdgpu_afmt_acr {
2421 u32 clock;
2422
2423 int n_32khz;
2424 int cts_32khz;
2425
2426 int n_44_1khz;
2427 int cts_44_1khz;
2428
2429 int n_48khz;
2430 int cts_48khz;
2431
2432};
2433
2434struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2435
2436/* amdgpu_acpi.c */
2437#if defined(CONFIG_ACPI)
2438int amdgpu_acpi_init(struct amdgpu_device *adev);
2439void amdgpu_acpi_fini(struct amdgpu_device *adev);
2440bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2441int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2442 u8 perf_req, bool advertise);
2443int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2444#else
2445static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2446static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2447#endif
2448
2449struct amdgpu_bo_va_mapping *
2450amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2451 uint64_t addr, struct amdgpu_bo **bo);
2452
2453#include "amdgpu_object.h"
2454
2455#endif
Linux 6.x block layer and io_uring tree(s)