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drm/amdgpu:new PM4 entry for VI/AI
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202
AD		 38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
c632d799 54#include "amdgpu_ttm.h"
0e5ca0d1 55#include "amdgpu_psp.h"
97b2e202 56#include "amdgpu_gds.h"
56113504 57#include "amdgpu_sync.h"
78023016 58#include "amdgpu_ring.h"
073440d2 59#include "amdgpu_vm.h"
1f7371b2 60#include "amd_powerplay.h"
cf097881 61#include "amdgpu_dpm.h"
a8fe58ce 62#include "amdgpu_acp.h"
4df654d2 63#include "amdgpu_uvd.h"
5e568178 64#include "amdgpu_vce.h"
97b2e202 65
b80d8475 66#include "gpu_scheduler.h"
ceeb50ed 67#include "amdgpu_virt.h"
b80d8475 68
97b2e202
AD		 69/*
70 * Modules parameters.
71 */
72extern int amdgpu_modeset;
73extern int amdgpu_vram_limit;
74extern int amdgpu_gart_size;
95844d20 75extern int amdgpu_moverate;
97b2e202
AD		 76extern int amdgpu_benchmarking;
77extern int amdgpu_testing;
78extern int amdgpu_audio;
79extern int amdgpu_disp_priority;
80extern int amdgpu_hw_i2c;
81extern int amdgpu_pcie_gen2;
82extern int amdgpu_msi;
83extern int amdgpu_lockup_timeout;
84extern int amdgpu_dpm;
e635ee07 85extern int amdgpu_fw_load_type;
97b2e202
AD		 86extern int amdgpu_aspm;
87extern int amdgpu_runtime_pm;
97b2e202
AD		 88extern unsigned amdgpu_ip_block_mask;
89extern int amdgpu_bapm;
90extern int amdgpu_deep_color;
91extern int amdgpu_vm_size;
92extern int amdgpu_vm_block_size;
d9c13156 93extern int amdgpu_vm_fault_stop;
b495bd3a 94extern int amdgpu_vm_debug;
1333f723 95extern int amdgpu_sched_jobs;
4afcb303 96extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 97extern int amdgpu_no_evict;
98extern int amdgpu_direct_gma_size;
cd474ba0
AD		 99extern unsigned amdgpu_pcie_gen_cap;
100extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 101extern unsigned amdgpu_cg_mask;
102extern unsigned amdgpu_pg_mask;
6f8941a2 103extern char *amdgpu_disable_cu;
9accf2fd 104extern char *amdgpu_virtual_display;
5141e9d2 105extern unsigned amdgpu_pp_feature_mask;
6a7f76e7 106extern int amdgpu_vram_page_split;
bce23e00
AD		 107extern int amdgpu_ngg;
108extern int amdgpu_prim_buf_per_se;
109extern int amdgpu_pos_buf_per_se;
110extern int amdgpu_cntl_sb_buf_per_se;
111extern int amdgpu_param_buf_per_se;
97b2e202 112
55ed8caf 113#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 114#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 115#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
116#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
117/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
118#define AMDGPU_IB_POOL_SIZE 16
119#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
120#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 121#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 122
36f523a7
JZ		 123/* max number of IP instances */
124#define AMDGPU_MAX_SDMA_INSTANCES 2
125
97b2e202
AD		 126/* hard reset data */
127#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
128
129/* reset flags */
130#define AMDGPU_RESET_GFX (1 << 0)
131#define AMDGPU_RESET_COMPUTE (1 << 1)
132#define AMDGPU_RESET_DMA (1 << 2)
133#define AMDGPU_RESET_CP (1 << 3)
134#define AMDGPU_RESET_GRBM (1 << 4)
135#define AMDGPU_RESET_DMA1 (1 << 5)
136#define AMDGPU_RESET_RLC (1 << 6)
137#define AMDGPU_RESET_SEM (1 << 7)
138#define AMDGPU_RESET_IH (1 << 8)
139#define AMDGPU_RESET_VMC (1 << 9)
140#define AMDGPU_RESET_MC (1 << 10)
141#define AMDGPU_RESET_DISPLAY (1 << 11)
142#define AMDGPU_RESET_UVD (1 << 12)
143#define AMDGPU_RESET_VCE (1 << 13)
144#define AMDGPU_RESET_VCE1 (1 << 14)
145
97b2e202
AD		 146/* GFX current status */
147#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
148#define AMDGPU_GFX_SAFE_MODE 0x00000001L
149#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
150#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
151#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
152
153/* max cursor sizes (in pixels) */
154#define CIK_CURSOR_WIDTH 128
155#define CIK_CURSOR_HEIGHT 128
156
157struct amdgpu_device;
97b2e202 158struct amdgpu_ib;
97b2e202 159struct amdgpu_cs_parser;
bb977d37 160struct amdgpu_job;
97b2e202 161struct amdgpu_irq_src;
0b492a4c 162struct amdgpu_fpriv;
97b2e202
AD		 163
164enum amdgpu_cp_irq {
165 AMDGPU_CP_IRQ_GFX_EOP = 0,
166 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
173 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
174
175 AMDGPU_CP_IRQ_LAST
176};
177
178enum amdgpu_sdma_irq {
179 AMDGPU_SDMA_IRQ_TRAP0 = 0,
180 AMDGPU_SDMA_IRQ_TRAP1,
181
182 AMDGPU_SDMA_IRQ_LAST
183};
184
185enum amdgpu_thermal_irq {
186 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
187 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
188
189 AMDGPU_THERMAL_IRQ_LAST
190};
191
4e638ae9
XY		 192enum amdgpu_kiq_irq {
193 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
194 AMDGPU_CP_KIQ_IRQ_LAST
195};
196
97b2e202 197int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 198 enum amd_ip_block_type block_type,
199 enum amd_clockgating_state state);
97b2e202 200int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 201 enum amd_ip_block_type block_type,
202 enum amd_powergating_state state);
6cb2d4e4 203void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 204int amdgpu_wait_for_idle(struct amdgpu_device *adev,
205 enum amd_ip_block_type block_type);
206bool amdgpu_is_idle(struct amdgpu_device *adev,
207 enum amd_ip_block_type block_type);
97b2e202 208
a1255107
AD		 209#define AMDGPU_MAX_IP_NUM 16
210
211struct amdgpu_ip_block_status {
212 bool valid;
213 bool sw;
214 bool hw;
215 bool late_initialized;
216 bool hang;
217};
218
97b2e202 219struct amdgpu_ip_block_version {
a1255107
AD		 220 const enum amd_ip_block_type type;
221 const u32 major;
222 const u32 minor;
223 const u32 rev;
5fc3aeeb 224 const struct amd_ip_funcs *funcs;
97b2e202
AD		 225};
226
a1255107
AD		 227struct amdgpu_ip_block {
228 struct amdgpu_ip_block_status status;
229 const struct amdgpu_ip_block_version *version;
230};
231
97b2e202 232int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 233 enum amd_ip_block_type type,
97b2e202
AD		 234 u32 major, u32 minor);
235
a1255107
AD		 236struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
237 enum amd_ip_block_type type);
238
239int amdgpu_ip_block_add(struct amdgpu_device *adev,
240 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 241
242/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
243struct amdgpu_buffer_funcs {
244 /* maximum bytes in a single operation */
245 uint32_t copy_max_bytes;
246
247 /* number of dw to reserve per operation */
248 unsigned copy_num_dw;
249
250 /* used for buffer migration */
c7ae72c0 251 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 252 /* src addr in bytes */
253 uint64_t src_offset,
254 /* dst addr in bytes */
255 uint64_t dst_offset,
256 /* number of byte to transfer */
257 uint32_t byte_count);
258
259 /* maximum bytes in a single operation */
260 uint32_t fill_max_bytes;
261
262 /* number of dw to reserve per operation */
263 unsigned fill_num_dw;
264
265 /* used for buffer clearing */
6e7a3840 266 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 267 /* value to write to memory */
268 uint32_t src_data,
269 /* dst addr in bytes */
270 uint64_t dst_offset,
271 /* number of byte to fill */
272 uint32_t byte_count);
273};
274
275/* provided by hw blocks that can write ptes, e.g., sdma */
276struct amdgpu_vm_pte_funcs {
277 /* copy pte entries from GART */
278 void (*copy_pte)(struct amdgpu_ib *ib,
279 uint64_t pe, uint64_t src,
280 unsigned count);
281 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 282 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
283 uint64_t value, unsigned count,
284 uint32_t incr);
97b2e202
AD		 285 /* for linear pte/pde updates without addr mapping */
286 void (*set_pte_pde)(struct amdgpu_ib *ib,
287 uint64_t pe,
288 uint64_t addr, unsigned count,
6b777607 289 uint32_t incr, uint64_t flags);
97b2e202
AD		 290};
291
292/* provided by the gmc block */
293struct amdgpu_gart_funcs {
294 /* flush the vm tlb via mmio */
295 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
296 uint32_t vmid);
297 /* write pte/pde updates using the cpu */
298 int (*set_pte_pde)(struct amdgpu_device *adev,
299 void *cpu_pt_addr, /* cpu addr of page table */
300 uint32_t gpu_page_idx, /* pte/pde to update */
301 uint64_t addr, /* addr to write into pte/pde */
6b777607 302 uint64_t flags); /* access flags */
284710fa
CK		 303 /* enable/disable PRT support */
304 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 305 /* set pte flags based per asic */
306 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
307 uint32_t flags);
e60f8db5
AX		 308 /* adjust mc addr in fb for APU case */
309 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
03f89feb 310 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 311};
312
97b2e202
AD		 313/* provided by the ih block */
314struct amdgpu_ih_funcs {
315 /* ring read/write ptr handling, called from interrupt context */
316 u32 (*get_wptr)(struct amdgpu_device *adev);
317 void (*decode_iv)(struct amdgpu_device *adev,
318 struct amdgpu_iv_entry *entry);
319 void (*set_rptr)(struct amdgpu_device *adev);
320};
321
97b2e202
AD		 322/*
323 * BIOS.
324 */
325bool amdgpu_get_bios(struct amdgpu_device *adev);
326bool amdgpu_read_bios(struct amdgpu_device *adev);
327
328/*
329 * Dummy page
330 */
331struct amdgpu_dummy_page {
332 struct page *page;
333 dma_addr_t addr;
334};
335int amdgpu_dummy_page_init(struct amdgpu_device *adev);
336void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
337
338
339/*
340 * Clocks
341 */
342
343#define AMDGPU_MAX_PPLL 3
344
345struct amdgpu_clock {
346 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
347 struct amdgpu_pll spll;
348 struct amdgpu_pll mpll;
349 /* 10 Khz units */
350 uint32_t default_mclk;
351 uint32_t default_sclk;
352 uint32_t default_dispclk;
353 uint32_t current_dispclk;
354 uint32_t dp_extclk;
355 uint32_t max_pixel_clock;
356};
357
97b2e202 358/*
c632d799 359 * BO.
97b2e202 360 */
97b2e202
AD		 361struct amdgpu_bo_list_entry {
362 struct amdgpu_bo *robj;
363 struct ttm_validate_buffer tv;
364 struct amdgpu_bo_va *bo_va;
97b2e202 365 uint32_t priority;
2f568dbd
CK		 366 struct page **user_pages;
367 int user_invalidated;
97b2e202
AD		 368};
369
370struct amdgpu_bo_va_mapping {
371 struct list_head list;
a9f87f64
CK		 372 struct rb_node rb;
373 uint64_t start;
374 uint64_t last;
375 uint64_t __subtree_last;
97b2e202 376 uint64_t offset;
268c3001 377 uint64_t flags;
97b2e202
AD		 378};
379
380/* bo virtual addresses in a specific vm */
381struct amdgpu_bo_va {
382 /* protected by bo being reserved */
383 struct list_head bo_list;
f54d1867 384 struct dma_fence *last_pt_update;
97b2e202
AD		 385 unsigned ref_count;
386
7fc11959 387 /* protected by vm mutex and spinlock */
97b2e202
AD		 388 struct list_head vm_status;
389
7fc11959
CK		 390 /* mappings for this bo_va */
391 struct list_head invalids;
392 struct list_head valids;
393
97b2e202
AD		 394 /* constant after initialization */
395 struct amdgpu_vm *vm;
396 struct amdgpu_bo *bo;
397};
398
7e5a547f
CZ		 399#define AMDGPU_GEM_DOMAIN_MAX 0x3
400
97b2e202 401struct amdgpu_bo {
97b2e202 402 /* Protected by tbo.reserved */
1ea863fd
CK		 403 u32 prefered_domains;
404 u32 allowed_domains;
7e5a547f 405 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 406 struct ttm_placement placement;
407 struct ttm_buffer_object tbo;
408 struct ttm_bo_kmap_obj kmap;
409 u64 flags;
410 unsigned pin_count;
411 void *kptr;
412 u64 tiling_flags;
413 u64 metadata_flags;
414 void *metadata;
415 u32 metadata_size;
8e94a46c 416 unsigned prime_shared_count;
97b2e202
AD		 417 /* list of all virtual address to which this bo
418 * is associated to
419 */
420 struct list_head va;
421 /* Constant after initialization */
97b2e202 422 struct drm_gem_object gem_base;
82b9c55b 423 struct amdgpu_bo *parent;
e7893c4b 424 struct amdgpu_bo *shadow;
97b2e202
AD		 425
426 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 427 struct amdgpu_mn *mn;
428 struct list_head mn_list;
0c4e7fa5 429 struct list_head shadow_list;
97b2e202
AD		 430};
431#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
432
433void amdgpu_gem_object_free(struct drm_gem_object *obj);
434int amdgpu_gem_object_open(struct drm_gem_object *obj,
435 struct drm_file *file_priv);
436void amdgpu_gem_object_close(struct drm_gem_object *obj,
437 struct drm_file *file_priv);
438unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
439struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 440struct drm_gem_object *
441amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
442 struct dma_buf_attachment *attach,
443 struct sg_table *sg);
97b2e202
AD		 444struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
445 struct drm_gem_object *gobj,
446 int flags);
447int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
448void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
449struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
450void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
451void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
452int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
453
454/* sub-allocation manager, it has to be protected by another lock.
455 * By conception this is an helper for other part of the driver
456 * like the indirect buffer or semaphore, which both have their
457 * locking.
458 *
459 * Principe is simple, we keep a list of sub allocation in offset
460 * order (first entry has offset == 0, last entry has the highest
461 * offset).
462 *
463 * When allocating new object we first check if there is room at
464 * the end total_size - (last_object_offset + last_object_size) >=
465 * alloc_size. If so we allocate new object there.
466 *
467 * When there is not enough room at the end, we start waiting for
468 * each sub object until we reach object_offset+object_size >=
469 * alloc_size, this object then become the sub object we return.
470 *
471 * Alignment can't be bigger than page size.
472 *
473 * Hole are not considered for allocation to keep things simple.
474 * Assumption is that there won't be hole (all object on same
475 * alignment).
476 */
6ba60b89
CK		 477
478#define AMDGPU_SA_NUM_FENCE_LISTS 32
479
97b2e202
AD		 480struct amdgpu_sa_manager {
481 wait_queue_head_t wq;
482 struct amdgpu_bo *bo;
483 struct list_head *hole;
6ba60b89 484 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 485 struct list_head olist;
486 unsigned size;
487 uint64_t gpu_addr;
488 void *cpu_ptr;
489 uint32_t domain;
490 uint32_t align;
491};
492
97b2e202
AD		 493/* sub-allocation buffer */
494struct amdgpu_sa_bo {
495 struct list_head olist;
496 struct list_head flist;
497 struct amdgpu_sa_manager *manager;
498 unsigned soffset;
499 unsigned eoffset;
f54d1867 500 struct dma_fence *fence;
97b2e202
AD		 501};
502
503/*
504 * GEM objects.
505 */
418aa0c2 506void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 507int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
508 int alignment, u32 initial_domain,
509 u64 flags, bool kernel,
510 struct drm_gem_object **obj);
511
512int amdgpu_mode_dumb_create(struct drm_file *file_priv,
513 struct drm_device *dev,
514 struct drm_mode_create_dumb *args);
515int amdgpu_mode_dumb_mmap(struct drm_file *filp,
516 struct drm_device *dev,
517 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 518int amdgpu_fence_slab_init(void);
519void amdgpu_fence_slab_fini(void);
97b2e202
AD		 520
521/*
522 * GART structures, functions & helpers
523 */
524struct amdgpu_mc;
525
526#define AMDGPU_GPU_PAGE_SIZE 4096
527#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
528#define AMDGPU_GPU_PAGE_SHIFT 12
529#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
530
531struct amdgpu_gart {
532 dma_addr_t table_addr;
533 struct amdgpu_bo *robj;
534 void *ptr;
535 unsigned num_gpu_pages;
536 unsigned num_cpu_pages;
537 unsigned table_size;
a1d29476 538#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 539 struct page **pages;
a1d29476 540#endif
97b2e202 541 bool ready;
4b98e0c4
AX		 542
543 /* Asic default pte flags */
544 uint64_t gart_pte_flags;
545
97b2e202
AD		 546 const struct amdgpu_gart_funcs *gart_funcs;
547};
548
549int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
550void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
551int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
552void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
553int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
554void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
555int amdgpu_gart_init(struct amdgpu_device *adev);
556void amdgpu_gart_fini(struct amdgpu_device *adev);
cab0b8d5 557void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 558 int pages);
cab0b8d5 559int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 560 int pages, struct page **pagelist,
6b777607 561 dma_addr_t *dma_addr, uint64_t flags);
2c0d7318 562int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
97b2e202 563
e60f8db5
AX		 564/*
565 * VMHUB structures, functions & helpers
566 */
567struct amdgpu_vmhub {
568 uint32_t ctx0_ptb_addr_lo32;
569 uint32_t ctx0_ptb_addr_hi32;
570 uint32_t vm_inv_eng0_req;
571 uint32_t vm_inv_eng0_ack;
572 uint32_t vm_context0_cntl;
573 uint32_t vm_l2_pro_fault_status;
574 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 575};
576
97b2e202
AD		 577/*
578 * GPU MC structures, functions & helpers
579 */
580struct amdgpu_mc {
581 resource_size_t aper_size;
582 resource_size_t aper_base;
583 resource_size_t agp_base;
584 /* for some chips with <= 32MB we need to lie
585 * about vram size near mc fb location */
586 u64 mc_vram_size;
587 u64 visible_vram_size;
588 u64 gtt_size;
589 u64 gtt_start;
590 u64 gtt_end;
591 u64 vram_start;
592 u64 vram_end;
593 unsigned vram_width;
594 u64 real_vram_size;
595 int vram_mtrr;
596 u64 gtt_base_align;
597 u64 mc_mask;
598 const struct firmware *fw; /* MC firmware */
599 uint32_t fw_version;
600 struct amdgpu_irq_src vm_fault;
81c59f54 601 uint32_t vram_type;
50b0197a
CZ		 602 uint32_t srbm_soft_reset;
603 struct amdgpu_mode_mc_save save;
f7c35abe 604 bool prt_warning;
8fe73328
JZ		 605 /* apertures */
606 u64 shared_aperture_start;
607 u64 shared_aperture_end;
608 u64 private_aperture_start;
609 u64 private_aperture_end;
e60f8db5
AX		 610 /* protects concurrent invalidation */
611 spinlock_t invalidate_lock;
97b2e202
AD		 612};
613
614/*
615 * GPU doorbell structures, functions & helpers
616 */
617typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
618{
619 AMDGPU_DOORBELL_KIQ = 0x000,
620 AMDGPU_DOORBELL_HIQ = 0x001,
621 AMDGPU_DOORBELL_DIQ = 0x002,
622 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
623 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
624 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
625 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
626 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
627 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
628 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
629 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
630 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
631 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
632 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
633 AMDGPU_DOORBELL_IH = 0x1E8,
634 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
635 AMDGPU_DOORBELL_INVALID = 0xFFFF
636} AMDGPU_DOORBELL_ASSIGNMENT;
637
638struct amdgpu_doorbell {
639 /* doorbell mmio */
640 resource_size_t base;
641 resource_size_t size;
642 u32 __iomem *ptr;
643 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
644};
645
39807b93
KW		 646/*
647 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
648 */
649typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
650{
651 /*
652 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
653 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
654 * Compute related doorbells are allocated from 0x00 to 0x8a
655 */
656
657
658 /* kernel scheduling */
659 AMDGPU_DOORBELL64_KIQ = 0x00,
660
661 /* HSA interface queue and debug queue */
662 AMDGPU_DOORBELL64_HIQ = 0x01,
663 AMDGPU_DOORBELL64_DIQ = 0x02,
664
665 /* Compute engines */
666 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
667 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
668 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
669 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
670 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
671 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
672 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
673 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
674
675 /* User queue doorbell range (128 doorbells) */
676 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
677 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
678
679 /* Graphics engine */
680 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
681
682 /*
683 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
684 * Graphics voltage island aperture 1
685 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
686 */
687
688 /* sDMA engines */
689 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
690 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
691 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
692 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
693
694 /* Interrupt handler */
695 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
696 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
697 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
698
e6b3ecb4
ML		 699 /* VCN engine use 32 bits doorbell */
700 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
701 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
702 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
703 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
704
705 /* overlap the doorbell assignment with VCN as they are mutually exclusive
706 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
707 */
708 AMDGPU_DOORBELL64_RING0_1 = 0xF8,
709 AMDGPU_DOORBELL64_RING2_3 = 0xF9,
710 AMDGPU_DOORBELL64_RING4_5 = 0xFA,
711 AMDGPU_DOORBELL64_RING6_7 = 0xFB,
712
713 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
714 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
715 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
716 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
39807b93
KW		 717
718 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
719 AMDGPU_DOORBELL64_INVALID = 0xFFFF
720} AMDGPU_DOORBELL64_ASSIGNMENT;
721
722
97b2e202
AD		 723void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
724 phys_addr_t *aperture_base,
725 size_t *aperture_size,
726 size_t *start_offset);
727
728/*
729 * IRQS.
730 */
731
732struct amdgpu_flip_work {
325cbba1 733 struct delayed_work flip_work;
97b2e202
AD		 734 struct work_struct unpin_work;
735 struct amdgpu_device *adev;
736 int crtc_id;
325cbba1 737 u32 target_vblank;
97b2e202
AD		 738 uint64_t base;
739 struct drm_pending_vblank_event *event;
765e7fbf 740 struct amdgpu_bo *old_abo;
f54d1867 741 struct dma_fence *excl;
1ffd2652 742 unsigned shared_count;
f54d1867
CW		 743 struct dma_fence **shared;
744 struct dma_fence_cb cb;
cb9e59d7 745 bool async;
97b2e202
AD		 746};
747
748
749/*
750 * CP & rings.
751 */
752
753struct amdgpu_ib {
754 struct amdgpu_sa_bo *sa_bo;
755 uint32_t length_dw;
756 uint64_t gpu_addr;
757 uint32_t *ptr;
de807f81 758 uint32_t flags;
97b2e202
AD		 759};
760
62250a91 761extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 762
50838c8c 763int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 764 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 765int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
766 struct amdgpu_job **job);
b6723c8d 767
a5fb4ec2 768void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 769void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 770int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 771 struct amd_sched_entity *entity, void *owner,
f54d1867 772 struct dma_fence **f);
8b4fb00b 773
97b2e202
AD		 774/*
775 * context related structures
776 */
777
21c16bf6 778struct amdgpu_ctx_ring {
91404fb2 779 uint64_t sequence;
f54d1867 780 struct dma_fence **fences;
91404fb2 781 struct amd_sched_entity entity;
21c16bf6
CK		 782};
783
97b2e202 784struct amdgpu_ctx {
0b492a4c 785 struct kref refcount;
9cb7e5a9 786 struct amdgpu_device *adev;
0b492a4c 787 unsigned reset_counter;
21c16bf6 788 spinlock_t ring_lock;
f54d1867 789 struct dma_fence **fences;
21c16bf6 790 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 791 bool preamble_presented;
97b2e202
AD		 792};
793
794struct amdgpu_ctx_mgr {
0b492a4c
AD		 795 struct amdgpu_device *adev;
796 struct mutex lock;
797 /* protected by lock */
798 struct idr ctx_handles;
97b2e202
AD		 799};
800
0b492a4c
AD		 801struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
802int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
803
21c16bf6 804uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
f54d1867
CW		 805 struct dma_fence *fence);
806struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6
CK		 807 struct amdgpu_ring *ring, uint64_t seq);
808
0b492a4c
AD		 809int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
810 struct drm_file *filp);
811
efd4ccb5
CK		 812void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
813void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 814
97b2e202
AD		 815/*
816 * file private structure
817 */
818
819struct amdgpu_fpriv {
820 struct amdgpu_vm vm;
b85891bd 821 struct amdgpu_bo_va *prt_va;
97b2e202
AD		 822 struct mutex bo_list_lock;
823 struct idr bo_list_handles;
0b492a4c 824 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 825};
826
827/*
828 * residency list
829 */
830
831struct amdgpu_bo_list {
832 struct mutex lock;
833 struct amdgpu_bo *gds_obj;
834 struct amdgpu_bo *gws_obj;
835 struct amdgpu_bo *oa_obj;
211dff55 836 unsigned first_userptr;
97b2e202
AD		 837 unsigned num_entries;
838 struct amdgpu_bo_list_entry *array;
839};
840
841struct amdgpu_bo_list *
842amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 843void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
844 struct list_head *validated);
97b2e202
AD		 845void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
846void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
847
848/*
849 * GFX stuff
850 */
851#include "clearstate_defs.h"
852
79e5412c
AD		 853struct amdgpu_rlc_funcs {
854 void (*enter_safe_mode)(struct amdgpu_device *adev);
855 void (*exit_safe_mode)(struct amdgpu_device *adev);
856};
857
97b2e202
AD		 858struct amdgpu_rlc {
859 /* for power gating */
860 struct amdgpu_bo *save_restore_obj;
861 uint64_t save_restore_gpu_addr;
862 volatile uint32_t *sr_ptr;
863 const u32 *reg_list;
864 u32 reg_list_size;
865 /* for clear state */
866 struct amdgpu_bo *clear_state_obj;
867 uint64_t clear_state_gpu_addr;
868 volatile uint32_t *cs_ptr;
869 const struct cs_section_def *cs_data;
870 u32 clear_state_size;
871 /* for cp tables */
872 struct amdgpu_bo *cp_table_obj;
873 uint64_t cp_table_gpu_addr;
874 volatile uint32_t *cp_table_ptr;
875 u32 cp_table_size;
79e5412c
AD		 876
877 /* safe mode for updating CG/PG state */
878 bool in_safe_mode;
879 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 880
881 /* for firmware data */
882 u32 save_and_restore_offset;
883 u32 clear_state_descriptor_offset;
884 u32 avail_scratch_ram_locations;
885 u32 reg_restore_list_size;
886 u32 reg_list_format_start;
887 u32 reg_list_format_separate_start;
888 u32 starting_offsets_start;
889 u32 reg_list_format_size_bytes;
890 u32 reg_list_size_bytes;
891
892 u32 *register_list_format;
893 u32 *register_restore;
97b2e202
AD		 894};
895
896struct amdgpu_mec {
897 struct amdgpu_bo *hpd_eop_obj;
898 u64 hpd_eop_gpu_addr;
b1023571
KW		 899 struct amdgpu_bo *mec_fw_obj;
900 u64 mec_fw_gpu_addr;
97b2e202
AD		 901 u32 num_pipe;
902 u32 num_mec;
903 u32 num_queue;
59a82d7d 904 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
97b2e202
AD		 905};
906
4e638ae9
XY		 907struct amdgpu_kiq {
908 u64 eop_gpu_addr;
909 struct amdgpu_bo *eop_obj;
cdf6adb2 910 struct mutex ring_mutex;
4e638ae9
XY		 911 struct amdgpu_ring ring;
912 struct amdgpu_irq_src irq;
913};
914
97b2e202
AD		 915/*
916 * GPU scratch registers structures, functions & helpers
917 */
918struct amdgpu_scratch {
919 unsigned num_reg;
920 uint32_t reg_base;
50261151 921 uint32_t free_mask;
97b2e202
AD		 922};
923
924/*
925 * GFX configurations
926 */
e3fa7630
AD		 927#define AMDGPU_GFX_MAX_SE 4
928#define AMDGPU_GFX_MAX_SH_PER_SE 2
929
930struct amdgpu_rb_config {
931 uint32_t rb_backend_disable;
932 uint32_t user_rb_backend_disable;
933 uint32_t raster_config;
934 uint32_t raster_config_1;
935};
936
d0e95758
AG		 937struct gb_addr_config {
938 uint16_t pipe_interleave_size;
939 uint8_t num_pipes;
940 uint8_t max_compress_frags;
941 uint8_t num_banks;
942 uint8_t num_se;
943 uint8_t num_rb_per_se;
944};
945
ea323f88 946struct amdgpu_gfx_config {
97b2e202
AD		 947 unsigned max_shader_engines;
948 unsigned max_tile_pipes;
949 unsigned max_cu_per_sh;
950 unsigned max_sh_per_se;
951 unsigned max_backends_per_se;
952 unsigned max_texture_channel_caches;
953 unsigned max_gprs;
954 unsigned max_gs_threads;
955 unsigned max_hw_contexts;
956 unsigned sc_prim_fifo_size_frontend;
957 unsigned sc_prim_fifo_size_backend;
958 unsigned sc_hiz_tile_fifo_size;
959 unsigned sc_earlyz_tile_fifo_size;
960
961 unsigned num_tile_pipes;
962 unsigned backend_enable_mask;
963 unsigned mem_max_burst_length_bytes;
964 unsigned mem_row_size_in_kb;
965 unsigned shader_engine_tile_size;
966 unsigned num_gpus;
967 unsigned multi_gpu_tile_size;
968 unsigned mc_arb_ramcfg;
969 unsigned gb_addr_config;
8f8e00c1 970 unsigned num_rbs;
408bfe7c
JZ		 971 unsigned gs_vgt_table_depth;
972 unsigned gs_prim_buffer_depth;
97b2e202
AD		 973
974 uint32_t tile_mode_array[32];
975 uint32_t macrotile_mode_array[16];
e3fa7630 976
d0e95758 977 struct gb_addr_config gb_addr_config_fields;
e3fa7630 978 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 979
980 /* gfx configure feature */
981 uint32_t double_offchip_lds_buf;
97b2e202
AD		 982};
983
7dae69a2
AD		 984struct amdgpu_cu_info {
985 uint32_t number; /* total active CU number */
986 uint32_t ao_cu_mask;
408bfe7c 987 uint32_t wave_front_size;
7dae69a2
AD		 988 uint32_t bitmap[4][4];
989};
990
b95e31fd
AD		 991struct amdgpu_gfx_funcs {
992 /* get the gpu clock counter */
993 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 994 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 995 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 996 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
997 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 998};
999
bce23e00
AD		 1000struct amdgpu_ngg_buf {
1001 struct amdgpu_bo *bo;
1002 uint64_t gpu_addr;
1003 uint32_t size;
1004 uint32_t bo_size;
1005};
1006
1007enum {
af8baf15
GR		 1008 NGG_PRIM = 0,
1009 NGG_POS,
1010 NGG_CNTL,
1011 NGG_PARAM,
bce23e00
AD		 1012 NGG_BUF_MAX
1013};
1014
1015struct amdgpu_ngg {
1016 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1017 uint32_t gds_reserve_addr;
1018 uint32_t gds_reserve_size;
1019 bool init;
1020};
1021
97b2e202
AD		 1022struct amdgpu_gfx {
1023 struct mutex gpu_clock_mutex;
ea323f88 1024 struct amdgpu_gfx_config config;
97b2e202
AD		 1025 struct amdgpu_rlc rlc;
1026 struct amdgpu_mec mec;
4e638ae9 1027 struct amdgpu_kiq kiq;
97b2e202
AD		 1028 struct amdgpu_scratch scratch;
1029 const struct firmware *me_fw; /* ME firmware */
1030 uint32_t me_fw_version;
1031 const struct firmware *pfp_fw; /* PFP firmware */
1032 uint32_t pfp_fw_version;
1033 const struct firmware *ce_fw; /* CE firmware */
1034 uint32_t ce_fw_version;
1035 const struct firmware *rlc_fw; /* RLC firmware */
1036 uint32_t rlc_fw_version;
1037 const struct firmware *mec_fw; /* MEC firmware */
1038 uint32_t mec_fw_version;
1039 const struct firmware *mec2_fw; /* MEC2 firmware */
1040 uint32_t mec2_fw_version;
02558a00
KW		 1041 uint32_t me_feature_version;
1042 uint32_t ce_feature_version;
1043 uint32_t pfp_feature_version;
351643d7
JZ		 1044 uint32_t rlc_feature_version;
1045 uint32_t mec_feature_version;
1046 uint32_t mec2_feature_version;
97b2e202
AD		 1047 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1048 unsigned num_gfx_rings;
1049 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1050 unsigned num_compute_rings;
1051 struct amdgpu_irq_src eop_irq;
1052 struct amdgpu_irq_src priv_reg_irq;
1053 struct amdgpu_irq_src priv_inst_irq;
1054 /* gfx status */
7dae69a2 1055 uint32_t gfx_current_status;
a101a899 1056 /* ce ram size*/
7dae69a2
AD		 1057 unsigned ce_ram_size;
1058 struct amdgpu_cu_info cu_info;
b95e31fd 1059 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1060
1061 /* reset mask */
1062 uint32_t grbm_soft_reset;
1063 uint32_t srbm_soft_reset;
223049cd 1064 bool in_reset;
b4e40676
DP		 1065 /* s3/s4 mask */
1066 bool in_suspend;
bce23e00
AD		 1067 /* NGG */
1068 struct amdgpu_ngg ngg;
97b2e202
AD		 1069};
1070
b07c60c0 1071int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1072 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1073void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1074 struct dma_fence *f);
b07c60c0 1075int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1076 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1077 struct dma_fence **f);
97b2e202
AD		 1078int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1079void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1080int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1081
1082/*
1083 * CS.
1084 */
1085struct amdgpu_cs_chunk {
1086 uint32_t chunk_id;
1087 uint32_t length_dw;
758ac17f 1088 void *kdata;
97b2e202
AD		 1089};
1090
1091struct amdgpu_cs_parser {
1092 struct amdgpu_device *adev;
1093 struct drm_file *filp;
3cb485f3 1094 struct amdgpu_ctx *ctx;
c3cca41e 1095
97b2e202
AD		 1096 /* chunks */
1097 unsigned nchunks;
1098 struct amdgpu_cs_chunk *chunks;
97b2e202 1099
50838c8c
CK		 1100 /* scheduler job object */
1101 struct amdgpu_job *job;
97b2e202 1102
c3cca41e
CK		 1103 /* buffer objects */
1104 struct ww_acquire_ctx ticket;
1105 struct amdgpu_bo_list *bo_list;
1106 struct amdgpu_bo_list_entry vm_pd;
1107 struct list_head validated;
f54d1867 1108 struct dma_fence *fence;
c3cca41e
CK		 1109 uint64_t bytes_moved_threshold;
1110 uint64_t bytes_moved;
662bfa61 1111 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1112
1113 /* user fence */
91acbeb6 1114 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1115};
1116
753ad49c
ML		 1117#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1118#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1119#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
7e6bf80f 1120#define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */
753ad49c 1121
bb977d37
CZ		 1122struct amdgpu_job {
1123 struct amd_sched_job base;
1124 struct amdgpu_device *adev;
edf600da 1125 struct amdgpu_vm *vm;
b07c60c0 1126 struct amdgpu_ring *ring;
e86f9cee 1127 struct amdgpu_sync sync;
bb977d37 1128 struct amdgpu_ib *ibs;
f54d1867 1129 struct dma_fence *fence; /* the hw fence */
753ad49c 1130 uint32_t preamble_status;
bb977d37 1131 uint32_t num_ibs;
e2840221 1132 void *owner;
3aecd24c 1133 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1134 bool vm_needs_flush;
30514dec 1135 bool need_pipeline_sync;
d88bf583
CK		 1136 unsigned vm_id;
1137 uint64_t vm_pd_addr;
1138 uint32_t gds_base, gds_size;
1139 uint32_t gws_base, gws_size;
1140 uint32_t oa_base, oa_size;
758ac17f
CK		 1141
1142 /* user fence handling */
b5f5acbc 1143 uint64_t uf_addr;
758ac17f
CK		 1144 uint64_t uf_sequence;
1145
bb977d37 1146};
a6db8a33
JZ		 1147#define to_amdgpu_job(sched_job) \
1148 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1149
7270f839
CK		 1150static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1151 uint32_t ib_idx, int idx)
97b2e202 1152{
50838c8c 1153 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1154}
1155
7270f839
CK		 1156static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1157 uint32_t ib_idx, int idx,
1158 uint32_t value)
1159{
50838c8c 1160 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1161}
1162
97b2e202
AD		 1163/*
1164 * Writeback
1165 */
1166#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1167
1168struct amdgpu_wb {
1169 struct amdgpu_bo *wb_obj;
1170 volatile uint32_t *wb;
1171 uint64_t gpu_addr;
1172 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1173 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1174};
1175
1176int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1177void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
7014285a
KW		 1178int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1179void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
97b2e202 1180
d0dd7f0c
AD		 1181void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1182
97b2e202
AD		 1183/*
1184 * SDMA
1185 */
c113ea1c 1186struct amdgpu_sdma_instance {
97b2e202
AD		 1187 /* SDMA firmware */
1188 const struct firmware *fw;
1189 uint32_t fw_version;
cfa2104f 1190 uint32_t feature_version;
97b2e202
AD		 1191
1192 struct amdgpu_ring ring;
18111de0 1193 bool burst_nop;
97b2e202
AD		 1194};
1195
c113ea1c
AD		 1196struct amdgpu_sdma {
1197 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1198#ifdef CONFIG_DRM_AMDGPU_SI
1199 //SI DMA has a difference trap irq number for the second engine
1200 struct amdgpu_irq_src trap_irq_1;
1201#endif
c113ea1c
AD		 1202 struct amdgpu_irq_src trap_irq;
1203 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1204 int num_instances;
e702a680 1205 uint32_t srbm_soft_reset;
c113ea1c
AD		 1206};
1207
97b2e202
AD		 1208/*
1209 * Firmware
1210 */
e635ee07
HR		 1211enum amdgpu_firmware_load_type {
1212 AMDGPU_FW_LOAD_DIRECT = 0,
1213 AMDGPU_FW_LOAD_SMU,
1214 AMDGPU_FW_LOAD_PSP,
1215};
1216
97b2e202
AD		 1217struct amdgpu_firmware {
1218 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1219 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1220 struct amdgpu_bo *fw_buf;
1221 unsigned int fw_size;
2445b227 1222 unsigned int max_ucodes;
0e5ca0d1
HR		 1223 /* firmwares are loaded by psp instead of smu from vega10 */
1224 const struct amdgpu_psp_funcs *funcs;
1225 struct amdgpu_bo *rbuf;
1226 struct mutex mutex;
97b2e202
AD		 1227};
1228
1229/*
1230 * Benchmarking
1231 */
1232void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1233
1234
1235/*
1236 * Testing
1237 */
1238void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202
AD		 1239
1240/*
1241 * MMU Notifier
1242 */
1243#if defined(CONFIG_MMU_NOTIFIER)
1244int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1245void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1246#else
1d1106b0 1247static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1248{
1249 return -ENODEV;
1250}
1d1106b0 1251static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1252#endif
1253
1254/*
1255 * Debugfs
1256 */
1257struct amdgpu_debugfs {
06ab6832 1258 const struct drm_info_list *files;
97b2e202
AD		 1259 unsigned num_files;
1260};
1261
1262int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1263 const struct drm_info_list *files,
97b2e202
AD		 1264 unsigned nfiles);
1265int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1266
1267#if defined(CONFIG_DEBUG_FS)
1268int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1269#endif
1270
50ab2533
HR		 1271int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1272
97b2e202
AD		 1273/*
1274 * amdgpu smumgr functions
1275 */
1276struct amdgpu_smumgr_funcs {
1277 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1278 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1279 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1280};
1281
1282/*
1283 * amdgpu smumgr
1284 */
1285struct amdgpu_smumgr {
1286 struct amdgpu_bo *toc_buf;
1287 struct amdgpu_bo *smu_buf;
1288 /* asic priv smu data */
1289 void *priv;
1290 spinlock_t smu_lock;
1291 /* smumgr functions */
1292 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1293 /* ucode loading complete flag */
1294 uint32_t fw_flags;
1295};
1296
1297/*
1298 * ASIC specific register table accessible by UMD
1299 */
1300struct amdgpu_allowed_register_entry {
1301 uint32_t reg_offset;
97b2e202
AD		 1302 bool grbm_indexed;
1303};
1304
97b2e202
AD		 1305/*
1306 * ASIC specific functions.
1307 */
1308struct amdgpu_asic_funcs {
1309 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1310 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1311 u8 *bios, u32 length_bytes);
97b2e202
AD		 1312 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1313 u32 sh_num, u32 reg_offset, u32 *value);
1314 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1315 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1316 /* get the reference clock */
1317 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1318 /* MM block clocks */
1319 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1320 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1321 /* static power management */
1322 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1323 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1324 /* get config memsize register */
1325 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1326};
1327
1328/*
1329 * IOCTL.
1330 */
1331int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1332 struct drm_file *filp);
1333int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
1335
1336int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1337 struct drm_file *filp);
1338int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *filp);
1340int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1341 struct drm_file *filp);
1342int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *filp);
1344int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *filp);
1346int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1347 struct drm_file *filp);
1348int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1349int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1350int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1351 struct drm_file *filp);
97b2e202
AD		 1352
1353int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1354 struct drm_file *filp);
1355
1356/* VRAM scratch page for HDP bug, default vram page */
1357struct amdgpu_vram_scratch {
1358 struct amdgpu_bo *robj;
1359 volatile uint32_t *ptr;
1360 u64 gpu_addr;
1361};
1362
1363/*
1364 * ACPI
1365 */
1366struct amdgpu_atif_notification_cfg {
1367 bool enabled;
1368 int command_code;
1369};
1370
1371struct amdgpu_atif_notifications {
1372 bool display_switch;
1373 bool expansion_mode_change;
1374 bool thermal_state;
1375 bool forced_power_state;
1376 bool system_power_state;
1377 bool display_conf_change;
1378 bool px_gfx_switch;
1379 bool brightness_change;
1380 bool dgpu_display_event;
1381};
1382
1383struct amdgpu_atif_functions {
1384 bool system_params;
1385 bool sbios_requests;
1386 bool select_active_disp;
1387 bool lid_state;
1388 bool get_tv_standard;
1389 bool set_tv_standard;
1390 bool get_panel_expansion_mode;
1391 bool set_panel_expansion_mode;
1392 bool temperature_change;
1393 bool graphics_device_types;
1394};
1395
1396struct amdgpu_atif {
1397 struct amdgpu_atif_notifications notifications;
1398 struct amdgpu_atif_functions functions;
1399 struct amdgpu_atif_notification_cfg notification_cfg;
1400 struct amdgpu_encoder *encoder_for_bl;
1401};
1402
1403struct amdgpu_atcs_functions {
1404 bool get_ext_state;
1405 bool pcie_perf_req;
1406 bool pcie_dev_rdy;
1407 bool pcie_bus_width;
1408};
1409
1410struct amdgpu_atcs {
1411 struct amdgpu_atcs_functions functions;
1412};
1413
d03846af
CZ		 1414/*
1415 * CGS
1416 */
110e6f26
DA		 1417struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1418void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1419
97b2e202
AD		 1420/*
1421 * Core structure, functions and helpers.
1422 */
1423typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1424typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1425
1426typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1427typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1428
1429struct amdgpu_device {
1430 struct device *dev;
1431 struct drm_device *ddev;
1432 struct pci_dev *pdev;
97b2e202 1433
a8fe58ce
MB		 1434#ifdef CONFIG_DRM_AMD_ACP
1435 struct amdgpu_acp acp;
1436#endif
1437
97b2e202 1438 /* ASIC */
2f7d10b3 1439 enum amd_asic_type asic_type;
97b2e202
AD		 1440 uint32_t family;
1441 uint32_t rev_id;
1442 uint32_t external_rev_id;
1443 unsigned long flags;
1444 int usec_timeout;
1445 const struct amdgpu_asic_funcs *asic_funcs;
1446 bool shutdown;
97b2e202
AD		 1447 bool need_dma32;
1448 bool accel_working;
edf600da 1449 struct work_struct reset_work;
97b2e202
AD		 1450 struct notifier_block acpi_nb;
1451 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1452 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1453 unsigned debugfs_count;
97b2e202 1454#if defined(CONFIG_DEBUG_FS)
adcec288 1455 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1456#endif
1457 struct amdgpu_atif atif;
1458 struct amdgpu_atcs atcs;
1459 struct mutex srbm_mutex;
1460 /* GRBM index mutex. Protects concurrent access to GRBM index */
1461 struct mutex grbm_idx_mutex;
1462 struct dev_pm_domain vga_pm_domain;
1463 bool have_disp_power_ref;
1464
1465 /* BIOS */
0cdd5005 1466 bool is_atom_fw;
97b2e202 1467 uint8_t *bios;
a9f5db9c 1468 uint32_t bios_size;
97b2e202 1469 struct amdgpu_bo *stollen_vga_memory;
a5bde2f9 1470 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1471 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1472
1473 /* Register/doorbell mmio */
1474 resource_size_t rmmio_base;
1475 resource_size_t rmmio_size;
1476 void __iomem *rmmio;
1477 /* protects concurrent MM_INDEX/DATA based register access */
1478 spinlock_t mmio_idx_lock;
1479 /* protects concurrent SMC based register access */
1480 spinlock_t smc_idx_lock;
1481 amdgpu_rreg_t smc_rreg;
1482 amdgpu_wreg_t smc_wreg;
1483 /* protects concurrent PCIE register access */
1484 spinlock_t pcie_idx_lock;
1485 amdgpu_rreg_t pcie_rreg;
1486 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1487 amdgpu_rreg_t pciep_rreg;
1488 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1489 /* protects concurrent UVD register access */
1490 spinlock_t uvd_ctx_idx_lock;
1491 amdgpu_rreg_t uvd_ctx_rreg;
1492 amdgpu_wreg_t uvd_ctx_wreg;
1493 /* protects concurrent DIDT register access */
1494 spinlock_t didt_idx_lock;
1495 amdgpu_rreg_t didt_rreg;
1496 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1497 /* protects concurrent gc_cac register access */
1498 spinlock_t gc_cac_idx_lock;
1499 amdgpu_rreg_t gc_cac_rreg;
1500 amdgpu_wreg_t gc_cac_wreg;
97b2e202
AD		 1501 /* protects concurrent ENDPOINT (audio) register access */
1502 spinlock_t audio_endpt_idx_lock;
1503 amdgpu_block_rreg_t audio_endpt_rreg;
1504 amdgpu_block_wreg_t audio_endpt_wreg;
1505 void __iomem *rio_mem;
1506 resource_size_t rio_mem_size;
1507 struct amdgpu_doorbell doorbell;
1508
1509 /* clock/pll info */
1510 struct amdgpu_clock clock;
1511
1512 /* MC */
1513 struct amdgpu_mc mc;
1514 struct amdgpu_gart gart;
1515 struct amdgpu_dummy_page dummy_page;
1516 struct amdgpu_vm_manager vm_manager;
e60f8db5 1517 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1518
1519 /* memory management */
1520 struct amdgpu_mman mman;
97b2e202
AD		 1521 struct amdgpu_vram_scratch vram_scratch;
1522 struct amdgpu_wb wb;
1523 atomic64_t vram_usage;
1524 atomic64_t vram_vis_usage;
1525 atomic64_t gtt_usage;
1526 atomic64_t num_bytes_moved;
dbd5ed60 1527 atomic64_t num_evictions;
d94aed5a 1528 atomic_t gpu_reset_counter;
97b2e202 1529
95844d20
MO		 1530 /* data for buffer migration throttling */
1531 struct {
1532 spinlock_t lock;
1533 s64 last_update_us;
1534 s64 accum_us; /* accumulated microseconds */
1535 u32 log2_max_MBps;
1536 } mm_stats;
1537
97b2e202 1538 /* display */
9accf2fd 1539 bool enable_virtual_display;
97b2e202
AD		 1540 struct amdgpu_mode_info mode_info;
1541 struct work_struct hotplug_work;
1542 struct amdgpu_irq_src crtc_irq;
1543 struct amdgpu_irq_src pageflip_irq;
1544 struct amdgpu_irq_src hpd_irq;
1545
1546 /* rings */
76bf0db5 1547 u64 fence_context;
97b2e202
AD		 1548 unsigned num_rings;
1549 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1550 bool ib_pool_ready;
1551 struct amdgpu_sa_manager ring_tmp_bo;
1552
1553 /* interrupts */
1554 struct amdgpu_irq irq;
1555
1f7371b2
AD		 1556 /* powerplay */
1557 struct amd_powerplay powerplay;
e61710c5 1558 bool pp_enabled;
f3898ea1 1559 bool pp_force_state_enabled;
1f7371b2 1560
97b2e202
AD		 1561 /* dpm */
1562 struct amdgpu_pm pm;
1563 u32 cg_flags;
1564 u32 pg_flags;
1565
1566 /* amdgpu smumgr */
1567 struct amdgpu_smumgr smu;
1568
1569 /* gfx */
1570 struct amdgpu_gfx gfx;
1571
1572 /* sdma */
c113ea1c 1573 struct amdgpu_sdma sdma;
97b2e202
AD		 1574
1575 /* uvd */
97b2e202
AD		 1576 struct amdgpu_uvd uvd;
1577
1578 /* vce */
1579 struct amdgpu_vce vce;
1580
1581 /* firmwares */
1582 struct amdgpu_firmware firmware;
1583
0e5ca0d1
HR		 1584 /* PSP */
1585 struct psp_context psp;
1586
97b2e202
AD		 1587 /* GDS */
1588 struct amdgpu_gds gds;
1589
a1255107 1590 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1591 int num_ip_blocks;
97b2e202
AD		 1592 struct mutex mn_lock;
1593 DECLARE_HASHTABLE(mn_hash, 7);
1594
1595 /* tracking pinned memory */
1596 u64 vram_pin_size;
e131b914 1597 u64 invisible_pin_size;
97b2e202 1598 u64 gart_pin_size;
130e0371
OG		 1599
1600 /* amdkfd interface */
1601 struct kfd_dev *kfd;
23ca0e4e 1602
5a5099cb 1603 struct amdgpu_virt virt;
0c4e7fa5
CZ		 1604
1605 /* link all shadow bo */
1606 struct list_head shadow_list;
1607 struct mutex shadow_list_lock;
5c1354bd
CZ		 1608 /* link all gtt */
1609 spinlock_t gtt_list_lock;
1610 struct list_head gtt_list;
1611
c836fec5
JQ		 1612 /* record hw reset is performed */
1613 bool has_hw_reset;
1614
97b2e202
AD		 1615};
1616
a7d64de6
CK		 1617static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1618{
1619 return container_of(bdev, struct amdgpu_device, mman.bdev);
1620}
1621
97b2e202
AD		 1622bool amdgpu_device_is_px(struct drm_device *dev);
1623int amdgpu_device_init(struct amdgpu_device *adev,
1624 struct drm_device *ddev,
1625 struct pci_dev *pdev,
1626 uint32_t flags);
1627void amdgpu_device_fini(struct amdgpu_device *adev);
1628int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1629
1630uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1631 uint32_t acc_flags);
97b2e202 1632void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1633 uint32_t acc_flags);
97b2e202
AD		 1634u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1635void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1636
1637u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1638void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1639u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1640void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1641
97b2e202
AD		 1642/*
1643 * Registers read & write functions.
1644 */
15d72fd7
ML		 1645
1646#define AMDGPU_REGS_IDX (1<<0)
1647#define AMDGPU_REGS_NO_KIQ (1<<1)
1648
1649#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1650#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1651
1652#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1653#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1654#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1655#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1656#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1657#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1658#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1659#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1660#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1661#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1662#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1663#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1664#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1665#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1666#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1667#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1668#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1669#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1670#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1671#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1672#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1673#define WREG32_P(reg, val, mask) \
1674 do { \
1675 uint32_t tmp_ = RREG32(reg); \
1676 tmp_ &= (mask); \
1677 tmp_ |= ((val) & ~(mask)); \
1678 WREG32(reg, tmp_); \
1679 } while (0)
1680#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1681#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1682#define WREG32_PLL_P(reg, val, mask) \
1683 do { \
1684 uint32_t tmp_ = RREG32_PLL(reg); \
1685 tmp_ &= (mask); \
1686 tmp_ |= ((val) & ~(mask)); \
1687 WREG32_PLL(reg, tmp_); \
1688 } while (0)
1689#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1690#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1691#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1692
1693#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1694#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1695#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1696#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1697
1698#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1699#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1700
1701#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1702 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1703 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1704
1705#define REG_GET_FIELD(value, reg, field) \
1706 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1707
1708#define WREG32_FIELD(reg, field, val) \
1709 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1710
ccaf3574
TSD		 1711#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1712 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1713
97b2e202
AD		 1714/*
1715 * BIOS helpers.
1716 */
1717#define RBIOS8(i) (adev->bios[i])
1718#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1719#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1720
1721/*
1722 * RING helpers.
1723 */
1724static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1725{
1726 if (ring->count_dw <= 0)
86c2b790 1727 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
536fbf94 1728 ring->ring[ring->wptr++ & ring->buf_mask] = v;
97b2e202
AD		 1729 ring->wptr &= ring->ptr_mask;
1730 ring->count_dw--;
97b2e202
AD		 1731}
1732
0a8e1473
ML		 1733static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1734{
1735 unsigned occupied, chunk1, chunk2;
1736 void *dst;
1737
1738 if (ring->count_dw < count_dw) {
1739 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1740 } else {
5846e355 1741 occupied = ring->wptr & ring->buf_mask;
0a8e1473 1742 dst = (void *)&ring->ring[occupied];
5846e355 1743 chunk1 = ring->buf_mask + 1 - occupied;
0a8e1473
ML		 1744 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1745 chunk2 = count_dw - chunk1;
1746 chunk1 <<= 2;
1747 chunk2 <<= 2;
1748
1749 if (chunk1)
1750 memcpy(dst, src, chunk1);
1751
1752 if (chunk2) {
1753 src += chunk1;
1754 dst = (void *)ring->ring;
1755 memcpy(dst, src, chunk2);
1756 }
1757
1758 ring->wptr += count_dw;
1759 ring->wptr &= ring->ptr_mask;
1760 ring->count_dw -= count_dw;
1761 }
1762}
1763
c113ea1c
AD		 1764static inline struct amdgpu_sdma_instance *
1765amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1766{
1767 struct amdgpu_device *adev = ring->adev;
1768 int i;
1769
c113ea1c
AD		 1770 for (i = 0; i < adev->sdma.num_instances; i++)
1771 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1772 break;
1773
1774 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1775 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1776 else
1777 return NULL;
1778}
1779
97b2e202
AD		 1780/*
1781 * ASICs macro.
1782 */
1783#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1784#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1785#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1786#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1787#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1788#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1789#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1790#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1791#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1792#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1793#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1794#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1795#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1796#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1797#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1798#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1799#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1800#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1801#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1802#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1803#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1804#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1805#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1806#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1807#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1808#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1809#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1810#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1811#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1812#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1813#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1814#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1815#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1816#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1817#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
9e5d5309 1818#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1819#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1820#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 1821#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1822#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1823#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1824#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1825#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1826#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1827#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1828#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1829#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1830#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1831#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1832#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1833#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1834#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1835#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1836#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1837#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1838#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 1839#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1840#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1841#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1842#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1843#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1844#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1845
1846/* Common functions */
1847int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1848bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1849void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1850bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1851void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1852
97b2e202
AD		 1853int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1854int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1855 u32 ip_instance, u32 ring,
1856 struct amdgpu_ring **out_ring);
fad06127 1857void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
765e7fbf 1858void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1859bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 1860int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 1861int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1862 uint32_t flags);
1863bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 1864struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 1865bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1866 unsigned long end);
2f568dbd
CK		 1867bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1868 int *last_invalidated);
97b2e202 1869bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
6b777607 1870uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
97b2e202
AD		 1871 struct ttm_mem_reg *mem);
1872void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1873void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1874void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1875int amdgpu_ttm_init(struct amdgpu_device *adev);
1876void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1877void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1878 const u32 *registers,
1879 const u32 array_size);
1880
1881bool amdgpu_device_is_px(struct drm_device *dev);
1882/* atpx handler */
1883#if defined(CONFIG_VGA_SWITCHEROO)
1884void amdgpu_register_atpx_handler(void);
1885void amdgpu_unregister_atpx_handler(void);
a78fe133 1886bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1887bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1888bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1889bool amdgpu_has_atpx(void);
97b2e202
AD		 1890#else
1891static inline void amdgpu_register_atpx_handler(void) {}
1892static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1893static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1894static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1895static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1896static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1897#endif
1898
1899/*
1900 * KMS
1901 */
1902extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1903extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1904
1905int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1906void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1907void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1908int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1909void amdgpu_driver_postclose_kms(struct drm_device *dev,
1910 struct drm_file *file_priv);
faefba95 1911int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1912int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1913int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1914u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1915int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1916void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1917long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1918 unsigned long arg);
1919
97b2e202
AD		 1920/*
1921 * functions used by amdgpu_encoder.c
1922 */
1923struct amdgpu_afmt_acr {
1924 u32 clock;
1925
1926 int n_32khz;
1927 int cts_32khz;
1928
1929 int n_44_1khz;
1930 int cts_44_1khz;
1931
1932 int n_48khz;
1933 int cts_48khz;
1934
1935};
1936
1937struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1938
1939/* amdgpu_acpi.c */
1940#if defined(CONFIG_ACPI)
1941int amdgpu_acpi_init(struct amdgpu_device *adev);
1942void amdgpu_acpi_fini(struct amdgpu_device *adev);
1943bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1944int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1945 u8 perf_req, bool advertise);
1946int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1947#else
1948static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1949static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1950#endif
1951
1952struct amdgpu_bo_va_mapping *
1953amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1954 uint64_t addr, struct amdgpu_bo **bo);
c855e250 1955int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
97b2e202
AD		 1956
1957#include "amdgpu_object.h"
97b2e202 1958#endif
Linux 6.x block layer and io_uring tree(s)