Commit | Line | Data |
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97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
31 | #include <linux/atomic.h> | |
32 | #include <linux/wait.h> | |
33 | #include <linux/list.h> | |
34 | #include <linux/kref.h> | |
35 | #include <linux/interval_tree.h> | |
36 | #include <linux/hashtable.h> | |
37 | #include <linux/fence.h> | |
38 | ||
39 | #include <ttm/ttm_bo_api.h> | |
40 | #include <ttm/ttm_bo_driver.h> | |
41 | #include <ttm/ttm_placement.h> | |
42 | #include <ttm/ttm_module.h> | |
43 | #include <ttm/ttm_execbuf_util.h> | |
44 | ||
d03846af | 45 | #include <drm/drmP.h> |
97b2e202 | 46 | #include <drm/drm_gem.h> |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
97b2e202 | 48 | |
5fc3aeeb | 49 | #include "amd_shared.h" |
97b2e202 AD |
50 | #include "amdgpu_mode.h" |
51 | #include "amdgpu_ih.h" | |
52 | #include "amdgpu_irq.h" | |
53 | #include "amdgpu_ucode.h" | |
54 | #include "amdgpu_gds.h" | |
55 | ||
b80d8475 AD |
56 | #include "gpu_scheduler.h" |
57 | ||
97b2e202 AD |
58 | /* |
59 | * Modules parameters. | |
60 | */ | |
61 | extern int amdgpu_modeset; | |
62 | extern int amdgpu_vram_limit; | |
63 | extern int amdgpu_gart_size; | |
64 | extern int amdgpu_benchmarking; | |
65 | extern int amdgpu_testing; | |
66 | extern int amdgpu_audio; | |
67 | extern int amdgpu_disp_priority; | |
68 | extern int amdgpu_hw_i2c; | |
69 | extern int amdgpu_pcie_gen2; | |
70 | extern int amdgpu_msi; | |
71 | extern int amdgpu_lockup_timeout; | |
72 | extern int amdgpu_dpm; | |
73 | extern int amdgpu_smc_load_fw; | |
74 | extern int amdgpu_aspm; | |
75 | extern int amdgpu_runtime_pm; | |
76 | extern int amdgpu_hard_reset; | |
77 | extern unsigned amdgpu_ip_block_mask; | |
78 | extern int amdgpu_bapm; | |
79 | extern int amdgpu_deep_color; | |
80 | extern int amdgpu_vm_size; | |
81 | extern int amdgpu_vm_block_size; | |
d9c13156 | 82 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 83 | extern int amdgpu_vm_debug; |
b80d8475 | 84 | extern int amdgpu_enable_scheduler; |
1333f723 | 85 | extern int amdgpu_sched_jobs; |
4afcb303 | 86 | extern int amdgpu_sched_hw_submission; |
3daea9e3 | 87 | extern int amdgpu_enable_semaphores; |
97b2e202 | 88 | |
4b559c90 | 89 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 AD |
90 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
91 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
92 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ | |
93 | #define AMDGPU_IB_POOL_SIZE 16 | |
94 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
95 | #define AMDGPUFB_CONN_LIMIT 4 | |
96 | #define AMDGPU_BIOS_NUM_SCRATCH 8 | |
97 | ||
97b2e202 AD |
98 | /* max number of rings */ |
99 | #define AMDGPU_MAX_RINGS 16 | |
100 | #define AMDGPU_MAX_GFX_RINGS 1 | |
101 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | |
102 | #define AMDGPU_MAX_VCE_RINGS 2 | |
103 | ||
36f523a7 JZ |
104 | /* max number of IP instances */ |
105 | #define AMDGPU_MAX_SDMA_INSTANCES 2 | |
106 | ||
97b2e202 AD |
107 | /* number of hw syncs before falling back on blocking */ |
108 | #define AMDGPU_NUM_SYNCS 4 | |
109 | ||
110 | /* hardcode that limit for now */ | |
111 | #define AMDGPU_VA_RESERVED_SIZE (8 << 20) | |
112 | ||
113 | /* hard reset data */ | |
114 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
115 | ||
116 | /* reset flags */ | |
117 | #define AMDGPU_RESET_GFX (1 << 0) | |
118 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
119 | #define AMDGPU_RESET_DMA (1 << 2) | |
120 | #define AMDGPU_RESET_CP (1 << 3) | |
121 | #define AMDGPU_RESET_GRBM (1 << 4) | |
122 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
123 | #define AMDGPU_RESET_RLC (1 << 6) | |
124 | #define AMDGPU_RESET_SEM (1 << 7) | |
125 | #define AMDGPU_RESET_IH (1 << 8) | |
126 | #define AMDGPU_RESET_VMC (1 << 9) | |
127 | #define AMDGPU_RESET_MC (1 << 10) | |
128 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
129 | #define AMDGPU_RESET_UVD (1 << 12) | |
130 | #define AMDGPU_RESET_VCE (1 << 13) | |
131 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
132 | ||
133 | /* CG block flags */ | |
134 | #define AMDGPU_CG_BLOCK_GFX (1 << 0) | |
135 | #define AMDGPU_CG_BLOCK_MC (1 << 1) | |
136 | #define AMDGPU_CG_BLOCK_SDMA (1 << 2) | |
137 | #define AMDGPU_CG_BLOCK_UVD (1 << 3) | |
138 | #define AMDGPU_CG_BLOCK_VCE (1 << 4) | |
139 | #define AMDGPU_CG_BLOCK_HDP (1 << 5) | |
140 | #define AMDGPU_CG_BLOCK_BIF (1 << 6) | |
141 | ||
142 | /* CG flags */ | |
143 | #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) | |
144 | #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) | |
145 | #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) | |
146 | #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) | |
147 | #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) | |
148 | #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
149 | #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
150 | #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
151 | #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) | |
152 | #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) | |
153 | #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) | |
154 | #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
155 | #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) | |
156 | #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) | |
157 | #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) | |
158 | #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) | |
159 | #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) | |
160 | ||
161 | /* PG flags */ | |
162 | #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) | |
163 | #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) | |
164 | #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) | |
165 | #define AMDGPU_PG_SUPPORT_UVD (1 << 3) | |
166 | #define AMDGPU_PG_SUPPORT_VCE (1 << 4) | |
167 | #define AMDGPU_PG_SUPPORT_CP (1 << 5) | |
168 | #define AMDGPU_PG_SUPPORT_GDS (1 << 6) | |
169 | #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
170 | #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) | |
171 | #define AMDGPU_PG_SUPPORT_ACP (1 << 9) | |
172 | #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) | |
173 | ||
174 | /* GFX current status */ | |
175 | #define AMDGPU_GFX_NORMAL_MODE 0x00000000L | |
176 | #define AMDGPU_GFX_SAFE_MODE 0x00000001L | |
177 | #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L | |
178 | #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L | |
179 | #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L | |
180 | ||
181 | /* max cursor sizes (in pixels) */ | |
182 | #define CIK_CURSOR_WIDTH 128 | |
183 | #define CIK_CURSOR_HEIGHT 128 | |
184 | ||
185 | struct amdgpu_device; | |
186 | struct amdgpu_fence; | |
187 | struct amdgpu_ib; | |
188 | struct amdgpu_vm; | |
189 | struct amdgpu_ring; | |
190 | struct amdgpu_semaphore; | |
191 | struct amdgpu_cs_parser; | |
bb977d37 | 192 | struct amdgpu_job; |
97b2e202 | 193 | struct amdgpu_irq_src; |
0b492a4c | 194 | struct amdgpu_fpriv; |
97b2e202 AD |
195 | |
196 | enum amdgpu_cp_irq { | |
197 | AMDGPU_CP_IRQ_GFX_EOP = 0, | |
198 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, | |
199 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
200 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
201 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
202 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
203 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
204 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
205 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
206 | ||
207 | AMDGPU_CP_IRQ_LAST | |
208 | }; | |
209 | ||
210 | enum amdgpu_sdma_irq { | |
211 | AMDGPU_SDMA_IRQ_TRAP0 = 0, | |
212 | AMDGPU_SDMA_IRQ_TRAP1, | |
213 | ||
214 | AMDGPU_SDMA_IRQ_LAST | |
215 | }; | |
216 | ||
217 | enum amdgpu_thermal_irq { | |
218 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
219 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
220 | ||
221 | AMDGPU_THERMAL_IRQ_LAST | |
222 | }; | |
223 | ||
97b2e202 | 224 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, |
5fc3aeeb | 225 | enum amd_ip_block_type block_type, |
226 | enum amd_clockgating_state state); | |
97b2e202 | 227 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, |
5fc3aeeb | 228 | enum amd_ip_block_type block_type, |
229 | enum amd_powergating_state state); | |
97b2e202 AD |
230 | |
231 | struct amdgpu_ip_block_version { | |
5fc3aeeb | 232 | enum amd_ip_block_type type; |
97b2e202 AD |
233 | u32 major; |
234 | u32 minor; | |
235 | u32 rev; | |
5fc3aeeb | 236 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
237 | }; |
238 | ||
239 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 240 | enum amd_ip_block_type type, |
97b2e202 AD |
241 | u32 major, u32 minor); |
242 | ||
243 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( | |
244 | struct amdgpu_device *adev, | |
5fc3aeeb | 245 | enum amd_ip_block_type type); |
97b2e202 AD |
246 | |
247 | /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ | |
248 | struct amdgpu_buffer_funcs { | |
249 | /* maximum bytes in a single operation */ | |
250 | uint32_t copy_max_bytes; | |
251 | ||
252 | /* number of dw to reserve per operation */ | |
253 | unsigned copy_num_dw; | |
254 | ||
255 | /* used for buffer migration */ | |
c7ae72c0 | 256 | void (*emit_copy_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
257 | /* src addr in bytes */ |
258 | uint64_t src_offset, | |
259 | /* dst addr in bytes */ | |
260 | uint64_t dst_offset, | |
261 | /* number of byte to transfer */ | |
262 | uint32_t byte_count); | |
263 | ||
264 | /* maximum bytes in a single operation */ | |
265 | uint32_t fill_max_bytes; | |
266 | ||
267 | /* number of dw to reserve per operation */ | |
268 | unsigned fill_num_dw; | |
269 | ||
270 | /* used for buffer clearing */ | |
6e7a3840 | 271 | void (*emit_fill_buffer)(struct amdgpu_ib *ib, |
97b2e202 AD |
272 | /* value to write to memory */ |
273 | uint32_t src_data, | |
274 | /* dst addr in bytes */ | |
275 | uint64_t dst_offset, | |
276 | /* number of byte to fill */ | |
277 | uint32_t byte_count); | |
278 | }; | |
279 | ||
280 | /* provided by hw blocks that can write ptes, e.g., sdma */ | |
281 | struct amdgpu_vm_pte_funcs { | |
282 | /* copy pte entries from GART */ | |
283 | void (*copy_pte)(struct amdgpu_ib *ib, | |
284 | uint64_t pe, uint64_t src, | |
285 | unsigned count); | |
286 | /* write pte one entry at a time with addr mapping */ | |
287 | void (*write_pte)(struct amdgpu_ib *ib, | |
288 | uint64_t pe, | |
289 | uint64_t addr, unsigned count, | |
290 | uint32_t incr, uint32_t flags); | |
291 | /* for linear pte/pde updates without addr mapping */ | |
292 | void (*set_pte_pde)(struct amdgpu_ib *ib, | |
293 | uint64_t pe, | |
294 | uint64_t addr, unsigned count, | |
295 | uint32_t incr, uint32_t flags); | |
296 | /* pad the indirect buffer to the necessary number of dw */ | |
297 | void (*pad_ib)(struct amdgpu_ib *ib); | |
298 | }; | |
299 | ||
300 | /* provided by the gmc block */ | |
301 | struct amdgpu_gart_funcs { | |
302 | /* flush the vm tlb via mmio */ | |
303 | void (*flush_gpu_tlb)(struct amdgpu_device *adev, | |
304 | uint32_t vmid); | |
305 | /* write pte/pde updates using the cpu */ | |
306 | int (*set_pte_pde)(struct amdgpu_device *adev, | |
307 | void *cpu_pt_addr, /* cpu addr of page table */ | |
308 | uint32_t gpu_page_idx, /* pte/pde to update */ | |
309 | uint64_t addr, /* addr to write into pte/pde */ | |
310 | uint32_t flags); /* access flags */ | |
311 | }; | |
312 | ||
313 | /* provided by the ih block */ | |
314 | struct amdgpu_ih_funcs { | |
315 | /* ring read/write ptr handling, called from interrupt context */ | |
316 | u32 (*get_wptr)(struct amdgpu_device *adev); | |
317 | void (*decode_iv)(struct amdgpu_device *adev, | |
318 | struct amdgpu_iv_entry *entry); | |
319 | void (*set_rptr)(struct amdgpu_device *adev); | |
320 | }; | |
321 | ||
322 | /* provided by hw blocks that expose a ring buffer for commands */ | |
323 | struct amdgpu_ring_funcs { | |
324 | /* ring read/write ptr handling */ | |
325 | u32 (*get_rptr)(struct amdgpu_ring *ring); | |
326 | u32 (*get_wptr)(struct amdgpu_ring *ring); | |
327 | void (*set_wptr)(struct amdgpu_ring *ring); | |
328 | /* validating and patching of IBs */ | |
329 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | |
330 | /* command emit functions */ | |
331 | void (*emit_ib)(struct amdgpu_ring *ring, | |
332 | struct amdgpu_ib *ib); | |
333 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | |
890ee23f | 334 | uint64_t seq, unsigned flags); |
97b2e202 AD |
335 | bool (*emit_semaphore)(struct amdgpu_ring *ring, |
336 | struct amdgpu_semaphore *semaphore, | |
337 | bool emit_wait); | |
338 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, | |
339 | uint64_t pd_addr); | |
d2edb07b | 340 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
97b2e202 AD |
341 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
342 | uint32_t gds_base, uint32_t gds_size, | |
343 | uint32_t gws_base, uint32_t gws_size, | |
344 | uint32_t oa_base, uint32_t oa_size); | |
345 | /* testing functions */ | |
346 | int (*test_ring)(struct amdgpu_ring *ring); | |
347 | int (*test_ib)(struct amdgpu_ring *ring); | |
edff0e28 JZ |
348 | /* insert NOP packets */ |
349 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
97b2e202 AD |
350 | }; |
351 | ||
352 | /* | |
353 | * BIOS. | |
354 | */ | |
355 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
356 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
357 | ||
358 | /* | |
359 | * Dummy page | |
360 | */ | |
361 | struct amdgpu_dummy_page { | |
362 | struct page *page; | |
363 | dma_addr_t addr; | |
364 | }; | |
365 | int amdgpu_dummy_page_init(struct amdgpu_device *adev); | |
366 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev); | |
367 | ||
368 | ||
369 | /* | |
370 | * Clocks | |
371 | */ | |
372 | ||
373 | #define AMDGPU_MAX_PPLL 3 | |
374 | ||
375 | struct amdgpu_clock { | |
376 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
377 | struct amdgpu_pll spll; | |
378 | struct amdgpu_pll mpll; | |
379 | /* 10 Khz units */ | |
380 | uint32_t default_mclk; | |
381 | uint32_t default_sclk; | |
382 | uint32_t default_dispclk; | |
383 | uint32_t current_dispclk; | |
384 | uint32_t dp_extclk; | |
385 | uint32_t max_pixel_clock; | |
386 | }; | |
387 | ||
388 | /* | |
389 | * Fences. | |
390 | */ | |
391 | struct amdgpu_fence_driver { | |
97b2e202 AD |
392 | uint64_t gpu_addr; |
393 | volatile uint32_t *cpu_addr; | |
394 | /* sync_seq is protected by ring emission lock */ | |
395 | uint64_t sync_seq[AMDGPU_MAX_RINGS]; | |
396 | atomic64_t last_seq; | |
397 | bool initialized; | |
97b2e202 AD |
398 | struct amdgpu_irq_src *irq_src; |
399 | unsigned irq_type; | |
c2776afe | 400 | struct timer_list fallback_timer; |
7f06c236 | 401 | wait_queue_head_t fence_queue; |
97b2e202 AD |
402 | }; |
403 | ||
404 | /* some special values for the owner field */ | |
405 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | |
406 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | |
97b2e202 | 407 | |
890ee23f CZ |
408 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) |
409 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
410 | ||
97b2e202 AD |
411 | struct amdgpu_fence { |
412 | struct fence base; | |
4cef9267 | 413 | |
97b2e202 AD |
414 | /* RB, DMA, etc. */ |
415 | struct amdgpu_ring *ring; | |
416 | uint64_t seq; | |
417 | ||
418 | /* filp or special value for fence creator */ | |
419 | void *owner; | |
420 | ||
421 | wait_queue_t fence_wake; | |
422 | }; | |
423 | ||
424 | struct amdgpu_user_fence { | |
425 | /* write-back bo */ | |
426 | struct amdgpu_bo *bo; | |
427 | /* write-back address offset to bo start */ | |
428 | uint32_t offset; | |
429 | }; | |
430 | ||
431 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | |
432 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | |
433 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); | |
434 | ||
4f839a24 | 435 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); |
97b2e202 AD |
436 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, |
437 | struct amdgpu_irq_src *irq_src, | |
438 | unsigned irq_type); | |
5ceb54c6 AD |
439 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); |
440 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | |
97b2e202 AD |
441 | int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, |
442 | struct amdgpu_fence **fence); | |
443 | void amdgpu_fence_process(struct amdgpu_ring *ring); | |
444 | int amdgpu_fence_wait_next(struct amdgpu_ring *ring); | |
445 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | |
446 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | |
447 | ||
97b2e202 AD |
448 | bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, |
449 | struct amdgpu_ring *ring); | |
450 | void amdgpu_fence_note_sync(struct amdgpu_fence *fence, | |
451 | struct amdgpu_ring *ring); | |
452 | ||
97b2e202 AD |
453 | /* |
454 | * TTM. | |
455 | */ | |
456 | struct amdgpu_mman { | |
457 | struct ttm_bo_global_ref bo_global_ref; | |
458 | struct drm_global_reference mem_global_ref; | |
459 | struct ttm_bo_device bdev; | |
460 | bool mem_global_referenced; | |
461 | bool initialized; | |
462 | ||
463 | #if defined(CONFIG_DEBUG_FS) | |
464 | struct dentry *vram; | |
465 | struct dentry *gtt; | |
466 | #endif | |
467 | ||
468 | /* buffer handling */ | |
469 | const struct amdgpu_buffer_funcs *buffer_funcs; | |
470 | struct amdgpu_ring *buffer_funcs_ring; | |
471 | }; | |
472 | ||
473 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, | |
474 | uint64_t src_offset, | |
475 | uint64_t dst_offset, | |
476 | uint32_t byte_count, | |
477 | struct reservation_object *resv, | |
c7ae72c0 | 478 | struct fence **fence); |
97b2e202 AD |
479 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); |
480 | ||
481 | struct amdgpu_bo_list_entry { | |
482 | struct amdgpu_bo *robj; | |
483 | struct ttm_validate_buffer tv; | |
484 | struct amdgpu_bo_va *bo_va; | |
485 | unsigned prefered_domains; | |
486 | unsigned allowed_domains; | |
487 | uint32_t priority; | |
488 | }; | |
489 | ||
490 | struct amdgpu_bo_va_mapping { | |
491 | struct list_head list; | |
492 | struct interval_tree_node it; | |
493 | uint64_t offset; | |
494 | uint32_t flags; | |
495 | }; | |
496 | ||
497 | /* bo virtual addresses in a specific vm */ | |
498 | struct amdgpu_bo_va { | |
69b576a1 | 499 | struct mutex mutex; |
97b2e202 AD |
500 | /* protected by bo being reserved */ |
501 | struct list_head bo_list; | |
bb1e38a4 | 502 | struct fence *last_pt_update; |
97b2e202 AD |
503 | unsigned ref_count; |
504 | ||
7fc11959 | 505 | /* protected by vm mutex and spinlock */ |
97b2e202 AD |
506 | struct list_head vm_status; |
507 | ||
7fc11959 CK |
508 | /* mappings for this bo_va */ |
509 | struct list_head invalids; | |
510 | struct list_head valids; | |
511 | ||
97b2e202 AD |
512 | /* constant after initialization */ |
513 | struct amdgpu_vm *vm; | |
514 | struct amdgpu_bo *bo; | |
515 | }; | |
516 | ||
7e5a547f CZ |
517 | #define AMDGPU_GEM_DOMAIN_MAX 0x3 |
518 | ||
97b2e202 AD |
519 | struct amdgpu_bo { |
520 | /* Protected by gem.mutex */ | |
521 | struct list_head list; | |
522 | /* Protected by tbo.reserved */ | |
523 | u32 initial_domain; | |
7e5a547f | 524 | struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; |
97b2e202 AD |
525 | struct ttm_placement placement; |
526 | struct ttm_buffer_object tbo; | |
527 | struct ttm_bo_kmap_obj kmap; | |
528 | u64 flags; | |
529 | unsigned pin_count; | |
530 | void *kptr; | |
531 | u64 tiling_flags; | |
532 | u64 metadata_flags; | |
533 | void *metadata; | |
534 | u32 metadata_size; | |
535 | /* list of all virtual address to which this bo | |
536 | * is associated to | |
537 | */ | |
538 | struct list_head va; | |
539 | /* Constant after initialization */ | |
540 | struct amdgpu_device *adev; | |
541 | struct drm_gem_object gem_base; | |
542 | ||
543 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
544 | pid_t pid; | |
545 | struct amdgpu_mn *mn; | |
546 | struct list_head mn_list; | |
547 | }; | |
548 | #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) | |
549 | ||
550 | void amdgpu_gem_object_free(struct drm_gem_object *obj); | |
551 | int amdgpu_gem_object_open(struct drm_gem_object *obj, | |
552 | struct drm_file *file_priv); | |
553 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
554 | struct drm_file *file_priv); | |
555 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); | |
556 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); | |
557 | struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
558 | struct dma_buf_attachment *attach, | |
559 | struct sg_table *sg); | |
560 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, | |
561 | struct drm_gem_object *gobj, | |
562 | int flags); | |
563 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj); | |
564 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); | |
565 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); | |
566 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); | |
567 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); | |
568 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); | |
569 | ||
570 | /* sub-allocation manager, it has to be protected by another lock. | |
571 | * By conception this is an helper for other part of the driver | |
572 | * like the indirect buffer or semaphore, which both have their | |
573 | * locking. | |
574 | * | |
575 | * Principe is simple, we keep a list of sub allocation in offset | |
576 | * order (first entry has offset == 0, last entry has the highest | |
577 | * offset). | |
578 | * | |
579 | * When allocating new object we first check if there is room at | |
580 | * the end total_size - (last_object_offset + last_object_size) >= | |
581 | * alloc_size. If so we allocate new object there. | |
582 | * | |
583 | * When there is not enough room at the end, we start waiting for | |
584 | * each sub object until we reach object_offset+object_size >= | |
585 | * alloc_size, this object then become the sub object we return. | |
586 | * | |
587 | * Alignment can't be bigger than page size. | |
588 | * | |
589 | * Hole are not considered for allocation to keep things simple. | |
590 | * Assumption is that there won't be hole (all object on same | |
591 | * alignment). | |
592 | */ | |
593 | struct amdgpu_sa_manager { | |
594 | wait_queue_head_t wq; | |
595 | struct amdgpu_bo *bo; | |
596 | struct list_head *hole; | |
597 | struct list_head flist[AMDGPU_MAX_RINGS]; | |
598 | struct list_head olist; | |
599 | unsigned size; | |
600 | uint64_t gpu_addr; | |
601 | void *cpu_ptr; | |
602 | uint32_t domain; | |
603 | uint32_t align; | |
604 | }; | |
605 | ||
606 | struct amdgpu_sa_bo; | |
607 | ||
608 | /* sub-allocation buffer */ | |
609 | struct amdgpu_sa_bo { | |
610 | struct list_head olist; | |
611 | struct list_head flist; | |
612 | struct amdgpu_sa_manager *manager; | |
613 | unsigned soffset; | |
614 | unsigned eoffset; | |
4ce9891e | 615 | struct fence *fence; |
97b2e202 AD |
616 | }; |
617 | ||
618 | /* | |
619 | * GEM objects. | |
620 | */ | |
621 | struct amdgpu_gem { | |
622 | struct mutex mutex; | |
623 | struct list_head objects; | |
624 | }; | |
625 | ||
626 | int amdgpu_gem_init(struct amdgpu_device *adev); | |
627 | void amdgpu_gem_fini(struct amdgpu_device *adev); | |
628 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
629 | int alignment, u32 initial_domain, | |
630 | u64 flags, bool kernel, | |
631 | struct drm_gem_object **obj); | |
632 | ||
633 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
634 | struct drm_device *dev, | |
635 | struct drm_mode_create_dumb *args); | |
636 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
637 | struct drm_device *dev, | |
638 | uint32_t handle, uint64_t *offset_p); | |
639 | ||
640 | /* | |
641 | * Semaphores. | |
642 | */ | |
643 | struct amdgpu_semaphore { | |
644 | struct amdgpu_sa_bo *sa_bo; | |
645 | signed waiters; | |
646 | uint64_t gpu_addr; | |
647 | }; | |
648 | ||
649 | int amdgpu_semaphore_create(struct amdgpu_device *adev, | |
650 | struct amdgpu_semaphore **semaphore); | |
651 | bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, | |
652 | struct amdgpu_semaphore *semaphore); | |
653 | bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | |
654 | struct amdgpu_semaphore *semaphore); | |
655 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | |
656 | struct amdgpu_semaphore **semaphore, | |
4ce9891e | 657 | struct fence *fence); |
97b2e202 AD |
658 | |
659 | /* | |
660 | * Synchronization | |
661 | */ | |
662 | struct amdgpu_sync { | |
663 | struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; | |
16545c32 | 664 | struct fence *sync_to[AMDGPU_MAX_RINGS]; |
f91b3a69 | 665 | DECLARE_HASHTABLE(fences, 4); |
3c62338c | 666 | struct fence *last_vm_update; |
97b2e202 AD |
667 | }; |
668 | ||
669 | void amdgpu_sync_create(struct amdgpu_sync *sync); | |
91e1a520 CK |
670 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
671 | struct fence *f); | |
97b2e202 AD |
672 | int amdgpu_sync_resv(struct amdgpu_device *adev, |
673 | struct amdgpu_sync *sync, | |
674 | struct reservation_object *resv, | |
675 | void *owner); | |
676 | int amdgpu_sync_rings(struct amdgpu_sync *sync, | |
677 | struct amdgpu_ring *ring); | |
e61235db | 678 | struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); |
f91b3a69 | 679 | int amdgpu_sync_wait(struct amdgpu_sync *sync); |
97b2e202 | 680 | void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
4ce9891e | 681 | struct fence *fence); |
97b2e202 AD |
682 | |
683 | /* | |
684 | * GART structures, functions & helpers | |
685 | */ | |
686 | struct amdgpu_mc; | |
687 | ||
688 | #define AMDGPU_GPU_PAGE_SIZE 4096 | |
689 | #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) | |
690 | #define AMDGPU_GPU_PAGE_SHIFT 12 | |
691 | #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) | |
692 | ||
693 | struct amdgpu_gart { | |
694 | dma_addr_t table_addr; | |
695 | struct amdgpu_bo *robj; | |
696 | void *ptr; | |
697 | unsigned num_gpu_pages; | |
698 | unsigned num_cpu_pages; | |
699 | unsigned table_size; | |
700 | struct page **pages; | |
701 | dma_addr_t *pages_addr; | |
702 | bool ready; | |
703 | const struct amdgpu_gart_funcs *gart_funcs; | |
704 | }; | |
705 | ||
706 | int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); | |
707 | void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); | |
708 | int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); | |
709 | void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); | |
710 | int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); | |
711 | void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); | |
712 | int amdgpu_gart_init(struct amdgpu_device *adev); | |
713 | void amdgpu_gart_fini(struct amdgpu_device *adev); | |
714 | void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, | |
715 | int pages); | |
716 | int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, | |
717 | int pages, struct page **pagelist, | |
718 | dma_addr_t *dma_addr, uint32_t flags); | |
719 | ||
720 | /* | |
721 | * GPU MC structures, functions & helpers | |
722 | */ | |
723 | struct amdgpu_mc { | |
724 | resource_size_t aper_size; | |
725 | resource_size_t aper_base; | |
726 | resource_size_t agp_base; | |
727 | /* for some chips with <= 32MB we need to lie | |
728 | * about vram size near mc fb location */ | |
729 | u64 mc_vram_size; | |
730 | u64 visible_vram_size; | |
731 | u64 gtt_size; | |
732 | u64 gtt_start; | |
733 | u64 gtt_end; | |
734 | u64 vram_start; | |
735 | u64 vram_end; | |
736 | unsigned vram_width; | |
737 | u64 real_vram_size; | |
738 | int vram_mtrr; | |
739 | u64 gtt_base_align; | |
740 | u64 mc_mask; | |
741 | const struct firmware *fw; /* MC firmware */ | |
742 | uint32_t fw_version; | |
743 | struct amdgpu_irq_src vm_fault; | |
81c59f54 | 744 | uint32_t vram_type; |
97b2e202 AD |
745 | }; |
746 | ||
747 | /* | |
748 | * GPU doorbell structures, functions & helpers | |
749 | */ | |
750 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
751 | { | |
752 | AMDGPU_DOORBELL_KIQ = 0x000, | |
753 | AMDGPU_DOORBELL_HIQ = 0x001, | |
754 | AMDGPU_DOORBELL_DIQ = 0x002, | |
755 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
756 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
757 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
758 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
759 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
760 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
761 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
762 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
763 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
764 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
765 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
766 | AMDGPU_DOORBELL_IH = 0x1E8, | |
767 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
768 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
769 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
770 | ||
771 | struct amdgpu_doorbell { | |
772 | /* doorbell mmio */ | |
773 | resource_size_t base; | |
774 | resource_size_t size; | |
775 | u32 __iomem *ptr; | |
776 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
777 | }; | |
778 | ||
779 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
780 | phys_addr_t *aperture_base, | |
781 | size_t *aperture_size, | |
782 | size_t *start_offset); | |
783 | ||
784 | /* | |
785 | * IRQS. | |
786 | */ | |
787 | ||
788 | struct amdgpu_flip_work { | |
789 | struct work_struct flip_work; | |
790 | struct work_struct unpin_work; | |
791 | struct amdgpu_device *adev; | |
792 | int crtc_id; | |
793 | uint64_t base; | |
794 | struct drm_pending_vblank_event *event; | |
795 | struct amdgpu_bo *old_rbo; | |
1ffd2652 CK |
796 | struct fence *excl; |
797 | unsigned shared_count; | |
798 | struct fence **shared; | |
97b2e202 AD |
799 | }; |
800 | ||
801 | ||
802 | /* | |
803 | * CP & rings. | |
804 | */ | |
805 | ||
806 | struct amdgpu_ib { | |
807 | struct amdgpu_sa_bo *sa_bo; | |
808 | uint32_t length_dw; | |
809 | uint64_t gpu_addr; | |
810 | uint32_t *ptr; | |
811 | struct amdgpu_ring *ring; | |
812 | struct amdgpu_fence *fence; | |
813 | struct amdgpu_user_fence *user; | |
814 | struct amdgpu_vm *vm; | |
3cb485f3 | 815 | struct amdgpu_ctx *ctx; |
97b2e202 | 816 | struct amdgpu_sync sync; |
97b2e202 AD |
817 | uint32_t gds_base, gds_size; |
818 | uint32_t gws_base, gws_size; | |
819 | uint32_t oa_base, oa_size; | |
de807f81 | 820 | uint32_t flags; |
5430a3ff CK |
821 | /* resulting sequence number */ |
822 | uint64_t sequence; | |
97b2e202 AD |
823 | }; |
824 | ||
825 | enum amdgpu_ring_type { | |
826 | AMDGPU_RING_TYPE_GFX, | |
827 | AMDGPU_RING_TYPE_COMPUTE, | |
828 | AMDGPU_RING_TYPE_SDMA, | |
829 | AMDGPU_RING_TYPE_UVD, | |
830 | AMDGPU_RING_TYPE_VCE | |
831 | }; | |
832 | ||
c1b69ed0 CZ |
833 | extern struct amd_sched_backend_ops amdgpu_sched_ops; |
834 | ||
3c704e93 CZ |
835 | int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, |
836 | struct amdgpu_ring *ring, | |
837 | struct amdgpu_ib *ibs, | |
838 | unsigned num_ibs, | |
bb977d37 | 839 | int (*free_job)(struct amdgpu_job *), |
1763552e CZ |
840 | void *owner, |
841 | struct fence **fence); | |
3c704e93 | 842 | |
97b2e202 AD |
843 | struct amdgpu_ring { |
844 | struct amdgpu_device *adev; | |
845 | const struct amdgpu_ring_funcs *funcs; | |
846 | struct amdgpu_fence_driver fence_drv; | |
4f839a24 | 847 | struct amd_gpu_scheduler sched; |
97b2e202 | 848 | |
176e1ab1 | 849 | spinlock_t fence_lock; |
97b2e202 AD |
850 | struct mutex *ring_lock; |
851 | struct amdgpu_bo *ring_obj; | |
852 | volatile uint32_t *ring; | |
853 | unsigned rptr_offs; | |
854 | u64 next_rptr_gpu_addr; | |
855 | volatile u32 *next_rptr_cpu_addr; | |
856 | unsigned wptr; | |
857 | unsigned wptr_old; | |
858 | unsigned ring_size; | |
859 | unsigned ring_free_dw; | |
860 | int count_dw; | |
97b2e202 AD |
861 | uint64_t gpu_addr; |
862 | uint32_t align_mask; | |
863 | uint32_t ptr_mask; | |
864 | bool ready; | |
865 | u32 nop; | |
866 | u32 idx; | |
867 | u64 last_semaphore_signal_addr; | |
868 | u64 last_semaphore_wait_addr; | |
869 | u32 me; | |
870 | u32 pipe; | |
871 | u32 queue; | |
872 | struct amdgpu_bo *mqd_obj; | |
873 | u32 doorbell_index; | |
874 | bool use_doorbell; | |
875 | unsigned wptr_offs; | |
876 | unsigned next_rptr_offs; | |
877 | unsigned fence_offs; | |
3cb485f3 | 878 | struct amdgpu_ctx *current_ctx; |
97b2e202 AD |
879 | enum amdgpu_ring_type type; |
880 | char name[16]; | |
4274f5d4 | 881 | bool is_pte_ring; |
97b2e202 AD |
882 | }; |
883 | ||
884 | /* | |
885 | * VM | |
886 | */ | |
887 | ||
888 | /* maximum number of VMIDs */ | |
889 | #define AMDGPU_NUM_VM 16 | |
890 | ||
891 | /* number of entries in page table */ | |
892 | #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) | |
893 | ||
894 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ | |
895 | #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 | |
896 | #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) | |
897 | #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) | |
898 | ||
899 | #define AMDGPU_PTE_VALID (1 << 0) | |
900 | #define AMDGPU_PTE_SYSTEM (1 << 1) | |
901 | #define AMDGPU_PTE_SNOOPED (1 << 2) | |
902 | ||
903 | /* VI only */ | |
904 | #define AMDGPU_PTE_EXECUTABLE (1 << 4) | |
905 | ||
906 | #define AMDGPU_PTE_READABLE (1 << 5) | |
907 | #define AMDGPU_PTE_WRITEABLE (1 << 6) | |
908 | ||
909 | /* PTE (Page Table Entry) fragment field for different page sizes */ | |
910 | #define AMDGPU_PTE_FRAG_4KB (0 << 7) | |
911 | #define AMDGPU_PTE_FRAG_64KB (4 << 7) | |
912 | #define AMDGPU_LOG2_PAGES_PER_FRAG 4 | |
913 | ||
d9c13156 CK |
914 | /* How to programm VM fault handling */ |
915 | #define AMDGPU_VM_FAULT_STOP_NEVER 0 | |
916 | #define AMDGPU_VM_FAULT_STOP_FIRST 1 | |
917 | #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 | |
918 | ||
97b2e202 | 919 | struct amdgpu_vm_pt { |
8b4fb00b CK |
920 | struct amdgpu_bo *bo; |
921 | uint64_t addr; | |
97b2e202 AD |
922 | }; |
923 | ||
924 | struct amdgpu_vm_id { | |
925 | unsigned id; | |
926 | uint64_t pd_gpu_addr; | |
927 | /* last flushed PD/PT update */ | |
3c62338c | 928 | struct fence *flushed_updates; |
97b2e202 AD |
929 | }; |
930 | ||
931 | struct amdgpu_vm { | |
97b2e202 AD |
932 | struct rb_root va; |
933 | ||
7fc11959 | 934 | /* protecting invalidated */ |
97b2e202 AD |
935 | spinlock_t status_lock; |
936 | ||
937 | /* BOs moved, but not yet updated in the PT */ | |
938 | struct list_head invalidated; | |
939 | ||
7fc11959 CK |
940 | /* BOs cleared in the PT because of a move */ |
941 | struct list_head cleared; | |
942 | ||
943 | /* BO mappings freed, but not yet updated in the PT */ | |
97b2e202 AD |
944 | struct list_head freed; |
945 | ||
946 | /* contains the page directory */ | |
947 | struct amdgpu_bo *page_directory; | |
948 | unsigned max_pde_used; | |
05906dec | 949 | struct fence *page_directory_fence; |
97b2e202 AD |
950 | |
951 | /* array of page tables, one for each page directory entry */ | |
952 | struct amdgpu_vm_pt *page_tables; | |
953 | ||
954 | /* for id and flush management per ring */ | |
955 | struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; | |
c25867df CZ |
956 | /* for interval tree */ |
957 | spinlock_t it_lock; | |
97b2e202 AD |
958 | }; |
959 | ||
960 | struct amdgpu_vm_manager { | |
1c16c0a7 CK |
961 | struct { |
962 | struct fence *active; | |
963 | atomic_long_t owner; | |
964 | } ids[AMDGPU_NUM_VM]; | |
965 | ||
8b4fb00b | 966 | uint32_t max_pfn; |
97b2e202 | 967 | /* number of VMIDs */ |
8b4fb00b | 968 | unsigned nvm; |
97b2e202 | 969 | /* vram base address for page table entry */ |
8b4fb00b | 970 | u64 vram_base_offset; |
97b2e202 | 971 | /* is vm enabled? */ |
8b4fb00b | 972 | bool enabled; |
97b2e202 AD |
973 | /* vm pte handling */ |
974 | const struct amdgpu_vm_pte_funcs *vm_pte_funcs; | |
975 | struct amdgpu_ring *vm_pte_funcs_ring; | |
976 | }; | |
977 | ||
ea89f8c9 | 978 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev); |
8b4fb00b CK |
979 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); |
980 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); | |
981 | struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, | |
982 | struct amdgpu_vm *vm, | |
983 | struct list_head *head); | |
984 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, | |
985 | struct amdgpu_sync *sync); | |
986 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
987 | struct amdgpu_vm *vm, | |
988 | struct fence *updates); | |
989 | void amdgpu_vm_fence(struct amdgpu_device *adev, | |
990 | struct amdgpu_vm *vm, | |
991 | struct fence *fence); | |
992 | uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); | |
993 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
994 | struct amdgpu_vm *vm); | |
995 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
996 | struct amdgpu_vm *vm); | |
997 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
998 | struct amdgpu_sync *sync); | |
999 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1000 | struct amdgpu_bo_va *bo_va, | |
1001 | struct ttm_mem_reg *mem); | |
1002 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1003 | struct amdgpu_bo *bo); | |
1004 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1005 | struct amdgpu_bo *bo); | |
1006 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1007 | struct amdgpu_vm *vm, | |
1008 | struct amdgpu_bo *bo); | |
1009 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1010 | struct amdgpu_bo_va *bo_va, | |
1011 | uint64_t addr, uint64_t offset, | |
1012 | uint64_t size, uint32_t flags); | |
1013 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1014 | struct amdgpu_bo_va *bo_va, | |
1015 | uint64_t addr); | |
1016 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1017 | struct amdgpu_bo_va *bo_va); | |
1018 | int amdgpu_vm_free_job(struct amdgpu_job *job); | |
1019 | ||
97b2e202 AD |
1020 | /* |
1021 | * context related structures | |
1022 | */ | |
1023 | ||
21c16bf6 CK |
1024 | #define AMDGPU_CTX_MAX_CS_PENDING 16 |
1025 | ||
1026 | struct amdgpu_ctx_ring { | |
91404fb2 CK |
1027 | uint64_t sequence; |
1028 | struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; | |
1029 | struct amd_sched_entity entity; | |
21c16bf6 CK |
1030 | }; |
1031 | ||
97b2e202 | 1032 | struct amdgpu_ctx { |
0b492a4c | 1033 | struct kref refcount; |
9cb7e5a9 | 1034 | struct amdgpu_device *adev; |
0b492a4c | 1035 | unsigned reset_counter; |
21c16bf6 CK |
1036 | spinlock_t ring_lock; |
1037 | struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; | |
97b2e202 AD |
1038 | }; |
1039 | ||
1040 | struct amdgpu_ctx_mgr { | |
0b492a4c AD |
1041 | struct amdgpu_device *adev; |
1042 | struct mutex lock; | |
1043 | /* protected by lock */ | |
1044 | struct idr ctx_handles; | |
97b2e202 AD |
1045 | }; |
1046 | ||
47f38501 CK |
1047 | int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, |
1048 | struct amdgpu_ctx *ctx); | |
1049 | void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); | |
0b492a4c | 1050 | |
0b492a4c AD |
1051 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); |
1052 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx); | |
1053 | ||
21c16bf6 | 1054 | uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, |
ce882e6d | 1055 | struct fence *fence); |
21c16bf6 CK |
1056 | struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, |
1057 | struct amdgpu_ring *ring, uint64_t seq); | |
1058 | ||
0b492a4c AD |
1059 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, |
1060 | struct drm_file *filp); | |
1061 | ||
efd4ccb5 CK |
1062 | void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); |
1063 | void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); | |
0b492a4c | 1064 | |
97b2e202 AD |
1065 | /* |
1066 | * file private structure | |
1067 | */ | |
1068 | ||
1069 | struct amdgpu_fpriv { | |
1070 | struct amdgpu_vm vm; | |
1071 | struct mutex bo_list_lock; | |
1072 | struct idr bo_list_handles; | |
0b492a4c | 1073 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
1074 | }; |
1075 | ||
1076 | /* | |
1077 | * residency list | |
1078 | */ | |
1079 | ||
1080 | struct amdgpu_bo_list { | |
1081 | struct mutex lock; | |
1082 | struct amdgpu_bo *gds_obj; | |
1083 | struct amdgpu_bo *gws_obj; | |
1084 | struct amdgpu_bo *oa_obj; | |
1085 | bool has_userptr; | |
1086 | unsigned num_entries; | |
1087 | struct amdgpu_bo_list_entry *array; | |
1088 | }; | |
1089 | ||
1090 | struct amdgpu_bo_list * | |
1091 | amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); | |
1092 | void amdgpu_bo_list_put(struct amdgpu_bo_list *list); | |
1093 | void amdgpu_bo_list_free(struct amdgpu_bo_list *list); | |
1094 | ||
1095 | /* | |
1096 | * GFX stuff | |
1097 | */ | |
1098 | #include "clearstate_defs.h" | |
1099 | ||
1100 | struct amdgpu_rlc { | |
1101 | /* for power gating */ | |
1102 | struct amdgpu_bo *save_restore_obj; | |
1103 | uint64_t save_restore_gpu_addr; | |
1104 | volatile uint32_t *sr_ptr; | |
1105 | const u32 *reg_list; | |
1106 | u32 reg_list_size; | |
1107 | /* for clear state */ | |
1108 | struct amdgpu_bo *clear_state_obj; | |
1109 | uint64_t clear_state_gpu_addr; | |
1110 | volatile uint32_t *cs_ptr; | |
1111 | const struct cs_section_def *cs_data; | |
1112 | u32 clear_state_size; | |
1113 | /* for cp tables */ | |
1114 | struct amdgpu_bo *cp_table_obj; | |
1115 | uint64_t cp_table_gpu_addr; | |
1116 | volatile uint32_t *cp_table_ptr; | |
1117 | u32 cp_table_size; | |
1118 | }; | |
1119 | ||
1120 | struct amdgpu_mec { | |
1121 | struct amdgpu_bo *hpd_eop_obj; | |
1122 | u64 hpd_eop_gpu_addr; | |
1123 | u32 num_pipe; | |
1124 | u32 num_mec; | |
1125 | u32 num_queue; | |
1126 | }; | |
1127 | ||
1128 | /* | |
1129 | * GPU scratch registers structures, functions & helpers | |
1130 | */ | |
1131 | struct amdgpu_scratch { | |
1132 | unsigned num_reg; | |
1133 | uint32_t reg_base; | |
1134 | bool free[32]; | |
1135 | uint32_t reg[32]; | |
1136 | }; | |
1137 | ||
1138 | /* | |
1139 | * GFX configurations | |
1140 | */ | |
1141 | struct amdgpu_gca_config { | |
1142 | unsigned max_shader_engines; | |
1143 | unsigned max_tile_pipes; | |
1144 | unsigned max_cu_per_sh; | |
1145 | unsigned max_sh_per_se; | |
1146 | unsigned max_backends_per_se; | |
1147 | unsigned max_texture_channel_caches; | |
1148 | unsigned max_gprs; | |
1149 | unsigned max_gs_threads; | |
1150 | unsigned max_hw_contexts; | |
1151 | unsigned sc_prim_fifo_size_frontend; | |
1152 | unsigned sc_prim_fifo_size_backend; | |
1153 | unsigned sc_hiz_tile_fifo_size; | |
1154 | unsigned sc_earlyz_tile_fifo_size; | |
1155 | ||
1156 | unsigned num_tile_pipes; | |
1157 | unsigned backend_enable_mask; | |
1158 | unsigned mem_max_burst_length_bytes; | |
1159 | unsigned mem_row_size_in_kb; | |
1160 | unsigned shader_engine_tile_size; | |
1161 | unsigned num_gpus; | |
1162 | unsigned multi_gpu_tile_size; | |
1163 | unsigned mc_arb_ramcfg; | |
1164 | unsigned gb_addr_config; | |
1165 | ||
1166 | uint32_t tile_mode_array[32]; | |
1167 | uint32_t macrotile_mode_array[16]; | |
1168 | }; | |
1169 | ||
1170 | struct amdgpu_gfx { | |
1171 | struct mutex gpu_clock_mutex; | |
1172 | struct amdgpu_gca_config config; | |
1173 | struct amdgpu_rlc rlc; | |
1174 | struct amdgpu_mec mec; | |
1175 | struct amdgpu_scratch scratch; | |
1176 | const struct firmware *me_fw; /* ME firmware */ | |
1177 | uint32_t me_fw_version; | |
1178 | const struct firmware *pfp_fw; /* PFP firmware */ | |
1179 | uint32_t pfp_fw_version; | |
1180 | const struct firmware *ce_fw; /* CE firmware */ | |
1181 | uint32_t ce_fw_version; | |
1182 | const struct firmware *rlc_fw; /* RLC firmware */ | |
1183 | uint32_t rlc_fw_version; | |
1184 | const struct firmware *mec_fw; /* MEC firmware */ | |
1185 | uint32_t mec_fw_version; | |
1186 | const struct firmware *mec2_fw; /* MEC2 firmware */ | |
1187 | uint32_t mec2_fw_version; | |
02558a00 KW |
1188 | uint32_t me_feature_version; |
1189 | uint32_t ce_feature_version; | |
1190 | uint32_t pfp_feature_version; | |
351643d7 JZ |
1191 | uint32_t rlc_feature_version; |
1192 | uint32_t mec_feature_version; | |
1193 | uint32_t mec2_feature_version; | |
97b2e202 AD |
1194 | struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; |
1195 | unsigned num_gfx_rings; | |
1196 | struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; | |
1197 | unsigned num_compute_rings; | |
1198 | struct amdgpu_irq_src eop_irq; | |
1199 | struct amdgpu_irq_src priv_reg_irq; | |
1200 | struct amdgpu_irq_src priv_inst_irq; | |
1201 | /* gfx status */ | |
1202 | uint32_t gfx_current_status; | |
a101a899 KW |
1203 | /* ce ram size*/ |
1204 | unsigned ce_ram_size; | |
97b2e202 AD |
1205 | }; |
1206 | ||
1207 | int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, | |
1208 | unsigned size, struct amdgpu_ib *ib); | |
1209 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); | |
1210 | int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, | |
1211 | struct amdgpu_ib *ib, void *owner); | |
1212 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); | |
1213 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
1214 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
1215 | /* Ring access between begin & end cannot sleep */ | |
1216 | void amdgpu_ring_free_size(struct amdgpu_ring *ring); | |
1217 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); | |
1218 | int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); | |
edff0e28 | 1219 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); |
97b2e202 AD |
1220 | void amdgpu_ring_commit(struct amdgpu_ring *ring); |
1221 | void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); | |
1222 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | |
1223 | void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); | |
97b2e202 AD |
1224 | unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, |
1225 | uint32_t **data); | |
1226 | int amdgpu_ring_restore(struct amdgpu_ring *ring, | |
1227 | unsigned size, uint32_t *data); | |
1228 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
1229 | unsigned ring_size, u32 nop, u32 align_mask, | |
1230 | struct amdgpu_irq_src *irq_src, unsigned irq_type, | |
1231 | enum amdgpu_ring_type ring_type); | |
1232 | void amdgpu_ring_fini(struct amdgpu_ring *ring); | |
8120b61f | 1233 | struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); |
97b2e202 AD |
1234 | |
1235 | /* | |
1236 | * CS. | |
1237 | */ | |
1238 | struct amdgpu_cs_chunk { | |
1239 | uint32_t chunk_id; | |
1240 | uint32_t length_dw; | |
1241 | uint32_t *kdata; | |
1242 | void __user *user_ptr; | |
1243 | }; | |
1244 | ||
1245 | struct amdgpu_cs_parser { | |
1246 | struct amdgpu_device *adev; | |
1247 | struct drm_file *filp; | |
3cb485f3 | 1248 | struct amdgpu_ctx *ctx; |
97b2e202 AD |
1249 | struct amdgpu_bo_list *bo_list; |
1250 | /* chunks */ | |
1251 | unsigned nchunks; | |
1252 | struct amdgpu_cs_chunk *chunks; | |
1253 | /* relocations */ | |
1254 | struct amdgpu_bo_list_entry *vm_bos; | |
97b2e202 | 1255 | struct list_head validated; |
984810fc | 1256 | struct fence *fence; |
97b2e202 AD |
1257 | |
1258 | struct amdgpu_ib *ibs; | |
1259 | uint32_t num_ibs; | |
1260 | ||
1261 | struct ww_acquire_ctx ticket; | |
1262 | ||
1263 | /* user fence */ | |
1264 | struct amdgpu_user_fence uf; | |
1265 | }; | |
1266 | ||
bb977d37 CZ |
1267 | struct amdgpu_job { |
1268 | struct amd_sched_job base; | |
1269 | struct amdgpu_device *adev; | |
bb977d37 CZ |
1270 | struct amdgpu_ib *ibs; |
1271 | uint32_t num_ibs; | |
e2840221 | 1272 | void *owner; |
bb977d37 | 1273 | struct amdgpu_user_fence uf; |
4c7eb91c | 1274 | int (*free_job)(struct amdgpu_job *job); |
bb977d37 | 1275 | }; |
a6db8a33 JZ |
1276 | #define to_amdgpu_job(sched_job) \ |
1277 | container_of((sched_job), struct amdgpu_job, base) | |
bb977d37 | 1278 | |
97b2e202 AD |
1279 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) |
1280 | { | |
1281 | return p->ibs[ib_idx].ptr[idx]; | |
1282 | } | |
1283 | ||
1284 | /* | |
1285 | * Writeback | |
1286 | */ | |
1287 | #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ | |
1288 | ||
1289 | struct amdgpu_wb { | |
1290 | struct amdgpu_bo *wb_obj; | |
1291 | volatile uint32_t *wb; | |
1292 | uint64_t gpu_addr; | |
1293 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
1294 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
1295 | }; | |
1296 | ||
1297 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); | |
1298 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); | |
1299 | ||
1300 | /** | |
1301 | * struct amdgpu_pm - power management datas | |
1302 | * It keeps track of various data needed to take powermanagement decision. | |
1303 | */ | |
1304 | ||
1305 | enum amdgpu_pm_state_type { | |
1306 | /* not used for dpm */ | |
1307 | POWER_STATE_TYPE_DEFAULT, | |
1308 | POWER_STATE_TYPE_POWERSAVE, | |
1309 | /* user selectable states */ | |
1310 | POWER_STATE_TYPE_BATTERY, | |
1311 | POWER_STATE_TYPE_BALANCED, | |
1312 | POWER_STATE_TYPE_PERFORMANCE, | |
1313 | /* internal states */ | |
1314 | POWER_STATE_TYPE_INTERNAL_UVD, | |
1315 | POWER_STATE_TYPE_INTERNAL_UVD_SD, | |
1316 | POWER_STATE_TYPE_INTERNAL_UVD_HD, | |
1317 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, | |
1318 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, | |
1319 | POWER_STATE_TYPE_INTERNAL_BOOT, | |
1320 | POWER_STATE_TYPE_INTERNAL_THERMAL, | |
1321 | POWER_STATE_TYPE_INTERNAL_ACPI, | |
1322 | POWER_STATE_TYPE_INTERNAL_ULV, | |
1323 | POWER_STATE_TYPE_INTERNAL_3DPERF, | |
1324 | }; | |
1325 | ||
1326 | enum amdgpu_int_thermal_type { | |
1327 | THERMAL_TYPE_NONE, | |
1328 | THERMAL_TYPE_EXTERNAL, | |
1329 | THERMAL_TYPE_EXTERNAL_GPIO, | |
1330 | THERMAL_TYPE_RV6XX, | |
1331 | THERMAL_TYPE_RV770, | |
1332 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, | |
1333 | THERMAL_TYPE_EVERGREEN, | |
1334 | THERMAL_TYPE_SUMO, | |
1335 | THERMAL_TYPE_NI, | |
1336 | THERMAL_TYPE_SI, | |
1337 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, | |
1338 | THERMAL_TYPE_CI, | |
1339 | THERMAL_TYPE_KV, | |
1340 | }; | |
1341 | ||
1342 | enum amdgpu_dpm_auto_throttle_src { | |
1343 | AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, | |
1344 | AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL | |
1345 | }; | |
1346 | ||
1347 | enum amdgpu_dpm_event_src { | |
1348 | AMDGPU_DPM_EVENT_SRC_ANALOG = 0, | |
1349 | AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, | |
1350 | AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, | |
1351 | AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, | |
1352 | AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 | |
1353 | }; | |
1354 | ||
1355 | #define AMDGPU_MAX_VCE_LEVELS 6 | |
1356 | ||
1357 | enum amdgpu_vce_level { | |
1358 | AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
1359 | AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
1360 | AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
1361 | AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
1362 | AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
1363 | AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
1364 | }; | |
1365 | ||
1366 | struct amdgpu_ps { | |
1367 | u32 caps; /* vbios flags */ | |
1368 | u32 class; /* vbios flags */ | |
1369 | u32 class2; /* vbios flags */ | |
1370 | /* UVD clocks */ | |
1371 | u32 vclk; | |
1372 | u32 dclk; | |
1373 | /* VCE clocks */ | |
1374 | u32 evclk; | |
1375 | u32 ecclk; | |
1376 | bool vce_active; | |
1377 | enum amdgpu_vce_level vce_level; | |
1378 | /* asic priv */ | |
1379 | void *ps_priv; | |
1380 | }; | |
1381 | ||
1382 | struct amdgpu_dpm_thermal { | |
1383 | /* thermal interrupt work */ | |
1384 | struct work_struct work; | |
1385 | /* low temperature threshold */ | |
1386 | int min_temp; | |
1387 | /* high temperature threshold */ | |
1388 | int max_temp; | |
1389 | /* was last interrupt low to high or high to low */ | |
1390 | bool high_to_low; | |
1391 | /* interrupt source */ | |
1392 | struct amdgpu_irq_src irq; | |
1393 | }; | |
1394 | ||
1395 | enum amdgpu_clk_action | |
1396 | { | |
1397 | AMDGPU_SCLK_UP = 1, | |
1398 | AMDGPU_SCLK_DOWN | |
1399 | }; | |
1400 | ||
1401 | struct amdgpu_blacklist_clocks | |
1402 | { | |
1403 | u32 sclk; | |
1404 | u32 mclk; | |
1405 | enum amdgpu_clk_action action; | |
1406 | }; | |
1407 | ||
1408 | struct amdgpu_clock_and_voltage_limits { | |
1409 | u32 sclk; | |
1410 | u32 mclk; | |
1411 | u16 vddc; | |
1412 | u16 vddci; | |
1413 | }; | |
1414 | ||
1415 | struct amdgpu_clock_array { | |
1416 | u32 count; | |
1417 | u32 *values; | |
1418 | }; | |
1419 | ||
1420 | struct amdgpu_clock_voltage_dependency_entry { | |
1421 | u32 clk; | |
1422 | u16 v; | |
1423 | }; | |
1424 | ||
1425 | struct amdgpu_clock_voltage_dependency_table { | |
1426 | u32 count; | |
1427 | struct amdgpu_clock_voltage_dependency_entry *entries; | |
1428 | }; | |
1429 | ||
1430 | union amdgpu_cac_leakage_entry { | |
1431 | struct { | |
1432 | u16 vddc; | |
1433 | u32 leakage; | |
1434 | }; | |
1435 | struct { | |
1436 | u16 vddc1; | |
1437 | u16 vddc2; | |
1438 | u16 vddc3; | |
1439 | }; | |
1440 | }; | |
1441 | ||
1442 | struct amdgpu_cac_leakage_table { | |
1443 | u32 count; | |
1444 | union amdgpu_cac_leakage_entry *entries; | |
1445 | }; | |
1446 | ||
1447 | struct amdgpu_phase_shedding_limits_entry { | |
1448 | u16 voltage; | |
1449 | u32 sclk; | |
1450 | u32 mclk; | |
1451 | }; | |
1452 | ||
1453 | struct amdgpu_phase_shedding_limits_table { | |
1454 | u32 count; | |
1455 | struct amdgpu_phase_shedding_limits_entry *entries; | |
1456 | }; | |
1457 | ||
1458 | struct amdgpu_uvd_clock_voltage_dependency_entry { | |
1459 | u32 vclk; | |
1460 | u32 dclk; | |
1461 | u16 v; | |
1462 | }; | |
1463 | ||
1464 | struct amdgpu_uvd_clock_voltage_dependency_table { | |
1465 | u8 count; | |
1466 | struct amdgpu_uvd_clock_voltage_dependency_entry *entries; | |
1467 | }; | |
1468 | ||
1469 | struct amdgpu_vce_clock_voltage_dependency_entry { | |
1470 | u32 ecclk; | |
1471 | u32 evclk; | |
1472 | u16 v; | |
1473 | }; | |
1474 | ||
1475 | struct amdgpu_vce_clock_voltage_dependency_table { | |
1476 | u8 count; | |
1477 | struct amdgpu_vce_clock_voltage_dependency_entry *entries; | |
1478 | }; | |
1479 | ||
1480 | struct amdgpu_ppm_table { | |
1481 | u8 ppm_design; | |
1482 | u16 cpu_core_number; | |
1483 | u32 platform_tdp; | |
1484 | u32 small_ac_platform_tdp; | |
1485 | u32 platform_tdc; | |
1486 | u32 small_ac_platform_tdc; | |
1487 | u32 apu_tdp; | |
1488 | u32 dgpu_tdp; | |
1489 | u32 dgpu_ulv_power; | |
1490 | u32 tj_max; | |
1491 | }; | |
1492 | ||
1493 | struct amdgpu_cac_tdp_table { | |
1494 | u16 tdp; | |
1495 | u16 configurable_tdp; | |
1496 | u16 tdc; | |
1497 | u16 battery_power_limit; | |
1498 | u16 small_power_limit; | |
1499 | u16 low_cac_leakage; | |
1500 | u16 high_cac_leakage; | |
1501 | u16 maximum_power_delivery_limit; | |
1502 | }; | |
1503 | ||
1504 | struct amdgpu_dpm_dynamic_state { | |
1505 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
1506 | struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
1507 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
1508 | struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; | |
1509 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; | |
1510 | struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; | |
1511 | struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; | |
1512 | struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; | |
1513 | struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
1514 | struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; | |
1515 | struct amdgpu_clock_array valid_sclk_values; | |
1516 | struct amdgpu_clock_array valid_mclk_values; | |
1517 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; | |
1518 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; | |
1519 | u32 mclk_sclk_ratio; | |
1520 | u32 sclk_mclk_delta; | |
1521 | u16 vddc_vddci_delta; | |
1522 | u16 min_vddc_for_pcie_gen2; | |
1523 | struct amdgpu_cac_leakage_table cac_leakage_table; | |
1524 | struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; | |
1525 | struct amdgpu_ppm_table *ppm_table; | |
1526 | struct amdgpu_cac_tdp_table *cac_tdp_table; | |
1527 | }; | |
1528 | ||
1529 | struct amdgpu_dpm_fan { | |
1530 | u16 t_min; | |
1531 | u16 t_med; | |
1532 | u16 t_high; | |
1533 | u16 pwm_min; | |
1534 | u16 pwm_med; | |
1535 | u16 pwm_high; | |
1536 | u8 t_hyst; | |
1537 | u32 cycle_delay; | |
1538 | u16 t_max; | |
1539 | u8 control_mode; | |
1540 | u16 default_max_fan_pwm; | |
1541 | u16 default_fan_output_sensitivity; | |
1542 | u16 fan_output_sensitivity; | |
1543 | bool ucode_fan_control; | |
1544 | }; | |
1545 | ||
1546 | enum amdgpu_pcie_gen { | |
1547 | AMDGPU_PCIE_GEN1 = 0, | |
1548 | AMDGPU_PCIE_GEN2 = 1, | |
1549 | AMDGPU_PCIE_GEN3 = 2, | |
1550 | AMDGPU_PCIE_GEN_INVALID = 0xffff | |
1551 | }; | |
1552 | ||
1553 | enum amdgpu_dpm_forced_level { | |
1554 | AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, | |
1555 | AMDGPU_DPM_FORCED_LEVEL_LOW = 1, | |
1556 | AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, | |
1557 | }; | |
1558 | ||
1559 | struct amdgpu_vce_state { | |
1560 | /* vce clocks */ | |
1561 | u32 evclk; | |
1562 | u32 ecclk; | |
1563 | /* gpu clocks */ | |
1564 | u32 sclk; | |
1565 | u32 mclk; | |
1566 | u8 clk_idx; | |
1567 | u8 pstate; | |
1568 | }; | |
1569 | ||
1570 | struct amdgpu_dpm_funcs { | |
1571 | int (*get_temperature)(struct amdgpu_device *adev); | |
1572 | int (*pre_set_power_state)(struct amdgpu_device *adev); | |
1573 | int (*set_power_state)(struct amdgpu_device *adev); | |
1574 | void (*post_set_power_state)(struct amdgpu_device *adev); | |
1575 | void (*display_configuration_changed)(struct amdgpu_device *adev); | |
1576 | u32 (*get_sclk)(struct amdgpu_device *adev, bool low); | |
1577 | u32 (*get_mclk)(struct amdgpu_device *adev, bool low); | |
1578 | void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); | |
1579 | void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); | |
1580 | int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); | |
1581 | bool (*vblank_too_short)(struct amdgpu_device *adev); | |
1582 | void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); | |
b7a07769 | 1583 | void (*powergate_vce)(struct amdgpu_device *adev, bool gate); |
97b2e202 AD |
1584 | void (*enable_bapm)(struct amdgpu_device *adev, bool enable); |
1585 | void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); | |
1586 | u32 (*get_fan_control_mode)(struct amdgpu_device *adev); | |
1587 | int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); | |
1588 | int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); | |
1589 | }; | |
1590 | ||
1591 | struct amdgpu_dpm { | |
1592 | struct amdgpu_ps *ps; | |
1593 | /* number of valid power states */ | |
1594 | int num_ps; | |
1595 | /* current power state that is active */ | |
1596 | struct amdgpu_ps *current_ps; | |
1597 | /* requested power state */ | |
1598 | struct amdgpu_ps *requested_ps; | |
1599 | /* boot up power state */ | |
1600 | struct amdgpu_ps *boot_ps; | |
1601 | /* default uvd power state */ | |
1602 | struct amdgpu_ps *uvd_ps; | |
1603 | /* vce requirements */ | |
1604 | struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; | |
1605 | enum amdgpu_vce_level vce_level; | |
1606 | enum amdgpu_pm_state_type state; | |
1607 | enum amdgpu_pm_state_type user_state; | |
1608 | u32 platform_caps; | |
1609 | u32 voltage_response_time; | |
1610 | u32 backbias_response_time; | |
1611 | void *priv; | |
1612 | u32 new_active_crtcs; | |
1613 | int new_active_crtc_count; | |
1614 | u32 current_active_crtcs; | |
1615 | int current_active_crtc_count; | |
1616 | struct amdgpu_dpm_dynamic_state dyn_state; | |
1617 | struct amdgpu_dpm_fan fan; | |
1618 | u32 tdp_limit; | |
1619 | u32 near_tdp_limit; | |
1620 | u32 near_tdp_limit_adjusted; | |
1621 | u32 sq_ramping_threshold; | |
1622 | u32 cac_leakage; | |
1623 | u16 tdp_od_limit; | |
1624 | u32 tdp_adjustment; | |
1625 | u16 load_line_slope; | |
1626 | bool power_control; | |
1627 | bool ac_power; | |
1628 | /* special states active */ | |
1629 | bool thermal_active; | |
1630 | bool uvd_active; | |
1631 | bool vce_active; | |
1632 | /* thermal handling */ | |
1633 | struct amdgpu_dpm_thermal thermal; | |
1634 | /* forced levels */ | |
1635 | enum amdgpu_dpm_forced_level forced_level; | |
1636 | }; | |
1637 | ||
1638 | struct amdgpu_pm { | |
1639 | struct mutex mutex; | |
97b2e202 AD |
1640 | u32 current_sclk; |
1641 | u32 current_mclk; | |
1642 | u32 default_sclk; | |
1643 | u32 default_mclk; | |
1644 | struct amdgpu_i2c_chan *i2c_bus; | |
1645 | /* internal thermal controller on rv6xx+ */ | |
1646 | enum amdgpu_int_thermal_type int_thermal_type; | |
1647 | struct device *int_hwmon_dev; | |
1648 | /* fan control parameters */ | |
1649 | bool no_fan; | |
1650 | u8 fan_pulses_per_revolution; | |
1651 | u8 fan_min_rpm; | |
1652 | u8 fan_max_rpm; | |
1653 | /* dpm */ | |
1654 | bool dpm_enabled; | |
c86f5ebf | 1655 | bool sysfs_initialized; |
97b2e202 AD |
1656 | struct amdgpu_dpm dpm; |
1657 | const struct firmware *fw; /* SMC firmware */ | |
1658 | uint32_t fw_version; | |
1659 | const struct amdgpu_dpm_funcs *funcs; | |
1660 | }; | |
1661 | ||
1662 | /* | |
1663 | * UVD | |
1664 | */ | |
1665 | #define AMDGPU_MAX_UVD_HANDLES 10 | |
1666 | #define AMDGPU_UVD_STACK_SIZE (1024*1024) | |
1667 | #define AMDGPU_UVD_HEAP_SIZE (1024*1024) | |
1668 | #define AMDGPU_UVD_FIRMWARE_OFFSET 256 | |
1669 | ||
1670 | struct amdgpu_uvd { | |
1671 | struct amdgpu_bo *vcpu_bo; | |
1672 | void *cpu_addr; | |
1673 | uint64_t gpu_addr; | |
97b2e202 AD |
1674 | atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; |
1675 | struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; | |
1676 | struct delayed_work idle_work; | |
1677 | const struct firmware *fw; /* UVD firmware */ | |
1678 | struct amdgpu_ring ring; | |
1679 | struct amdgpu_irq_src irq; | |
1680 | bool address_64_bit; | |
1681 | }; | |
1682 | ||
1683 | /* | |
1684 | * VCE | |
1685 | */ | |
1686 | #define AMDGPU_MAX_VCE_HANDLES 16 | |
97b2e202 AD |
1687 | #define AMDGPU_VCE_FIRMWARE_OFFSET 256 |
1688 | ||
6a585777 AD |
1689 | #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) |
1690 | #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) | |
1691 | ||
97b2e202 AD |
1692 | struct amdgpu_vce { |
1693 | struct amdgpu_bo *vcpu_bo; | |
1694 | uint64_t gpu_addr; | |
1695 | unsigned fw_version; | |
1696 | unsigned fb_version; | |
1697 | atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; | |
1698 | struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; | |
f1689ec1 | 1699 | uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; |
97b2e202 AD |
1700 | struct delayed_work idle_work; |
1701 | const struct firmware *fw; /* VCE firmware */ | |
1702 | struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; | |
1703 | struct amdgpu_irq_src irq; | |
6a585777 | 1704 | unsigned harvest_config; |
97b2e202 AD |
1705 | }; |
1706 | ||
1707 | /* | |
1708 | * SDMA | |
1709 | */ | |
c113ea1c | 1710 | struct amdgpu_sdma_instance { |
97b2e202 AD |
1711 | /* SDMA firmware */ |
1712 | const struct firmware *fw; | |
1713 | uint32_t fw_version; | |
cfa2104f | 1714 | uint32_t feature_version; |
97b2e202 AD |
1715 | |
1716 | struct amdgpu_ring ring; | |
18111de0 | 1717 | bool burst_nop; |
97b2e202 AD |
1718 | }; |
1719 | ||
c113ea1c AD |
1720 | struct amdgpu_sdma { |
1721 | struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; | |
1722 | struct amdgpu_irq_src trap_irq; | |
1723 | struct amdgpu_irq_src illegal_inst_irq; | |
1724 | int num_instances; | |
1725 | }; | |
1726 | ||
97b2e202 AD |
1727 | /* |
1728 | * Firmware | |
1729 | */ | |
1730 | struct amdgpu_firmware { | |
1731 | struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; | |
1732 | bool smu_load; | |
1733 | struct amdgpu_bo *fw_buf; | |
1734 | unsigned int fw_size; | |
1735 | }; | |
1736 | ||
1737 | /* | |
1738 | * Benchmarking | |
1739 | */ | |
1740 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
1741 | ||
1742 | ||
1743 | /* | |
1744 | * Testing | |
1745 | */ | |
1746 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
1747 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, | |
1748 | struct amdgpu_ring *cpA, | |
1749 | struct amdgpu_ring *cpB); | |
1750 | void amdgpu_test_syncing(struct amdgpu_device *adev); | |
1751 | ||
1752 | /* | |
1753 | * MMU Notifier | |
1754 | */ | |
1755 | #if defined(CONFIG_MMU_NOTIFIER) | |
1756 | int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); | |
1757 | void amdgpu_mn_unregister(struct amdgpu_bo *bo); | |
1758 | #else | |
1d1106b0 | 1759 | static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) |
97b2e202 AD |
1760 | { |
1761 | return -ENODEV; | |
1762 | } | |
1d1106b0 | 1763 | static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} |
97b2e202 AD |
1764 | #endif |
1765 | ||
1766 | /* | |
1767 | * Debugfs | |
1768 | */ | |
1769 | struct amdgpu_debugfs { | |
1770 | struct drm_info_list *files; | |
1771 | unsigned num_files; | |
1772 | }; | |
1773 | ||
1774 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
1775 | struct drm_info_list *files, | |
1776 | unsigned nfiles); | |
1777 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); | |
1778 | ||
1779 | #if defined(CONFIG_DEBUG_FS) | |
1780 | int amdgpu_debugfs_init(struct drm_minor *minor); | |
1781 | void amdgpu_debugfs_cleanup(struct drm_minor *minor); | |
1782 | #endif | |
1783 | ||
1784 | /* | |
1785 | * amdgpu smumgr functions | |
1786 | */ | |
1787 | struct amdgpu_smumgr_funcs { | |
1788 | int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); | |
1789 | int (*request_smu_load_fw)(struct amdgpu_device *adev); | |
1790 | int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); | |
1791 | }; | |
1792 | ||
1793 | /* | |
1794 | * amdgpu smumgr | |
1795 | */ | |
1796 | struct amdgpu_smumgr { | |
1797 | struct amdgpu_bo *toc_buf; | |
1798 | struct amdgpu_bo *smu_buf; | |
1799 | /* asic priv smu data */ | |
1800 | void *priv; | |
1801 | spinlock_t smu_lock; | |
1802 | /* smumgr functions */ | |
1803 | const struct amdgpu_smumgr_funcs *smumgr_funcs; | |
1804 | /* ucode loading complete flag */ | |
1805 | uint32_t fw_flags; | |
1806 | }; | |
1807 | ||
1808 | /* | |
1809 | * ASIC specific register table accessible by UMD | |
1810 | */ | |
1811 | struct amdgpu_allowed_register_entry { | |
1812 | uint32_t reg_offset; | |
1813 | bool untouched; | |
1814 | bool grbm_indexed; | |
1815 | }; | |
1816 | ||
1817 | struct amdgpu_cu_info { | |
1818 | uint32_t number; /* total active CU number */ | |
1819 | uint32_t ao_cu_mask; | |
1820 | uint32_t bitmap[4][4]; | |
1821 | }; | |
1822 | ||
1823 | ||
1824 | /* | |
1825 | * ASIC specific functions. | |
1826 | */ | |
1827 | struct amdgpu_asic_funcs { | |
1828 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
1829 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, | |
1830 | u32 sh_num, u32 reg_offset, u32 *value); | |
1831 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
1832 | int (*reset)(struct amdgpu_device *adev); | |
1833 | /* wait for mc_idle */ | |
1834 | int (*wait_for_mc_idle)(struct amdgpu_device *adev); | |
1835 | /* get the reference clock */ | |
1836 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
1837 | /* get the gpu clock counter */ | |
1838 | uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); | |
1839 | int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); | |
1840 | /* MM block clocks */ | |
1841 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
1842 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
1843 | }; | |
1844 | ||
1845 | /* | |
1846 | * IOCTL. | |
1847 | */ | |
1848 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
1849 | struct drm_file *filp); | |
1850 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, | |
1851 | struct drm_file *filp); | |
1852 | ||
1853 | int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, | |
1854 | struct drm_file *filp); | |
1855 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
1856 | struct drm_file *filp); | |
1857 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1858 | struct drm_file *filp); | |
1859 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1860 | struct drm_file *filp); | |
1861 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
1862 | struct drm_file *filp); | |
1863 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
1864 | struct drm_file *filp); | |
1865 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1866 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
1867 | ||
1868 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
1869 | struct drm_file *filp); | |
1870 | ||
1871 | /* VRAM scratch page for HDP bug, default vram page */ | |
1872 | struct amdgpu_vram_scratch { | |
1873 | struct amdgpu_bo *robj; | |
1874 | volatile uint32_t *ptr; | |
1875 | u64 gpu_addr; | |
1876 | }; | |
1877 | ||
1878 | /* | |
1879 | * ACPI | |
1880 | */ | |
1881 | struct amdgpu_atif_notification_cfg { | |
1882 | bool enabled; | |
1883 | int command_code; | |
1884 | }; | |
1885 | ||
1886 | struct amdgpu_atif_notifications { | |
1887 | bool display_switch; | |
1888 | bool expansion_mode_change; | |
1889 | bool thermal_state; | |
1890 | bool forced_power_state; | |
1891 | bool system_power_state; | |
1892 | bool display_conf_change; | |
1893 | bool px_gfx_switch; | |
1894 | bool brightness_change; | |
1895 | bool dgpu_display_event; | |
1896 | }; | |
1897 | ||
1898 | struct amdgpu_atif_functions { | |
1899 | bool system_params; | |
1900 | bool sbios_requests; | |
1901 | bool select_active_disp; | |
1902 | bool lid_state; | |
1903 | bool get_tv_standard; | |
1904 | bool set_tv_standard; | |
1905 | bool get_panel_expansion_mode; | |
1906 | bool set_panel_expansion_mode; | |
1907 | bool temperature_change; | |
1908 | bool graphics_device_types; | |
1909 | }; | |
1910 | ||
1911 | struct amdgpu_atif { | |
1912 | struct amdgpu_atif_notifications notifications; | |
1913 | struct amdgpu_atif_functions functions; | |
1914 | struct amdgpu_atif_notification_cfg notification_cfg; | |
1915 | struct amdgpu_encoder *encoder_for_bl; | |
1916 | }; | |
1917 | ||
1918 | struct amdgpu_atcs_functions { | |
1919 | bool get_ext_state; | |
1920 | bool pcie_perf_req; | |
1921 | bool pcie_dev_rdy; | |
1922 | bool pcie_bus_width; | |
1923 | }; | |
1924 | ||
1925 | struct amdgpu_atcs { | |
1926 | struct amdgpu_atcs_functions functions; | |
1927 | }; | |
1928 | ||
d03846af CZ |
1929 | /* |
1930 | * CGS | |
1931 | */ | |
1932 | void *amdgpu_cgs_create_device(struct amdgpu_device *adev); | |
1933 | void amdgpu_cgs_destroy_device(void *cgs_device); | |
1934 | ||
1935 | ||
97b2e202 AD |
1936 | /* |
1937 | * Core structure, functions and helpers. | |
1938 | */ | |
1939 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
1940 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1941 | ||
1942 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
1943 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
1944 | ||
8faf0e08 AD |
1945 | struct amdgpu_ip_block_status { |
1946 | bool valid; | |
1947 | bool sw; | |
1948 | bool hw; | |
1949 | }; | |
1950 | ||
97b2e202 AD |
1951 | struct amdgpu_device { |
1952 | struct device *dev; | |
1953 | struct drm_device *ddev; | |
1954 | struct pci_dev *pdev; | |
97b2e202 AD |
1955 | |
1956 | /* ASIC */ | |
2f7d10b3 | 1957 | enum amd_asic_type asic_type; |
97b2e202 AD |
1958 | uint32_t family; |
1959 | uint32_t rev_id; | |
1960 | uint32_t external_rev_id; | |
1961 | unsigned long flags; | |
1962 | int usec_timeout; | |
1963 | const struct amdgpu_asic_funcs *asic_funcs; | |
1964 | bool shutdown; | |
1965 | bool suspend; | |
1966 | bool need_dma32; | |
1967 | bool accel_working; | |
97b2e202 AD |
1968 | struct work_struct reset_work; |
1969 | struct notifier_block acpi_nb; | |
1970 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
1971 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
1972 | unsigned debugfs_count; | |
1973 | #if defined(CONFIG_DEBUG_FS) | |
1974 | struct dentry *debugfs_regs; | |
1975 | #endif | |
1976 | struct amdgpu_atif atif; | |
1977 | struct amdgpu_atcs atcs; | |
1978 | struct mutex srbm_mutex; | |
1979 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
1980 | struct mutex grbm_idx_mutex; | |
1981 | struct dev_pm_domain vga_pm_domain; | |
1982 | bool have_disp_power_ref; | |
1983 | ||
1984 | /* BIOS */ | |
1985 | uint8_t *bios; | |
1986 | bool is_atom_bios; | |
1987 | uint16_t bios_header_start; | |
1988 | struct amdgpu_bo *stollen_vga_memory; | |
1989 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; | |
1990 | ||
1991 | /* Register/doorbell mmio */ | |
1992 | resource_size_t rmmio_base; | |
1993 | resource_size_t rmmio_size; | |
1994 | void __iomem *rmmio; | |
1995 | /* protects concurrent MM_INDEX/DATA based register access */ | |
1996 | spinlock_t mmio_idx_lock; | |
1997 | /* protects concurrent SMC based register access */ | |
1998 | spinlock_t smc_idx_lock; | |
1999 | amdgpu_rreg_t smc_rreg; | |
2000 | amdgpu_wreg_t smc_wreg; | |
2001 | /* protects concurrent PCIE register access */ | |
2002 | spinlock_t pcie_idx_lock; | |
2003 | amdgpu_rreg_t pcie_rreg; | |
2004 | amdgpu_wreg_t pcie_wreg; | |
2005 | /* protects concurrent UVD register access */ | |
2006 | spinlock_t uvd_ctx_idx_lock; | |
2007 | amdgpu_rreg_t uvd_ctx_rreg; | |
2008 | amdgpu_wreg_t uvd_ctx_wreg; | |
2009 | /* protects concurrent DIDT register access */ | |
2010 | spinlock_t didt_idx_lock; | |
2011 | amdgpu_rreg_t didt_rreg; | |
2012 | amdgpu_wreg_t didt_wreg; | |
2013 | /* protects concurrent ENDPOINT (audio) register access */ | |
2014 | spinlock_t audio_endpt_idx_lock; | |
2015 | amdgpu_block_rreg_t audio_endpt_rreg; | |
2016 | amdgpu_block_wreg_t audio_endpt_wreg; | |
2017 | void __iomem *rio_mem; | |
2018 | resource_size_t rio_mem_size; | |
2019 | struct amdgpu_doorbell doorbell; | |
2020 | ||
2021 | /* clock/pll info */ | |
2022 | struct amdgpu_clock clock; | |
2023 | ||
2024 | /* MC */ | |
2025 | struct amdgpu_mc mc; | |
2026 | struct amdgpu_gart gart; | |
2027 | struct amdgpu_dummy_page dummy_page; | |
2028 | struct amdgpu_vm_manager vm_manager; | |
2029 | ||
2030 | /* memory management */ | |
2031 | struct amdgpu_mman mman; | |
2032 | struct amdgpu_gem gem; | |
2033 | struct amdgpu_vram_scratch vram_scratch; | |
2034 | struct amdgpu_wb wb; | |
2035 | atomic64_t vram_usage; | |
2036 | atomic64_t vram_vis_usage; | |
2037 | atomic64_t gtt_usage; | |
2038 | atomic64_t num_bytes_moved; | |
d94aed5a | 2039 | atomic_t gpu_reset_counter; |
97b2e202 AD |
2040 | |
2041 | /* display */ | |
2042 | struct amdgpu_mode_info mode_info; | |
2043 | struct work_struct hotplug_work; | |
2044 | struct amdgpu_irq_src crtc_irq; | |
2045 | struct amdgpu_irq_src pageflip_irq; | |
2046 | struct amdgpu_irq_src hpd_irq; | |
2047 | ||
2048 | /* rings */ | |
97b2e202 AD |
2049 | unsigned fence_context; |
2050 | struct mutex ring_lock; | |
2051 | unsigned num_rings; | |
2052 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
2053 | bool ib_pool_ready; | |
2054 | struct amdgpu_sa_manager ring_tmp_bo; | |
2055 | ||
2056 | /* interrupts */ | |
2057 | struct amdgpu_irq irq; | |
2058 | ||
2059 | /* dpm */ | |
2060 | struct amdgpu_pm pm; | |
2061 | u32 cg_flags; | |
2062 | u32 pg_flags; | |
2063 | ||
2064 | /* amdgpu smumgr */ | |
2065 | struct amdgpu_smumgr smu; | |
2066 | ||
2067 | /* gfx */ | |
2068 | struct amdgpu_gfx gfx; | |
2069 | ||
2070 | /* sdma */ | |
c113ea1c | 2071 | struct amdgpu_sdma sdma; |
97b2e202 AD |
2072 | |
2073 | /* uvd */ | |
2074 | bool has_uvd; | |
2075 | struct amdgpu_uvd uvd; | |
2076 | ||
2077 | /* vce */ | |
2078 | struct amdgpu_vce vce; | |
2079 | ||
2080 | /* firmwares */ | |
2081 | struct amdgpu_firmware firmware; | |
2082 | ||
2083 | /* GDS */ | |
2084 | struct amdgpu_gds gds; | |
2085 | ||
2086 | const struct amdgpu_ip_block_version *ip_blocks; | |
2087 | int num_ip_blocks; | |
8faf0e08 | 2088 | struct amdgpu_ip_block_status *ip_block_status; |
97b2e202 AD |
2089 | struct mutex mn_lock; |
2090 | DECLARE_HASHTABLE(mn_hash, 7); | |
2091 | ||
2092 | /* tracking pinned memory */ | |
2093 | u64 vram_pin_size; | |
2094 | u64 gart_pin_size; | |
130e0371 OG |
2095 | |
2096 | /* amdkfd interface */ | |
2097 | struct kfd_dev *kfd; | |
23ca0e4e CZ |
2098 | |
2099 | /* kernel conext for IB submission */ | |
47f38501 | 2100 | struct amdgpu_ctx kernel_ctx; |
97b2e202 AD |
2101 | }; |
2102 | ||
2103 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2104 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2105 | struct drm_device *ddev, | |
2106 | struct pci_dev *pdev, | |
2107 | uint32_t flags); | |
2108 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
2109 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
2110 | ||
2111 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
2112 | bool always_indirect); | |
2113 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
2114 | bool always_indirect); | |
2115 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); | |
2116 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
2117 | ||
2118 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
2119 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
2120 | ||
2121 | /* | |
2122 | * Cast helper | |
2123 | */ | |
2124 | extern const struct fence_ops amdgpu_fence_ops; | |
2125 | static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) | |
2126 | { | |
2127 | struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); | |
2128 | ||
2129 | if (__f->base.ops == &amdgpu_fence_ops) | |
2130 | return __f; | |
2131 | ||
2132 | return NULL; | |
2133 | } | |
2134 | ||
2135 | /* | |
2136 | * Registers read & write functions. | |
2137 | */ | |
2138 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) | |
2139 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) | |
2140 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) | |
2141 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) | |
2142 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) | |
2143 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2144 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2145 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
2146 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
2147 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) | |
2148 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
2149 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
2150 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
2151 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
2152 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
2153 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) | |
2154 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
2155 | #define WREG32_P(reg, val, mask) \ | |
2156 | do { \ | |
2157 | uint32_t tmp_ = RREG32(reg); \ | |
2158 | tmp_ &= (mask); \ | |
2159 | tmp_ |= ((val) & ~(mask)); \ | |
2160 | WREG32(reg, tmp_); \ | |
2161 | } while (0) | |
2162 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
2163 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
2164 | #define WREG32_PLL_P(reg, val, mask) \ | |
2165 | do { \ | |
2166 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
2167 | tmp_ &= (mask); \ | |
2168 | tmp_ |= ((val) & ~(mask)); \ | |
2169 | WREG32_PLL(reg, tmp_); \ | |
2170 | } while (0) | |
2171 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
2172 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
2173 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
2174 | ||
2175 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
2176 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
2177 | ||
2178 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT | |
2179 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
2180 | ||
2181 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
2182 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
2183 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
2184 | ||
2185 | #define REG_GET_FIELD(value, reg, field) \ | |
2186 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
2187 | ||
2188 | /* | |
2189 | * BIOS helpers. | |
2190 | */ | |
2191 | #define RBIOS8(i) (adev->bios[i]) | |
2192 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2193 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2194 | ||
2195 | /* | |
2196 | * RING helpers. | |
2197 | */ | |
2198 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) | |
2199 | { | |
2200 | if (ring->count_dw <= 0) | |
86c2b790 | 2201 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
97b2e202 AD |
2202 | ring->ring[ring->wptr++] = v; |
2203 | ring->wptr &= ring->ptr_mask; | |
2204 | ring->count_dw--; | |
2205 | ring->ring_free_dw--; | |
2206 | } | |
2207 | ||
c113ea1c AD |
2208 | static inline struct amdgpu_sdma_instance * |
2209 | amdgpu_get_sdma_instance(struct amdgpu_ring *ring) | |
4b2f7e2c JZ |
2210 | { |
2211 | struct amdgpu_device *adev = ring->adev; | |
2212 | int i; | |
2213 | ||
c113ea1c AD |
2214 | for (i = 0; i < adev->sdma.num_instances; i++) |
2215 | if (&adev->sdma.instance[i].ring == ring) | |
4b2f7e2c JZ |
2216 | break; |
2217 | ||
2218 | if (i < AMDGPU_MAX_SDMA_INSTANCES) | |
c113ea1c | 2219 | return &adev->sdma.instance[i]; |
4b2f7e2c JZ |
2220 | else |
2221 | return NULL; | |
2222 | } | |
2223 | ||
97b2e202 AD |
2224 | /* |
2225 | * ASICs macro. | |
2226 | */ | |
2227 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
2228 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
2229 | #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) | |
2230 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) | |
2231 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
2232 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
2233 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
2234 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) | |
2235 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) | |
2236 | #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) | |
2237 | #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) | |
2238 | #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) | |
2239 | #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) | |
2240 | #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) | |
2241 | #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) | |
2242 | #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) | |
2243 | #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) | |
2244 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) | |
2245 | #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) | |
97b2e202 AD |
2246 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) |
2247 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
2248 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
2249 | #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) | |
2250 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) | |
890ee23f | 2251 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) |
97b2e202 AD |
2252 | #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) |
2253 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) | |
d2edb07b | 2254 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) |
97b2e202 AD |
2255 | #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) |
2256 | #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) | |
2257 | #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) | |
2258 | #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) | |
2259 | #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) | |
2260 | #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) | |
2261 | #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) | |
2262 | #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) | |
2263 | #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) | |
2264 | #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) | |
2265 | #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) | |
2266 | #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) | |
2267 | #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) | |
2268 | #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) | |
2269 | #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) | |
2270 | #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) | |
2271 | #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) | |
2272 | #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) | |
2273 | #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) | |
c7ae72c0 | 2274 | #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) |
6e7a3840 | 2275 | #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) |
97b2e202 AD |
2276 | #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) |
2277 | #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) | |
2278 | #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) | |
2279 | #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) | |
2280 | #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) | |
2281 | #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) | |
2282 | #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) | |
2283 | #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) | |
2284 | #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) | |
2285 | #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) | |
2286 | #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) | |
2287 | #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) | |
b7a07769 | 2288 | #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) |
97b2e202 AD |
2289 | #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) |
2290 | #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) | |
2291 | #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) | |
2292 | #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) | |
2293 | #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) | |
2294 | ||
2295 | #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) | |
2296 | ||
2297 | /* Common functions */ | |
2298 | int amdgpu_gpu_reset(struct amdgpu_device *adev); | |
2299 | void amdgpu_pci_config_reset(struct amdgpu_device *adev); | |
2300 | bool amdgpu_card_posted(struct amdgpu_device *adev); | |
2301 | void amdgpu_update_display_priority(struct amdgpu_device *adev); | |
2302 | bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); | |
d5fc5e82 | 2303 | |
97b2e202 AD |
2304 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); |
2305 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
2306 | u32 ip_instance, u32 ring, | |
2307 | struct amdgpu_ring **out_ring); | |
2308 | void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); | |
2309 | bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); | |
2310 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, | |
2311 | uint32_t flags); | |
2312 | bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); | |
2313 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); | |
2314 | uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, | |
2315 | struct ttm_mem_reg *mem); | |
2316 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); | |
2317 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); | |
2318 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); | |
2319 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
2320 | const u32 *registers, | |
2321 | const u32 array_size); | |
2322 | ||
2323 | bool amdgpu_device_is_px(struct drm_device *dev); | |
2324 | /* atpx handler */ | |
2325 | #if defined(CONFIG_VGA_SWITCHEROO) | |
2326 | void amdgpu_register_atpx_handler(void); | |
2327 | void amdgpu_unregister_atpx_handler(void); | |
2328 | #else | |
2329 | static inline void amdgpu_register_atpx_handler(void) {} | |
2330 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
2331 | #endif | |
2332 | ||
2333 | /* | |
2334 | * KMS | |
2335 | */ | |
2336 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
2337 | extern int amdgpu_max_kms_ioctl; | |
2338 | ||
2339 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
2340 | int amdgpu_driver_unload_kms(struct drm_device *dev); | |
2341 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); | |
2342 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
2343 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
2344 | struct drm_file *file_priv); | |
2345 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
2346 | struct drm_file *file_priv); | |
2347 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); | |
2348 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
2349 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
2350 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2351 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
2352 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, | |
97b2e202 AD |
2353 | int *max_error, |
2354 | struct timeval *vblank_time, | |
2355 | unsigned flags); | |
2356 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, | |
2357 | unsigned long arg); | |
2358 | ||
97b2e202 AD |
2359 | /* |
2360 | * functions used by amdgpu_encoder.c | |
2361 | */ | |
2362 | struct amdgpu_afmt_acr { | |
2363 | u32 clock; | |
2364 | ||
2365 | int n_32khz; | |
2366 | int cts_32khz; | |
2367 | ||
2368 | int n_44_1khz; | |
2369 | int cts_44_1khz; | |
2370 | ||
2371 | int n_48khz; | |
2372 | int cts_48khz; | |
2373 | ||
2374 | }; | |
2375 | ||
2376 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
2377 | ||
2378 | /* amdgpu_acpi.c */ | |
2379 | #if defined(CONFIG_ACPI) | |
2380 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
2381 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
2382 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
2383 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
2384 | u8 perf_req, bool advertise); | |
2385 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
2386 | #else | |
2387 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
2388 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
2389 | #endif | |
2390 | ||
2391 | struct amdgpu_bo_va_mapping * | |
2392 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
2393 | uint64_t addr, struct amdgpu_bo **bo); | |
2394 | ||
2395 | #include "amdgpu_object.h" | |
2396 | ||
2397 | #endif |