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drm/amdgpu: remove detect_hw_virtualization interface
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202
AD		 38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
c632d799 54#include "amdgpu_ttm.h"
97b2e202 55#include "amdgpu_gds.h"
56113504 56#include "amdgpu_sync.h"
78023016 57#include "amdgpu_ring.h"
073440d2 58#include "amdgpu_vm.h"
1f7371b2 59#include "amd_powerplay.h"
cf097881 60#include "amdgpu_dpm.h"
a8fe58ce 61#include "amdgpu_acp.h"
97b2e202 62
b80d8475 63#include "gpu_scheduler.h"
ceeb50ed 64#include "amdgpu_virt.h"
b80d8475 65
97b2e202
AD		 66/*
67 * Modules parameters.
68 */
69extern int amdgpu_modeset;
70extern int amdgpu_vram_limit;
71extern int amdgpu_gart_size;
95844d20 72extern int amdgpu_moverate;
97b2e202
AD		 73extern int amdgpu_benchmarking;
74extern int amdgpu_testing;
75extern int amdgpu_audio;
76extern int amdgpu_disp_priority;
77extern int amdgpu_hw_i2c;
78extern int amdgpu_pcie_gen2;
79extern int amdgpu_msi;
80extern int amdgpu_lockup_timeout;
81extern int amdgpu_dpm;
82extern int amdgpu_smc_load_fw;
83extern int amdgpu_aspm;
84extern int amdgpu_runtime_pm;
97b2e202
AD		 85extern unsigned amdgpu_ip_block_mask;
86extern int amdgpu_bapm;
87extern int amdgpu_deep_color;
88extern int amdgpu_vm_size;
89extern int amdgpu_vm_block_size;
d9c13156 90extern int amdgpu_vm_fault_stop;
b495bd3a 91extern int amdgpu_vm_debug;
1333f723 92extern int amdgpu_sched_jobs;
4afcb303 93extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 94extern int amdgpu_no_evict;
95extern int amdgpu_direct_gma_size;
cd474ba0
AD		 96extern unsigned amdgpu_pcie_gen_cap;
97extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 98extern unsigned amdgpu_cg_mask;
99extern unsigned amdgpu_pg_mask;
6f8941a2 100extern char *amdgpu_disable_cu;
9accf2fd 101extern char *amdgpu_virtual_display;
5141e9d2 102extern unsigned amdgpu_pp_feature_mask;
6a7f76e7 103extern int amdgpu_vram_page_split;
97b2e202 104
4b559c90 105#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 106#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
109#define AMDGPU_IB_POOL_SIZE 16
110#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
111#define AMDGPUFB_CONN_LIMIT 4
112#define AMDGPU_BIOS_NUM_SCRATCH 8
113
36f523a7
JZ		 114/* max number of IP instances */
115#define AMDGPU_MAX_SDMA_INSTANCES 2
116
97b2e202
AD		 117/* hardcode that limit for now */
118#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
119
120/* hard reset data */
121#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
122
123/* reset flags */
124#define AMDGPU_RESET_GFX (1 << 0)
125#define AMDGPU_RESET_COMPUTE (1 << 1)
126#define AMDGPU_RESET_DMA (1 << 2)
127#define AMDGPU_RESET_CP (1 << 3)
128#define AMDGPU_RESET_GRBM (1 << 4)
129#define AMDGPU_RESET_DMA1 (1 << 5)
130#define AMDGPU_RESET_RLC (1 << 6)
131#define AMDGPU_RESET_SEM (1 << 7)
132#define AMDGPU_RESET_IH (1 << 8)
133#define AMDGPU_RESET_VMC (1 << 9)
134#define AMDGPU_RESET_MC (1 << 10)
135#define AMDGPU_RESET_DISPLAY (1 << 11)
136#define AMDGPU_RESET_UVD (1 << 12)
137#define AMDGPU_RESET_VCE (1 << 13)
138#define AMDGPU_RESET_VCE1 (1 << 14)
139
97b2e202
AD		 140/* GFX current status */
141#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
142#define AMDGPU_GFX_SAFE_MODE 0x00000001L
143#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
144#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
145#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
146
147/* max cursor sizes (in pixels) */
148#define CIK_CURSOR_WIDTH 128
149#define CIK_CURSOR_HEIGHT 128
150
151struct amdgpu_device;
97b2e202 152struct amdgpu_ib;
97b2e202 153struct amdgpu_cs_parser;
bb977d37 154struct amdgpu_job;
97b2e202 155struct amdgpu_irq_src;
0b492a4c 156struct amdgpu_fpriv;
97b2e202
AD		 157
158enum amdgpu_cp_irq {
159 AMDGPU_CP_IRQ_GFX_EOP = 0,
160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
168
169 AMDGPU_CP_IRQ_LAST
170};
171
172enum amdgpu_sdma_irq {
173 AMDGPU_SDMA_IRQ_TRAP0 = 0,
174 AMDGPU_SDMA_IRQ_TRAP1,
175
176 AMDGPU_SDMA_IRQ_LAST
177};
178
179enum amdgpu_thermal_irq {
180 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
181 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
182
183 AMDGPU_THERMAL_IRQ_LAST
184};
185
4e638ae9
XY		 186enum amdgpu_kiq_irq {
187 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
188 AMDGPU_CP_KIQ_IRQ_LAST
189};
190
97b2e202 191int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 192 enum amd_ip_block_type block_type,
193 enum amd_clockgating_state state);
97b2e202 194int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 195 enum amd_ip_block_type block_type,
196 enum amd_powergating_state state);
5dbbb60b
AD		 197int amdgpu_wait_for_idle(struct amdgpu_device *adev,
198 enum amd_ip_block_type block_type);
199bool amdgpu_is_idle(struct amdgpu_device *adev,
200 enum amd_ip_block_type block_type);
97b2e202 201
a1255107
AD		 202#define AMDGPU_MAX_IP_NUM 16
203
204struct amdgpu_ip_block_status {
205 bool valid;
206 bool sw;
207 bool hw;
208 bool late_initialized;
209 bool hang;
210};
211
97b2e202 212struct amdgpu_ip_block_version {
a1255107
AD		 213 const enum amd_ip_block_type type;
214 const u32 major;
215 const u32 minor;
216 const u32 rev;
5fc3aeeb 217 const struct amd_ip_funcs *funcs;
97b2e202
AD		 218};
219
a1255107
AD		 220struct amdgpu_ip_block {
221 struct amdgpu_ip_block_status status;
222 const struct amdgpu_ip_block_version *version;
223};
224
97b2e202 225int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 226 enum amd_ip_block_type type,
97b2e202
AD		 227 u32 major, u32 minor);
228
a1255107
AD		 229struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
230 enum amd_ip_block_type type);
231
232int amdgpu_ip_block_add(struct amdgpu_device *adev,
233 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 234
235/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
236struct amdgpu_buffer_funcs {
237 /* maximum bytes in a single operation */
238 uint32_t copy_max_bytes;
239
240 /* number of dw to reserve per operation */
241 unsigned copy_num_dw;
242
243 /* used for buffer migration */
c7ae72c0 244 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 245 /* src addr in bytes */
246 uint64_t src_offset,
247 /* dst addr in bytes */
248 uint64_t dst_offset,
249 /* number of byte to transfer */
250 uint32_t byte_count);
251
252 /* maximum bytes in a single operation */
253 uint32_t fill_max_bytes;
254
255 /* number of dw to reserve per operation */
256 unsigned fill_num_dw;
257
258 /* used for buffer clearing */
6e7a3840 259 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 260 /* value to write to memory */
261 uint32_t src_data,
262 /* dst addr in bytes */
263 uint64_t dst_offset,
264 /* number of byte to fill */
265 uint32_t byte_count);
266};
267
268/* provided by hw blocks that can write ptes, e.g., sdma */
269struct amdgpu_vm_pte_funcs {
270 /* copy pte entries from GART */
271 void (*copy_pte)(struct amdgpu_ib *ib,
272 uint64_t pe, uint64_t src,
273 unsigned count);
274 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 275 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
276 uint64_t value, unsigned count,
277 uint32_t incr);
97b2e202
AD		 278 /* for linear pte/pde updates without addr mapping */
279 void (*set_pte_pde)(struct amdgpu_ib *ib,
280 uint64_t pe,
281 uint64_t addr, unsigned count,
282 uint32_t incr, uint32_t flags);
97b2e202
AD		 283};
284
285/* provided by the gmc block */
286struct amdgpu_gart_funcs {
287 /* flush the vm tlb via mmio */
288 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
289 uint32_t vmid);
290 /* write pte/pde updates using the cpu */
291 int (*set_pte_pde)(struct amdgpu_device *adev,
292 void *cpu_pt_addr, /* cpu addr of page table */
293 uint32_t gpu_page_idx, /* pte/pde to update */
294 uint64_t addr, /* addr to write into pte/pde */
295 uint32_t flags); /* access flags */
296};
297
298/* provided by the ih block */
299struct amdgpu_ih_funcs {
300 /* ring read/write ptr handling, called from interrupt context */
301 u32 (*get_wptr)(struct amdgpu_device *adev);
302 void (*decode_iv)(struct amdgpu_device *adev,
303 struct amdgpu_iv_entry *entry);
304 void (*set_rptr)(struct amdgpu_device *adev);
305};
306
97b2e202
AD		 307/*
308 * BIOS.
309 */
310bool amdgpu_get_bios(struct amdgpu_device *adev);
311bool amdgpu_read_bios(struct amdgpu_device *adev);
312
313/*
314 * Dummy page
315 */
316struct amdgpu_dummy_page {
317 struct page *page;
318 dma_addr_t addr;
319};
320int amdgpu_dummy_page_init(struct amdgpu_device *adev);
321void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
322
323
324/*
325 * Clocks
326 */
327
328#define AMDGPU_MAX_PPLL 3
329
330struct amdgpu_clock {
331 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
332 struct amdgpu_pll spll;
333 struct amdgpu_pll mpll;
334 /* 10 Khz units */
335 uint32_t default_mclk;
336 uint32_t default_sclk;
337 uint32_t default_dispclk;
338 uint32_t current_dispclk;
339 uint32_t dp_extclk;
340 uint32_t max_pixel_clock;
341};
342
97b2e202 343/*
c632d799 344 * BO.
97b2e202 345 */
97b2e202
AD		 346struct amdgpu_bo_list_entry {
347 struct amdgpu_bo *robj;
348 struct ttm_validate_buffer tv;
349 struct amdgpu_bo_va *bo_va;
97b2e202 350 uint32_t priority;
2f568dbd
CK		 351 struct page **user_pages;
352 int user_invalidated;
97b2e202
AD		 353};
354
355struct amdgpu_bo_va_mapping {
356 struct list_head list;
357 struct interval_tree_node it;
358 uint64_t offset;
359 uint32_t flags;
360};
361
362/* bo virtual addresses in a specific vm */
363struct amdgpu_bo_va {
364 /* protected by bo being reserved */
365 struct list_head bo_list;
f54d1867 366 struct dma_fence *last_pt_update;
97b2e202
AD		 367 unsigned ref_count;
368
7fc11959 369 /* protected by vm mutex and spinlock */
97b2e202
AD		 370 struct list_head vm_status;
371
7fc11959
CK		 372 /* mappings for this bo_va */
373 struct list_head invalids;
374 struct list_head valids;
375
97b2e202
AD		 376 /* constant after initialization */
377 struct amdgpu_vm *vm;
378 struct amdgpu_bo *bo;
379};
380
7e5a547f
CZ		 381#define AMDGPU_GEM_DOMAIN_MAX 0x3
382
97b2e202 383struct amdgpu_bo {
97b2e202 384 /* Protected by tbo.reserved */
1ea863fd
CK		 385 u32 prefered_domains;
386 u32 allowed_domains;
7e5a547f 387 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 388 struct ttm_placement placement;
389 struct ttm_buffer_object tbo;
390 struct ttm_bo_kmap_obj kmap;
391 u64 flags;
392 unsigned pin_count;
393 void *kptr;
394 u64 tiling_flags;
395 u64 metadata_flags;
396 void *metadata;
397 u32 metadata_size;
8e94a46c 398 unsigned prime_shared_count;
97b2e202
AD		 399 /* list of all virtual address to which this bo
400 * is associated to
401 */
402 struct list_head va;
403 /* Constant after initialization */
97b2e202 404 struct drm_gem_object gem_base;
82b9c55b 405 struct amdgpu_bo *parent;
e7893c4b 406 struct amdgpu_bo *shadow;
97b2e202
AD		 407
408 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 409 struct amdgpu_mn *mn;
410 struct list_head mn_list;
0c4e7fa5 411 struct list_head shadow_list;
97b2e202
AD		 412};
413#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
414
415void amdgpu_gem_object_free(struct drm_gem_object *obj);
416int amdgpu_gem_object_open(struct drm_gem_object *obj,
417 struct drm_file *file_priv);
418void amdgpu_gem_object_close(struct drm_gem_object *obj,
419 struct drm_file *file_priv);
420unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
421struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 422struct drm_gem_object *
423amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
424 struct dma_buf_attachment *attach,
425 struct sg_table *sg);
97b2e202
AD		 426struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
427 struct drm_gem_object *gobj,
428 int flags);
429int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
430void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
431struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
432void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
433void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
434int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
435
436/* sub-allocation manager, it has to be protected by another lock.
437 * By conception this is an helper for other part of the driver
438 * like the indirect buffer or semaphore, which both have their
439 * locking.
440 *
441 * Principe is simple, we keep a list of sub allocation in offset
442 * order (first entry has offset == 0, last entry has the highest
443 * offset).
444 *
445 * When allocating new object we first check if there is room at
446 * the end total_size - (last_object_offset + last_object_size) >=
447 * alloc_size. If so we allocate new object there.
448 *
449 * When there is not enough room at the end, we start waiting for
450 * each sub object until we reach object_offset+object_size >=
451 * alloc_size, this object then become the sub object we return.
452 *
453 * Alignment can't be bigger than page size.
454 *
455 * Hole are not considered for allocation to keep things simple.
456 * Assumption is that there won't be hole (all object on same
457 * alignment).
458 */
6ba60b89
CK		 459
460#define AMDGPU_SA_NUM_FENCE_LISTS 32
461
97b2e202
AD		 462struct amdgpu_sa_manager {
463 wait_queue_head_t wq;
464 struct amdgpu_bo *bo;
465 struct list_head *hole;
6ba60b89 466 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 467 struct list_head olist;
468 unsigned size;
469 uint64_t gpu_addr;
470 void *cpu_ptr;
471 uint32_t domain;
472 uint32_t align;
473};
474
97b2e202
AD		 475/* sub-allocation buffer */
476struct amdgpu_sa_bo {
477 struct list_head olist;
478 struct list_head flist;
479 struct amdgpu_sa_manager *manager;
480 unsigned soffset;
481 unsigned eoffset;
f54d1867 482 struct dma_fence *fence;
97b2e202
AD		 483};
484
485/*
486 * GEM objects.
487 */
418aa0c2 488void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 489int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
490 int alignment, u32 initial_domain,
491 u64 flags, bool kernel,
492 struct drm_gem_object **obj);
493
494int amdgpu_mode_dumb_create(struct drm_file *file_priv,
495 struct drm_device *dev,
496 struct drm_mode_create_dumb *args);
497int amdgpu_mode_dumb_mmap(struct drm_file *filp,
498 struct drm_device *dev,
499 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 500int amdgpu_fence_slab_init(void);
501void amdgpu_fence_slab_fini(void);
97b2e202
AD		 502
503/*
504 * GART structures, functions & helpers
505 */
506struct amdgpu_mc;
507
508#define AMDGPU_GPU_PAGE_SIZE 4096
509#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
510#define AMDGPU_GPU_PAGE_SHIFT 12
511#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
512
513struct amdgpu_gart {
514 dma_addr_t table_addr;
515 struct amdgpu_bo *robj;
516 void *ptr;
517 unsigned num_gpu_pages;
518 unsigned num_cpu_pages;
519 unsigned table_size;
a1d29476 520#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 521 struct page **pages;
a1d29476 522#endif
97b2e202
AD		 523 bool ready;
524 const struct amdgpu_gart_funcs *gart_funcs;
525};
526
527int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
528void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
529int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
530void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
531int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
532void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
533int amdgpu_gart_init(struct amdgpu_device *adev);
534void amdgpu_gart_fini(struct amdgpu_device *adev);
cab0b8d5 535void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 536 int pages);
cab0b8d5 537int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
97b2e202
AD		 538 int pages, struct page **pagelist,
539 dma_addr_t *dma_addr, uint32_t flags);
2c0d7318 540int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
97b2e202
AD		 541
542/*
543 * GPU MC structures, functions & helpers
544 */
545struct amdgpu_mc {
546 resource_size_t aper_size;
547 resource_size_t aper_base;
548 resource_size_t agp_base;
549 /* for some chips with <= 32MB we need to lie
550 * about vram size near mc fb location */
551 u64 mc_vram_size;
552 u64 visible_vram_size;
553 u64 gtt_size;
554 u64 gtt_start;
555 u64 gtt_end;
556 u64 vram_start;
557 u64 vram_end;
558 unsigned vram_width;
559 u64 real_vram_size;
560 int vram_mtrr;
561 u64 gtt_base_align;
562 u64 mc_mask;
563 const struct firmware *fw; /* MC firmware */
564 uint32_t fw_version;
565 struct amdgpu_irq_src vm_fault;
81c59f54 566 uint32_t vram_type;
50b0197a
CZ		 567 uint32_t srbm_soft_reset;
568 struct amdgpu_mode_mc_save save;
97b2e202
AD		 569};
570
571/*
572 * GPU doorbell structures, functions & helpers
573 */
574typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
575{
576 AMDGPU_DOORBELL_KIQ = 0x000,
577 AMDGPU_DOORBELL_HIQ = 0x001,
578 AMDGPU_DOORBELL_DIQ = 0x002,
579 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
580 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
581 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
582 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
583 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
584 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
585 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
586 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
587 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
588 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
589 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
590 AMDGPU_DOORBELL_IH = 0x1E8,
591 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
592 AMDGPU_DOORBELL_INVALID = 0xFFFF
593} AMDGPU_DOORBELL_ASSIGNMENT;
594
595struct amdgpu_doorbell {
596 /* doorbell mmio */
597 resource_size_t base;
598 resource_size_t size;
599 u32 __iomem *ptr;
600 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
601};
602
603void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
604 phys_addr_t *aperture_base,
605 size_t *aperture_size,
606 size_t *start_offset);
607
608/*
609 * IRQS.
610 */
611
612struct amdgpu_flip_work {
325cbba1 613 struct delayed_work flip_work;
97b2e202
AD		 614 struct work_struct unpin_work;
615 struct amdgpu_device *adev;
616 int crtc_id;
325cbba1 617 u32 target_vblank;
97b2e202
AD		 618 uint64_t base;
619 struct drm_pending_vblank_event *event;
765e7fbf 620 struct amdgpu_bo *old_abo;
f54d1867 621 struct dma_fence *excl;
1ffd2652 622 unsigned shared_count;
f54d1867
CW		 623 struct dma_fence **shared;
624 struct dma_fence_cb cb;
cb9e59d7 625 bool async;
97b2e202
AD		 626};
627
628
629/*
630 * CP & rings.
631 */
632
633struct amdgpu_ib {
634 struct amdgpu_sa_bo *sa_bo;
635 uint32_t length_dw;
636 uint64_t gpu_addr;
637 uint32_t *ptr;
de807f81 638 uint32_t flags;
97b2e202
AD		 639};
640
62250a91 641extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 642
50838c8c 643int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 644 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 645int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
646 struct amdgpu_job **job);
b6723c8d 647
a5fb4ec2 648void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 649void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 650int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 651 struct amd_sched_entity *entity, void *owner,
f54d1867 652 struct dma_fence **f);
8b4fb00b 653
97b2e202
AD		 654/*
655 * context related structures
656 */
657
21c16bf6 658struct amdgpu_ctx_ring {
91404fb2 659 uint64_t sequence;
f54d1867 660 struct dma_fence **fences;
91404fb2 661 struct amd_sched_entity entity;
21c16bf6
CK		 662};
663
97b2e202 664struct amdgpu_ctx {
0b492a4c 665 struct kref refcount;
9cb7e5a9 666 struct amdgpu_device *adev;
0b492a4c 667 unsigned reset_counter;
21c16bf6 668 spinlock_t ring_lock;
f54d1867 669 struct dma_fence **fences;
21c16bf6 670 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 671 bool preamble_presented;
97b2e202
AD		 672};
673
674struct amdgpu_ctx_mgr {
0b492a4c
AD		 675 struct amdgpu_device *adev;
676 struct mutex lock;
677 /* protected by lock */
678 struct idr ctx_handles;
97b2e202
AD		 679};
680
0b492a4c
AD		 681struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
682int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
683
21c16bf6 684uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
f54d1867
CW		 685 struct dma_fence *fence);
686struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6
CK		 687 struct amdgpu_ring *ring, uint64_t seq);
688
0b492a4c
AD		 689int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
690 struct drm_file *filp);
691
efd4ccb5
CK		 692void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
693void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 694
97b2e202
AD		 695/*
696 * file private structure
697 */
698
699struct amdgpu_fpriv {
700 struct amdgpu_vm vm;
701 struct mutex bo_list_lock;
702 struct idr bo_list_handles;
0b492a4c 703 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 704};
705
706/*
707 * residency list
708 */
709
710struct amdgpu_bo_list {
711 struct mutex lock;
712 struct amdgpu_bo *gds_obj;
713 struct amdgpu_bo *gws_obj;
714 struct amdgpu_bo *oa_obj;
211dff55 715 unsigned first_userptr;
97b2e202
AD		 716 unsigned num_entries;
717 struct amdgpu_bo_list_entry *array;
718};
719
720struct amdgpu_bo_list *
721amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 722void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
723 struct list_head *validated);
97b2e202
AD		 724void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
725void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
726
727/*
728 * GFX stuff
729 */
730#include "clearstate_defs.h"
731
79e5412c
AD		 732struct amdgpu_rlc_funcs {
733 void (*enter_safe_mode)(struct amdgpu_device *adev);
734 void (*exit_safe_mode)(struct amdgpu_device *adev);
735};
736
97b2e202
AD		 737struct amdgpu_rlc {
738 /* for power gating */
739 struct amdgpu_bo *save_restore_obj;
740 uint64_t save_restore_gpu_addr;
741 volatile uint32_t *sr_ptr;
742 const u32 *reg_list;
743 u32 reg_list_size;
744 /* for clear state */
745 struct amdgpu_bo *clear_state_obj;
746 uint64_t clear_state_gpu_addr;
747 volatile uint32_t *cs_ptr;
748 const struct cs_section_def *cs_data;
749 u32 clear_state_size;
750 /* for cp tables */
751 struct amdgpu_bo *cp_table_obj;
752 uint64_t cp_table_gpu_addr;
753 volatile uint32_t *cp_table_ptr;
754 u32 cp_table_size;
79e5412c
AD		 755
756 /* safe mode for updating CG/PG state */
757 bool in_safe_mode;
758 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 759
760 /* for firmware data */
761 u32 save_and_restore_offset;
762 u32 clear_state_descriptor_offset;
763 u32 avail_scratch_ram_locations;
764 u32 reg_restore_list_size;
765 u32 reg_list_format_start;
766 u32 reg_list_format_separate_start;
767 u32 starting_offsets_start;
768 u32 reg_list_format_size_bytes;
769 u32 reg_list_size_bytes;
770
771 u32 *register_list_format;
772 u32 *register_restore;
97b2e202
AD		 773};
774
775struct amdgpu_mec {
776 struct amdgpu_bo *hpd_eop_obj;
777 u64 hpd_eop_gpu_addr;
778 u32 num_pipe;
779 u32 num_mec;
780 u32 num_queue;
781};
782
4e638ae9
XY		 783struct amdgpu_kiq {
784 u64 eop_gpu_addr;
785 struct amdgpu_bo *eop_obj;
786 struct amdgpu_ring ring;
787 struct amdgpu_irq_src irq;
788};
789
97b2e202
AD		 790/*
791 * GPU scratch registers structures, functions & helpers
792 */
793struct amdgpu_scratch {
794 unsigned num_reg;
795 uint32_t reg_base;
796 bool free[32];
797 uint32_t reg[32];
798};
799
800/*
801 * GFX configurations
802 */
e3fa7630
AD		 803#define AMDGPU_GFX_MAX_SE 4
804#define AMDGPU_GFX_MAX_SH_PER_SE 2
805
806struct amdgpu_rb_config {
807 uint32_t rb_backend_disable;
808 uint32_t user_rb_backend_disable;
809 uint32_t raster_config;
810 uint32_t raster_config_1;
811};
812
97b2e202
AD		 813struct amdgpu_gca_config {
814 unsigned max_shader_engines;
815 unsigned max_tile_pipes;
816 unsigned max_cu_per_sh;
817 unsigned max_sh_per_se;
818 unsigned max_backends_per_se;
819 unsigned max_texture_channel_caches;
820 unsigned max_gprs;
821 unsigned max_gs_threads;
822 unsigned max_hw_contexts;
823 unsigned sc_prim_fifo_size_frontend;
824 unsigned sc_prim_fifo_size_backend;
825 unsigned sc_hiz_tile_fifo_size;
826 unsigned sc_earlyz_tile_fifo_size;
827
828 unsigned num_tile_pipes;
829 unsigned backend_enable_mask;
830 unsigned mem_max_burst_length_bytes;
831 unsigned mem_row_size_in_kb;
832 unsigned shader_engine_tile_size;
833 unsigned num_gpus;
834 unsigned multi_gpu_tile_size;
835 unsigned mc_arb_ramcfg;
836 unsigned gb_addr_config;
8f8e00c1 837 unsigned num_rbs;
97b2e202
AD		 838
839 uint32_t tile_mode_array[32];
840 uint32_t macrotile_mode_array[16];
e3fa7630
AD		 841
842 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
97b2e202
AD		 843};
844
7dae69a2
AD		 845struct amdgpu_cu_info {
846 uint32_t number; /* total active CU number */
847 uint32_t ao_cu_mask;
848 uint32_t bitmap[4][4];
849};
850
b95e31fd
AD		 851struct amdgpu_gfx_funcs {
852 /* get the gpu clock counter */
853 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 854 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 855 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 856 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
857 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 858};
859
97b2e202
AD		 860struct amdgpu_gfx {
861 struct mutex gpu_clock_mutex;
862 struct amdgpu_gca_config config;
863 struct amdgpu_rlc rlc;
864 struct amdgpu_mec mec;
4e638ae9 865 struct amdgpu_kiq kiq;
97b2e202
AD		 866 struct amdgpu_scratch scratch;
867 const struct firmware *me_fw; /* ME firmware */
868 uint32_t me_fw_version;
869 const struct firmware *pfp_fw; /* PFP firmware */
870 uint32_t pfp_fw_version;
871 const struct firmware *ce_fw; /* CE firmware */
872 uint32_t ce_fw_version;
873 const struct firmware *rlc_fw; /* RLC firmware */
874 uint32_t rlc_fw_version;
875 const struct firmware *mec_fw; /* MEC firmware */
876 uint32_t mec_fw_version;
877 const struct firmware *mec2_fw; /* MEC2 firmware */
878 uint32_t mec2_fw_version;
02558a00
KW		 879 uint32_t me_feature_version;
880 uint32_t ce_feature_version;
881 uint32_t pfp_feature_version;
351643d7
JZ		 882 uint32_t rlc_feature_version;
883 uint32_t mec_feature_version;
884 uint32_t mec2_feature_version;
97b2e202
AD		 885 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
886 unsigned num_gfx_rings;
887 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
888 unsigned num_compute_rings;
889 struct amdgpu_irq_src eop_irq;
890 struct amdgpu_irq_src priv_reg_irq;
891 struct amdgpu_irq_src priv_inst_irq;
892 /* gfx status */
7dae69a2 893 uint32_t gfx_current_status;
a101a899 894 /* ce ram size*/
7dae69a2
AD		 895 unsigned ce_ram_size;
896 struct amdgpu_cu_info cu_info;
b95e31fd 897 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 898
899 /* reset mask */
900 uint32_t grbm_soft_reset;
901 uint32_t srbm_soft_reset;
97b2e202
AD		 902};
903
b07c60c0 904int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 905 unsigned size, struct amdgpu_ib *ib);
4d9c514d 906void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 907 struct dma_fence *f);
b07c60c0 908int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
f54d1867
CW		 909 struct amdgpu_ib *ib, struct dma_fence *last_vm_update,
910 struct amdgpu_job *job, struct dma_fence **f);
97b2e202
AD		 911int amdgpu_ib_pool_init(struct amdgpu_device *adev);
912void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
913int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 914
915/*
916 * CS.
917 */
918struct amdgpu_cs_chunk {
919 uint32_t chunk_id;
920 uint32_t length_dw;
758ac17f 921 void *kdata;
97b2e202
AD		 922};
923
924struct amdgpu_cs_parser {
925 struct amdgpu_device *adev;
926 struct drm_file *filp;
3cb485f3 927 struct amdgpu_ctx *ctx;
c3cca41e 928
97b2e202
AD		 929 /* chunks */
930 unsigned nchunks;
931 struct amdgpu_cs_chunk *chunks;
97b2e202 932
50838c8c
CK		 933 /* scheduler job object */
934 struct amdgpu_job *job;
97b2e202 935
c3cca41e
CK		 936 /* buffer objects */
937 struct ww_acquire_ctx ticket;
938 struct amdgpu_bo_list *bo_list;
939 struct amdgpu_bo_list_entry vm_pd;
940 struct list_head validated;
f54d1867 941 struct dma_fence *fence;
c3cca41e
CK		 942 uint64_t bytes_moved_threshold;
943 uint64_t bytes_moved;
662bfa61 944 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 945
946 /* user fence */
91acbeb6 947 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 948};
949
753ad49c
ML		 950#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
951#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
952#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
953
bb977d37
CZ		 954struct amdgpu_job {
955 struct amd_sched_job base;
956 struct amdgpu_device *adev;
edf600da 957 struct amdgpu_vm *vm;
b07c60c0 958 struct amdgpu_ring *ring;
e86f9cee 959 struct amdgpu_sync sync;
bb977d37 960 struct amdgpu_ib *ibs;
f54d1867 961 struct dma_fence *fence; /* the hw fence */
753ad49c 962 uint32_t preamble_status;
bb977d37 963 uint32_t num_ibs;
e2840221 964 void *owner;
3aecd24c 965 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 966 bool vm_needs_flush;
d88bf583
CK		 967 unsigned vm_id;
968 uint64_t vm_pd_addr;
969 uint32_t gds_base, gds_size;
970 uint32_t gws_base, gws_size;
971 uint32_t oa_base, oa_size;
758ac17f
CK		 972
973 /* user fence handling */
b5f5acbc 974 uint64_t uf_addr;
758ac17f
CK		 975 uint64_t uf_sequence;
976
bb977d37 977};
a6db8a33
JZ		 978#define to_amdgpu_job(sched_job) \
979 container_of((sched_job), struct amdgpu_job, base)
bb977d37 980
7270f839
CK		 981static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
982 uint32_t ib_idx, int idx)
97b2e202 983{
50838c8c 984 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 985}
986
7270f839
CK		 987static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
988 uint32_t ib_idx, int idx,
989 uint32_t value)
990{
50838c8c 991 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 992}
993
97b2e202
AD		 994/*
995 * Writeback
996 */
997#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
998
999struct amdgpu_wb {
1000 struct amdgpu_bo *wb_obj;
1001 volatile uint32_t *wb;
1002 uint64_t gpu_addr;
1003 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1004 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1005};
1006
1007int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1008void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1009
d0dd7f0c
AD		 1010void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1011
97b2e202
AD		 1012/*
1013 * UVD
1014 */
c0365541
AN		 1015#define AMDGPU_DEFAULT_UVD_HANDLES 10
1016#define AMDGPU_MAX_UVD_HANDLES 40
1017#define AMDGPU_UVD_STACK_SIZE (200*1024)
1018#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1019#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1020#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1021
1022struct amdgpu_uvd {
1023 struct amdgpu_bo *vcpu_bo;
1024 void *cpu_addr;
1025 uint64_t gpu_addr;
562e2689 1026 unsigned fw_version;
3f99dd81 1027 void *saved_bo;
c0365541 1028 unsigned max_handles;
97b2e202
AD		 1029 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1030 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1031 struct delayed_work idle_work;
1032 const struct firmware *fw; /* UVD firmware */
1033 struct amdgpu_ring ring;
1034 struct amdgpu_irq_src irq;
1035 bool address_64_bit;
4cb5877c 1036 bool use_ctx_buf;
ead833ec 1037 struct amd_sched_entity entity;
fc0b3b90 1038 uint32_t srbm_soft_reset;
97b2e202
AD		 1039};
1040
1041/*
1042 * VCE
1043 */
1044#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1045#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1046
6a585777
AD		 1047#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1048#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1049
97b2e202
AD		 1050struct amdgpu_vce {
1051 struct amdgpu_bo *vcpu_bo;
1052 uint64_t gpu_addr;
1053 unsigned fw_version;
1054 unsigned fb_version;
1055 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1056 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1057 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202 1058 struct delayed_work idle_work;
ebff485e 1059 struct mutex idle_mutex;
97b2e202
AD		 1060 const struct firmware *fw; /* VCE firmware */
1061 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1062 struct amdgpu_irq_src irq;
6a585777 1063 unsigned harvest_config;
c594989c 1064 struct amd_sched_entity entity;
115933a5 1065 uint32_t srbm_soft_reset;
75c65480 1066 unsigned num_rings;
97b2e202
AD		 1067};
1068
1069/*
1070 * SDMA
1071 */
c113ea1c 1072struct amdgpu_sdma_instance {
97b2e202
AD		 1073 /* SDMA firmware */
1074 const struct firmware *fw;
1075 uint32_t fw_version;
cfa2104f 1076 uint32_t feature_version;
97b2e202
AD		 1077
1078 struct amdgpu_ring ring;
18111de0 1079 bool burst_nop;
97b2e202
AD		 1080};
1081
c113ea1c
AD		 1082struct amdgpu_sdma {
1083 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1084#ifdef CONFIG_DRM_AMDGPU_SI
1085 //SI DMA has a difference trap irq number for the second engine
1086 struct amdgpu_irq_src trap_irq_1;
1087#endif
c113ea1c
AD		 1088 struct amdgpu_irq_src trap_irq;
1089 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1090 int num_instances;
e702a680 1091 uint32_t srbm_soft_reset;
c113ea1c
AD		 1092};
1093
97b2e202
AD		 1094/*
1095 * Firmware
1096 */
1097struct amdgpu_firmware {
1098 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1099 bool smu_load;
1100 struct amdgpu_bo *fw_buf;
1101 unsigned int fw_size;
1102};
1103
1104/*
1105 * Benchmarking
1106 */
1107void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1108
1109
1110/*
1111 * Testing
1112 */
1113void amdgpu_test_moves(struct amdgpu_device *adev);
1114void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1115 struct amdgpu_ring *cpA,
1116 struct amdgpu_ring *cpB);
1117void amdgpu_test_syncing(struct amdgpu_device *adev);
1118
1119/*
1120 * MMU Notifier
1121 */
1122#if defined(CONFIG_MMU_NOTIFIER)
1123int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1124void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1125#else
1d1106b0 1126static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1127{
1128 return -ENODEV;
1129}
1d1106b0 1130static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1131#endif
1132
1133/*
1134 * Debugfs
1135 */
1136struct amdgpu_debugfs {
06ab6832 1137 const struct drm_info_list *files;
97b2e202
AD		 1138 unsigned num_files;
1139};
1140
1141int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1142 const struct drm_info_list *files,
97b2e202
AD		 1143 unsigned nfiles);
1144int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1145
1146#if defined(CONFIG_DEBUG_FS)
1147int amdgpu_debugfs_init(struct drm_minor *minor);
1148void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1149#endif
1150
50ab2533
HR		 1151int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1152
97b2e202
AD		 1153/*
1154 * amdgpu smumgr functions
1155 */
1156struct amdgpu_smumgr_funcs {
1157 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1158 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1159 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1160};
1161
1162/*
1163 * amdgpu smumgr
1164 */
1165struct amdgpu_smumgr {
1166 struct amdgpu_bo *toc_buf;
1167 struct amdgpu_bo *smu_buf;
1168 /* asic priv smu data */
1169 void *priv;
1170 spinlock_t smu_lock;
1171 /* smumgr functions */
1172 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1173 /* ucode loading complete flag */
1174 uint32_t fw_flags;
1175};
1176
1177/*
1178 * ASIC specific register table accessible by UMD
1179 */
1180struct amdgpu_allowed_register_entry {
1181 uint32_t reg_offset;
1182 bool untouched;
1183 bool grbm_indexed;
1184};
1185
97b2e202
AD		 1186/*
1187 * ASIC specific functions.
1188 */
1189struct amdgpu_asic_funcs {
1190 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1191 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1192 u8 *bios, u32 length_bytes);
97b2e202
AD		 1193 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1194 u32 sh_num, u32 reg_offset, u32 *value);
1195 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1196 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1197 /* get the reference clock */
1198 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1199 /* MM block clocks */
1200 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1201 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1202 /* static power management */
1203 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1204 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
97b2e202
AD		 1205};
1206
1207/*
1208 * IOCTL.
1209 */
1210int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1211 struct drm_file *filp);
1212int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1213 struct drm_file *filp);
1214
1215int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1216 struct drm_file *filp);
1217int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1218 struct drm_file *filp);
1219int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1220 struct drm_file *filp);
1221int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1222 struct drm_file *filp);
1223int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1224 struct drm_file *filp);
1225int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1226 struct drm_file *filp);
1227int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1228int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1229int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1230 struct drm_file *filp);
97b2e202
AD		 1231
1232int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1233 struct drm_file *filp);
1234
1235/* VRAM scratch page for HDP bug, default vram page */
1236struct amdgpu_vram_scratch {
1237 struct amdgpu_bo *robj;
1238 volatile uint32_t *ptr;
1239 u64 gpu_addr;
1240};
1241
1242/*
1243 * ACPI
1244 */
1245struct amdgpu_atif_notification_cfg {
1246 bool enabled;
1247 int command_code;
1248};
1249
1250struct amdgpu_atif_notifications {
1251 bool display_switch;
1252 bool expansion_mode_change;
1253 bool thermal_state;
1254 bool forced_power_state;
1255 bool system_power_state;
1256 bool display_conf_change;
1257 bool px_gfx_switch;
1258 bool brightness_change;
1259 bool dgpu_display_event;
1260};
1261
1262struct amdgpu_atif_functions {
1263 bool system_params;
1264 bool sbios_requests;
1265 bool select_active_disp;
1266 bool lid_state;
1267 bool get_tv_standard;
1268 bool set_tv_standard;
1269 bool get_panel_expansion_mode;
1270 bool set_panel_expansion_mode;
1271 bool temperature_change;
1272 bool graphics_device_types;
1273};
1274
1275struct amdgpu_atif {
1276 struct amdgpu_atif_notifications notifications;
1277 struct amdgpu_atif_functions functions;
1278 struct amdgpu_atif_notification_cfg notification_cfg;
1279 struct amdgpu_encoder *encoder_for_bl;
1280};
1281
1282struct amdgpu_atcs_functions {
1283 bool get_ext_state;
1284 bool pcie_perf_req;
1285 bool pcie_dev_rdy;
1286 bool pcie_bus_width;
1287};
1288
1289struct amdgpu_atcs {
1290 struct amdgpu_atcs_functions functions;
1291};
1292
d03846af
CZ		 1293/*
1294 * CGS
1295 */
110e6f26
DA		 1296struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1297void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1298
97b2e202
AD		 1299/*
1300 * Core structure, functions and helpers.
1301 */
1302typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1303typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1304
1305typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1306typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1307
1308struct amdgpu_device {
1309 struct device *dev;
1310 struct drm_device *ddev;
1311 struct pci_dev *pdev;
97b2e202 1312
a8fe58ce
MB		 1313#ifdef CONFIG_DRM_AMD_ACP
1314 struct amdgpu_acp acp;
1315#endif
1316
97b2e202 1317 /* ASIC */
2f7d10b3 1318 enum amd_asic_type asic_type;
97b2e202
AD		 1319 uint32_t family;
1320 uint32_t rev_id;
1321 uint32_t external_rev_id;
1322 unsigned long flags;
1323 int usec_timeout;
1324 const struct amdgpu_asic_funcs *asic_funcs;
1325 bool shutdown;
97b2e202
AD		 1326 bool need_dma32;
1327 bool accel_working;
edf600da 1328 struct work_struct reset_work;
97b2e202
AD		 1329 struct notifier_block acpi_nb;
1330 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1331 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1332 unsigned debugfs_count;
97b2e202 1333#if defined(CONFIG_DEBUG_FS)
adcec288 1334 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1335#endif
1336 struct amdgpu_atif atif;
1337 struct amdgpu_atcs atcs;
1338 struct mutex srbm_mutex;
1339 /* GRBM index mutex. Protects concurrent access to GRBM index */
1340 struct mutex grbm_idx_mutex;
1341 struct dev_pm_domain vga_pm_domain;
1342 bool have_disp_power_ref;
1343
1344 /* BIOS */
1345 uint8_t *bios;
a9f5db9c 1346 uint32_t bios_size;
97b2e202
AD		 1347 struct amdgpu_bo *stollen_vga_memory;
1348 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1349
1350 /* Register/doorbell mmio */
1351 resource_size_t rmmio_base;
1352 resource_size_t rmmio_size;
1353 void __iomem *rmmio;
1354 /* protects concurrent MM_INDEX/DATA based register access */
1355 spinlock_t mmio_idx_lock;
1356 /* protects concurrent SMC based register access */
1357 spinlock_t smc_idx_lock;
1358 amdgpu_rreg_t smc_rreg;
1359 amdgpu_wreg_t smc_wreg;
1360 /* protects concurrent PCIE register access */
1361 spinlock_t pcie_idx_lock;
1362 amdgpu_rreg_t pcie_rreg;
1363 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1364 amdgpu_rreg_t pciep_rreg;
1365 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1366 /* protects concurrent UVD register access */
1367 spinlock_t uvd_ctx_idx_lock;
1368 amdgpu_rreg_t uvd_ctx_rreg;
1369 amdgpu_wreg_t uvd_ctx_wreg;
1370 /* protects concurrent DIDT register access */
1371 spinlock_t didt_idx_lock;
1372 amdgpu_rreg_t didt_rreg;
1373 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1374 /* protects concurrent gc_cac register access */
1375 spinlock_t gc_cac_idx_lock;
1376 amdgpu_rreg_t gc_cac_rreg;
1377 amdgpu_wreg_t gc_cac_wreg;
97b2e202
AD		 1378 /* protects concurrent ENDPOINT (audio) register access */
1379 spinlock_t audio_endpt_idx_lock;
1380 amdgpu_block_rreg_t audio_endpt_rreg;
1381 amdgpu_block_wreg_t audio_endpt_wreg;
1382 void __iomem *rio_mem;
1383 resource_size_t rio_mem_size;
1384 struct amdgpu_doorbell doorbell;
1385
1386 /* clock/pll info */
1387 struct amdgpu_clock clock;
1388
1389 /* MC */
1390 struct amdgpu_mc mc;
1391 struct amdgpu_gart gart;
1392 struct amdgpu_dummy_page dummy_page;
1393 struct amdgpu_vm_manager vm_manager;
1394
1395 /* memory management */
1396 struct amdgpu_mman mman;
97b2e202
AD		 1397 struct amdgpu_vram_scratch vram_scratch;
1398 struct amdgpu_wb wb;
1399 atomic64_t vram_usage;
1400 atomic64_t vram_vis_usage;
1401 atomic64_t gtt_usage;
1402 atomic64_t num_bytes_moved;
dbd5ed60 1403 atomic64_t num_evictions;
d94aed5a 1404 atomic_t gpu_reset_counter;
97b2e202 1405
95844d20
MO		 1406 /* data for buffer migration throttling */
1407 struct {
1408 spinlock_t lock;
1409 s64 last_update_us;
1410 s64 accum_us; /* accumulated microseconds */
1411 u32 log2_max_MBps;
1412 } mm_stats;
1413
97b2e202 1414 /* display */
9accf2fd 1415 bool enable_virtual_display;
97b2e202
AD		 1416 struct amdgpu_mode_info mode_info;
1417 struct work_struct hotplug_work;
1418 struct amdgpu_irq_src crtc_irq;
1419 struct amdgpu_irq_src pageflip_irq;
1420 struct amdgpu_irq_src hpd_irq;
1421
1422 /* rings */
76bf0db5 1423 u64 fence_context;
97b2e202
AD		 1424 unsigned num_rings;
1425 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1426 bool ib_pool_ready;
1427 struct amdgpu_sa_manager ring_tmp_bo;
1428
1429 /* interrupts */
1430 struct amdgpu_irq irq;
1431
1f7371b2
AD		 1432 /* powerplay */
1433 struct amd_powerplay powerplay;
e61710c5 1434 bool pp_enabled;
f3898ea1 1435 bool pp_force_state_enabled;
1f7371b2 1436
97b2e202
AD		 1437 /* dpm */
1438 struct amdgpu_pm pm;
1439 u32 cg_flags;
1440 u32 pg_flags;
1441
1442 /* amdgpu smumgr */
1443 struct amdgpu_smumgr smu;
1444
1445 /* gfx */
1446 struct amdgpu_gfx gfx;
1447
1448 /* sdma */
c113ea1c 1449 struct amdgpu_sdma sdma;
97b2e202
AD		 1450
1451 /* uvd */
97b2e202
AD		 1452 struct amdgpu_uvd uvd;
1453
1454 /* vce */
1455 struct amdgpu_vce vce;
1456
1457 /* firmwares */
1458 struct amdgpu_firmware firmware;
1459
1460 /* GDS */
1461 struct amdgpu_gds gds;
1462
a1255107 1463 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1464 int num_ip_blocks;
97b2e202
AD		 1465 struct mutex mn_lock;
1466 DECLARE_HASHTABLE(mn_hash, 7);
1467
1468 /* tracking pinned memory */
1469 u64 vram_pin_size;
e131b914 1470 u64 invisible_pin_size;
97b2e202 1471 u64 gart_pin_size;
130e0371
OG		 1472
1473 /* amdkfd interface */
1474 struct kfd_dev *kfd;
23ca0e4e 1475
5a5099cb 1476 struct amdgpu_virt virt;
0c4e7fa5
CZ		 1477
1478 /* link all shadow bo */
1479 struct list_head shadow_list;
1480 struct mutex shadow_list_lock;
5c1354bd
CZ		 1481 /* link all gtt */
1482 spinlock_t gtt_list_lock;
1483 struct list_head gtt_list;
1484
97b2e202
AD		 1485};
1486
a7d64de6
CK		 1487static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1488{
1489 return container_of(bdev, struct amdgpu_device, mman.bdev);
1490}
1491
97b2e202
AD		 1492bool amdgpu_device_is_px(struct drm_device *dev);
1493int amdgpu_device_init(struct amdgpu_device *adev,
1494 struct drm_device *ddev,
1495 struct pci_dev *pdev,
1496 uint32_t flags);
1497void amdgpu_device_fini(struct amdgpu_device *adev);
1498int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1499
1500uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1501 bool always_indirect);
1502void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1503 bool always_indirect);
1504u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1505void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1506
1507u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1508void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1509
97b2e202
AD		 1510/*
1511 * Registers read & write functions.
1512 */
1513#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
1514#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
1515#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
1516#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
1517#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
1518#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1519#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1520#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1521#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1522#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1523#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1524#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1525#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1526#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1527#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1528#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1529#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1530#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1531#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1532#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1533#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1534#define WREG32_P(reg, val, mask) \
1535 do { \
1536 uint32_t tmp_ = RREG32(reg); \
1537 tmp_ &= (mask); \
1538 tmp_ |= ((val) & ~(mask)); \
1539 WREG32(reg, tmp_); \
1540 } while (0)
1541#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1542#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1543#define WREG32_PLL_P(reg, val, mask) \
1544 do { \
1545 uint32_t tmp_ = RREG32_PLL(reg); \
1546 tmp_ &= (mask); \
1547 tmp_ |= ((val) & ~(mask)); \
1548 WREG32_PLL(reg, tmp_); \
1549 } while (0)
1550#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1551#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1552#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1553
1554#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1555#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1556
1557#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1558#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1559
1560#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1561 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1562 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1563
1564#define REG_GET_FIELD(value, reg, field) \
1565 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1566
1567#define WREG32_FIELD(reg, field, val) \
1568 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202
AD		 1569
1570/*
1571 * BIOS helpers.
1572 */
1573#define RBIOS8(i) (adev->bios[i])
1574#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1575#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1576
1577/*
1578 * RING helpers.
1579 */
1580static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1581{
1582 if (ring->count_dw <= 0)
86c2b790 1583 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 1584 ring->ring[ring->wptr++] = v;
1585 ring->wptr &= ring->ptr_mask;
1586 ring->count_dw--;
97b2e202
AD		 1587}
1588
c113ea1c
AD		 1589static inline struct amdgpu_sdma_instance *
1590amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1591{
1592 struct amdgpu_device *adev = ring->adev;
1593 int i;
1594
c113ea1c
AD		 1595 for (i = 0; i < adev->sdma.num_instances; i++)
1596 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1597 break;
1598
1599 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1600 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1601 else
1602 return NULL;
1603}
1604
97b2e202
AD		 1605/*
1606 * ASICs macro.
1607 */
1608#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1609#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1610#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1611#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1612#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1613#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1614#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1615#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1616#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1617#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1618#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
97b2e202
AD		 1619#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1620#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1621#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1622#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1623#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 1624#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1625#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1626#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1627#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1628#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1629#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1630#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1631#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1632#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1633#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1634#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1635#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1636#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1637#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1638#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
9e5d5309 1639#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1640#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1641#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 1642#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1643#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1644#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1645#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1646#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1647#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1648#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1649#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1650#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1651#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1652#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1653#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1654#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1655#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1656#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1657#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1658#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1659#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 1660#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1661#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1662#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1663#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202
AD		 1664#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1665
1666/* Common functions */
1667int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1668bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202
AD		 1669void amdgpu_pci_config_reset(struct amdgpu_device *adev);
1670bool amdgpu_card_posted(struct amdgpu_device *adev);
1671void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1672
97b2e202
AD		 1673int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1674int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1675 u32 ip_instance, u32 ring,
1676 struct amdgpu_ring **out_ring);
765e7fbf 1677void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1678bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 1679int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 1680int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1681 uint32_t flags);
1682bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 1683struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 1684bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1685 unsigned long end);
2f568dbd
CK		 1686bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1687 int *last_invalidated);
97b2e202
AD		 1688bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
1689uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1690 struct ttm_mem_reg *mem);
1691void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1692void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1693void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1694int amdgpu_ttm_init(struct amdgpu_device *adev);
1695void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1696void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1697 const u32 *registers,
1698 const u32 array_size);
1699
1700bool amdgpu_device_is_px(struct drm_device *dev);
1701/* atpx handler */
1702#if defined(CONFIG_VGA_SWITCHEROO)
1703void amdgpu_register_atpx_handler(void);
1704void amdgpu_unregister_atpx_handler(void);
a78fe133 1705bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1706bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1707bool amdgpu_atpx_dgpu_req_power_for_displays(void);
97b2e202
AD		 1708#else
1709static inline void amdgpu_register_atpx_handler(void) {}
1710static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1711static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1712static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1713static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
97b2e202
AD		 1714#endif
1715
1716/*
1717 * KMS
1718 */
1719extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1720extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1721
1722int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1723void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1724void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1725int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1726void amdgpu_driver_postclose_kms(struct drm_device *dev,
1727 struct drm_file *file_priv);
1728void amdgpu_driver_preclose_kms(struct drm_device *dev,
1729 struct drm_file *file_priv);
faefba95 1730int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1731int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1732int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1733u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1734int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1735void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1736int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 1737 int *max_error,
1738 struct timeval *vblank_time,
1739 unsigned flags);
1740long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1741 unsigned long arg);
1742
97b2e202
AD		 1743/*
1744 * functions used by amdgpu_encoder.c
1745 */
1746struct amdgpu_afmt_acr {
1747 u32 clock;
1748
1749 int n_32khz;
1750 int cts_32khz;
1751
1752 int n_44_1khz;
1753 int cts_44_1khz;
1754
1755 int n_48khz;
1756 int cts_48khz;
1757
1758};
1759
1760struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1761
1762/* amdgpu_acpi.c */
1763#if defined(CONFIG_ACPI)
1764int amdgpu_acpi_init(struct amdgpu_device *adev);
1765void amdgpu_acpi_fini(struct amdgpu_device *adev);
1766bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1767int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1768 u8 perf_req, bool advertise);
1769int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1770#else
1771static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1772static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1773#endif
1774
1775struct amdgpu_bo_va_mapping *
1776amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1777 uint64_t addr, struct amdgpu_bo **bo);
c855e250 1778int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
97b2e202
AD		 1779
1780#include "amdgpu_object.h"
97b2e202 1781#endif
Linux 6.x block layer and io_uring tree(s)