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drm/amdgpu: Enable XGMI mapping for peer device
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
8290268f
CK		 31#include "amdgpu_ctx.h"
32
97b2e202
AD		 33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
a9f87f64 37#include <linux/rbtree.h>
97b2e202 38#include <linux/hashtable.h>
f54d1867 39#include <linux/dma-fence.h>
97b2e202 40
248a1d6f
MY		 41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 46
d03846af 47#include <drm/drmP.h>
97b2e202 48#include <drm/drm_gem.h>
7e5a547f 49#include <drm/amdgpu_drm.h>
1b1f42d8 50#include <drm/gpu_scheduler.h>
97b2e202 51
78c16834 52#include <kgd_kfd_interface.h>
c79563a3
RZ		 53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
78c16834 55
5fc3aeeb 56#include "amd_shared.h"
97b2e202
AD		 57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
c632d799 61#include "amdgpu_ttm.h"
0e5ca0d1 62#include "amdgpu_psp.h"
97b2e202 63#include "amdgpu_gds.h"
56113504 64#include "amdgpu_sync.h"
78023016 65#include "amdgpu_ring.h"
073440d2 66#include "amdgpu_vm.h"
cf097881 67#include "amdgpu_dpm.h"
a8fe58ce 68#include "amdgpu_acp.h"
4df654d2 69#include "amdgpu_uvd.h"
5e568178 70#include "amdgpu_vce.h"
95aa13f6 71#include "amdgpu_vcn.h"
9a189996 72#include "amdgpu_mn.h"
770d13b1 73#include "amdgpu_gmc.h"
448fe192 74#include "amdgpu_gfx.h"
bb7743bc 75#include "amdgpu_sdma.h"
4562236b 76#include "amdgpu_dm.h"
ceeb50ed 77#include "amdgpu_virt.h"
7946340f 78#include "amdgpu_csa.h"
3490bdb5 79#include "amdgpu_gart.h"
75758255 80#include "amdgpu_debugfs.h"
050d9d43 81#include "amdgpu_job.h"
4a8c21a1 82#include "amdgpu_bo_list.h"
2cddc50e 83#include "amdgpu_gem.h"
cde577bd 84#include "amdgpu_doorbell.h"
611736d8 85#include "amdgpu_amdkfd.h"
137d63ab 86#include "amdgpu_smu.h"
c79563a3 87
62d73fbc
EQ		 88#define MAX_GPU_INSTANCE 16
89
90struct amdgpu_gpu_instance
91{
92 struct amdgpu_device *adev;
93 int mgpu_fan_enabled;
94};
95
96struct amdgpu_mgpu_info
97{
98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
99 struct mutex mutex;
100 uint32_t num_gpu;
101 uint32_t num_dgpu;
102 uint32_t num_apu;
103};
104
97b2e202
AD		 105/*
106 * Modules parameters.
107 */
108extern int amdgpu_modeset;
109extern int amdgpu_vram_limit;
218b5dcd 110extern int amdgpu_vis_vram_limit;
83e74db6 111extern int amdgpu_gart_size;
36d38372 112extern int amdgpu_gtt_size;
95844d20 113extern int amdgpu_moverate;
97b2e202
AD		 114extern int amdgpu_benchmarking;
115extern int amdgpu_testing;
116extern int amdgpu_audio;
117extern int amdgpu_disp_priority;
118extern int amdgpu_hw_i2c;
119extern int amdgpu_pcie_gen2;
120extern int amdgpu_msi;
121extern int amdgpu_lockup_timeout;
122extern int amdgpu_dpm;
e635ee07 123extern int amdgpu_fw_load_type;
97b2e202
AD		 124extern int amdgpu_aspm;
125extern int amdgpu_runtime_pm;
0b693f0b 126extern uint amdgpu_ip_block_mask;
97b2e202
AD		 127extern int amdgpu_bapm;
128extern int amdgpu_deep_color;
129extern int amdgpu_vm_size;
130extern int amdgpu_vm_block_size;
d07f14be 131extern int amdgpu_vm_fragment_size;
d9c13156 132extern int amdgpu_vm_fault_stop;
b495bd3a 133extern int amdgpu_vm_debug;
9a4b7d4c 134extern int amdgpu_vm_update_mode;
4562236b 135extern int amdgpu_dc;
1333f723 136extern int amdgpu_sched_jobs;
4afcb303 137extern int amdgpu_sched_hw_submission;
0b693f0b
RZ		 138extern uint amdgpu_pcie_gen_cap;
139extern uint amdgpu_pcie_lane_cap;
140extern uint amdgpu_cg_mask;
141extern uint amdgpu_pg_mask;
142extern uint amdgpu_sdma_phase_quantum;
6f8941a2 143extern char *amdgpu_disable_cu;
9accf2fd 144extern char *amdgpu_virtual_display;
0b693f0b 145extern uint amdgpu_pp_feature_mask;
6a7f76e7 146extern int amdgpu_vram_page_split;
bce23e00
AD		 147extern int amdgpu_ngg;
148extern int amdgpu_prim_buf_per_se;
149extern int amdgpu_pos_buf_per_se;
150extern int amdgpu_cntl_sb_buf_per_se;
151extern int amdgpu_param_buf_per_se;
65781c78 152extern int amdgpu_job_hang_limit;
e8835e0e 153extern int amdgpu_lbpw;
4a75aefe 154extern int amdgpu_compute_multipipe;
dcebf026 155extern int amdgpu_gpu_recovery;
bfca0289 156extern int amdgpu_emu_mode;
7951e376 157extern uint amdgpu_smu_memory_pool_size;
7875a226 158extern uint amdgpu_dc_feature_mask;
62d73fbc 159extern struct amdgpu_mgpu_info mgpu_info;
97b2e202 160
6dd13096
FK		 161#ifdef CONFIG_DRM_AMDGPU_SI
162extern int amdgpu_si_support;
163#endif
7df28986
FK		 164#ifdef CONFIG_DRM_AMDGPU_CIK
165extern int amdgpu_cik_support;
166#endif
97b2e202 167
08d1bdd4 168#define AMDGPU_VM_MAX_NUM_CTX 4096
6c8d74ca 169#define AMDGPU_SG_THRESHOLD (256*1024*1024)
55ed8caf 170#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 171#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202 172#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
8c5e13ec 173#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
97b2e202
AD		 174/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
175#define AMDGPU_IB_POOL_SIZE 16
176#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
177#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 178#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 179
97b2e202
AD		 180/* hard reset data */
181#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
182
183/* reset flags */
184#define AMDGPU_RESET_GFX (1 << 0)
185#define AMDGPU_RESET_COMPUTE (1 << 1)
186#define AMDGPU_RESET_DMA (1 << 2)
187#define AMDGPU_RESET_CP (1 << 3)
188#define AMDGPU_RESET_GRBM (1 << 4)
189#define AMDGPU_RESET_DMA1 (1 << 5)
190#define AMDGPU_RESET_RLC (1 << 6)
191#define AMDGPU_RESET_SEM (1 << 7)
192#define AMDGPU_RESET_IH (1 << 8)
193#define AMDGPU_RESET_VMC (1 << 9)
194#define AMDGPU_RESET_MC (1 << 10)
195#define AMDGPU_RESET_DISPLAY (1 << 11)
196#define AMDGPU_RESET_UVD (1 << 12)
197#define AMDGPU_RESET_VCE (1 << 13)
198#define AMDGPU_RESET_VCE1 (1 << 14)
199
97b2e202
AD		 200/* max cursor sizes (in pixels) */
201#define CIK_CURSOR_WIDTH 128
202#define CIK_CURSOR_HEIGHT 128
203
204struct amdgpu_device;
97b2e202 205struct amdgpu_ib;
97b2e202 206struct amdgpu_cs_parser;
bb977d37 207struct amdgpu_job;
97b2e202 208struct amdgpu_irq_src;
0b492a4c 209struct amdgpu_fpriv;
9cca0b8e 210struct amdgpu_bo_va_mapping;
102c16a0 211struct amdgpu_atif;
97b2e202
AD		 212
213enum amdgpu_cp_irq {
214 AMDGPU_CP_IRQ_GFX_EOP = 0,
215 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
216 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
218 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
219 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
220 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
222 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
223
224 AMDGPU_CP_IRQ_LAST
225};
226
97b2e202
AD		 227enum amdgpu_thermal_irq {
228 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
229 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
230
231 AMDGPU_THERMAL_IRQ_LAST
232};
233
4e638ae9
XY		 234enum amdgpu_kiq_irq {
235 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
236 AMDGPU_CP_KIQ_IRQ_LAST
237};
238
3890d111
ED		 239#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
240#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
4944af67 241#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
3890d111 242
43fa561f 243int amdgpu_device_ip_set_clockgating_state(void *dev,
2990a1fc
AD		 244 enum amd_ip_block_type block_type,
245 enum amd_clockgating_state state);
43fa561f 246int amdgpu_device_ip_set_powergating_state(void *dev,
2990a1fc
AD		 247 enum amd_ip_block_type block_type,
248 enum amd_powergating_state state);
249void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
250 u32 *flags);
251int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
252 enum amd_ip_block_type block_type);
253bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
254 enum amd_ip_block_type block_type);
97b2e202 255
a1255107
AD		 256#define AMDGPU_MAX_IP_NUM 16
257
258struct amdgpu_ip_block_status {
259 bool valid;
260 bool sw;
261 bool hw;
262 bool late_initialized;
263 bool hang;
264};
265
97b2e202 266struct amdgpu_ip_block_version {
a1255107
AD		 267 const enum amd_ip_block_type type;
268 const u32 major;
269 const u32 minor;
270 const u32 rev;
5fc3aeeb 271 const struct amd_ip_funcs *funcs;
97b2e202
AD		 272};
273
a1255107
AD		 274struct amdgpu_ip_block {
275 struct amdgpu_ip_block_status status;
276 const struct amdgpu_ip_block_version *version;
277};
278
2990a1fc
AD		 279int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
280 enum amd_ip_block_type type,
281 u32 major, u32 minor);
97b2e202 282
2990a1fc
AD		 283struct amdgpu_ip_block *
284amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
285 enum amd_ip_block_type type);
a1255107 286
2990a1fc
AD		 287int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
288 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202 289
97b2e202
AD		 290/*
291 * BIOS.
292 */
293bool amdgpu_get_bios(struct amdgpu_device *adev);
294bool amdgpu_read_bios(struct amdgpu_device *adev);
295
97b2e202
AD		 296/*
297 * Clocks
298 */
299
300#define AMDGPU_MAX_PPLL 3
301
302struct amdgpu_clock {
303 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
304 struct amdgpu_pll spll;
305 struct amdgpu_pll mpll;
306 /* 10 Khz units */
307 uint32_t default_mclk;
308 uint32_t default_sclk;
309 uint32_t default_dispclk;
310 uint32_t current_dispclk;
311 uint32_t dp_extclk;
312 uint32_t max_pixel_clock;
313};
314
97b2e202
AD		 315/* sub-allocation manager, it has to be protected by another lock.
316 * By conception this is an helper for other part of the driver
317 * like the indirect buffer or semaphore, which both have their
318 * locking.
319 *
320 * Principe is simple, we keep a list of sub allocation in offset
321 * order (first entry has offset == 0, last entry has the highest
322 * offset).
323 *
324 * When allocating new object we first check if there is room at
325 * the end total_size - (last_object_offset + last_object_size) >=
326 * alloc_size. If so we allocate new object there.
327 *
328 * When there is not enough room at the end, we start waiting for
329 * each sub object until we reach object_offset+object_size >=
330 * alloc_size, this object then become the sub object we return.
331 *
332 * Alignment can't be bigger than page size.
333 *
334 * Hole are not considered for allocation to keep things simple.
335 * Assumption is that there won't be hole (all object on same
336 * alignment).
337 */
6ba60b89
CK		 338
339#define AMDGPU_SA_NUM_FENCE_LISTS 32
340
97b2e202
AD		 341struct amdgpu_sa_manager {
342 wait_queue_head_t wq;
343 struct amdgpu_bo *bo;
344 struct list_head *hole;
6ba60b89 345 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 346 struct list_head olist;
347 unsigned size;
348 uint64_t gpu_addr;
349 void *cpu_ptr;
350 uint32_t domain;
351 uint32_t align;
352};
353
97b2e202
AD		 354/* sub-allocation buffer */
355struct amdgpu_sa_bo {
356 struct list_head olist;
357 struct list_head flist;
358 struct amdgpu_sa_manager *manager;
359 unsigned soffset;
360 unsigned eoffset;
f54d1867 361 struct dma_fence *fence;
97b2e202
AD		 362};
363
d573de2d
RZ		 364int amdgpu_fence_slab_init(void);
365void amdgpu_fence_slab_fini(void);
97b2e202 366
97b2e202
AD		 367/*
368 * IRQS.
369 */
370
371struct amdgpu_flip_work {
325cbba1 372 struct delayed_work flip_work;
97b2e202
AD		 373 struct work_struct unpin_work;
374 struct amdgpu_device *adev;
375 int crtc_id;
325cbba1 376 u32 target_vblank;
97b2e202
AD		 377 uint64_t base;
378 struct drm_pending_vblank_event *event;
765e7fbf 379 struct amdgpu_bo *old_abo;
f54d1867 380 struct dma_fence *excl;
1ffd2652 381 unsigned shared_count;
f54d1867
CW		 382 struct dma_fence **shared;
383 struct dma_fence_cb cb;
cb9e59d7 384 bool async;
97b2e202
AD		 385};
386
387
388/*
389 * CP & rings.
390 */
391
392struct amdgpu_ib {
393 struct amdgpu_sa_bo *sa_bo;
394 uint32_t length_dw;
395 uint64_t gpu_addr;
396 uint32_t *ptr;
de807f81 397 uint32_t flags;
97b2e202
AD		 398};
399
1b1f42d8 400extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 401
97b2e202
AD		 402/*
403 * file private structure
404 */
405
406struct amdgpu_fpriv {
407 struct amdgpu_vm vm;
b85891bd 408 struct amdgpu_bo_va *prt_va;
0f4b3c68 409 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 410 struct mutex bo_list_lock;
411 struct idr bo_list_handles;
0b492a4c 412 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 413};
414
021830d2
BN		 415int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
416
b07c60c0 417int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 418 unsigned size, struct amdgpu_ib *ib);
4d9c514d 419void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 420 struct dma_fence *f);
b07c60c0 421int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 422 struct amdgpu_ib *ibs, struct amdgpu_job *job,
423 struct dma_fence **f);
97b2e202
AD		 424int amdgpu_ib_pool_init(struct amdgpu_device *adev);
425void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
426int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 427
428/*
429 * CS.
430 */
431struct amdgpu_cs_chunk {
432 uint32_t chunk_id;
433 uint32_t length_dw;
758ac17f 434 void *kdata;
97b2e202
AD		 435};
436
437struct amdgpu_cs_parser {
438 struct amdgpu_device *adev;
439 struct drm_file *filp;
3cb485f3 440 struct amdgpu_ctx *ctx;
c3cca41e 441
97b2e202
AD		 442 /* chunks */
443 unsigned nchunks;
444 struct amdgpu_cs_chunk *chunks;
97b2e202 445
50838c8c
CK		 446 /* scheduler job object */
447 struct amdgpu_job *job;
0d346a14 448 struct drm_sched_entity *entity;
97b2e202 449
c3cca41e
CK		 450 /* buffer objects */
451 struct ww_acquire_ctx ticket;
452 struct amdgpu_bo_list *bo_list;
3fe89771 453 struct amdgpu_mn *mn;
c3cca41e
CK		 454 struct amdgpu_bo_list_entry vm_pd;
455 struct list_head validated;
f54d1867 456 struct dma_fence *fence;
c3cca41e 457 uint64_t bytes_moved_threshold;
00f06b24 458 uint64_t bytes_moved_vis_threshold;
c3cca41e 459 uint64_t bytes_moved;
00f06b24 460 uint64_t bytes_moved_vis;
662bfa61 461 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 462
463 /* user fence */
91acbeb6 464 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 465
466 unsigned num_post_dep_syncobjs;
467 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 468};
469
7270f839
CK		 470static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
471 uint32_t ib_idx, int idx)
97b2e202 472{
50838c8c 473 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 474}
475
7270f839
CK		 476static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
477 uint32_t ib_idx, int idx,
478 uint32_t value)
479{
50838c8c 480 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 481}
482
97b2e202
AD		 483/*
484 * Writeback
485 */
73469585 486#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
97b2e202
AD		 487
488struct amdgpu_wb {
489 struct amdgpu_bo *wb_obj;
490 volatile uint32_t *wb;
491 uint64_t gpu_addr;
492 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
493 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
494};
495
131b4b36
AD		 496int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
497void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 498
97b2e202
AD		 499/*
500 * Benchmarking
501 */
502void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
503
504
505/*
506 * Testing
507 */
508void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 509
97b2e202
AD		 510/*
511 * ASIC specific register table accessible by UMD
512 */
513struct amdgpu_allowed_register_entry {
514 uint32_t reg_offset;
97b2e202
AD		 515 bool grbm_indexed;
516};
517
97b2e202
AD		 518/*
519 * ASIC specific functions.
520 */
521struct amdgpu_asic_funcs {
522 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 523 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
524 u8 *bios, u32 length_bytes);
97b2e202
AD		 525 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
526 u32 sh_num, u32 reg_offset, u32 *value);
527 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
528 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 529 /* get the reference clock */
530 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 531 /* MM block clocks */
532 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
533 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 534 /* static power management */
535 int (*get_pcie_lanes)(struct amdgpu_device *adev);
536 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 537 /* get config memsize register */
538 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6 539 /* flush hdp write queue */
69882565 540 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
2df1b8b6 541 /* invalidate hdp read cache */
69882565
CK		 542 void (*invalidate_hdp)(struct amdgpu_device *adev,
543 struct amdgpu_ring *ring);
69070690
AD		 544 /* check if the asic needs a full reset of if soft reset will work */
545 bool (*need_full_reset)(struct amdgpu_device *adev);
5253163a
OZ		 546 /* initialize doorbell layout for specific asic*/
547 void (*init_doorbell_index)(struct amdgpu_device *adev);
b45e18ac
KR		 548 /* PCIe bandwidth usage */
549 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
550 uint64_t *count1);
44401889
AD		 551 /* do we need to reset the asic at init time (e.g., kexec) */
552 bool (*need_reset_on_init)(struct amdgpu_device *adev);
97b2e202
AD		 553};
554
555/*
556 * IOCTL.
557 */
97b2e202
AD		 558int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
559 struct drm_file *filp);
560
97b2e202 561int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 562int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
563 struct drm_file *filp);
97b2e202 564int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 565int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
566 struct drm_file *filp);
97b2e202 567
97b2e202
AD		 568/* VRAM scratch page for HDP bug, default vram page */
569struct amdgpu_vram_scratch {
570 struct amdgpu_bo *robj;
571 volatile uint32_t *ptr;
572 u64 gpu_addr;
573};
574
575/*
576 * ACPI
577 */
97b2e202
AD		 578struct amdgpu_atcs_functions {
579 bool get_ext_state;
580 bool pcie_perf_req;
581 bool pcie_dev_rdy;
582 bool pcie_bus_width;
583};
584
585struct amdgpu_atcs {
586 struct amdgpu_atcs_functions functions;
587};
588
a05502e5
HC		 589/*
590 * Firmware VRAM reservation
591 */
592struct amdgpu_fw_vram_usage {
593 u64 start_offset;
594 u64 size;
595 struct amdgpu_bo *reserved_bo;
596 void *va;
597};
598
d03846af
CZ		 599/*
600 * CGS
601 */
110e6f26
DA		 602struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
603void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 604
97b2e202
AD		 605/*
606 * Core structure, functions and helpers.
607 */
608typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
609typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
610
611typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
612typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
613
946a4d5b
SL		 614
615/*
616 * amdgpu nbio functions
617 *
946a4d5b 618 */
bf383fb6
AD		 619struct nbio_hdp_flush_reg {
620 u32 ref_and_mask_cp0;
621 u32 ref_and_mask_cp1;
622 u32 ref_and_mask_cp2;
623 u32 ref_and_mask_cp3;
624 u32 ref_and_mask_cp4;
625 u32 ref_and_mask_cp5;
626 u32 ref_and_mask_cp6;
627 u32 ref_and_mask_cp7;
628 u32 ref_and_mask_cp8;
629 u32 ref_and_mask_cp9;
630 u32 ref_and_mask_sdma0;
631 u32 ref_and_mask_sdma1;
632};
946a4d5b
SL		 633
634struct amdgpu_nbio_funcs {
bf383fb6
AD		 635 const struct nbio_hdp_flush_reg *hdp_flush_reg;
636 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
637 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
638 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
639 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
640 u32 (*get_rev_id)(struct amdgpu_device *adev);
bf383fb6 641 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
69882565 642 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
bf383fb6
AD		 643 u32 (*get_memsize)(struct amdgpu_device *adev);
644 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
8987e2e2 645 bool use_doorbell, int doorbell_index, int doorbell_size);
bf383fb6
AD		 646 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
647 bool enable);
648 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
649 bool enable);
650 void (*ih_doorbell_range)(struct amdgpu_device *adev,
651 bool use_doorbell, int doorbell_index);
652 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
653 bool enable);
654 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
655 bool enable);
656 void (*get_clockgating_state)(struct amdgpu_device *adev,
657 u32 *flags);
658 void (*ih_control)(struct amdgpu_device *adev);
659 void (*init_registers)(struct amdgpu_device *adev);
660 void (*detect_hw_virt)(struct amdgpu_device *adev);
946a4d5b
SL		 661};
662
634c96e3
HZ		 663struct amdgpu_df_funcs {
664 void (*init)(struct amdgpu_device *adev);
665 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
666 bool enable);
667 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
668 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
669 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
670 bool enable);
671 void (*get_clockgating_state)(struct amdgpu_device *adev,
672 u32 *flags);
8f9b2e50
AD		 673 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
674 bool enable);
634c96e3 675};
4522824c
SL		 676/* Define the HW IP blocks will be used in driver , add more if necessary */
677enum amd_hw_ip_block_type {
678 GC_HWIP = 1,
679 HDP_HWIP,
680 SDMA0_HWIP,
681 SDMA1_HWIP,
682 MMHUB_HWIP,
683 ATHUB_HWIP,
684 NBIO_HWIP,
685 MP0_HWIP,
e6636ae1 686 MP1_HWIP,
4522824c
SL		 687 UVD_HWIP,
688 VCN_HWIP = UVD_HWIP,
689 VCE_HWIP,
690 DF_HWIP,
691 DCE_HWIP,
692 OSSSYS_HWIP,
693 SMUIO_HWIP,
694 PWR_HWIP,
695 NBIF_HWIP,
e6636ae1 696 THM_HWIP,
73b19174 697 CLK_HWIP,
4522824c
SL		 698 MAX_HWIP
699};
700
701#define HWIP_MAX_INSTANCE 6
702
11dc9364 703struct amd_powerplay {
11dc9364 704 void *pp_handle;
11dc9364
RZ		 705 const struct amd_pm_funcs *pp_funcs;
706};
707
0c49e0b8 708#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 709struct amdgpu_device {
710 struct device *dev;
711 struct drm_device *ddev;
712 struct pci_dev *pdev;
97b2e202 713
a8fe58ce
MB		 714#ifdef CONFIG_DRM_AMD_ACP
715 struct amdgpu_acp acp;
716#endif
717
97b2e202 718 /* ASIC */
2f7d10b3 719 enum amd_asic_type asic_type;
97b2e202
AD		 720 uint32_t family;
721 uint32_t rev_id;
722 uint32_t external_rev_id;
723 unsigned long flags;
724 int usec_timeout;
725 const struct amdgpu_asic_funcs *asic_funcs;
726 bool shutdown;
97b2e202 727 bool need_dma32;
fd5fd480 728 bool need_swiotlb;
97b2e202 729 bool accel_working;
97b2e202
AD		 730 struct notifier_block acpi_nb;
731 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
732 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 733 unsigned debugfs_count;
97b2e202 734#if defined(CONFIG_DEBUG_FS)
adcec288 735 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202 736#endif
102c16a0 737 struct amdgpu_atif *atif;
97b2e202
AD		 738 struct amdgpu_atcs atcs;
739 struct mutex srbm_mutex;
740 /* GRBM index mutex. Protects concurrent access to GRBM index */
741 struct mutex grbm_idx_mutex;
742 struct dev_pm_domain vga_pm_domain;
743 bool have_disp_power_ref;
744
745 /* BIOS */
0cdd5005 746 bool is_atom_fw;
97b2e202 747 uint8_t *bios;
a9f5db9c 748 uint32_t bios_size;
5af2c10d 749 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 750 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 751 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
752
753 /* Register/doorbell mmio */
754 resource_size_t rmmio_base;
755 resource_size_t rmmio_size;
756 void __iomem *rmmio;
757 /* protects concurrent MM_INDEX/DATA based register access */
758 spinlock_t mmio_idx_lock;
759 /* protects concurrent SMC based register access */
760 spinlock_t smc_idx_lock;
761 amdgpu_rreg_t smc_rreg;
762 amdgpu_wreg_t smc_wreg;
763 /* protects concurrent PCIE register access */
764 spinlock_t pcie_idx_lock;
765 amdgpu_rreg_t pcie_rreg;
766 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 767 amdgpu_rreg_t pciep_rreg;
768 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 769 /* protects concurrent UVD register access */
770 spinlock_t uvd_ctx_idx_lock;
771 amdgpu_rreg_t uvd_ctx_rreg;
772 amdgpu_wreg_t uvd_ctx_wreg;
773 /* protects concurrent DIDT register access */
774 spinlock_t didt_idx_lock;
775 amdgpu_rreg_t didt_rreg;
776 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 777 /* protects concurrent gc_cac register access */
778 spinlock_t gc_cac_idx_lock;
779 amdgpu_rreg_t gc_cac_rreg;
780 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 781 /* protects concurrent se_cac register access */
782 spinlock_t se_cac_idx_lock;
783 amdgpu_rreg_t se_cac_rreg;
784 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 785 /* protects concurrent ENDPOINT (audio) register access */
786 spinlock_t audio_endpt_idx_lock;
787 amdgpu_block_rreg_t audio_endpt_rreg;
788 amdgpu_block_wreg_t audio_endpt_wreg;
789 void __iomem *rio_mem;
790 resource_size_t rio_mem_size;
791 struct amdgpu_doorbell doorbell;
792
793 /* clock/pll info */
794 struct amdgpu_clock clock;
795
796 /* MC */
770d13b1 797 struct amdgpu_gmc gmc;
97b2e202 798 struct amdgpu_gart gart;
92e71b06 799 dma_addr_t dummy_page_addr;
97b2e202 800 struct amdgpu_vm_manager vm_manager;
e60f8db5 801 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 802
803 /* memory management */
804 struct amdgpu_mman mman;
97b2e202
AD		 805 struct amdgpu_vram_scratch vram_scratch;
806 struct amdgpu_wb wb;
97b2e202 807 atomic64_t num_bytes_moved;
dbd5ed60 808 atomic64_t num_evictions;
68e2c5ff 809 atomic64_t num_vram_cpu_page_faults;
d94aed5a 810 atomic_t gpu_reset_counter;
f1892138 811 atomic_t vram_lost_counter;
97b2e202 812
95844d20
MO		 813 /* data for buffer migration throttling */
814 struct {
815 spinlock_t lock;
816 s64 last_update_us;
817 s64 accum_us; /* accumulated microseconds */
00f06b24 818 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 819 u32 log2_max_MBps;
820 } mm_stats;
821
97b2e202 822 /* display */
9accf2fd 823 bool enable_virtual_display;
97b2e202 824 struct amdgpu_mode_info mode_info;
4562236b 825 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 826 struct work_struct hotplug_work;
827 struct amdgpu_irq_src crtc_irq;
828 struct amdgpu_irq_src pageflip_irq;
829 struct amdgpu_irq_src hpd_irq;
830
831 /* rings */
76bf0db5 832 u64 fence_context;
97b2e202
AD		 833 unsigned num_rings;
834 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
835 bool ib_pool_ready;
836 struct amdgpu_sa_manager ring_tmp_bo;
837
838 /* interrupts */
839 struct amdgpu_irq irq;
840
1f7371b2
AD		 841 /* powerplay */
842 struct amd_powerplay powerplay;
f3898ea1 843 bool pp_force_state_enabled;
1f7371b2 844
137d63ab
HR		 845 /* smu */
846 struct smu_context smu;
847
97b2e202
AD		 848 /* dpm */
849 struct amdgpu_pm pm;
850 u32 cg_flags;
851 u32 pg_flags;
852
97b2e202
AD		 853 /* gfx */
854 struct amdgpu_gfx gfx;
855
856 /* sdma */
c113ea1c 857 struct amdgpu_sdma sdma;
97b2e202 858
b43aaee6
LL		 859 /* uvd */
860 struct amdgpu_uvd uvd;
861
862 /* vce */
863 struct amdgpu_vce vce;
864
865 /* vcn */
866 struct amdgpu_vcn vcn;
97b2e202
AD		 867
868 /* firmwares */
869 struct amdgpu_firmware firmware;
870
0e5ca0d1
HR		 871 /* PSP */
872 struct psp_context psp;
873
97b2e202
AD		 874 /* GDS */
875 struct amdgpu_gds gds;
876
611736d8
FK		 877 /* KFD */
878 struct amdgpu_kfd_dev kfd;
879
4562236b
HW		 880 /* display related functionality */
881 struct amdgpu_display_manager dm;
882
a1255107 883 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 884 int num_ip_blocks;
97b2e202
AD		 885 struct mutex mn_lock;
886 DECLARE_HASHTABLE(mn_hash, 7);
887
888 /* tracking pinned memory */
a5ccfe5c
MD		 889 atomic64_t vram_pin_size;
890 atomic64_t visible_pin_size;
891 atomic64_t gart_pin_size;
130e0371 892
4522824c
SL		 893 /* soc15 register offset based on ip, instance and segment */
894 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
895
946a4d5b 896 const struct amdgpu_nbio_funcs *nbio_funcs;
634c96e3 897 const struct amdgpu_df_funcs *df_funcs;
946a4d5b 898
2dc80b00
S		 899 /* delayed work_func for deferring clockgating during resume */
900 struct delayed_work late_init_work;
901
5a5099cb 902 struct amdgpu_virt virt;
a05502e5
HC		 903 /* firmware VRAM reservation */
904 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 905
906 /* link all shadow bo */
907 struct list_head shadow_list;
908 struct mutex shadow_list_lock;
795f2813
AR		 909 /* keep an lru list of rings by HW IP */
910 struct list_head ring_lru_list;
911 spinlock_t ring_lru_list_lock;
5c1354bd 912
c836fec5
JQ		 913 /* record hw reset is performed */
914 bool has_hw_reset;
0c49e0b8 915 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 916
44779b43
RZ		 917 /* s3/s4 mask */
918 bool in_suspend;
919
47ed4e1c
KW		 920 /* record last mm index being written through WREG32*/
921 unsigned long last_mm_index;
13a752e3
ML		 922 bool in_gpu_reset;
923 struct mutex lock_reset;
409c5191 924 struct amdgpu_doorbell_index doorbell_index;
d4535e2c 925
26bc5340 926 int asic_reset_res;
d4535e2c 927 struct work_struct xgmi_reset_work;
97b2e202
AD		 928};
929
a7d64de6
CK		 930static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
931{
932 return container_of(bdev, struct amdgpu_device, mman.bdev);
933}
934
97b2e202
AD		 935int amdgpu_device_init(struct amdgpu_device *adev,
936 struct drm_device *ddev,
937 struct pci_dev *pdev,
938 uint32_t flags);
939void amdgpu_device_fini(struct amdgpu_device *adev);
940int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
941
942uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 943 uint32_t acc_flags);
97b2e202 944void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 945 uint32_t acc_flags);
421a2a30
ML		 946void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
947uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
948
97b2e202
AD		 949u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
950void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
951
4562236b
HW		 952bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
953bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
954
9475a943
SL		 955int emu_soc_asic_init(struct amdgpu_device *adev);
956
97b2e202
AD		 957/*
958 * Registers read & write functions.
959 */
15d72fd7
ML		 960
961#define AMDGPU_REGS_IDX (1<<0)
962#define AMDGPU_REGS_NO_KIQ (1<<1)
963
964#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
965#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
966
421a2a30
ML		 967#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
968#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
969
15d72fd7
ML		 970#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
971#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
972#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
973#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
974#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 975#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
976#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
977#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
978#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 979#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
980#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 981#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
982#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
983#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
984#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
985#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
986#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 987#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
988#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 989#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
990#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 991#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
992#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
993#define WREG32_P(reg, val, mask) \
994 do { \
995 uint32_t tmp_ = RREG32(reg); \
996 tmp_ &= (mask); \
997 tmp_ |= ((val) & ~(mask)); \
998 WREG32(reg, tmp_); \
999 } while (0)
1000#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1001#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1002#define WREG32_PLL_P(reg, val, mask) \
1003 do { \
1004 uint32_t tmp_ = RREG32_PLL(reg); \
1005 tmp_ &= (mask); \
1006 tmp_ |= ((val) & ~(mask)); \
1007 WREG32_PLL(reg, tmp_); \
1008 } while (0)
1009#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1010#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1011#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1012
97b2e202
AD		 1013#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1014#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1015
1016#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1017 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1018 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1019
1020#define REG_GET_FIELD(value, reg, field) \
1021 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1022
1023#define WREG32_FIELD(reg, field, val) \
1024 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1025
ccaf3574
TSD		 1026#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1027 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1028
97b2e202
AD		 1029/*
1030 * BIOS helpers.
1031 */
1032#define RBIOS8(i) (adev->bios[i])
1033#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1034#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1035
97b2e202
AD		 1036/*
1037 * ASICs macro.
1038 */
1039#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1040#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1041#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1042#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1043#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1044#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1045#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1046#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1047#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1048#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1049#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1050#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
69882565
CK		 1051#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1052#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
69070690 1053#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
5253163a 1054#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
b45e18ac 1055#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
44401889 1056#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
97b2e202
AD		 1057
1058/* Common functions */
12938fad 1059bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
5f152b5e 1060int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12938fad 1061 struct amdgpu_job* job);
8111c387 1062void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1063bool amdgpu_device_need_post(struct amdgpu_device *adev);
d5fc5e82 1064
00f06b24
JB		 1065void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1066 u64 num_vis_bytes);
d6895ad3 1067int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
9c3f2b54 1068void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1069 const u32 *registers,
1070 const u32 array_size);
1071
1072bool amdgpu_device_is_px(struct drm_device *dev);
1073/* atpx handler */
1074#if defined(CONFIG_VGA_SWITCHEROO)
1075void amdgpu_register_atpx_handler(void);
1076void amdgpu_unregister_atpx_handler(void);
a78fe133 1077bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1078bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1079bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1080bool amdgpu_has_atpx(void);
97b2e202
AD		 1081#else
1082static inline void amdgpu_register_atpx_handler(void) {}
1083static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1084static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1085static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1086static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1087static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1088#endif
1089
24aeefcd
LP		 1090#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1091void *amdgpu_atpx_get_dhandle(void);
1092#else
1093static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1094#endif
1095
97b2e202
AD		 1096/*
1097 * KMS
1098 */
1099extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1100extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1101
1102int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1103void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1104void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1105int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1106void amdgpu_driver_postclose_kms(struct drm_device *dev,
1107 struct drm_file *file_priv);
cdd61df6 1108int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1109int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1110int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1111u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1112int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1113void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1114long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1115 unsigned long arg);
1116
97b2e202
AD		 1117/*
1118 * functions used by amdgpu_encoder.c
1119 */
1120struct amdgpu_afmt_acr {
1121 u32 clock;
1122
1123 int n_32khz;
1124 int cts_32khz;
1125
1126 int n_44_1khz;
1127 int cts_44_1khz;
1128
1129 int n_48khz;
1130 int cts_48khz;
1131
1132};
1133
1134struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1135
1136/* amdgpu_acpi.c */
1137#if defined(CONFIG_ACPI)
1138int amdgpu_acpi_init(struct amdgpu_device *adev);
1139void amdgpu_acpi_fini(struct amdgpu_device *adev);
1140bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1141int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1142 u8 perf_req, bool advertise);
1143int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
206bbafe
DF		 1144
1145void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1146 struct amdgpu_dm_backlight_caps *caps);
97b2e202
AD		 1147#else
1148static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1149static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1150#endif
1151
9cca0b8e
CK		 1152int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1153 uint64_t addr, struct amdgpu_bo **bo,
1154 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1155
4562236b
HW		 1156#if defined(CONFIG_DRM_AMD_DC)
1157int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1158#else
1159static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1160#endif
1161
97b2e202 1162#include "amdgpu_object.h"
97b2e202 1163#endif
Linux 6.x block layer and io_uring tree(s)