Commit | Line | Data |
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97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
8290268f CK |
31 | #include "amdgpu_ctx.h" |
32 | ||
97b2e202 AD |
33 | #include <linux/atomic.h> |
34 | #include <linux/wait.h> | |
35 | #include <linux/list.h> | |
36 | #include <linux/kref.h> | |
a9f87f64 | 37 | #include <linux/rbtree.h> |
97b2e202 | 38 | #include <linux/hashtable.h> |
f54d1867 | 39 | #include <linux/dma-fence.h> |
97b2e202 | 40 | |
248a1d6f MY |
41 | #include <drm/ttm/ttm_bo_api.h> |
42 | #include <drm/ttm/ttm_bo_driver.h> | |
43 | #include <drm/ttm/ttm_placement.h> | |
44 | #include <drm/ttm/ttm_module.h> | |
45 | #include <drm/ttm/ttm_execbuf_util.h> | |
97b2e202 | 46 | |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
f867723b SR |
48 | #include <drm/drm_gem.h> |
49 | #include <drm/drm_ioctl.h> | |
1b1f42d8 | 50 | #include <drm/gpu_scheduler.h> |
97b2e202 | 51 | |
78c16834 | 52 | #include <kgd_kfd_interface.h> |
c79563a3 RZ |
53 | #include "dm_pp_interface.h" |
54 | #include "kgd_pp_interface.h" | |
78c16834 | 55 | |
5fc3aeeb | 56 | #include "amd_shared.h" |
97b2e202 AD |
57 | #include "amdgpu_mode.h" |
58 | #include "amdgpu_ih.h" | |
59 | #include "amdgpu_irq.h" | |
60 | #include "amdgpu_ucode.h" | |
c632d799 | 61 | #include "amdgpu_ttm.h" |
0e5ca0d1 | 62 | #include "amdgpu_psp.h" |
97b2e202 | 63 | #include "amdgpu_gds.h" |
56113504 | 64 | #include "amdgpu_sync.h" |
78023016 | 65 | #include "amdgpu_ring.h" |
073440d2 | 66 | #include "amdgpu_vm.h" |
cf097881 | 67 | #include "amdgpu_dpm.h" |
a8fe58ce | 68 | #include "amdgpu_acp.h" |
4df654d2 | 69 | #include "amdgpu_uvd.h" |
5e568178 | 70 | #include "amdgpu_vce.h" |
95aa13f6 | 71 | #include "amdgpu_vcn.h" |
9a189996 | 72 | #include "amdgpu_mn.h" |
770d13b1 | 73 | #include "amdgpu_gmc.h" |
448fe192 | 74 | #include "amdgpu_gfx.h" |
bb7743bc | 75 | #include "amdgpu_sdma.h" |
4562236b | 76 | #include "amdgpu_dm.h" |
ceeb50ed | 77 | #include "amdgpu_virt.h" |
7946340f | 78 | #include "amdgpu_csa.h" |
3490bdb5 | 79 | #include "amdgpu_gart.h" |
75758255 | 80 | #include "amdgpu_debugfs.h" |
050d9d43 | 81 | #include "amdgpu_job.h" |
4a8c21a1 | 82 | #include "amdgpu_bo_list.h" |
2cddc50e | 83 | #include "amdgpu_gem.h" |
cde577bd | 84 | #include "amdgpu_doorbell.h" |
611736d8 | 85 | #include "amdgpu_amdkfd.h" |
137d63ab | 86 | #include "amdgpu_smu.h" |
f39f5bb1 | 87 | #include "amdgpu_discovery.h" |
a538bbe7 | 88 | #include "amdgpu_mes.h" |
c79563a3 | 89 | |
62d73fbc EQ |
90 | #define MAX_GPU_INSTANCE 16 |
91 | ||
92 | struct amdgpu_gpu_instance | |
93 | { | |
94 | struct amdgpu_device *adev; | |
95 | int mgpu_fan_enabled; | |
96 | }; | |
97 | ||
98 | struct amdgpu_mgpu_info | |
99 | { | |
100 | struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; | |
101 | struct mutex mutex; | |
102 | uint32_t num_gpu; | |
103 | uint32_t num_dgpu; | |
104 | uint32_t num_apu; | |
105 | }; | |
106 | ||
97b2e202 AD |
107 | /* |
108 | * Modules parameters. | |
109 | */ | |
110 | extern int amdgpu_modeset; | |
111 | extern int amdgpu_vram_limit; | |
218b5dcd | 112 | extern int amdgpu_vis_vram_limit; |
83e74db6 | 113 | extern int amdgpu_gart_size; |
36d38372 | 114 | extern int amdgpu_gtt_size; |
95844d20 | 115 | extern int amdgpu_moverate; |
97b2e202 AD |
116 | extern int amdgpu_benchmarking; |
117 | extern int amdgpu_testing; | |
118 | extern int amdgpu_audio; | |
119 | extern int amdgpu_disp_priority; | |
120 | extern int amdgpu_hw_i2c; | |
121 | extern int amdgpu_pcie_gen2; | |
122 | extern int amdgpu_msi; | |
97b2e202 | 123 | extern int amdgpu_dpm; |
e635ee07 | 124 | extern int amdgpu_fw_load_type; |
97b2e202 AD |
125 | extern int amdgpu_aspm; |
126 | extern int amdgpu_runtime_pm; | |
0b693f0b | 127 | extern uint amdgpu_ip_block_mask; |
97b2e202 AD |
128 | extern int amdgpu_bapm; |
129 | extern int amdgpu_deep_color; | |
130 | extern int amdgpu_vm_size; | |
131 | extern int amdgpu_vm_block_size; | |
d07f14be | 132 | extern int amdgpu_vm_fragment_size; |
d9c13156 | 133 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 134 | extern int amdgpu_vm_debug; |
9a4b7d4c | 135 | extern int amdgpu_vm_update_mode; |
4562236b | 136 | extern int amdgpu_dc; |
1333f723 | 137 | extern int amdgpu_sched_jobs; |
4afcb303 | 138 | extern int amdgpu_sched_hw_submission; |
0b693f0b RZ |
139 | extern uint amdgpu_pcie_gen_cap; |
140 | extern uint amdgpu_pcie_lane_cap; | |
141 | extern uint amdgpu_cg_mask; | |
142 | extern uint amdgpu_pg_mask; | |
143 | extern uint amdgpu_sdma_phase_quantum; | |
6f8941a2 | 144 | extern char *amdgpu_disable_cu; |
9accf2fd | 145 | extern char *amdgpu_virtual_display; |
0b693f0b | 146 | extern uint amdgpu_pp_feature_mask; |
bce23e00 AD |
147 | extern int amdgpu_ngg; |
148 | extern int amdgpu_prim_buf_per_se; | |
149 | extern int amdgpu_pos_buf_per_se; | |
150 | extern int amdgpu_cntl_sb_buf_per_se; | |
151 | extern int amdgpu_param_buf_per_se; | |
65781c78 | 152 | extern int amdgpu_job_hang_limit; |
e8835e0e | 153 | extern int amdgpu_lbpw; |
4a75aefe | 154 | extern int amdgpu_compute_multipipe; |
dcebf026 | 155 | extern int amdgpu_gpu_recovery; |
bfca0289 | 156 | extern int amdgpu_emu_mode; |
7951e376 | 157 | extern uint amdgpu_smu_memory_pool_size; |
7875a226 | 158 | extern uint amdgpu_dc_feature_mask; |
ad4de27f | 159 | extern uint amdgpu_dm_abm_level; |
62d73fbc | 160 | extern struct amdgpu_mgpu_info mgpu_info; |
1218252f | 161 | extern int amdgpu_ras_enable; |
162 | extern uint amdgpu_ras_mask; | |
51bcce46 | 163 | extern int amdgpu_async_gfx_ring; |
b239c017 | 164 | extern int amdgpu_mcbp; |
a190d1c7 | 165 | extern int amdgpu_discovery; |
38487284 | 166 | extern int amdgpu_mes; |
75ee6487 | 167 | extern int amdgpu_noretry; |
97b2e202 | 168 | |
6dd13096 FK |
169 | #ifdef CONFIG_DRM_AMDGPU_SI |
170 | extern int amdgpu_si_support; | |
171 | #endif | |
7df28986 FK |
172 | #ifdef CONFIG_DRM_AMDGPU_CIK |
173 | extern int amdgpu_cik_support; | |
174 | #endif | |
97b2e202 | 175 | |
08d1bdd4 | 176 | #define AMDGPU_VM_MAX_NUM_CTX 4096 |
6c8d74ca | 177 | #define AMDGPU_SG_THRESHOLD (256*1024*1024) |
55ed8caf | 178 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
4b559c90 | 179 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 | 180 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
8c5e13ec | 181 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
97b2e202 AD |
182 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ |
183 | #define AMDGPU_IB_POOL_SIZE 16 | |
184 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
185 | #define AMDGPUFB_CONN_LIMIT 4 | |
a5bde2f9 | 186 | #define AMDGPU_BIOS_NUM_SCRATCH 16 |
97b2e202 | 187 | |
97b2e202 AD |
188 | /* hard reset data */ |
189 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
190 | ||
191 | /* reset flags */ | |
192 | #define AMDGPU_RESET_GFX (1 << 0) | |
193 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
194 | #define AMDGPU_RESET_DMA (1 << 2) | |
195 | #define AMDGPU_RESET_CP (1 << 3) | |
196 | #define AMDGPU_RESET_GRBM (1 << 4) | |
197 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
198 | #define AMDGPU_RESET_RLC (1 << 6) | |
199 | #define AMDGPU_RESET_SEM (1 << 7) | |
200 | #define AMDGPU_RESET_IH (1 << 8) | |
201 | #define AMDGPU_RESET_VMC (1 << 9) | |
202 | #define AMDGPU_RESET_MC (1 << 10) | |
203 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
204 | #define AMDGPU_RESET_UVD (1 << 12) | |
205 | #define AMDGPU_RESET_VCE (1 << 13) | |
206 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
207 | ||
97b2e202 AD |
208 | /* max cursor sizes (in pixels) */ |
209 | #define CIK_CURSOR_WIDTH 128 | |
210 | #define CIK_CURSOR_HEIGHT 128 | |
211 | ||
212 | struct amdgpu_device; | |
97b2e202 | 213 | struct amdgpu_ib; |
97b2e202 | 214 | struct amdgpu_cs_parser; |
bb977d37 | 215 | struct amdgpu_job; |
97b2e202 | 216 | struct amdgpu_irq_src; |
0b492a4c | 217 | struct amdgpu_fpriv; |
9cca0b8e | 218 | struct amdgpu_bo_va_mapping; |
102c16a0 | 219 | struct amdgpu_atif; |
992af942 | 220 | struct kfd_vm_fault_info; |
97b2e202 AD |
221 | |
222 | enum amdgpu_cp_irq { | |
53b2fe41 HZ |
223 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, |
224 | AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, | |
97b2e202 AD |
225 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, |
226 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
227 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
228 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
229 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
230 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
231 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
232 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
233 | ||
234 | AMDGPU_CP_IRQ_LAST | |
235 | }; | |
236 | ||
97b2e202 AD |
237 | enum amdgpu_thermal_irq { |
238 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
239 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
240 | ||
241 | AMDGPU_THERMAL_IRQ_LAST | |
242 | }; | |
243 | ||
4e638ae9 XY |
244 | enum amdgpu_kiq_irq { |
245 | AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, | |
246 | AMDGPU_CP_KIQ_IRQ_LAST | |
247 | }; | |
248 | ||
3890d111 ED |
249 | #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ |
250 | #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ | |
4944af67 | 251 | #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ |
3890d111 | 252 | |
43fa561f | 253 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
254 | enum amd_ip_block_type block_type, |
255 | enum amd_clockgating_state state); | |
43fa561f | 256 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
257 | enum amd_ip_block_type block_type, |
258 | enum amd_powergating_state state); | |
259 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, | |
260 | u32 *flags); | |
261 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, | |
262 | enum amd_ip_block_type block_type); | |
263 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, | |
264 | enum amd_ip_block_type block_type); | |
97b2e202 | 265 | |
a1255107 AD |
266 | #define AMDGPU_MAX_IP_NUM 16 |
267 | ||
268 | struct amdgpu_ip_block_status { | |
269 | bool valid; | |
270 | bool sw; | |
271 | bool hw; | |
272 | bool late_initialized; | |
273 | bool hang; | |
274 | }; | |
275 | ||
97b2e202 | 276 | struct amdgpu_ip_block_version { |
a1255107 AD |
277 | const enum amd_ip_block_type type; |
278 | const u32 major; | |
279 | const u32 minor; | |
280 | const u32 rev; | |
5fc3aeeb | 281 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
282 | }; |
283 | ||
a1255107 AD |
284 | struct amdgpu_ip_block { |
285 | struct amdgpu_ip_block_status status; | |
286 | const struct amdgpu_ip_block_version *version; | |
287 | }; | |
288 | ||
2990a1fc AD |
289 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
290 | enum amd_ip_block_type type, | |
291 | u32 major, u32 minor); | |
97b2e202 | 292 | |
2990a1fc AD |
293 | struct amdgpu_ip_block * |
294 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
295 | enum amd_ip_block_type type); | |
a1255107 | 296 | |
2990a1fc AD |
297 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
298 | const struct amdgpu_ip_block_version *ip_block_version); | |
97b2e202 | 299 | |
97b2e202 AD |
300 | /* |
301 | * BIOS. | |
302 | */ | |
303 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
304 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
305 | ||
97b2e202 AD |
306 | /* |
307 | * Clocks | |
308 | */ | |
309 | ||
310 | #define AMDGPU_MAX_PPLL 3 | |
311 | ||
312 | struct amdgpu_clock { | |
313 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
314 | struct amdgpu_pll spll; | |
315 | struct amdgpu_pll mpll; | |
316 | /* 10 Khz units */ | |
317 | uint32_t default_mclk; | |
318 | uint32_t default_sclk; | |
319 | uint32_t default_dispclk; | |
320 | uint32_t current_dispclk; | |
321 | uint32_t dp_extclk; | |
322 | uint32_t max_pixel_clock; | |
323 | }; | |
324 | ||
97b2e202 AD |
325 | /* sub-allocation manager, it has to be protected by another lock. |
326 | * By conception this is an helper for other part of the driver | |
327 | * like the indirect buffer or semaphore, which both have their | |
328 | * locking. | |
329 | * | |
330 | * Principe is simple, we keep a list of sub allocation in offset | |
331 | * order (first entry has offset == 0, last entry has the highest | |
332 | * offset). | |
333 | * | |
334 | * When allocating new object we first check if there is room at | |
335 | * the end total_size - (last_object_offset + last_object_size) >= | |
336 | * alloc_size. If so we allocate new object there. | |
337 | * | |
338 | * When there is not enough room at the end, we start waiting for | |
339 | * each sub object until we reach object_offset+object_size >= | |
340 | * alloc_size, this object then become the sub object we return. | |
341 | * | |
342 | * Alignment can't be bigger than page size. | |
343 | * | |
344 | * Hole are not considered for allocation to keep things simple. | |
345 | * Assumption is that there won't be hole (all object on same | |
346 | * alignment). | |
347 | */ | |
6ba60b89 CK |
348 | |
349 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 | |
350 | ||
97b2e202 AD |
351 | struct amdgpu_sa_manager { |
352 | wait_queue_head_t wq; | |
353 | struct amdgpu_bo *bo; | |
354 | struct list_head *hole; | |
6ba60b89 | 355 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
97b2e202 AD |
356 | struct list_head olist; |
357 | unsigned size; | |
358 | uint64_t gpu_addr; | |
359 | void *cpu_ptr; | |
360 | uint32_t domain; | |
361 | uint32_t align; | |
362 | }; | |
363 | ||
97b2e202 AD |
364 | /* sub-allocation buffer */ |
365 | struct amdgpu_sa_bo { | |
366 | struct list_head olist; | |
367 | struct list_head flist; | |
368 | struct amdgpu_sa_manager *manager; | |
369 | unsigned soffset; | |
370 | unsigned eoffset; | |
f54d1867 | 371 | struct dma_fence *fence; |
97b2e202 AD |
372 | }; |
373 | ||
d573de2d RZ |
374 | int amdgpu_fence_slab_init(void); |
375 | void amdgpu_fence_slab_fini(void); | |
97b2e202 | 376 | |
97b2e202 AD |
377 | /* |
378 | * IRQS. | |
379 | */ | |
380 | ||
381 | struct amdgpu_flip_work { | |
325cbba1 | 382 | struct delayed_work flip_work; |
97b2e202 AD |
383 | struct work_struct unpin_work; |
384 | struct amdgpu_device *adev; | |
385 | int crtc_id; | |
325cbba1 | 386 | u32 target_vblank; |
97b2e202 AD |
387 | uint64_t base; |
388 | struct drm_pending_vblank_event *event; | |
765e7fbf | 389 | struct amdgpu_bo *old_abo; |
f54d1867 | 390 | struct dma_fence *excl; |
1ffd2652 | 391 | unsigned shared_count; |
f54d1867 CW |
392 | struct dma_fence **shared; |
393 | struct dma_fence_cb cb; | |
cb9e59d7 | 394 | bool async; |
97b2e202 AD |
395 | }; |
396 | ||
397 | ||
398 | /* | |
399 | * CP & rings. | |
400 | */ | |
401 | ||
402 | struct amdgpu_ib { | |
403 | struct amdgpu_sa_bo *sa_bo; | |
404 | uint32_t length_dw; | |
405 | uint64_t gpu_addr; | |
406 | uint32_t *ptr; | |
de807f81 | 407 | uint32_t flags; |
97b2e202 AD |
408 | }; |
409 | ||
1b1f42d8 | 410 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
c1b69ed0 | 411 | |
97b2e202 AD |
412 | /* |
413 | * file private structure | |
414 | */ | |
415 | ||
416 | struct amdgpu_fpriv { | |
417 | struct amdgpu_vm vm; | |
b85891bd | 418 | struct amdgpu_bo_va *prt_va; |
0f4b3c68 | 419 | struct amdgpu_bo_va *csa_va; |
97b2e202 AD |
420 | struct mutex bo_list_lock; |
421 | struct idr bo_list_handles; | |
0b492a4c | 422 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
423 | }; |
424 | ||
021830d2 | 425 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); |
912dfc84 | 426 | int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); |
021830d2 | 427 | |
b07c60c0 | 428 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
97b2e202 | 429 | unsigned size, struct amdgpu_ib *ib); |
4d9c514d | 430 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, |
f54d1867 | 431 | struct dma_fence *f); |
b07c60c0 | 432 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
50ddc75e JZ |
433 | struct amdgpu_ib *ibs, struct amdgpu_job *job, |
434 | struct dma_fence **f); | |
97b2e202 AD |
435 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
436 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
437 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
97b2e202 AD |
438 | |
439 | /* | |
440 | * CS. | |
441 | */ | |
442 | struct amdgpu_cs_chunk { | |
443 | uint32_t chunk_id; | |
444 | uint32_t length_dw; | |
758ac17f | 445 | void *kdata; |
97b2e202 AD |
446 | }; |
447 | ||
2624dd15 CZ |
448 | struct amdgpu_cs_post_dep { |
449 | struct drm_syncobj *syncobj; | |
450 | struct dma_fence_chain *chain; | |
451 | u64 point; | |
452 | }; | |
453 | ||
97b2e202 AD |
454 | struct amdgpu_cs_parser { |
455 | struct amdgpu_device *adev; | |
456 | struct drm_file *filp; | |
3cb485f3 | 457 | struct amdgpu_ctx *ctx; |
c3cca41e | 458 | |
97b2e202 AD |
459 | /* chunks */ |
460 | unsigned nchunks; | |
461 | struct amdgpu_cs_chunk *chunks; | |
97b2e202 | 462 | |
50838c8c CK |
463 | /* scheduler job object */ |
464 | struct amdgpu_job *job; | |
0d346a14 | 465 | struct drm_sched_entity *entity; |
97b2e202 | 466 | |
c3cca41e CK |
467 | /* buffer objects */ |
468 | struct ww_acquire_ctx ticket; | |
469 | struct amdgpu_bo_list *bo_list; | |
3fe89771 | 470 | struct amdgpu_mn *mn; |
c3cca41e CK |
471 | struct amdgpu_bo_list_entry vm_pd; |
472 | struct list_head validated; | |
f54d1867 | 473 | struct dma_fence *fence; |
c3cca41e | 474 | uint64_t bytes_moved_threshold; |
00f06b24 | 475 | uint64_t bytes_moved_vis_threshold; |
c3cca41e | 476 | uint64_t bytes_moved; |
00f06b24 | 477 | uint64_t bytes_moved_vis; |
662bfa61 | 478 | struct amdgpu_bo_list_entry *evictable; |
97b2e202 AD |
479 | |
480 | /* user fence */ | |
91acbeb6 | 481 | struct amdgpu_bo_list_entry uf_entry; |
660e8558 | 482 | |
2624dd15 CZ |
483 | unsigned num_post_deps; |
484 | struct amdgpu_cs_post_dep *post_deps; | |
97b2e202 AD |
485 | }; |
486 | ||
7270f839 CK |
487 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
488 | uint32_t ib_idx, int idx) | |
97b2e202 | 489 | { |
50838c8c | 490 | return p->job->ibs[ib_idx].ptr[idx]; |
97b2e202 AD |
491 | } |
492 | ||
7270f839 CK |
493 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
494 | uint32_t ib_idx, int idx, | |
495 | uint32_t value) | |
496 | { | |
50838c8c | 497 | p->job->ibs[ib_idx].ptr[idx] = value; |
7270f839 CK |
498 | } |
499 | ||
97b2e202 AD |
500 | /* |
501 | * Writeback | |
502 | */ | |
73469585 | 503 | #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ |
97b2e202 AD |
504 | |
505 | struct amdgpu_wb { | |
506 | struct amdgpu_bo *wb_obj; | |
507 | volatile uint32_t *wb; | |
508 | uint64_t gpu_addr; | |
509 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
510 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
511 | }; | |
512 | ||
131b4b36 AD |
513 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); |
514 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); | |
97b2e202 | 515 | |
97b2e202 AD |
516 | /* |
517 | * Benchmarking | |
518 | */ | |
519 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
520 | ||
521 | ||
522 | /* | |
523 | * Testing | |
524 | */ | |
525 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
97b2e202 | 526 | |
97b2e202 AD |
527 | /* |
528 | * ASIC specific register table accessible by UMD | |
529 | */ | |
530 | struct amdgpu_allowed_register_entry { | |
531 | uint32_t reg_offset; | |
97b2e202 AD |
532 | bool grbm_indexed; |
533 | }; | |
534 | ||
0cf3c64f AD |
535 | enum amd_reset_method { |
536 | AMD_RESET_METHOD_LEGACY = 0, | |
537 | AMD_RESET_METHOD_MODE0, | |
538 | AMD_RESET_METHOD_MODE1, | |
539 | AMD_RESET_METHOD_MODE2, | |
540 | AMD_RESET_METHOD_BACO | |
541 | }; | |
542 | ||
97b2e202 AD |
543 | /* |
544 | * ASIC specific functions. | |
545 | */ | |
546 | struct amdgpu_asic_funcs { | |
547 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
548 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
549 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
550 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
551 | u32 sh_num, u32 reg_offset, u32 *value); | |
552 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
553 | int (*reset)(struct amdgpu_device *adev); | |
0cf3c64f | 554 | enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); |
97b2e202 AD |
555 | /* get the reference clock */ |
556 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
97b2e202 AD |
557 | /* MM block clocks */ |
558 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
559 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
841686df MB |
560 | /* static power management */ |
561 | int (*get_pcie_lanes)(struct amdgpu_device *adev); | |
562 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); | |
bbf282d8 AD |
563 | /* get config memsize register */ |
564 | u32 (*get_config_memsize)(struct amdgpu_device *adev); | |
2df1b8b6 | 565 | /* flush hdp write queue */ |
69882565 | 566 | void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
2df1b8b6 | 567 | /* invalidate hdp read cache */ |
69882565 CK |
568 | void (*invalidate_hdp)(struct amdgpu_device *adev, |
569 | struct amdgpu_ring *ring); | |
69070690 AD |
570 | /* check if the asic needs a full reset of if soft reset will work */ |
571 | bool (*need_full_reset)(struct amdgpu_device *adev); | |
5253163a OZ |
572 | /* initialize doorbell layout for specific asic*/ |
573 | void (*init_doorbell_index)(struct amdgpu_device *adev); | |
b45e18ac KR |
574 | /* PCIe bandwidth usage */ |
575 | void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, | |
576 | uint64_t *count1); | |
44401889 AD |
577 | /* do we need to reset the asic at init time (e.g., kexec) */ |
578 | bool (*need_reset_on_init)(struct amdgpu_device *adev); | |
dcea6e65 KR |
579 | /* PCIe replay counter */ |
580 | uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); | |
97b2e202 AD |
581 | }; |
582 | ||
583 | /* | |
584 | * IOCTL. | |
585 | */ | |
97b2e202 AD |
586 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, |
587 | struct drm_file *filp); | |
588 | ||
97b2e202 | 589 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
7ca24cf2 MO |
590 | int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, |
591 | struct drm_file *filp); | |
97b2e202 | 592 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
eef18a82 JZ |
593 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, |
594 | struct drm_file *filp); | |
97b2e202 | 595 | |
97b2e202 AD |
596 | /* VRAM scratch page for HDP bug, default vram page */ |
597 | struct amdgpu_vram_scratch { | |
598 | struct amdgpu_bo *robj; | |
599 | volatile uint32_t *ptr; | |
600 | u64 gpu_addr; | |
601 | }; | |
602 | ||
603 | /* | |
604 | * ACPI | |
605 | */ | |
97b2e202 AD |
606 | struct amdgpu_atcs_functions { |
607 | bool get_ext_state; | |
608 | bool pcie_perf_req; | |
609 | bool pcie_dev_rdy; | |
610 | bool pcie_bus_width; | |
611 | }; | |
612 | ||
613 | struct amdgpu_atcs { | |
614 | struct amdgpu_atcs_functions functions; | |
615 | }; | |
616 | ||
a05502e5 HC |
617 | /* |
618 | * Firmware VRAM reservation | |
619 | */ | |
620 | struct amdgpu_fw_vram_usage { | |
621 | u64 start_offset; | |
622 | u64 size; | |
623 | struct amdgpu_bo *reserved_bo; | |
624 | void *va; | |
625 | }; | |
626 | ||
d03846af CZ |
627 | /* |
628 | * CGS | |
629 | */ | |
110e6f26 DA |
630 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
631 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); | |
a8fe58ce | 632 | |
97b2e202 AD |
633 | /* |
634 | * Core structure, functions and helpers. | |
635 | */ | |
636 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
637 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
638 | ||
639 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
640 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
641 | ||
946a4d5b SL |
642 | |
643 | /* | |
644 | * amdgpu nbio functions | |
645 | * | |
946a4d5b | 646 | */ |
bf383fb6 AD |
647 | struct nbio_hdp_flush_reg { |
648 | u32 ref_and_mask_cp0; | |
649 | u32 ref_and_mask_cp1; | |
650 | u32 ref_and_mask_cp2; | |
651 | u32 ref_and_mask_cp3; | |
652 | u32 ref_and_mask_cp4; | |
653 | u32 ref_and_mask_cp5; | |
654 | u32 ref_and_mask_cp6; | |
655 | u32 ref_and_mask_cp7; | |
656 | u32 ref_and_mask_cp8; | |
657 | u32 ref_and_mask_cp9; | |
658 | u32 ref_and_mask_sdma0; | |
659 | u32 ref_and_mask_sdma1; | |
0fe6a7b4 LM |
660 | u32 ref_and_mask_sdma2; |
661 | u32 ref_and_mask_sdma3; | |
662 | u32 ref_and_mask_sdma4; | |
663 | u32 ref_and_mask_sdma5; | |
664 | u32 ref_and_mask_sdma6; | |
665 | u32 ref_and_mask_sdma7; | |
bf383fb6 | 666 | }; |
946a4d5b | 667 | |
88807dc8 OZ |
668 | struct amdgpu_mmio_remap { |
669 | u32 reg_offset; | |
670 | resource_size_t bus_addr; | |
671 | }; | |
672 | ||
946a4d5b | 673 | struct amdgpu_nbio_funcs { |
bf383fb6 AD |
674 | const struct nbio_hdp_flush_reg *hdp_flush_reg; |
675 | u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); | |
676 | u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); | |
677 | u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); | |
678 | u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); | |
679 | u32 (*get_rev_id)(struct amdgpu_device *adev); | |
bf383fb6 | 680 | void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); |
69882565 | 681 | void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
bf383fb6 AD |
682 | u32 (*get_memsize)(struct amdgpu_device *adev); |
683 | void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, | |
8987e2e2 | 684 | bool use_doorbell, int doorbell_index, int doorbell_size); |
b45ddfe8 | 685 | void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, |
989b6a05 | 686 | int doorbell_index, int instance); |
bf383fb6 AD |
687 | void (*enable_doorbell_aperture)(struct amdgpu_device *adev, |
688 | bool enable); | |
689 | void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, | |
690 | bool enable); | |
691 | void (*ih_doorbell_range)(struct amdgpu_device *adev, | |
692 | bool use_doorbell, int doorbell_index); | |
693 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, | |
694 | bool enable); | |
695 | void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, | |
696 | bool enable); | |
697 | void (*get_clockgating_state)(struct amdgpu_device *adev, | |
698 | u32 *flags); | |
699 | void (*ih_control)(struct amdgpu_device *adev); | |
700 | void (*init_registers)(struct amdgpu_device *adev); | |
701 | void (*detect_hw_virt)(struct amdgpu_device *adev); | |
88807dc8 | 702 | void (*remap_hdp_registers)(struct amdgpu_device *adev); |
946a4d5b SL |
703 | }; |
704 | ||
634c96e3 | 705 | struct amdgpu_df_funcs { |
e4cf4bf5 | 706 | void (*sw_init)(struct amdgpu_device *adev); |
634c96e3 HZ |
707 | void (*enable_broadcast_mode)(struct amdgpu_device *adev, |
708 | bool enable); | |
709 | u32 (*get_fb_channel_number)(struct amdgpu_device *adev); | |
710 | u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); | |
711 | void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, | |
712 | bool enable); | |
713 | void (*get_clockgating_state)(struct amdgpu_device *adev, | |
714 | u32 *flags); | |
8f9b2e50 AD |
715 | void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, |
716 | bool enable); | |
992af942 JK |
717 | int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, |
718 | int is_enable); | |
719 | int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, | |
720 | int is_disable); | |
721 | void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, | |
722 | uint64_t *count); | |
64671c0f JK |
723 | uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); |
724 | void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, | |
725 | uint32_t ficadl_val, uint32_t ficadh_val); | |
634c96e3 | 726 | }; |
4522824c SL |
727 | /* Define the HW IP blocks will be used in driver , add more if necessary */ |
728 | enum amd_hw_ip_block_type { | |
729 | GC_HWIP = 1, | |
730 | HDP_HWIP, | |
731 | SDMA0_HWIP, | |
732 | SDMA1_HWIP, | |
fa5d2e6f LM |
733 | SDMA2_HWIP, |
734 | SDMA3_HWIP, | |
735 | SDMA4_HWIP, | |
736 | SDMA5_HWIP, | |
737 | SDMA6_HWIP, | |
738 | SDMA7_HWIP, | |
4522824c SL |
739 | MMHUB_HWIP, |
740 | ATHUB_HWIP, | |
741 | NBIO_HWIP, | |
742 | MP0_HWIP, | |
e6636ae1 | 743 | MP1_HWIP, |
4522824c SL |
744 | UVD_HWIP, |
745 | VCN_HWIP = UVD_HWIP, | |
746 | VCE_HWIP, | |
747 | DF_HWIP, | |
748 | DCE_HWIP, | |
749 | OSSSYS_HWIP, | |
750 | SMUIO_HWIP, | |
751 | PWR_HWIP, | |
752 | NBIF_HWIP, | |
e6636ae1 | 753 | THM_HWIP, |
73b19174 | 754 | CLK_HWIP, |
4522824c SL |
755 | MAX_HWIP |
756 | }; | |
757 | ||
113b47e7 | 758 | #define HWIP_MAX_INSTANCE 8 |
4522824c | 759 | |
11dc9364 | 760 | struct amd_powerplay { |
11dc9364 | 761 | void *pp_handle; |
11dc9364 RZ |
762 | const struct amd_pm_funcs *pp_funcs; |
763 | }; | |
764 | ||
0c49e0b8 | 765 | #define AMDGPU_RESET_MAGIC_NUM 64 |
e4cf4bf5 | 766 | #define AMDGPU_MAX_DF_PERFMONS 4 |
97b2e202 AD |
767 | struct amdgpu_device { |
768 | struct device *dev; | |
769 | struct drm_device *ddev; | |
770 | struct pci_dev *pdev; | |
97b2e202 | 771 | |
a8fe58ce MB |
772 | #ifdef CONFIG_DRM_AMD_ACP |
773 | struct amdgpu_acp acp; | |
774 | #endif | |
775 | ||
97b2e202 | 776 | /* ASIC */ |
2f7d10b3 | 777 | enum amd_asic_type asic_type; |
97b2e202 AD |
778 | uint32_t family; |
779 | uint32_t rev_id; | |
780 | uint32_t external_rev_id; | |
781 | unsigned long flags; | |
782 | int usec_timeout; | |
783 | const struct amdgpu_asic_funcs *asic_funcs; | |
784 | bool shutdown; | |
97b2e202 | 785 | bool need_dma32; |
fd5fd480 | 786 | bool need_swiotlb; |
97b2e202 | 787 | bool accel_working; |
97b2e202 AD |
788 | struct notifier_block acpi_nb; |
789 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
790 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
edf600da | 791 | unsigned debugfs_count; |
97b2e202 | 792 | #if defined(CONFIG_DEBUG_FS) |
6698a3d0 | 793 | struct dentry *debugfs_preempt; |
adcec288 | 794 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
97b2e202 | 795 | #endif |
102c16a0 | 796 | struct amdgpu_atif *atif; |
97b2e202 AD |
797 | struct amdgpu_atcs atcs; |
798 | struct mutex srbm_mutex; | |
799 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
800 | struct mutex grbm_idx_mutex; | |
801 | struct dev_pm_domain vga_pm_domain; | |
802 | bool have_disp_power_ref; | |
bae17d2a | 803 | bool have_atomics_support; |
97b2e202 AD |
804 | |
805 | /* BIOS */ | |
0cdd5005 | 806 | bool is_atom_fw; |
97b2e202 | 807 | uint8_t *bios; |
a9f5db9c | 808 | uint32_t bios_size; |
5af2c10d | 809 | struct amdgpu_bo *stolen_vga_memory; |
a5bde2f9 | 810 | uint32_t bios_scratch_reg_offset; |
97b2e202 AD |
811 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
812 | ||
813 | /* Register/doorbell mmio */ | |
814 | resource_size_t rmmio_base; | |
815 | resource_size_t rmmio_size; | |
816 | void __iomem *rmmio; | |
817 | /* protects concurrent MM_INDEX/DATA based register access */ | |
818 | spinlock_t mmio_idx_lock; | |
88807dc8 | 819 | struct amdgpu_mmio_remap rmmio_remap; |
97b2e202 AD |
820 | /* protects concurrent SMC based register access */ |
821 | spinlock_t smc_idx_lock; | |
822 | amdgpu_rreg_t smc_rreg; | |
823 | amdgpu_wreg_t smc_wreg; | |
824 | /* protects concurrent PCIE register access */ | |
825 | spinlock_t pcie_idx_lock; | |
826 | amdgpu_rreg_t pcie_rreg; | |
827 | amdgpu_wreg_t pcie_wreg; | |
36b9a952 HR |
828 | amdgpu_rreg_t pciep_rreg; |
829 | amdgpu_wreg_t pciep_wreg; | |
97b2e202 AD |
830 | /* protects concurrent UVD register access */ |
831 | spinlock_t uvd_ctx_idx_lock; | |
832 | amdgpu_rreg_t uvd_ctx_rreg; | |
833 | amdgpu_wreg_t uvd_ctx_wreg; | |
834 | /* protects concurrent DIDT register access */ | |
835 | spinlock_t didt_idx_lock; | |
836 | amdgpu_rreg_t didt_rreg; | |
837 | amdgpu_wreg_t didt_wreg; | |
ccdbb20a RZ |
838 | /* protects concurrent gc_cac register access */ |
839 | spinlock_t gc_cac_idx_lock; | |
840 | amdgpu_rreg_t gc_cac_rreg; | |
841 | amdgpu_wreg_t gc_cac_wreg; | |
16abb5d2 EQ |
842 | /* protects concurrent se_cac register access */ |
843 | spinlock_t se_cac_idx_lock; | |
844 | amdgpu_rreg_t se_cac_rreg; | |
845 | amdgpu_wreg_t se_cac_wreg; | |
97b2e202 AD |
846 | /* protects concurrent ENDPOINT (audio) register access */ |
847 | spinlock_t audio_endpt_idx_lock; | |
848 | amdgpu_block_rreg_t audio_endpt_rreg; | |
849 | amdgpu_block_wreg_t audio_endpt_wreg; | |
850 | void __iomem *rio_mem; | |
851 | resource_size_t rio_mem_size; | |
852 | struct amdgpu_doorbell doorbell; | |
853 | ||
854 | /* clock/pll info */ | |
855 | struct amdgpu_clock clock; | |
856 | ||
857 | /* MC */ | |
770d13b1 | 858 | struct amdgpu_gmc gmc; |
97b2e202 | 859 | struct amdgpu_gart gart; |
92e71b06 | 860 | dma_addr_t dummy_page_addr; |
97b2e202 | 861 | struct amdgpu_vm_manager vm_manager; |
e60f8db5 | 862 | struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; |
1daa2bfa | 863 | unsigned num_vmhubs; |
97b2e202 AD |
864 | |
865 | /* memory management */ | |
866 | struct amdgpu_mman mman; | |
97b2e202 AD |
867 | struct amdgpu_vram_scratch vram_scratch; |
868 | struct amdgpu_wb wb; | |
97b2e202 | 869 | atomic64_t num_bytes_moved; |
dbd5ed60 | 870 | atomic64_t num_evictions; |
68e2c5ff | 871 | atomic64_t num_vram_cpu_page_faults; |
d94aed5a | 872 | atomic_t gpu_reset_counter; |
f1892138 | 873 | atomic_t vram_lost_counter; |
97b2e202 | 874 | |
95844d20 MO |
875 | /* data for buffer migration throttling */ |
876 | struct { | |
877 | spinlock_t lock; | |
878 | s64 last_update_us; | |
879 | s64 accum_us; /* accumulated microseconds */ | |
00f06b24 | 880 | s64 accum_us_vis; /* for visible VRAM */ |
95844d20 MO |
881 | u32 log2_max_MBps; |
882 | } mm_stats; | |
883 | ||
97b2e202 | 884 | /* display */ |
9accf2fd | 885 | bool enable_virtual_display; |
97b2e202 | 886 | struct amdgpu_mode_info mode_info; |
4562236b | 887 | /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ |
97b2e202 AD |
888 | struct work_struct hotplug_work; |
889 | struct amdgpu_irq_src crtc_irq; | |
d2574c33 | 890 | struct amdgpu_irq_src vupdate_irq; |
97b2e202 AD |
891 | struct amdgpu_irq_src pageflip_irq; |
892 | struct amdgpu_irq_src hpd_irq; | |
893 | ||
894 | /* rings */ | |
76bf0db5 | 895 | u64 fence_context; |
97b2e202 AD |
896 | unsigned num_rings; |
897 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
898 | bool ib_pool_ready; | |
899 | struct amdgpu_sa_manager ring_tmp_bo; | |
900 | ||
901 | /* interrupts */ | |
902 | struct amdgpu_irq irq; | |
903 | ||
1f7371b2 AD |
904 | /* powerplay */ |
905 | struct amd_powerplay powerplay; | |
f3898ea1 | 906 | bool pp_force_state_enabled; |
1f7371b2 | 907 | |
137d63ab HR |
908 | /* smu */ |
909 | struct smu_context smu; | |
910 | ||
97b2e202 AD |
911 | /* dpm */ |
912 | struct amdgpu_pm pm; | |
913 | u32 cg_flags; | |
914 | u32 pg_flags; | |
915 | ||
97b2e202 AD |
916 | /* gfx */ |
917 | struct amdgpu_gfx gfx; | |
918 | ||
919 | /* sdma */ | |
c113ea1c | 920 | struct amdgpu_sdma sdma; |
97b2e202 | 921 | |
b43aaee6 LL |
922 | /* uvd */ |
923 | struct amdgpu_uvd uvd; | |
924 | ||
925 | /* vce */ | |
926 | struct amdgpu_vce vce; | |
927 | ||
928 | /* vcn */ | |
929 | struct amdgpu_vcn vcn; | |
97b2e202 AD |
930 | |
931 | /* firmwares */ | |
932 | struct amdgpu_firmware firmware; | |
933 | ||
0e5ca0d1 HR |
934 | /* PSP */ |
935 | struct psp_context psp; | |
936 | ||
97b2e202 AD |
937 | /* GDS */ |
938 | struct amdgpu_gds gds; | |
939 | ||
611736d8 FK |
940 | /* KFD */ |
941 | struct amdgpu_kfd_dev kfd; | |
942 | ||
4562236b HW |
943 | /* display related functionality */ |
944 | struct amdgpu_display_manager dm; | |
945 | ||
f39f5bb1 XY |
946 | /* discovery */ |
947 | uint8_t *discovery; | |
948 | ||
a538bbe7 JX |
949 | /* mes */ |
950 | bool enable_mes; | |
951 | struct amdgpu_mes mes; | |
952 | ||
a1255107 | 953 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
97b2e202 | 954 | int num_ip_blocks; |
97b2e202 AD |
955 | struct mutex mn_lock; |
956 | DECLARE_HASHTABLE(mn_hash, 7); | |
957 | ||
958 | /* tracking pinned memory */ | |
a5ccfe5c MD |
959 | atomic64_t vram_pin_size; |
960 | atomic64_t visible_pin_size; | |
961 | atomic64_t gart_pin_size; | |
130e0371 | 962 | |
4522824c SL |
963 | /* soc15 register offset based on ip, instance and segment */ |
964 | uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; | |
965 | ||
946a4d5b | 966 | const struct amdgpu_nbio_funcs *nbio_funcs; |
634c96e3 | 967 | const struct amdgpu_df_funcs *df_funcs; |
946a4d5b | 968 | |
2dc80b00 | 969 | /* delayed work_func for deferring clockgating during resume */ |
beff74bc | 970 | struct delayed_work delayed_init_work; |
2dc80b00 | 971 | |
5a5099cb | 972 | struct amdgpu_virt virt; |
a05502e5 HC |
973 | /* firmware VRAM reservation */ |
974 | struct amdgpu_fw_vram_usage fw_vram_usage; | |
0c4e7fa5 CZ |
975 | |
976 | /* link all shadow bo */ | |
977 | struct list_head shadow_list; | |
978 | struct mutex shadow_list_lock; | |
795f2813 AR |
979 | /* keep an lru list of rings by HW IP */ |
980 | struct list_head ring_lru_list; | |
981 | spinlock_t ring_lru_list_lock; | |
5c1354bd | 982 | |
c836fec5 JQ |
983 | /* record hw reset is performed */ |
984 | bool has_hw_reset; | |
0c49e0b8 | 985 | u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; |
c836fec5 | 986 | |
44779b43 RZ |
987 | /* s3/s4 mask */ |
988 | bool in_suspend; | |
989 | ||
47ed4e1c KW |
990 | /* record last mm index being written through WREG32*/ |
991 | unsigned long last_mm_index; | |
13a752e3 | 992 | bool in_gpu_reset; |
a3a09142 | 993 | enum pp_mp1_state mp1_state; |
13a752e3 | 994 | struct mutex lock_reset; |
409c5191 | 995 | struct amdgpu_doorbell_index doorbell_index; |
d4535e2c | 996 | |
26bc5340 | 997 | int asic_reset_res; |
d4535e2c | 998 | struct work_struct xgmi_reset_work; |
9b638f97 | 999 | |
0c5ccf14 | 1000 | bool in_baco_reset; |
912dfc84 EQ |
1001 | |
1002 | long gfx_timeout; | |
1003 | long sdma_timeout; | |
1004 | long video_timeout; | |
1005 | long compute_timeout; | |
fb2dbfd2 KR |
1006 | |
1007 | uint64_t unique_id; | |
e4cf4bf5 | 1008 | uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; |
97b2e202 AD |
1009 | }; |
1010 | ||
a7d64de6 CK |
1011 | static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) |
1012 | { | |
1013 | return container_of(bdev, struct amdgpu_device, mman.bdev); | |
1014 | } | |
1015 | ||
97b2e202 AD |
1016 | int amdgpu_device_init(struct amdgpu_device *adev, |
1017 | struct drm_device *ddev, | |
1018 | struct pci_dev *pdev, | |
1019 | uint32_t flags); | |
1020 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
1021 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
1022 | ||
1023 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
15d72fd7 | 1024 | uint32_t acc_flags); |
97b2e202 | 1025 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 1026 | uint32_t acc_flags); |
421a2a30 ML |
1027 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); |
1028 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); | |
1029 | ||
97b2e202 AD |
1030 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
1031 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
1032 | ||
4562236b HW |
1033 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); |
1034 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); | |
1035 | ||
9475a943 SL |
1036 | int emu_soc_asic_init(struct amdgpu_device *adev); |
1037 | ||
97b2e202 AD |
1038 | /* |
1039 | * Registers read & write functions. | |
1040 | */ | |
15d72fd7 ML |
1041 | |
1042 | #define AMDGPU_REGS_IDX (1<<0) | |
1043 | #define AMDGPU_REGS_NO_KIQ (1<<1) | |
1044 | ||
1045 | #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) | |
1046 | #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) | |
1047 | ||
421a2a30 ML |
1048 | #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) |
1049 | #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) | |
1050 | ||
15d72fd7 ML |
1051 | #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) |
1052 | #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) | |
1053 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) | |
1054 | #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) | |
1055 | #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) | |
97b2e202 AD |
1056 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1057 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1058 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
1059 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
36b9a952 HR |
1060 | #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) |
1061 | #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1062 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
1063 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
1064 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
1065 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
1066 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
1067 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
ccdbb20a RZ |
1068 | #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) |
1069 | #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) | |
16abb5d2 EQ |
1070 | #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) |
1071 | #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1072 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
1073 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
1074 | #define WREG32_P(reg, val, mask) \ | |
1075 | do { \ | |
1076 | uint32_t tmp_ = RREG32(reg); \ | |
1077 | tmp_ &= (mask); \ | |
1078 | tmp_ |= ((val) & ~(mask)); \ | |
1079 | WREG32(reg, tmp_); \ | |
1080 | } while (0) | |
1081 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
1082 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
1083 | #define WREG32_PLL_P(reg, val, mask) \ | |
1084 | do { \ | |
1085 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1086 | tmp_ &= (mask); \ | |
1087 | tmp_ |= ((val) & ~(mask)); \ | |
1088 | WREG32_PLL(reg, tmp_); \ | |
1089 | } while (0) | |
1090 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | |
1091 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) | |
1092 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
1093 | ||
97b2e202 AD |
1094 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
1095 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
1096 | ||
1097 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
1098 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
1099 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
1100 | ||
1101 | #define REG_GET_FIELD(value, reg, field) \ | |
1102 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
61cb8cef TSD |
1103 | |
1104 | #define WREG32_FIELD(reg, field, val) \ | |
1105 | WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
97b2e202 | 1106 | |
ccaf3574 TSD |
1107 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
1108 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
1109 | ||
97b2e202 AD |
1110 | /* |
1111 | * BIOS helpers. | |
1112 | */ | |
1113 | #define RBIOS8(i) (adev->bios[i]) | |
1114 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1115 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1116 | ||
97b2e202 AD |
1117 | /* |
1118 | * ASICs macro. | |
1119 | */ | |
1120 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
1121 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
0cf3c64f | 1122 | #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) |
97b2e202 AD |
1123 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
1124 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
1125 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
841686df MB |
1126 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
1127 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) | |
1128 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
97b2e202 | 1129 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
7946b878 | 1130 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 | 1131 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
bbf282d8 | 1132 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
69882565 CK |
1133 | #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) |
1134 | #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) | |
69070690 | 1135 | #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) |
5253163a | 1136 | #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) |
b45e18ac | 1137 | #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) |
44401889 | 1138 | #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) |
dcea6e65 | 1139 | #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) |
97b2e202 AD |
1140 | |
1141 | /* Common functions */ | |
12938fad | 1142 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); |
5f152b5e | 1143 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
12938fad | 1144 | struct amdgpu_job* job); |
8111c387 | 1145 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); |
39c640c0 | 1146 | bool amdgpu_device_need_post(struct amdgpu_device *adev); |
d5fc5e82 | 1147 | |
00f06b24 JB |
1148 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
1149 | u64 num_vis_bytes); | |
d6895ad3 | 1150 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); |
9c3f2b54 | 1151 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
97b2e202 AD |
1152 | const u32 *registers, |
1153 | const u32 array_size); | |
1154 | ||
1155 | bool amdgpu_device_is_px(struct drm_device *dev); | |
992af942 JK |
1156 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, |
1157 | struct amdgpu_device *peer_adev); | |
1158 | ||
97b2e202 AD |
1159 | /* atpx handler */ |
1160 | #if defined(CONFIG_VGA_SWITCHEROO) | |
1161 | void amdgpu_register_atpx_handler(void); | |
1162 | void amdgpu_unregister_atpx_handler(void); | |
a78fe133 | 1163 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
2f5af82e | 1164 | bool amdgpu_is_atpx_hybrid(void); |
efc83cf4 | 1165 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); |
714f88e0 | 1166 | bool amdgpu_has_atpx(void); |
97b2e202 AD |
1167 | #else |
1168 | static inline void amdgpu_register_atpx_handler(void) {} | |
1169 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
a78fe133 | 1170 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
2f5af82e | 1171 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
efc83cf4 | 1172 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } |
714f88e0 | 1173 | static inline bool amdgpu_has_atpx(void) { return false; } |
97b2e202 AD |
1174 | #endif |
1175 | ||
24aeefcd LP |
1176 | #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) |
1177 | void *amdgpu_atpx_get_dhandle(void); | |
1178 | #else | |
1179 | static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } | |
1180 | #endif | |
1181 | ||
97b2e202 AD |
1182 | /* |
1183 | * KMS | |
1184 | */ | |
1185 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
f498d9ed | 1186 | extern const int amdgpu_max_kms_ioctl; |
97b2e202 AD |
1187 | |
1188 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
11b3c20b | 1189 | void amdgpu_driver_unload_kms(struct drm_device *dev); |
97b2e202 AD |
1190 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
1191 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
1192 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
1193 | struct drm_file *file_priv); | |
cdd61df6 | 1194 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev); |
810ddc3a AD |
1195 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); |
1196 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); | |
88e72717 TR |
1197 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); |
1198 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
1199 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); | |
97b2e202 AD |
1200 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
1201 | unsigned long arg); | |
1202 | ||
97b2e202 AD |
1203 | /* |
1204 | * functions used by amdgpu_encoder.c | |
1205 | */ | |
1206 | struct amdgpu_afmt_acr { | |
1207 | u32 clock; | |
1208 | ||
1209 | int n_32khz; | |
1210 | int cts_32khz; | |
1211 | ||
1212 | int n_44_1khz; | |
1213 | int cts_44_1khz; | |
1214 | ||
1215 | int n_48khz; | |
1216 | int cts_48khz; | |
1217 | ||
1218 | }; | |
1219 | ||
1220 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
1221 | ||
1222 | /* amdgpu_acpi.c */ | |
1223 | #if defined(CONFIG_ACPI) | |
1224 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
1225 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
1226 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
1227 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
1228 | u8 perf_req, bool advertise); | |
1229 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
206bbafe DF |
1230 | |
1231 | void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, | |
1232 | struct amdgpu_dm_backlight_caps *caps); | |
97b2e202 AD |
1233 | #else |
1234 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
1235 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
1236 | #endif | |
1237 | ||
9cca0b8e CK |
1238 | int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
1239 | uint64_t addr, struct amdgpu_bo **bo, | |
1240 | struct amdgpu_bo_va_mapping **mapping); | |
97b2e202 | 1241 | |
4562236b HW |
1242 | #if defined(CONFIG_DRM_AMD_DC) |
1243 | int amdgpu_dm_display_resume(struct amdgpu_device *adev ); | |
1244 | #else | |
1245 | static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } | |
1246 | #endif | |
1247 | ||
fdafb359 EQ |
1248 | |
1249 | void amdgpu_register_gpu_instance(struct amdgpu_device *adev); | |
1250 | void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); | |
1251 | ||
97b2e202 | 1252 | #include "amdgpu_object.h" |
e4cf4bf5 JK |
1253 | |
1254 | /* used by df_v3_6.c and amdgpu_pmu.c */ | |
1255 | #define AMDGPU_PMU_ATTR(_name, _object) \ | |
1256 | static ssize_t \ | |
1257 | _name##_show(struct device *dev, \ | |
1258 | struct device_attribute *attr, \ | |
1259 | char *page) \ | |
1260 | { \ | |
1261 | BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ | |
1262 | return sprintf(page, _object "\n"); \ | |
1263 | } \ | |
1264 | \ | |
1265 | static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) | |
1266 | ||
97b2e202 | 1267 | #endif |
e4cf4bf5 | 1268 |