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drm/amdgpu: make function names consistent in nbio files
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
1b1f42d8 48#include <drm/gpu_scheduler.h>
97b2e202 49
78c16834 50#include <kgd_kfd_interface.h>
c79563a3
RZ		 51#include "dm_pp_interface.h"
52#include "kgd_pp_interface.h"
78c16834 53
5fc3aeeb 54#include "amd_shared.h"
97b2e202
AD		 55#include "amdgpu_mode.h"
56#include "amdgpu_ih.h"
57#include "amdgpu_irq.h"
58#include "amdgpu_ucode.h"
c632d799 59#include "amdgpu_ttm.h"
0e5ca0d1 60#include "amdgpu_psp.h"
97b2e202 61#include "amdgpu_gds.h"
56113504 62#include "amdgpu_sync.h"
78023016 63#include "amdgpu_ring.h"
073440d2 64#include "amdgpu_vm.h"
cf097881 65#include "amdgpu_dpm.h"
a8fe58ce 66#include "amdgpu_acp.h"
4df654d2 67#include "amdgpu_uvd.h"
5e568178 68#include "amdgpu_vce.h"
95aa13f6 69#include "amdgpu_vcn.h"
9a189996 70#include "amdgpu_mn.h"
4562236b 71#include "amdgpu_dm.h"
ceeb50ed 72#include "amdgpu_virt.h"
3490bdb5 73#include "amdgpu_gart.h"
b80d8475 74
c79563a3 75
97b2e202
AD		 76/*
77 * Modules parameters.
78 */
79extern int amdgpu_modeset;
80extern int amdgpu_vram_limit;
218b5dcd 81extern int amdgpu_vis_vram_limit;
83e74db6 82extern int amdgpu_gart_size;
36d38372 83extern int amdgpu_gtt_size;
95844d20 84extern int amdgpu_moverate;
97b2e202
AD		 85extern int amdgpu_benchmarking;
86extern int amdgpu_testing;
87extern int amdgpu_audio;
88extern int amdgpu_disp_priority;
89extern int amdgpu_hw_i2c;
90extern int amdgpu_pcie_gen2;
91extern int amdgpu_msi;
92extern int amdgpu_lockup_timeout;
93extern int amdgpu_dpm;
e635ee07 94extern int amdgpu_fw_load_type;
97b2e202
AD		 95extern int amdgpu_aspm;
96extern int amdgpu_runtime_pm;
0b693f0b 97extern uint amdgpu_ip_block_mask;
97b2e202
AD		 98extern int amdgpu_bapm;
99extern int amdgpu_deep_color;
100extern int amdgpu_vm_size;
101extern int amdgpu_vm_block_size;
d07f14be 102extern int amdgpu_vm_fragment_size;
d9c13156 103extern int amdgpu_vm_fault_stop;
b495bd3a 104extern int amdgpu_vm_debug;
9a4b7d4c 105extern int amdgpu_vm_update_mode;
4562236b 106extern int amdgpu_dc;
02e749dc 107extern int amdgpu_dc_log;
1333f723 108extern int amdgpu_sched_jobs;
4afcb303 109extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 110extern int amdgpu_no_evict;
111extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 112extern uint amdgpu_pcie_gen_cap;
113extern uint amdgpu_pcie_lane_cap;
114extern uint amdgpu_cg_mask;
115extern uint amdgpu_pg_mask;
116extern uint amdgpu_sdma_phase_quantum;
6f8941a2 117extern char *amdgpu_disable_cu;
9accf2fd 118extern char *amdgpu_virtual_display;
0b693f0b 119extern uint amdgpu_pp_feature_mask;
6a7f76e7 120extern int amdgpu_vram_page_split;
bce23e00
AD		 121extern int amdgpu_ngg;
122extern int amdgpu_prim_buf_per_se;
123extern int amdgpu_pos_buf_per_se;
124extern int amdgpu_cntl_sb_buf_per_se;
125extern int amdgpu_param_buf_per_se;
65781c78 126extern int amdgpu_job_hang_limit;
e8835e0e 127extern int amdgpu_lbpw;
4a75aefe 128extern int amdgpu_compute_multipipe;
97b2e202 129
6dd13096
FK		 130#ifdef CONFIG_DRM_AMDGPU_SI
131extern int amdgpu_si_support;
132#endif
7df28986
FK		 133#ifdef CONFIG_DRM_AMDGPU_CIK
134extern int amdgpu_cik_support;
135#endif
97b2e202 136
55ed8caf 137#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 138#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 139#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
140#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
141/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
142#define AMDGPU_IB_POOL_SIZE 16
143#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
144#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 145#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 146
36f523a7
JZ		 147/* max number of IP instances */
148#define AMDGPU_MAX_SDMA_INSTANCES 2
149
97b2e202
AD		 150/* hard reset data */
151#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
152
153/* reset flags */
154#define AMDGPU_RESET_GFX (1 << 0)
155#define AMDGPU_RESET_COMPUTE (1 << 1)
156#define AMDGPU_RESET_DMA (1 << 2)
157#define AMDGPU_RESET_CP (1 << 3)
158#define AMDGPU_RESET_GRBM (1 << 4)
159#define AMDGPU_RESET_DMA1 (1 << 5)
160#define AMDGPU_RESET_RLC (1 << 6)
161#define AMDGPU_RESET_SEM (1 << 7)
162#define AMDGPU_RESET_IH (1 << 8)
163#define AMDGPU_RESET_VMC (1 << 9)
164#define AMDGPU_RESET_MC (1 << 10)
165#define AMDGPU_RESET_DISPLAY (1 << 11)
166#define AMDGPU_RESET_UVD (1 << 12)
167#define AMDGPU_RESET_VCE (1 << 13)
168#define AMDGPU_RESET_VCE1 (1 << 14)
169
97b2e202
AD		 170/* GFX current status */
171#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
172#define AMDGPU_GFX_SAFE_MODE 0x00000001L
173#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
174#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
175#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
176
177/* max cursor sizes (in pixels) */
178#define CIK_CURSOR_WIDTH 128
179#define CIK_CURSOR_HEIGHT 128
180
5740682e
ML		 181/* GPU RESET flags */
182#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0)
183#define AMDGPU_RESET_INFO_FULLRESET (1 << 1)
184
97b2e202 185struct amdgpu_device;
97b2e202 186struct amdgpu_ib;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
9cca0b8e 191struct amdgpu_bo_va_mapping;
97b2e202
AD		 192
193enum amdgpu_cp_irq {
194 AMDGPU_CP_IRQ_GFX_EOP = 0,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
203
204 AMDGPU_CP_IRQ_LAST
205};
206
207enum amdgpu_sdma_irq {
208 AMDGPU_SDMA_IRQ_TRAP0 = 0,
209 AMDGPU_SDMA_IRQ_TRAP1,
210
211 AMDGPU_SDMA_IRQ_LAST
212};
213
214enum amdgpu_thermal_irq {
215 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
216 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
217
218 AMDGPU_THERMAL_IRQ_LAST
219};
220
4e638ae9
XY		 221enum amdgpu_kiq_irq {
222 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
223 AMDGPU_CP_KIQ_IRQ_LAST
224};
225
97b2e202 226int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
97b2e202 229int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
6cb2d4e4 232void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 233int amdgpu_wait_for_idle(struct amdgpu_device *adev,
234 enum amd_ip_block_type block_type);
235bool amdgpu_is_idle(struct amdgpu_device *adev,
236 enum amd_ip_block_type block_type);
97b2e202 237
a1255107
AD		 238#define AMDGPU_MAX_IP_NUM 16
239
240struct amdgpu_ip_block_status {
241 bool valid;
242 bool sw;
243 bool hw;
244 bool late_initialized;
245 bool hang;
246};
247
97b2e202 248struct amdgpu_ip_block_version {
a1255107
AD		 249 const enum amd_ip_block_type type;
250 const u32 major;
251 const u32 minor;
252 const u32 rev;
5fc3aeeb 253 const struct amd_ip_funcs *funcs;
97b2e202
AD		 254};
255
a1255107
AD		 256struct amdgpu_ip_block {
257 struct amdgpu_ip_block_status status;
258 const struct amdgpu_ip_block_version *version;
259};
260
97b2e202 261int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 262 enum amd_ip_block_type type,
97b2e202
AD		 263 u32 major, u32 minor);
264
a1255107
AD		 265struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
266 enum amd_ip_block_type type);
267
268int amdgpu_ip_block_add(struct amdgpu_device *adev,
269 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 270
271/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
272struct amdgpu_buffer_funcs {
273 /* maximum bytes in a single operation */
274 uint32_t copy_max_bytes;
275
276 /* number of dw to reserve per operation */
277 unsigned copy_num_dw;
278
279 /* used for buffer migration */
c7ae72c0 280 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 281 /* src addr in bytes */
282 uint64_t src_offset,
283 /* dst addr in bytes */
284 uint64_t dst_offset,
285 /* number of byte to transfer */
286 uint32_t byte_count);
287
288 /* maximum bytes in a single operation */
289 uint32_t fill_max_bytes;
290
291 /* number of dw to reserve per operation */
292 unsigned fill_num_dw;
293
294 /* used for buffer clearing */
6e7a3840 295 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 296 /* value to write to memory */
297 uint32_t src_data,
298 /* dst addr in bytes */
299 uint64_t dst_offset,
300 /* number of byte to fill */
301 uint32_t byte_count);
302};
303
304/* provided by hw blocks that can write ptes, e.g., sdma */
305struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 306 /* number of dw to reserve per operation */
307 unsigned copy_pte_num_dw;
308
97b2e202
AD		 309 /* copy pte entries from GART */
310 void (*copy_pte)(struct amdgpu_ib *ib,
311 uint64_t pe, uint64_t src,
312 unsigned count);
e6d92197 313
97b2e202 314 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 315 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
316 uint64_t value, unsigned count,
317 uint32_t incr);
7bdc53f9
YZ		 318
319 /* maximum nums of PTEs/PDEs in a single operation */
320 uint32_t set_max_nums_pte_pde;
321
322 /* number of dw to reserve per operation */
323 unsigned set_pte_pde_num_dw;
324
97b2e202
AD		 325 /* for linear pte/pde updates without addr mapping */
326 void (*set_pte_pde)(struct amdgpu_ib *ib,
327 uint64_t pe,
328 uint64_t addr, unsigned count,
6b777607 329 uint32_t incr, uint64_t flags);
97b2e202
AD		 330};
331
332/* provided by the gmc block */
333struct amdgpu_gart_funcs {
334 /* flush the vm tlb via mmio */
335 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
336 uint32_t vmid);
337 /* write pte/pde updates using the cpu */
338 int (*set_pte_pde)(struct amdgpu_device *adev,
339 void *cpu_pt_addr, /* cpu addr of page table */
340 uint32_t gpu_page_idx, /* pte/pde to update */
341 uint64_t addr, /* addr to write into pte/pde */
6b777607 342 uint64_t flags); /* access flags */
284710fa
CK		 343 /* enable/disable PRT support */
344 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 345 /* set pte flags based per asic */
346 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
347 uint32_t flags);
b1166325 348 /* get the pde for a given mc addr */
3de676d8
CK		 349 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
350 u64 *dst, u64 *flags);
03f89feb 351 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 352};
353
97b2e202
AD		 354/* provided by the ih block */
355struct amdgpu_ih_funcs {
356 /* ring read/write ptr handling, called from interrupt context */
357 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 358 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 359 void (*decode_iv)(struct amdgpu_device *adev,
360 struct amdgpu_iv_entry *entry);
361 void (*set_rptr)(struct amdgpu_device *adev);
362};
363
97b2e202
AD		 364/*
365 * BIOS.
366 */
367bool amdgpu_get_bios(struct amdgpu_device *adev);
368bool amdgpu_read_bios(struct amdgpu_device *adev);
369
370/*
371 * Dummy page
372 */
373struct amdgpu_dummy_page {
374 struct page *page;
375 dma_addr_t addr;
376};
377int amdgpu_dummy_page_init(struct amdgpu_device *adev);
378void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
379
380
381/*
382 * Clocks
383 */
384
385#define AMDGPU_MAX_PPLL 3
386
387struct amdgpu_clock {
388 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
389 struct amdgpu_pll spll;
390 struct amdgpu_pll mpll;
391 /* 10 Khz units */
392 uint32_t default_mclk;
393 uint32_t default_sclk;
394 uint32_t default_dispclk;
395 uint32_t current_dispclk;
396 uint32_t dp_extclk;
397 uint32_t max_pixel_clock;
398};
399
97b2e202 400/*
9124a398 401 * GEM.
97b2e202 402 */
97b2e202 403
7e5a547f 404#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 405#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
406
407void amdgpu_gem_object_free(struct drm_gem_object *obj);
408int amdgpu_gem_object_open(struct drm_gem_object *obj,
409 struct drm_file *file_priv);
410void amdgpu_gem_object_close(struct drm_gem_object *obj,
411 struct drm_file *file_priv);
412unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
413struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 414struct drm_gem_object *
415amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
416 struct dma_buf_attachment *attach,
417 struct sg_table *sg);
97b2e202
AD		 418struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
419 struct drm_gem_object *gobj,
420 int flags);
421int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
422void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
423struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
424void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
425void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 426int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 427int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
428
429/* sub-allocation manager, it has to be protected by another lock.
430 * By conception this is an helper for other part of the driver
431 * like the indirect buffer or semaphore, which both have their
432 * locking.
433 *
434 * Principe is simple, we keep a list of sub allocation in offset
435 * order (first entry has offset == 0, last entry has the highest
436 * offset).
437 *
438 * When allocating new object we first check if there is room at
439 * the end total_size - (last_object_offset + last_object_size) >=
440 * alloc_size. If so we allocate new object there.
441 *
442 * When there is not enough room at the end, we start waiting for
443 * each sub object until we reach object_offset+object_size >=
444 * alloc_size, this object then become the sub object we return.
445 *
446 * Alignment can't be bigger than page size.
447 *
448 * Hole are not considered for allocation to keep things simple.
449 * Assumption is that there won't be hole (all object on same
450 * alignment).
451 */
6ba60b89
CK		 452
453#define AMDGPU_SA_NUM_FENCE_LISTS 32
454
97b2e202
AD		 455struct amdgpu_sa_manager {
456 wait_queue_head_t wq;
457 struct amdgpu_bo *bo;
458 struct list_head *hole;
6ba60b89 459 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 460 struct list_head olist;
461 unsigned size;
462 uint64_t gpu_addr;
463 void *cpu_ptr;
464 uint32_t domain;
465 uint32_t align;
466};
467
97b2e202
AD		 468/* sub-allocation buffer */
469struct amdgpu_sa_bo {
470 struct list_head olist;
471 struct list_head flist;
472 struct amdgpu_sa_manager *manager;
473 unsigned soffset;
474 unsigned eoffset;
f54d1867 475 struct dma_fence *fence;
97b2e202
AD		 476};
477
478/*
479 * GEM objects.
480 */
418aa0c2 481void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 482int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 483 int alignment, u32 initial_domain,
484 u64 flags, bool kernel,
485 struct reservation_object *resv,
486 struct drm_gem_object **obj);
97b2e202
AD		 487
488int amdgpu_mode_dumb_create(struct drm_file *file_priv,
489 struct drm_device *dev,
490 struct drm_mode_create_dumb *args);
491int amdgpu_mode_dumb_mmap(struct drm_file *filp,
492 struct drm_device *dev,
493 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 494int amdgpu_fence_slab_init(void);
495void amdgpu_fence_slab_fini(void);
97b2e202 496
e60f8db5
AX		 497/*
498 * VMHUB structures, functions & helpers
499 */
500struct amdgpu_vmhub {
501 uint32_t ctx0_ptb_addr_lo32;
502 uint32_t ctx0_ptb_addr_hi32;
503 uint32_t vm_inv_eng0_req;
504 uint32_t vm_inv_eng0_ack;
505 uint32_t vm_context0_cntl;
506 uint32_t vm_l2_pro_fault_status;
507 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 508};
509
97b2e202
AD		 510/*
511 * GPU MC structures, functions & helpers
512 */
513struct amdgpu_mc {
514 resource_size_t aper_size;
515 resource_size_t aper_base;
516 resource_size_t agp_base;
517 /* for some chips with <= 32MB we need to lie
518 * about vram size near mc fb location */
519 u64 mc_vram_size;
520 u64 visible_vram_size;
6f02a696
CK		 521 u64 gart_size;
522 u64 gart_start;
523 u64 gart_end;
97b2e202
AD		 524 u64 vram_start;
525 u64 vram_end;
526 unsigned vram_width;
527 u64 real_vram_size;
528 int vram_mtrr;
97b2e202
AD		 529 u64 mc_mask;
530 const struct firmware *fw; /* MC firmware */
531 uint32_t fw_version;
532 struct amdgpu_irq_src vm_fault;
81c59f54 533 uint32_t vram_type;
50b0197a 534 uint32_t srbm_soft_reset;
f7c35abe 535 bool prt_warning;
916910ad 536 uint64_t stolen_size;
8fe73328
JZ		 537 /* apertures */
538 u64 shared_aperture_start;
539 u64 shared_aperture_end;
540 u64 private_aperture_start;
541 u64 private_aperture_end;
e60f8db5
AX		 542 /* protects concurrent invalidation */
543 spinlock_t invalidate_lock;
97b2e202
AD		 544};
545
546/*
547 * GPU doorbell structures, functions & helpers
548 */
549typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
550{
551 AMDGPU_DOORBELL_KIQ = 0x000,
552 AMDGPU_DOORBELL_HIQ = 0x001,
553 AMDGPU_DOORBELL_DIQ = 0x002,
554 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
555 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
556 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
557 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
558 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
559 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
560 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
561 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
562 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
563 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
564 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
565 AMDGPU_DOORBELL_IH = 0x1E8,
566 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
567 AMDGPU_DOORBELL_INVALID = 0xFFFF
568} AMDGPU_DOORBELL_ASSIGNMENT;
569
570struct amdgpu_doorbell {
571 /* doorbell mmio */
572 resource_size_t base;
573 resource_size_t size;
574 u32 __iomem *ptr;
575 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
576};
577
39807b93
KW		 578/*
579 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
580 */
581typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
582{
583 /*
584 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
585 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
586 * Compute related doorbells are allocated from 0x00 to 0x8a
587 */
588
589
590 /* kernel scheduling */
591 AMDGPU_DOORBELL64_KIQ = 0x00,
592
593 /* HSA interface queue and debug queue */
594 AMDGPU_DOORBELL64_HIQ = 0x01,
595 AMDGPU_DOORBELL64_DIQ = 0x02,
596
597 /* Compute engines */
598 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
599 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
600 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
601 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
602 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
603 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
604 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
605 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
606
607 /* User queue doorbell range (128 doorbells) */
608 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
609 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
610
611 /* Graphics engine */
612 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
613
614 /*
615 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
616 * Graphics voltage island aperture 1
617 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
618 */
619
620 /* sDMA engines */
621 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
622 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
623 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
624 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
625
626 /* Interrupt handler */
627 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
628 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
629 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
630
e6b3ecb4
ML		 631 /* VCN engine use 32 bits doorbell */
632 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
633 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
634 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
635 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
636
637 /* overlap the doorbell assignment with VCN as they are mutually exclusive
638 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
639 */
4ed11d79
FM		 640 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
641 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
642 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
643 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
644
645 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
646 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
647 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
648 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 649
650 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
651 AMDGPU_DOORBELL64_INVALID = 0xFFFF
652} AMDGPU_DOORBELL64_ASSIGNMENT;
653
654
97b2e202
AD		 655void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
656 phys_addr_t *aperture_base,
657 size_t *aperture_size,
658 size_t *start_offset);
659
660/*
661 * IRQS.
662 */
663
664struct amdgpu_flip_work {
325cbba1 665 struct delayed_work flip_work;
97b2e202
AD		 666 struct work_struct unpin_work;
667 struct amdgpu_device *adev;
668 int crtc_id;
325cbba1 669 u32 target_vblank;
97b2e202
AD		 670 uint64_t base;
671 struct drm_pending_vblank_event *event;
765e7fbf 672 struct amdgpu_bo *old_abo;
f54d1867 673 struct dma_fence *excl;
1ffd2652 674 unsigned shared_count;
f54d1867
CW		 675 struct dma_fence **shared;
676 struct dma_fence_cb cb;
cb9e59d7 677 bool async;
97b2e202
AD		 678};
679
680
681/*
682 * CP & rings.
683 */
684
685struct amdgpu_ib {
686 struct amdgpu_sa_bo *sa_bo;
687 uint32_t length_dw;
688 uint64_t gpu_addr;
689 uint32_t *ptr;
de807f81 690 uint32_t flags;
97b2e202
AD		 691};
692
1b1f42d8 693extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 694
50838c8c 695int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 696 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 697int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
698 struct amdgpu_job **job);
b6723c8d 699
a5fb4ec2 700void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 701void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 702int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
1b1f42d8 703 struct drm_sched_entity *entity, void *owner,
f54d1867 704 struct dma_fence **f);
8b4fb00b 705
effd924d
AR		 706/*
707 * Queue manager
708 */
709struct amdgpu_queue_mapper {
710 int hw_ip;
711 struct mutex lock;
712 /* protected by lock */
713 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
714};
715
716struct amdgpu_queue_mgr {
717 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
718};
719
720int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
721 struct amdgpu_queue_mgr *mgr);
722int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
723 struct amdgpu_queue_mgr *mgr);
724int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
725 struct amdgpu_queue_mgr *mgr,
fa7c7939 726 u32 hw_ip, u32 instance, u32 ring,
effd924d
AR		 727 struct amdgpu_ring **out_ring);
728
97b2e202
AD		 729/*
730 * context related structures
731 */
732
21c16bf6 733struct amdgpu_ctx_ring {
91404fb2 734 uint64_t sequence;
f54d1867 735 struct dma_fence **fences;
1b1f42d8 736 struct drm_sched_entity entity;
21c16bf6
CK		 737};
738
97b2e202 739struct amdgpu_ctx {
0b492a4c 740 struct kref refcount;
9cb7e5a9 741 struct amdgpu_device *adev;
effd924d 742 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 743 unsigned reset_counter;
668ca1b4 744 unsigned reset_counter_query;
e55f2b64 745 uint32_t vram_lost_counter;
21c16bf6 746 spinlock_t ring_lock;
f54d1867 747 struct dma_fence **fences;
21c16bf6 748 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
e55f2b64 749 bool preamble_presented;
1b1f42d8
LS		 750 enum drm_sched_priority init_priority;
751 enum drm_sched_priority override_priority;
0ae94444 752 struct mutex lock;
1102900d 753 atomic_t guilty;
97b2e202
AD		 754};
755
756struct amdgpu_ctx_mgr {
0b492a4c
AD		 757 struct amdgpu_device *adev;
758 struct mutex lock;
759 /* protected by lock */
760 struct idr ctx_handles;
97b2e202
AD		 761};
762
0b492a4c
AD		 763struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
764int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
765
eb01abc7
ML		 766int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
767 struct dma_fence *fence, uint64_t *seq);
f54d1867 768struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 769 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae 770void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
1b1f42d8 771 enum drm_sched_priority priority);
21c16bf6 772
0b492a4c
AD		 773int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
774 struct drm_file *filp);
775
0ae94444
AG		 776int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
777
efd4ccb5
CK		 778void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
779void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 780
0ae94444 781
97b2e202
AD		 782/*
783 * file private structure
784 */
785
786struct amdgpu_fpriv {
787 struct amdgpu_vm vm;
b85891bd 788 struct amdgpu_bo_va *prt_va;
0f4b3c68 789 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 790 struct mutex bo_list_lock;
791 struct idr bo_list_handles;
0b492a4c 792 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 793};
794
795/*
796 * residency list
797 */
9124a398
CK		 798struct amdgpu_bo_list_entry {
799 struct amdgpu_bo *robj;
800 struct ttm_validate_buffer tv;
801 struct amdgpu_bo_va *bo_va;
802 uint32_t priority;
803 struct page **user_pages;
804 int user_invalidated;
805};
97b2e202
AD		 806
807struct amdgpu_bo_list {
808 struct mutex lock;
5ac55629
AX		 809 struct rcu_head rhead;
810 struct kref refcount;
97b2e202
AD		 811 struct amdgpu_bo *gds_obj;
812 struct amdgpu_bo *gws_obj;
813 struct amdgpu_bo *oa_obj;
211dff55 814 unsigned first_userptr;
97b2e202
AD		 815 unsigned num_entries;
816 struct amdgpu_bo_list_entry *array;
817};
818
819struct amdgpu_bo_list *
820amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 821void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
822 struct list_head *validated);
97b2e202
AD		 823void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
824void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
825
826/*
827 * GFX stuff
828 */
829#include "clearstate_defs.h"
830
79e5412c
AD		 831struct amdgpu_rlc_funcs {
832 void (*enter_safe_mode)(struct amdgpu_device *adev);
833 void (*exit_safe_mode)(struct amdgpu_device *adev);
834};
835
97b2e202
AD		 836struct amdgpu_rlc {
837 /* for power gating */
838 struct amdgpu_bo *save_restore_obj;
839 uint64_t save_restore_gpu_addr;
840 volatile uint32_t *sr_ptr;
841 const u32 *reg_list;
842 u32 reg_list_size;
843 /* for clear state */
844 struct amdgpu_bo *clear_state_obj;
845 uint64_t clear_state_gpu_addr;
846 volatile uint32_t *cs_ptr;
847 const struct cs_section_def *cs_data;
848 u32 clear_state_size;
849 /* for cp tables */
850 struct amdgpu_bo *cp_table_obj;
851 uint64_t cp_table_gpu_addr;
852 volatile uint32_t *cp_table_ptr;
853 u32 cp_table_size;
79e5412c
AD		 854
855 /* safe mode for updating CG/PG state */
856 bool in_safe_mode;
857 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 858
859 /* for firmware data */
860 u32 save_and_restore_offset;
861 u32 clear_state_descriptor_offset;
862 u32 avail_scratch_ram_locations;
863 u32 reg_restore_list_size;
864 u32 reg_list_format_start;
865 u32 reg_list_format_separate_start;
866 u32 starting_offsets_start;
867 u32 reg_list_format_size_bytes;
868 u32 reg_list_size_bytes;
869
870 u32 *register_list_format;
871 u32 *register_restore;
97b2e202
AD		 872};
873
78c16834
AR		 874#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
875
97b2e202
AD		 876struct amdgpu_mec {
877 struct amdgpu_bo *hpd_eop_obj;
878 u64 hpd_eop_gpu_addr;
b1023571
KW		 879 struct amdgpu_bo *mec_fw_obj;
880 u64 mec_fw_gpu_addr;
97b2e202 881 u32 num_mec;
42794b27
AR		 882 u32 num_pipe_per_mec;
883 u32 num_queue_per_pipe;
59a82d7d 884 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 885
886 /* These are the resources for which amdgpu takes ownership */
887 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 888};
889
4e638ae9
XY		 890struct amdgpu_kiq {
891 u64 eop_gpu_addr;
892 struct amdgpu_bo *eop_obj;
43ca8efa 893 spinlock_t ring_lock;
4e638ae9
XY		 894 struct amdgpu_ring ring;
895 struct amdgpu_irq_src irq;
896};
897
97b2e202
AD		 898/*
899 * GPU scratch registers structures, functions & helpers
900 */
901struct amdgpu_scratch {
902 unsigned num_reg;
903 uint32_t reg_base;
50261151 904 uint32_t free_mask;
97b2e202
AD		 905};
906
907/*
908 * GFX configurations
909 */
e3fa7630
AD		 910#define AMDGPU_GFX_MAX_SE 4
911#define AMDGPU_GFX_MAX_SH_PER_SE 2
912
913struct amdgpu_rb_config {
914 uint32_t rb_backend_disable;
915 uint32_t user_rb_backend_disable;
916 uint32_t raster_config;
917 uint32_t raster_config_1;
918};
919
d0e95758
AG		 920struct gb_addr_config {
921 uint16_t pipe_interleave_size;
922 uint8_t num_pipes;
923 uint8_t max_compress_frags;
924 uint8_t num_banks;
925 uint8_t num_se;
926 uint8_t num_rb_per_se;
927};
928
ea323f88 929struct amdgpu_gfx_config {
97b2e202
AD		 930 unsigned max_shader_engines;
931 unsigned max_tile_pipes;
932 unsigned max_cu_per_sh;
933 unsigned max_sh_per_se;
934 unsigned max_backends_per_se;
935 unsigned max_texture_channel_caches;
936 unsigned max_gprs;
937 unsigned max_gs_threads;
938 unsigned max_hw_contexts;
939 unsigned sc_prim_fifo_size_frontend;
940 unsigned sc_prim_fifo_size_backend;
941 unsigned sc_hiz_tile_fifo_size;
942 unsigned sc_earlyz_tile_fifo_size;
943
944 unsigned num_tile_pipes;
945 unsigned backend_enable_mask;
946 unsigned mem_max_burst_length_bytes;
947 unsigned mem_row_size_in_kb;
948 unsigned shader_engine_tile_size;
949 unsigned num_gpus;
950 unsigned multi_gpu_tile_size;
951 unsigned mc_arb_ramcfg;
952 unsigned gb_addr_config;
8f8e00c1 953 unsigned num_rbs;
408bfe7c
JZ		 954 unsigned gs_vgt_table_depth;
955 unsigned gs_prim_buffer_depth;
97b2e202
AD		 956
957 uint32_t tile_mode_array[32];
958 uint32_t macrotile_mode_array[16];
e3fa7630 959
d0e95758 960 struct gb_addr_config gb_addr_config_fields;
e3fa7630 961 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 962
963 /* gfx configure feature */
964 uint32_t double_offchip_lds_buf;
97b2e202
AD		 965};
966
7dae69a2 967struct amdgpu_cu_info {
51fd0370 968 uint32_t max_waves_per_simd;
408bfe7c 969 uint32_t wave_front_size;
51fd0370
HZ		 970 uint32_t max_scratch_slots_per_cu;
971 uint32_t lds_size;
dbfe85ea
FC		 972
973 /* total active CU number */
974 uint32_t number;
975 uint32_t ao_cu_mask;
976 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 977 uint32_t bitmap[4][4];
978};
979
b95e31fd
AD		 980struct amdgpu_gfx_funcs {
981 /* get the gpu clock counter */
982 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 983 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 984 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 985 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
986 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 987};
988
bce23e00
AD		 989struct amdgpu_ngg_buf {
990 struct amdgpu_bo *bo;
991 uint64_t gpu_addr;
992 uint32_t size;
993 uint32_t bo_size;
994};
995
996enum {
af8baf15
GR		 997 NGG_PRIM = 0,
998 NGG_POS,
999 NGG_CNTL,
1000 NGG_PARAM,
bce23e00
AD		 1001 NGG_BUF_MAX
1002};
1003
1004struct amdgpu_ngg {
1005 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1006 uint32_t gds_reserve_addr;
1007 uint32_t gds_reserve_size;
1008 bool init;
1009};
1010
97b2e202
AD		 1011struct amdgpu_gfx {
1012 struct mutex gpu_clock_mutex;
ea323f88 1013 struct amdgpu_gfx_config config;
97b2e202
AD		 1014 struct amdgpu_rlc rlc;
1015 struct amdgpu_mec mec;
4e638ae9 1016 struct amdgpu_kiq kiq;
97b2e202
AD		 1017 struct amdgpu_scratch scratch;
1018 const struct firmware *me_fw; /* ME firmware */
1019 uint32_t me_fw_version;
1020 const struct firmware *pfp_fw; /* PFP firmware */
1021 uint32_t pfp_fw_version;
1022 const struct firmware *ce_fw; /* CE firmware */
1023 uint32_t ce_fw_version;
1024 const struct firmware *rlc_fw; /* RLC firmware */
1025 uint32_t rlc_fw_version;
1026 const struct firmware *mec_fw; /* MEC firmware */
1027 uint32_t mec_fw_version;
1028 const struct firmware *mec2_fw; /* MEC2 firmware */
1029 uint32_t mec2_fw_version;
02558a00
KW		 1030 uint32_t me_feature_version;
1031 uint32_t ce_feature_version;
1032 uint32_t pfp_feature_version;
351643d7
JZ		 1033 uint32_t rlc_feature_version;
1034 uint32_t mec_feature_version;
1035 uint32_t mec2_feature_version;
97b2e202
AD		 1036 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1037 unsigned num_gfx_rings;
1038 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1039 unsigned num_compute_rings;
1040 struct amdgpu_irq_src eop_irq;
1041 struct amdgpu_irq_src priv_reg_irq;
1042 struct amdgpu_irq_src priv_inst_irq;
1043 /* gfx status */
7dae69a2 1044 uint32_t gfx_current_status;
a101a899 1045 /* ce ram size*/
7dae69a2
AD		 1046 unsigned ce_ram_size;
1047 struct amdgpu_cu_info cu_info;
b95e31fd 1048 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1049
1050 /* reset mask */
1051 uint32_t grbm_soft_reset;
1052 uint32_t srbm_soft_reset;
b4e40676
DP		 1053 /* s3/s4 mask */
1054 bool in_suspend;
bce23e00
AD		 1055 /* NGG */
1056 struct amdgpu_ngg ngg;
b8866c26
AR		 1057
1058 /* pipe reservation */
1059 struct mutex pipe_reserve_mutex;
1060 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 1061};
1062
b07c60c0 1063int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1064 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1065void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1066 struct dma_fence *f);
b07c60c0 1067int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1068 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1069 struct dma_fence **f);
97b2e202
AD		 1070int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1071void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1072int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1073
1074/*
1075 * CS.
1076 */
1077struct amdgpu_cs_chunk {
1078 uint32_t chunk_id;
1079 uint32_t length_dw;
758ac17f 1080 void *kdata;
97b2e202
AD		 1081};
1082
1083struct amdgpu_cs_parser {
1084 struct amdgpu_device *adev;
1085 struct drm_file *filp;
3cb485f3 1086 struct amdgpu_ctx *ctx;
c3cca41e 1087
97b2e202
AD		 1088 /* chunks */
1089 unsigned nchunks;
1090 struct amdgpu_cs_chunk *chunks;
97b2e202 1091
50838c8c
CK		 1092 /* scheduler job object */
1093 struct amdgpu_job *job;
97b2e202 1094
c3cca41e
CK		 1095 /* buffer objects */
1096 struct ww_acquire_ctx ticket;
1097 struct amdgpu_bo_list *bo_list;
3fe89771 1098 struct amdgpu_mn *mn;
c3cca41e
CK		 1099 struct amdgpu_bo_list_entry vm_pd;
1100 struct list_head validated;
f54d1867 1101 struct dma_fence *fence;
c3cca41e 1102 uint64_t bytes_moved_threshold;
00f06b24 1103 uint64_t bytes_moved_vis_threshold;
c3cca41e 1104 uint64_t bytes_moved;
00f06b24 1105 uint64_t bytes_moved_vis;
662bfa61 1106 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1107
1108 /* user fence */
91acbeb6 1109 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1110
1111 unsigned num_post_dep_syncobjs;
1112 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1113};
1114
753ad49c
ML		 1115#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1116#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1117#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1118
bb977d37 1119struct amdgpu_job {
1b1f42d8 1120 struct drm_sched_job base;
bb977d37 1121 struct amdgpu_device *adev;
edf600da 1122 struct amdgpu_vm *vm;
b07c60c0 1123 struct amdgpu_ring *ring;
e86f9cee 1124 struct amdgpu_sync sync;
df83d1eb 1125 struct amdgpu_sync sched_sync;
bb977d37 1126 struct amdgpu_ib *ibs;
f54d1867 1127 struct dma_fence *fence; /* the hw fence */
753ad49c 1128 uint32_t preamble_status;
bb977d37 1129 uint32_t num_ibs;
e2840221 1130 void *owner;
3aecd24c 1131 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1132 bool vm_needs_flush;
d88bf583
CK		 1133 unsigned vm_id;
1134 uint64_t vm_pd_addr;
1135 uint32_t gds_base, gds_size;
1136 uint32_t gws_base, gws_size;
1137 uint32_t oa_base, oa_size;
14e47f93 1138 uint32_t vram_lost_counter;
758ac17f
CK		 1139
1140 /* user fence handling */
b5f5acbc 1141 uint64_t uf_addr;
758ac17f
CK		 1142 uint64_t uf_sequence;
1143
bb977d37 1144};
a6db8a33
JZ		 1145#define to_amdgpu_job(sched_job) \
1146 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1147
7270f839
CK		 1148static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1149 uint32_t ib_idx, int idx)
97b2e202 1150{
50838c8c 1151 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1152}
1153
7270f839
CK		 1154static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1155 uint32_t ib_idx, int idx,
1156 uint32_t value)
1157{
50838c8c 1158 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1159}
1160
97b2e202
AD		 1161/*
1162 * Writeback
1163 */
896a664c 1164#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
97b2e202
AD		 1165
1166struct amdgpu_wb {
1167 struct amdgpu_bo *wb_obj;
1168 volatile uint32_t *wb;
1169 uint64_t gpu_addr;
1170 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1171 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1172};
1173
1174int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1175void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1176
d0dd7f0c
AD		 1177void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1178
97b2e202
AD		 1179/*
1180 * SDMA
1181 */
c113ea1c 1182struct amdgpu_sdma_instance {
97b2e202
AD		 1183 /* SDMA firmware */
1184 const struct firmware *fw;
1185 uint32_t fw_version;
cfa2104f 1186 uint32_t feature_version;
97b2e202
AD		 1187
1188 struct amdgpu_ring ring;
18111de0 1189 bool burst_nop;
97b2e202
AD		 1190};
1191
c113ea1c
AD		 1192struct amdgpu_sdma {
1193 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1194#ifdef CONFIG_DRM_AMDGPU_SI
1195 //SI DMA has a difference trap irq number for the second engine
1196 struct amdgpu_irq_src trap_irq_1;
1197#endif
c113ea1c
AD		 1198 struct amdgpu_irq_src trap_irq;
1199 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1200 int num_instances;
e702a680 1201 uint32_t srbm_soft_reset;
c113ea1c
AD		 1202};
1203
97b2e202
AD		 1204/*
1205 * Firmware
1206 */
e635ee07
HR		 1207enum amdgpu_firmware_load_type {
1208 AMDGPU_FW_LOAD_DIRECT = 0,
1209 AMDGPU_FW_LOAD_SMU,
1210 AMDGPU_FW_LOAD_PSP,
1211};
1212
97b2e202
AD		 1213struct amdgpu_firmware {
1214 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1215 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1216 struct amdgpu_bo *fw_buf;
1217 unsigned int fw_size;
2445b227 1218 unsigned int max_ucodes;
0e5ca0d1
HR		 1219 /* firmwares are loaded by psp instead of smu from vega10 */
1220 const struct amdgpu_psp_funcs *funcs;
1221 struct amdgpu_bo *rbuf;
1222 struct mutex mutex;
ab4fe3e1
HR		 1223
1224 /* gpu info firmware data pointer */
1225 const struct firmware *gpu_info_fw;
d59c026b
ML		 1226
1227 void *fw_buf_ptr;
1228 uint64_t fw_buf_mc;
97b2e202
AD		 1229};
1230
1231/*
1232 * Benchmarking
1233 */
1234void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1235
1236
1237/*
1238 * Testing
1239 */
1240void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1241
97b2e202
AD		 1242/*
1243 * Debugfs
1244 */
1245struct amdgpu_debugfs {
06ab6832 1246 const struct drm_info_list *files;
97b2e202
AD		 1247 unsigned num_files;
1248};
1249
1250int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1251 const struct drm_info_list *files,
97b2e202
AD		 1252 unsigned nfiles);
1253int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
50ab2533
HR		 1254int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1255
97b2e202
AD		 1256/*
1257 * amdgpu smumgr functions
1258 */
1259struct amdgpu_smumgr_funcs {
1260 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1261 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1262 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1263};
1264
1265/*
1266 * amdgpu smumgr
1267 */
1268struct amdgpu_smumgr {
1269 struct amdgpu_bo *toc_buf;
1270 struct amdgpu_bo *smu_buf;
1271 /* asic priv smu data */
1272 void *priv;
1273 spinlock_t smu_lock;
1274 /* smumgr functions */
1275 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1276 /* ucode loading complete flag */
1277 uint32_t fw_flags;
1278};
1279
1280/*
1281 * ASIC specific register table accessible by UMD
1282 */
1283struct amdgpu_allowed_register_entry {
1284 uint32_t reg_offset;
97b2e202
AD		 1285 bool grbm_indexed;
1286};
1287
97b2e202
AD		 1288/*
1289 * ASIC specific functions.
1290 */
1291struct amdgpu_asic_funcs {
1292 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1293 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1294 u8 *bios, u32 length_bytes);
97b2e202
AD		 1295 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1296 u32 sh_num, u32 reg_offset, u32 *value);
1297 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1298 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1299 /* get the reference clock */
1300 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1301 /* MM block clocks */
1302 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1303 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1304 /* static power management */
1305 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1306 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1307 /* get config memsize register */
1308 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1309};
1310
1311/*
1312 * IOCTL.
1313 */
1314int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1315 struct drm_file *filp);
1316int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1317 struct drm_file *filp);
1318
1319int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *filp);
1321int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
1323int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *filp);
1325int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1326 struct drm_file *filp);
1327int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1328 struct drm_file *filp);
1329int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1330 struct drm_file *filp);
1331int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1332int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1333 struct drm_file *filp);
97b2e202 1334int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1335int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *filp);
97b2e202
AD		 1337
1338int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1339 struct drm_file *filp);
1340
1341/* VRAM scratch page for HDP bug, default vram page */
1342struct amdgpu_vram_scratch {
1343 struct amdgpu_bo *robj;
1344 volatile uint32_t *ptr;
1345 u64 gpu_addr;
1346};
1347
1348/*
1349 * ACPI
1350 */
1351struct amdgpu_atif_notification_cfg {
1352 bool enabled;
1353 int command_code;
1354};
1355
1356struct amdgpu_atif_notifications {
1357 bool display_switch;
1358 bool expansion_mode_change;
1359 bool thermal_state;
1360 bool forced_power_state;
1361 bool system_power_state;
1362 bool display_conf_change;
1363 bool px_gfx_switch;
1364 bool brightness_change;
1365 bool dgpu_display_event;
1366};
1367
1368struct amdgpu_atif_functions {
1369 bool system_params;
1370 bool sbios_requests;
1371 bool select_active_disp;
1372 bool lid_state;
1373 bool get_tv_standard;
1374 bool set_tv_standard;
1375 bool get_panel_expansion_mode;
1376 bool set_panel_expansion_mode;
1377 bool temperature_change;
1378 bool graphics_device_types;
1379};
1380
1381struct amdgpu_atif {
1382 struct amdgpu_atif_notifications notifications;
1383 struct amdgpu_atif_functions functions;
1384 struct amdgpu_atif_notification_cfg notification_cfg;
1385 struct amdgpu_encoder *encoder_for_bl;
1386};
1387
1388struct amdgpu_atcs_functions {
1389 bool get_ext_state;
1390 bool pcie_perf_req;
1391 bool pcie_dev_rdy;
1392 bool pcie_bus_width;
1393};
1394
1395struct amdgpu_atcs {
1396 struct amdgpu_atcs_functions functions;
1397};
1398
a05502e5
HC		 1399/*
1400 * Firmware VRAM reservation
1401 */
1402struct amdgpu_fw_vram_usage {
1403 u64 start_offset;
1404 u64 size;
1405 struct amdgpu_bo *reserved_bo;
1406 void *va;
1407};
1408
1409int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
f59548c8 1410void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);
a05502e5 1411
d03846af
CZ		 1412/*
1413 * CGS
1414 */
110e6f26
DA		 1415struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1416void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1417
97b2e202
AD		 1418/*
1419 * Core structure, functions and helpers.
1420 */
1421typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1422typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1423
1424typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1425typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1426
946a4d5b
SL		 1427
1428/*
1429 * amdgpu nbio functions
1430 *
1431 * Fix me :
1432 * Put more NBIO specifc func wraper here , for now just try to minimize the
1433 * change to avoid use SOC15_REG_OFFSET in the constant array
1434 */
1435
1436struct amdgpu_nbio_funcs {
1437 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*);
1438 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*);
1439 u32 (*get_pcie_index_offset)(struct amdgpu_device*);
1440 u32 (*get_pcie_data_offset)(struct amdgpu_device*);
1441};
1442
1443
4522824c
SL		 1444/* Define the HW IP blocks will be used in driver , add more if necessary */
1445enum amd_hw_ip_block_type {
1446 GC_HWIP = 1,
1447 HDP_HWIP,
1448 SDMA0_HWIP,
1449 SDMA1_HWIP,
1450 MMHUB_HWIP,
1451 ATHUB_HWIP,
1452 NBIO_HWIP,
1453 MP0_HWIP,
1454 UVD_HWIP,
1455 VCN_HWIP = UVD_HWIP,
1456 VCE_HWIP,
1457 DF_HWIP,
1458 DCE_HWIP,
1459 OSSSYS_HWIP,
1460 SMUIO_HWIP,
1461 PWR_HWIP,
1462 NBIF_HWIP,
1463 MAX_HWIP
1464};
1465
1466#define HWIP_MAX_INSTANCE 6
1467
11dc9364
RZ		 1468struct amd_powerplay {
1469 struct cgs_device *cgs_device;
1470 void *pp_handle;
1471 const struct amd_ip_funcs *ip_funcs;
1472 const struct amd_pm_funcs *pp_funcs;
1473};
1474
0c49e0b8 1475#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1476struct amdgpu_device {
1477 struct device *dev;
1478 struct drm_device *ddev;
1479 struct pci_dev *pdev;
97b2e202 1480
a8fe58ce
MB		 1481#ifdef CONFIG_DRM_AMD_ACP
1482 struct amdgpu_acp acp;
1483#endif
1484
97b2e202 1485 /* ASIC */
2f7d10b3 1486 enum amd_asic_type asic_type;
97b2e202
AD		 1487 uint32_t family;
1488 uint32_t rev_id;
1489 uint32_t external_rev_id;
1490 unsigned long flags;
1491 int usec_timeout;
1492 const struct amdgpu_asic_funcs *asic_funcs;
1493 bool shutdown;
97b2e202
AD		 1494 bool need_dma32;
1495 bool accel_working;
edf600da 1496 struct work_struct reset_work;
97b2e202
AD		 1497 struct notifier_block acpi_nb;
1498 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1499 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1500 unsigned debugfs_count;
97b2e202 1501#if defined(CONFIG_DEBUG_FS)
adcec288 1502 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1503#endif
1504 struct amdgpu_atif atif;
1505 struct amdgpu_atcs atcs;
1506 struct mutex srbm_mutex;
1507 /* GRBM index mutex. Protects concurrent access to GRBM index */
1508 struct mutex grbm_idx_mutex;
1509 struct dev_pm_domain vga_pm_domain;
1510 bool have_disp_power_ref;
1511
1512 /* BIOS */
0cdd5005 1513 bool is_atom_fw;
97b2e202 1514 uint8_t *bios;
a9f5db9c 1515 uint32_t bios_size;
5af2c10d 1516 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1517 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1518 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1519
1520 /* Register/doorbell mmio */
1521 resource_size_t rmmio_base;
1522 resource_size_t rmmio_size;
1523 void __iomem *rmmio;
1524 /* protects concurrent MM_INDEX/DATA based register access */
1525 spinlock_t mmio_idx_lock;
1526 /* protects concurrent SMC based register access */
1527 spinlock_t smc_idx_lock;
1528 amdgpu_rreg_t smc_rreg;
1529 amdgpu_wreg_t smc_wreg;
1530 /* protects concurrent PCIE register access */
1531 spinlock_t pcie_idx_lock;
1532 amdgpu_rreg_t pcie_rreg;
1533 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1534 amdgpu_rreg_t pciep_rreg;
1535 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1536 /* protects concurrent UVD register access */
1537 spinlock_t uvd_ctx_idx_lock;
1538 amdgpu_rreg_t uvd_ctx_rreg;
1539 amdgpu_wreg_t uvd_ctx_wreg;
1540 /* protects concurrent DIDT register access */
1541 spinlock_t didt_idx_lock;
1542 amdgpu_rreg_t didt_rreg;
1543 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1544 /* protects concurrent gc_cac register access */
1545 spinlock_t gc_cac_idx_lock;
1546 amdgpu_rreg_t gc_cac_rreg;
1547 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1548 /* protects concurrent se_cac register access */
1549 spinlock_t se_cac_idx_lock;
1550 amdgpu_rreg_t se_cac_rreg;
1551 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1552 /* protects concurrent ENDPOINT (audio) register access */
1553 spinlock_t audio_endpt_idx_lock;
1554 amdgpu_block_rreg_t audio_endpt_rreg;
1555 amdgpu_block_wreg_t audio_endpt_wreg;
1556 void __iomem *rio_mem;
1557 resource_size_t rio_mem_size;
1558 struct amdgpu_doorbell doorbell;
1559
1560 /* clock/pll info */
1561 struct amdgpu_clock clock;
1562
1563 /* MC */
1564 struct amdgpu_mc mc;
1565 struct amdgpu_gart gart;
1566 struct amdgpu_dummy_page dummy_page;
1567 struct amdgpu_vm_manager vm_manager;
e60f8db5 1568 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1569
1570 /* memory management */
1571 struct amdgpu_mman mman;
97b2e202
AD		 1572 struct amdgpu_vram_scratch vram_scratch;
1573 struct amdgpu_wb wb;
97b2e202 1574 atomic64_t num_bytes_moved;
dbd5ed60 1575 atomic64_t num_evictions;
68e2c5ff 1576 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1577 atomic_t gpu_reset_counter;
f1892138 1578 atomic_t vram_lost_counter;
97b2e202 1579
95844d20
MO		 1580 /* data for buffer migration throttling */
1581 struct {
1582 spinlock_t lock;
1583 s64 last_update_us;
1584 s64 accum_us; /* accumulated microseconds */
00f06b24 1585 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1586 u32 log2_max_MBps;
1587 } mm_stats;
1588
97b2e202 1589 /* display */
9accf2fd 1590 bool enable_virtual_display;
97b2e202 1591 struct amdgpu_mode_info mode_info;
4562236b 1592 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 1593 struct work_struct hotplug_work;
1594 struct amdgpu_irq_src crtc_irq;
1595 struct amdgpu_irq_src pageflip_irq;
1596 struct amdgpu_irq_src hpd_irq;
1597
1598 /* rings */
76bf0db5 1599 u64 fence_context;
97b2e202
AD		 1600 unsigned num_rings;
1601 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1602 bool ib_pool_ready;
1603 struct amdgpu_sa_manager ring_tmp_bo;
1604
1605 /* interrupts */
1606 struct amdgpu_irq irq;
1607
1f7371b2
AD		 1608 /* powerplay */
1609 struct amd_powerplay powerplay;
f3898ea1 1610 bool pp_force_state_enabled;
1f7371b2 1611
97b2e202
AD		 1612 /* dpm */
1613 struct amdgpu_pm pm;
1614 u32 cg_flags;
1615 u32 pg_flags;
1616
1617 /* amdgpu smumgr */
1618 struct amdgpu_smumgr smu;
1619
1620 /* gfx */
1621 struct amdgpu_gfx gfx;
1622
1623 /* sdma */
c113ea1c 1624 struct amdgpu_sdma sdma;
97b2e202 1625
b43aaee6
LL		 1626 /* uvd */
1627 struct amdgpu_uvd uvd;
1628
1629 /* vce */
1630 struct amdgpu_vce vce;
1631
1632 /* vcn */
1633 struct amdgpu_vcn vcn;
97b2e202
AD		 1634
1635 /* firmwares */
1636 struct amdgpu_firmware firmware;
1637
0e5ca0d1
HR		 1638 /* PSP */
1639 struct psp_context psp;
1640
97b2e202
AD		 1641 /* GDS */
1642 struct amdgpu_gds gds;
1643
4562236b
HW		 1644 /* display related functionality */
1645 struct amdgpu_display_manager dm;
1646
a1255107 1647 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1648 int num_ip_blocks;
97b2e202
AD		 1649 struct mutex mn_lock;
1650 DECLARE_HASHTABLE(mn_hash, 7);
1651
1652 /* tracking pinned memory */
1653 u64 vram_pin_size;
e131b914 1654 u64 invisible_pin_size;
97b2e202 1655 u64 gart_pin_size;
130e0371
OG		 1656
1657 /* amdkfd interface */
1658 struct kfd_dev *kfd;
23ca0e4e 1659
4522824c
SL		 1660 /* soc15 register offset based on ip, instance and segment */
1661 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1662
946a4d5b
SL		 1663 const struct amdgpu_nbio_funcs *nbio_funcs;
1664
2dc80b00
S		 1665 /* delayed work_func for deferring clockgating during resume */
1666 struct delayed_work late_init_work;
1667
5a5099cb 1668 struct amdgpu_virt virt;
a05502e5
HC		 1669 /* firmware VRAM reservation */
1670 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1671
1672 /* link all shadow bo */
1673 struct list_head shadow_list;
1674 struct mutex shadow_list_lock;
795f2813
AR		 1675 /* keep an lru list of rings by HW IP */
1676 struct list_head ring_lru_list;
1677 spinlock_t ring_lru_list_lock;
5c1354bd 1678
c836fec5
JQ		 1679 /* record hw reset is performed */
1680 bool has_hw_reset;
0c49e0b8 1681 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1682
47ed4e1c
KW		 1683 /* record last mm index being written through WREG32*/
1684 unsigned long last_mm_index;
13a752e3
ML		 1685 bool in_gpu_reset;
1686 struct mutex lock_reset;
97b2e202
AD		 1687};
1688
a7d64de6
CK		 1689static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1690{
1691 return container_of(bdev, struct amdgpu_device, mman.bdev);
1692}
1693
97b2e202
AD		 1694int amdgpu_device_init(struct amdgpu_device *adev,
1695 struct drm_device *ddev,
1696 struct pci_dev *pdev,
1697 uint32_t flags);
1698void amdgpu_device_fini(struct amdgpu_device *adev);
1699int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1700
1701uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1702 uint32_t acc_flags);
97b2e202 1703void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1704 uint32_t acc_flags);
97b2e202
AD		 1705u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1706void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1707
1708u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1709void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1710u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1711void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1712
4562236b
HW		 1713bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1714bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1715
97b2e202
AD		 1716/*
1717 * Registers read & write functions.
1718 */
15d72fd7
ML		 1719
1720#define AMDGPU_REGS_IDX (1<<0)
1721#define AMDGPU_REGS_NO_KIQ (1<<1)
1722
1723#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1724#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1725
1726#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1727#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1728#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1729#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1730#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1731#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1732#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1733#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1734#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1735#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1736#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1737#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1738#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1739#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1740#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1741#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1742#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1743#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1744#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1745#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1746#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1747#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1748#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1749#define WREG32_P(reg, val, mask) \
1750 do { \
1751 uint32_t tmp_ = RREG32(reg); \
1752 tmp_ &= (mask); \
1753 tmp_ |= ((val) & ~(mask)); \
1754 WREG32(reg, tmp_); \
1755 } while (0)
1756#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1757#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1758#define WREG32_PLL_P(reg, val, mask) \
1759 do { \
1760 uint32_t tmp_ = RREG32_PLL(reg); \
1761 tmp_ &= (mask); \
1762 tmp_ |= ((val) & ~(mask)); \
1763 WREG32_PLL(reg, tmp_); \
1764 } while (0)
1765#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1766#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1767#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1768
1769#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1770#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1771#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1772#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1773
1774#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1775#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1776
1777#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1778 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1779 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1780
1781#define REG_GET_FIELD(value, reg, field) \
1782 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1783
1784#define WREG32_FIELD(reg, field, val) \
1785 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1786
ccaf3574
TSD		 1787#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1788 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1789
97b2e202
AD		 1790/*
1791 * BIOS helpers.
1792 */
1793#define RBIOS8(i) (adev->bios[i])
1794#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1795#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1796
c113ea1c
AD		 1797static inline struct amdgpu_sdma_instance *
1798amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1799{
1800 struct amdgpu_device *adev = ring->adev;
1801 int i;
1802
c113ea1c
AD		 1803 for (i = 0; i < adev->sdma.num_instances; i++)
1804 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1805 break;
1806
1807 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1808 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1809 else
1810 return NULL;
1811}
1812
97b2e202
AD		 1813/*
1814 * ASICs macro.
1815 */
1816#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1817#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1818#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1819#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1820#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1821#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1822#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1823#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1824#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1825#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1826#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1827#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1828#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1829#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
3de676d8 1830#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
97b2e202 1831#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1832#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1833#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1834#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1835#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1836#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1837#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1838#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1839#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1840#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1841#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1842#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1843#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1844#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1845#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1846#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1847#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1848#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1849#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1850#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1851#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1852#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1853#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1854#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1855#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1856#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1857#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1858#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1859#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1860#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1861#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1862#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1863#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1864#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1865#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1866#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1867#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1868#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1869#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1870#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1871#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1872#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1873#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1874#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1875#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1876#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1877#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1878
1879/* Common functions */
5740682e 1880int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);
3ad81f16 1881bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1882void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1883bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1884void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1885
00f06b24
JB		 1886void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1887 u64 num_vis_bytes);
765e7fbf 1888void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1889bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1890void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1891void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
d6895ad3 1892int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
97b2e202 1893void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1894int amdgpu_ttm_init(struct amdgpu_device *adev);
1895void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1896void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1897 const u32 *registers,
1898 const u32 array_size);
1899
1900bool amdgpu_device_is_px(struct drm_device *dev);
1901/* atpx handler */
1902#if defined(CONFIG_VGA_SWITCHEROO)
1903void amdgpu_register_atpx_handler(void);
1904void amdgpu_unregister_atpx_handler(void);
a78fe133 1905bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1906bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1907bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1908bool amdgpu_has_atpx(void);
97b2e202
AD		 1909#else
1910static inline void amdgpu_register_atpx_handler(void) {}
1911static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1912static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1913static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1914static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1915static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1916#endif
1917
1918/*
1919 * KMS
1920 */
1921extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1922extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1923
1924int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1925void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1926void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1927int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1928void amdgpu_driver_postclose_kms(struct drm_device *dev,
1929 struct drm_file *file_priv);
faefba95 1930int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1931int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1932int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1933u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1934int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1935void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1936long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1937 unsigned long arg);
1938
97b2e202
AD		 1939/*
1940 * functions used by amdgpu_encoder.c
1941 */
1942struct amdgpu_afmt_acr {
1943 u32 clock;
1944
1945 int n_32khz;
1946 int cts_32khz;
1947
1948 int n_44_1khz;
1949 int cts_44_1khz;
1950
1951 int n_48khz;
1952 int cts_48khz;
1953
1954};
1955
1956struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1957
1958/* amdgpu_acpi.c */
1959#if defined(CONFIG_ACPI)
1960int amdgpu_acpi_init(struct amdgpu_device *adev);
1961void amdgpu_acpi_fini(struct amdgpu_device *adev);
1962bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1963int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1964 u8 perf_req, bool advertise);
1965int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1966#else
1967static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1968static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1969#endif
1970
9cca0b8e
CK		 1971int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1972 uint64_t addr, struct amdgpu_bo **bo,
1973 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1974
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HW		 1975#if defined(CONFIG_DRM_AMD_DC)
1976int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1977#else
1978static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1979#endif
1980
97b2e202 1981#include "amdgpu_object.h"
97b2e202 1982#endif
Linux 6.x block layer and io_uring tree(s)