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drm/amdgpu: add VRAM manager v2
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
c632d799 54#include "amdgpu_ttm.h"
97b2e202 55#include "amdgpu_gds.h"
1f7371b2 56#include "amd_powerplay.h"
a8fe58ce 57#include "amdgpu_acp.h"
97b2e202 58
b80d8475 59#include "gpu_scheduler.h"
ceeb50ed 60#include "amdgpu_virt.h"
b80d8475 61
97b2e202
AD		 62/*
63 * Modules parameters.
64 */
65extern int amdgpu_modeset;
66extern int amdgpu_vram_limit;
67extern int amdgpu_gart_size;
95844d20 68extern int amdgpu_moverate;
97b2e202
AD		 69extern int amdgpu_benchmarking;
70extern int amdgpu_testing;
71extern int amdgpu_audio;
72extern int amdgpu_disp_priority;
73extern int amdgpu_hw_i2c;
74extern int amdgpu_pcie_gen2;
75extern int amdgpu_msi;
76extern int amdgpu_lockup_timeout;
77extern int amdgpu_dpm;
78extern int amdgpu_smc_load_fw;
79extern int amdgpu_aspm;
80extern int amdgpu_runtime_pm;
97b2e202
AD		 81extern unsigned amdgpu_ip_block_mask;
82extern int amdgpu_bapm;
83extern int amdgpu_deep_color;
84extern int amdgpu_vm_size;
85extern int amdgpu_vm_block_size;
d9c13156 86extern int amdgpu_vm_fault_stop;
b495bd3a 87extern int amdgpu_vm_debug;
1333f723 88extern int amdgpu_sched_jobs;
4afcb303 89extern int amdgpu_sched_hw_submission;
1f7371b2 90extern int amdgpu_powerplay;
6bb6b297 91extern int amdgpu_powercontainment;
cd474ba0
AD		 92extern unsigned amdgpu_pcie_gen_cap;
93extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 94extern unsigned amdgpu_cg_mask;
95extern unsigned amdgpu_pg_mask;
6f8941a2 96extern char *amdgpu_disable_cu;
66bc3f7f 97extern int amdgpu_sclk_deep_sleep_en;
9accf2fd 98extern char *amdgpu_virtual_display;
5141e9d2 99extern unsigned amdgpu_pp_feature_mask;
6a7f76e7 100extern int amdgpu_vram_page_split;
97b2e202 101
4b559c90 102#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 103#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
106#define AMDGPU_IB_POOL_SIZE 16
107#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
108#define AMDGPUFB_CONN_LIMIT 4
109#define AMDGPU_BIOS_NUM_SCRATCH 8
110
97b2e202
AD		 111/* max number of rings */
112#define AMDGPU_MAX_RINGS 16
113#define AMDGPU_MAX_GFX_RINGS 1
114#define AMDGPU_MAX_COMPUTE_RINGS 8
6f0359ff 115#define AMDGPU_MAX_VCE_RINGS 3
97b2e202 116
36f523a7
JZ		 117/* max number of IP instances */
118#define AMDGPU_MAX_SDMA_INSTANCES 2
119
97b2e202
AD		 120/* hardcode that limit for now */
121#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
122
123/* hard reset data */
124#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
125
126/* reset flags */
127#define AMDGPU_RESET_GFX (1 << 0)
128#define AMDGPU_RESET_COMPUTE (1 << 1)
129#define AMDGPU_RESET_DMA (1 << 2)
130#define AMDGPU_RESET_CP (1 << 3)
131#define AMDGPU_RESET_GRBM (1 << 4)
132#define AMDGPU_RESET_DMA1 (1 << 5)
133#define AMDGPU_RESET_RLC (1 << 6)
134#define AMDGPU_RESET_SEM (1 << 7)
135#define AMDGPU_RESET_IH (1 << 8)
136#define AMDGPU_RESET_VMC (1 << 9)
137#define AMDGPU_RESET_MC (1 << 10)
138#define AMDGPU_RESET_DISPLAY (1 << 11)
139#define AMDGPU_RESET_UVD (1 << 12)
140#define AMDGPU_RESET_VCE (1 << 13)
141#define AMDGPU_RESET_VCE1 (1 << 14)
142
97b2e202
AD		 143/* GFX current status */
144#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
145#define AMDGPU_GFX_SAFE_MODE 0x00000001L
146#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
147#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
148#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
149
150/* max cursor sizes (in pixels) */
151#define CIK_CURSOR_WIDTH 128
152#define CIK_CURSOR_HEIGHT 128
153
154struct amdgpu_device;
97b2e202
AD		 155struct amdgpu_ib;
156struct amdgpu_vm;
157struct amdgpu_ring;
97b2e202 158struct amdgpu_cs_parser;
bb977d37 159struct amdgpu_job;
97b2e202 160struct amdgpu_irq_src;
0b492a4c 161struct amdgpu_fpriv;
97b2e202
AD		 162
163enum amdgpu_cp_irq {
164 AMDGPU_CP_IRQ_GFX_EOP = 0,
165 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
170 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
171 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
173
174 AMDGPU_CP_IRQ_LAST
175};
176
177enum amdgpu_sdma_irq {
178 AMDGPU_SDMA_IRQ_TRAP0 = 0,
179 AMDGPU_SDMA_IRQ_TRAP1,
180
181 AMDGPU_SDMA_IRQ_LAST
182};
183
184enum amdgpu_thermal_irq {
185 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
186 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
187
188 AMDGPU_THERMAL_IRQ_LAST
189};
190
97b2e202 191int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 192 enum amd_ip_block_type block_type,
193 enum amd_clockgating_state state);
97b2e202 194int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 195 enum amd_ip_block_type block_type,
196 enum amd_powergating_state state);
5dbbb60b
AD		 197int amdgpu_wait_for_idle(struct amdgpu_device *adev,
198 enum amd_ip_block_type block_type);
199bool amdgpu_is_idle(struct amdgpu_device *adev,
200 enum amd_ip_block_type block_type);
97b2e202
AD		 201
202struct amdgpu_ip_block_version {
5fc3aeeb 203 enum amd_ip_block_type type;
97b2e202
AD		 204 u32 major;
205 u32 minor;
206 u32 rev;
5fc3aeeb 207 const struct amd_ip_funcs *funcs;
97b2e202
AD		 208};
209
210int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 211 enum amd_ip_block_type type,
97b2e202
AD		 212 u32 major, u32 minor);
213
214const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
215 struct amdgpu_device *adev,
5fc3aeeb 216 enum amd_ip_block_type type);
97b2e202
AD		 217
218/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
219struct amdgpu_buffer_funcs {
220 /* maximum bytes in a single operation */
221 uint32_t copy_max_bytes;
222
223 /* number of dw to reserve per operation */
224 unsigned copy_num_dw;
225
226 /* used for buffer migration */
c7ae72c0 227 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 228 /* src addr in bytes */
229 uint64_t src_offset,
230 /* dst addr in bytes */
231 uint64_t dst_offset,
232 /* number of byte to transfer */
233 uint32_t byte_count);
234
235 /* maximum bytes in a single operation */
236 uint32_t fill_max_bytes;
237
238 /* number of dw to reserve per operation */
239 unsigned fill_num_dw;
240
241 /* used for buffer clearing */
6e7a3840 242 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 243 /* value to write to memory */
244 uint32_t src_data,
245 /* dst addr in bytes */
246 uint64_t dst_offset,
247 /* number of byte to fill */
248 uint32_t byte_count);
249};
250
251/* provided by hw blocks that can write ptes, e.g., sdma */
252struct amdgpu_vm_pte_funcs {
253 /* copy pte entries from GART */
254 void (*copy_pte)(struct amdgpu_ib *ib,
255 uint64_t pe, uint64_t src,
256 unsigned count);
257 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 258 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
259 uint64_t value, unsigned count,
260 uint32_t incr);
97b2e202
AD		 261 /* for linear pte/pde updates without addr mapping */
262 void (*set_pte_pde)(struct amdgpu_ib *ib,
263 uint64_t pe,
264 uint64_t addr, unsigned count,
265 uint32_t incr, uint32_t flags);
97b2e202
AD		 266};
267
268/* provided by the gmc block */
269struct amdgpu_gart_funcs {
270 /* flush the vm tlb via mmio */
271 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
272 uint32_t vmid);
273 /* write pte/pde updates using the cpu */
274 int (*set_pte_pde)(struct amdgpu_device *adev,
275 void *cpu_pt_addr, /* cpu addr of page table */
276 uint32_t gpu_page_idx, /* pte/pde to update */
277 uint64_t addr, /* addr to write into pte/pde */
278 uint32_t flags); /* access flags */
279};
280
281/* provided by the ih block */
282struct amdgpu_ih_funcs {
283 /* ring read/write ptr handling, called from interrupt context */
284 u32 (*get_wptr)(struct amdgpu_device *adev);
285 void (*decode_iv)(struct amdgpu_device *adev,
286 struct amdgpu_iv_entry *entry);
287 void (*set_rptr)(struct amdgpu_device *adev);
288};
289
290/* provided by hw blocks that expose a ring buffer for commands */
291struct amdgpu_ring_funcs {
292 /* ring read/write ptr handling */
293 u32 (*get_rptr)(struct amdgpu_ring *ring);
294 u32 (*get_wptr)(struct amdgpu_ring *ring);
295 void (*set_wptr)(struct amdgpu_ring *ring);
296 /* validating and patching of IBs */
297 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
298 /* command emit functions */
299 void (*emit_ib)(struct amdgpu_ring *ring,
d88bf583
CK		 300 struct amdgpu_ib *ib,
301 unsigned vm_id, bool ctx_switch);
97b2e202 302 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 303 uint64_t seq, unsigned flags);
b8c7b39e 304 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 305 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
306 uint64_t pd_addr);
d2edb07b 307 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 308 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 309 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
310 uint32_t gds_base, uint32_t gds_size,
311 uint32_t gws_base, uint32_t gws_size,
312 uint32_t oa_base, uint32_t oa_size);
313 /* testing functions */
314 int (*test_ring)(struct amdgpu_ring *ring);
bbec97aa 315 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
edff0e28
JZ		 316 /* insert NOP packets */
317 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 318 /* pad the indirect buffer to the necessary number of dw */
319 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
03ccf481
ML		 320 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
321 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
f06505b8
CK		 322 /* note usage for clock and power gating */
323 void (*begin_use)(struct amdgpu_ring *ring);
324 void (*end_use)(struct amdgpu_ring *ring);
c2167a65 325 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
753ad49c 326 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
b6384ff5
AD		 327 unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring);
328 unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring);
97b2e202
AD		 329};
330
331/*
332 * BIOS.
333 */
334bool amdgpu_get_bios(struct amdgpu_device *adev);
335bool amdgpu_read_bios(struct amdgpu_device *adev);
336
337/*
338 * Dummy page
339 */
340struct amdgpu_dummy_page {
341 struct page *page;
342 dma_addr_t addr;
343};
344int amdgpu_dummy_page_init(struct amdgpu_device *adev);
345void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
346
347
348/*
349 * Clocks
350 */
351
352#define AMDGPU_MAX_PPLL 3
353
354struct amdgpu_clock {
355 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
356 struct amdgpu_pll spll;
357 struct amdgpu_pll mpll;
358 /* 10 Khz units */
359 uint32_t default_mclk;
360 uint32_t default_sclk;
361 uint32_t default_dispclk;
362 uint32_t current_dispclk;
363 uint32_t dp_extclk;
364 uint32_t max_pixel_clock;
365};
366
367/*
368 * Fences.
369 */
370struct amdgpu_fence_driver {
97b2e202
AD		 371 uint64_t gpu_addr;
372 volatile uint32_t *cpu_addr;
373 /* sync_seq is protected by ring emission lock */
742c085f
CK		 374 uint32_t sync_seq;
375 atomic_t last_seq;
97b2e202 376 bool initialized;
97b2e202
AD		 377 struct amdgpu_irq_src *irq_src;
378 unsigned irq_type;
c2776afe 379 struct timer_list fallback_timer;
c89377d1 380 unsigned num_fences_mask;
4a7d74f1 381 spinlock_t lock;
c89377d1 382 struct fence **fences;
97b2e202
AD		 383};
384
385/* some special values for the owner field */
386#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
387#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 388
890ee23f
CZ		 389#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
390#define AMDGPU_FENCE_FLAG_INT (1 << 1)
391
97b2e202
AD		 392int amdgpu_fence_driver_init(struct amdgpu_device *adev);
393void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
394void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
395
e6151a08
CK		 396int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
397 unsigned num_hw_submission);
97b2e202
AD		 398int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
399 struct amdgpu_irq_src *irq_src,
400 unsigned irq_type);
5ceb54c6
AD		 401void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
402void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 403int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202 404void amdgpu_fence_process(struct amdgpu_ring *ring);
97b2e202
AD		 405int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
406unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
407
97b2e202 408/*
c632d799 409 * BO.
97b2e202 410 */
97b2e202
AD		 411struct amdgpu_bo_list_entry {
412 struct amdgpu_bo *robj;
413 struct ttm_validate_buffer tv;
414 struct amdgpu_bo_va *bo_va;
97b2e202 415 uint32_t priority;
2f568dbd
CK		 416 struct page **user_pages;
417 int user_invalidated;
97b2e202
AD		 418};
419
420struct amdgpu_bo_va_mapping {
421 struct list_head list;
422 struct interval_tree_node it;
423 uint64_t offset;
424 uint32_t flags;
425};
426
427/* bo virtual addresses in a specific vm */
428struct amdgpu_bo_va {
429 /* protected by bo being reserved */
430 struct list_head bo_list;
bb1e38a4 431 struct fence *last_pt_update;
97b2e202
AD		 432 unsigned ref_count;
433
7fc11959 434 /* protected by vm mutex and spinlock */
97b2e202
AD		 435 struct list_head vm_status;
436
7fc11959
CK		 437 /* mappings for this bo_va */
438 struct list_head invalids;
439 struct list_head valids;
440
97b2e202
AD		 441 /* constant after initialization */
442 struct amdgpu_vm *vm;
443 struct amdgpu_bo *bo;
444};
445
7e5a547f
CZ		 446#define AMDGPU_GEM_DOMAIN_MAX 0x3
447
97b2e202 448struct amdgpu_bo {
97b2e202 449 /* Protected by tbo.reserved */
1ea863fd
CK		 450 u32 prefered_domains;
451 u32 allowed_domains;
7e5a547f 452 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 453 struct ttm_placement placement;
454 struct ttm_buffer_object tbo;
455 struct ttm_bo_kmap_obj kmap;
456 u64 flags;
457 unsigned pin_count;
458 void *kptr;
459 u64 tiling_flags;
460 u64 metadata_flags;
461 void *metadata;
462 u32 metadata_size;
463 /* list of all virtual address to which this bo
464 * is associated to
465 */
466 struct list_head va;
467 /* Constant after initialization */
468 struct amdgpu_device *adev;
469 struct drm_gem_object gem_base;
82b9c55b 470 struct amdgpu_bo *parent;
e7893c4b 471 struct amdgpu_bo *shadow;
97b2e202
AD		 472
473 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 474 struct amdgpu_mn *mn;
475 struct list_head mn_list;
0c4e7fa5 476 struct list_head shadow_list;
97b2e202
AD		 477};
478#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
479
480void amdgpu_gem_object_free(struct drm_gem_object *obj);
481int amdgpu_gem_object_open(struct drm_gem_object *obj,
482 struct drm_file *file_priv);
483void amdgpu_gem_object_close(struct drm_gem_object *obj,
484 struct drm_file *file_priv);
485unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
486struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 487struct drm_gem_object *
488amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
489 struct dma_buf_attachment *attach,
490 struct sg_table *sg);
97b2e202
AD		 491struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
492 struct drm_gem_object *gobj,
493 int flags);
494int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
495void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
496struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
497void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
498void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
499int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
500
501/* sub-allocation manager, it has to be protected by another lock.
502 * By conception this is an helper for other part of the driver
503 * like the indirect buffer or semaphore, which both have their
504 * locking.
505 *
506 * Principe is simple, we keep a list of sub allocation in offset
507 * order (first entry has offset == 0, last entry has the highest
508 * offset).
509 *
510 * When allocating new object we first check if there is room at
511 * the end total_size - (last_object_offset + last_object_size) >=
512 * alloc_size. If so we allocate new object there.
513 *
514 * When there is not enough room at the end, we start waiting for
515 * each sub object until we reach object_offset+object_size >=
516 * alloc_size, this object then become the sub object we return.
517 *
518 * Alignment can't be bigger than page size.
519 *
520 * Hole are not considered for allocation to keep things simple.
521 * Assumption is that there won't be hole (all object on same
522 * alignment).
523 */
6ba60b89
CK		 524
525#define AMDGPU_SA_NUM_FENCE_LISTS 32
526
97b2e202
AD		 527struct amdgpu_sa_manager {
528 wait_queue_head_t wq;
529 struct amdgpu_bo *bo;
530 struct list_head *hole;
6ba60b89 531 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 532 struct list_head olist;
533 unsigned size;
534 uint64_t gpu_addr;
535 void *cpu_ptr;
536 uint32_t domain;
537 uint32_t align;
538};
539
97b2e202
AD		 540/* sub-allocation buffer */
541struct amdgpu_sa_bo {
542 struct list_head olist;
543 struct list_head flist;
544 struct amdgpu_sa_manager *manager;
545 unsigned soffset;
546 unsigned eoffset;
4ce9891e 547 struct fence *fence;
97b2e202
AD		 548};
549
550/*
551 * GEM objects.
552 */
418aa0c2 553void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 554int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
555 int alignment, u32 initial_domain,
556 u64 flags, bool kernel,
557 struct drm_gem_object **obj);
558
559int amdgpu_mode_dumb_create(struct drm_file *file_priv,
560 struct drm_device *dev,
561 struct drm_mode_create_dumb *args);
562int amdgpu_mode_dumb_mmap(struct drm_file *filp,
563 struct drm_device *dev,
564 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 565/*
566 * Synchronization
567 */
568struct amdgpu_sync {
f91b3a69 569 DECLARE_HASHTABLE(fences, 4);
3c62338c 570 struct fence *last_vm_update;
97b2e202
AD		 571};
572
573void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 574int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
575 struct fence *f);
97b2e202
AD		 576int amdgpu_sync_resv(struct amdgpu_device *adev,
577 struct amdgpu_sync *sync,
578 struct reservation_object *resv,
579 void *owner);
1fbb2e92
CK		 580struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
581 struct amdgpu_ring *ring);
e61235db 582struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
8a8f0b48 583void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 584int amdgpu_sync_init(void);
585void amdgpu_sync_fini(void);
d573de2d
RZ		 586int amdgpu_fence_slab_init(void);
587void amdgpu_fence_slab_fini(void);
97b2e202
AD		 588
589/*
590 * GART structures, functions & helpers
591 */
592struct amdgpu_mc;
593
594#define AMDGPU_GPU_PAGE_SIZE 4096
595#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
596#define AMDGPU_GPU_PAGE_SHIFT 12
597#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
598
599struct amdgpu_gart {
600 dma_addr_t table_addr;
601 struct amdgpu_bo *robj;
602 void *ptr;
603 unsigned num_gpu_pages;
604 unsigned num_cpu_pages;
605 unsigned table_size;
a1d29476 606#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 607 struct page **pages;
a1d29476 608#endif
97b2e202
AD		 609 bool ready;
610 const struct amdgpu_gart_funcs *gart_funcs;
611};
612
613int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
614void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
615int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
616void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
617int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
618void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
619int amdgpu_gart_init(struct amdgpu_device *adev);
620void amdgpu_gart_fini(struct amdgpu_device *adev);
cab0b8d5 621void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 622 int pages);
cab0b8d5 623int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
97b2e202
AD		 624 int pages, struct page **pagelist,
625 dma_addr_t *dma_addr, uint32_t flags);
2c0d7318 626int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
97b2e202
AD		 627
628/*
629 * GPU MC structures, functions & helpers
630 */
631struct amdgpu_mc {
632 resource_size_t aper_size;
633 resource_size_t aper_base;
634 resource_size_t agp_base;
635 /* for some chips with <= 32MB we need to lie
636 * about vram size near mc fb location */
637 u64 mc_vram_size;
638 u64 visible_vram_size;
639 u64 gtt_size;
640 u64 gtt_start;
641 u64 gtt_end;
642 u64 vram_start;
643 u64 vram_end;
644 unsigned vram_width;
645 u64 real_vram_size;
646 int vram_mtrr;
647 u64 gtt_base_align;
648 u64 mc_mask;
649 const struct firmware *fw; /* MC firmware */
650 uint32_t fw_version;
651 struct amdgpu_irq_src vm_fault;
81c59f54 652 uint32_t vram_type;
50b0197a
CZ		 653 uint32_t srbm_soft_reset;
654 struct amdgpu_mode_mc_save save;
97b2e202
AD		 655};
656
657/*
658 * GPU doorbell structures, functions & helpers
659 */
660typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
661{
662 AMDGPU_DOORBELL_KIQ = 0x000,
663 AMDGPU_DOORBELL_HIQ = 0x001,
664 AMDGPU_DOORBELL_DIQ = 0x002,
665 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
666 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
667 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
668 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
669 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
670 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
671 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
672 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
673 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
674 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
675 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
676 AMDGPU_DOORBELL_IH = 0x1E8,
677 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
678 AMDGPU_DOORBELL_INVALID = 0xFFFF
679} AMDGPU_DOORBELL_ASSIGNMENT;
680
681struct amdgpu_doorbell {
682 /* doorbell mmio */
683 resource_size_t base;
684 resource_size_t size;
685 u32 __iomem *ptr;
686 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
687};
688
689void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
690 phys_addr_t *aperture_base,
691 size_t *aperture_size,
692 size_t *start_offset);
693
694/*
695 * IRQS.
696 */
697
698struct amdgpu_flip_work {
325cbba1 699 struct delayed_work flip_work;
97b2e202
AD		 700 struct work_struct unpin_work;
701 struct amdgpu_device *adev;
702 int crtc_id;
325cbba1 703 u32 target_vblank;
97b2e202
AD		 704 uint64_t base;
705 struct drm_pending_vblank_event *event;
765e7fbf 706 struct amdgpu_bo *old_abo;
1ffd2652
CK		 707 struct fence *excl;
708 unsigned shared_count;
709 struct fence **shared;
c3874b75 710 struct fence_cb cb;
cb9e59d7 711 bool async;
97b2e202
AD		 712};
713
714
715/*
716 * CP & rings.
717 */
718
719struct amdgpu_ib {
720 struct amdgpu_sa_bo *sa_bo;
721 uint32_t length_dw;
722 uint64_t gpu_addr;
723 uint32_t *ptr;
de807f81 724 uint32_t flags;
97b2e202
AD		 725};
726
727enum amdgpu_ring_type {
728 AMDGPU_RING_TYPE_GFX,
729 AMDGPU_RING_TYPE_COMPUTE,
730 AMDGPU_RING_TYPE_SDMA,
731 AMDGPU_RING_TYPE_UVD,
732 AMDGPU_RING_TYPE_VCE
733};
734
62250a91 735extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 736
50838c8c 737int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 738 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 739int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
740 struct amdgpu_job **job);
b6723c8d 741
a5fb4ec2 742void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 743void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 744int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 745 struct amd_sched_entity *entity, void *owner,
746 struct fence **f);
3c704e93 747
97b2e202
AD		 748struct amdgpu_ring {
749 struct amdgpu_device *adev;
750 const struct amdgpu_ring_funcs *funcs;
751 struct amdgpu_fence_driver fence_drv;
edf600da 752 struct amd_gpu_scheduler sched;
97b2e202 753
97b2e202
AD		 754 struct amdgpu_bo *ring_obj;
755 volatile uint32_t *ring;
756 unsigned rptr_offs;
97b2e202
AD		 757 unsigned wptr;
758 unsigned wptr_old;
759 unsigned ring_size;
c7e6be23 760 unsigned max_dw;
97b2e202 761 int count_dw;
97b2e202
AD		 762 uint64_t gpu_addr;
763 uint32_t align_mask;
764 uint32_t ptr_mask;
765 bool ready;
766 u32 nop;
767 u32 idx;
97b2e202
AD		 768 u32 me;
769 u32 pipe;
770 u32 queue;
771 struct amdgpu_bo *mqd_obj;
772 u32 doorbell_index;
773 bool use_doorbell;
774 unsigned wptr_offs;
97b2e202 775 unsigned fence_offs;
aa3b73f6 776 uint64_t current_ctx;
97b2e202
AD		 777 enum amdgpu_ring_type type;
778 char name[16];
128cff1a 779 unsigned cond_exe_offs;
92c023c4
CK		 780 u64 cond_exe_gpu_addr;
781 volatile u32 *cond_exe_cpu_addr;
a909c6bd
ML		 782#if defined(CONFIG_DEBUG_FS)
783 struct dentry *ent;
784#endif
97b2e202
AD		 785};
786
787/*
788 * VM
789 */
790
791/* maximum number of VMIDs */
792#define AMDGPU_NUM_VM 16
793
96105e53
CK		 794/* Maximum number of PTEs the hardware can write with one command */
795#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
796
97b2e202
AD		 797/* number of entries in page table */
798#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
799
800/* PTBs (Page Table Blocks) need to be aligned to 32K */
801#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
97b2e202 802
1303c73c
CK		 803/* LOG2 number of continuous pages for the fragment field */
804#define AMDGPU_LOG2_PAGES_PER_FRAG 4
805
97b2e202
AD		 806#define AMDGPU_PTE_VALID (1 << 0)
807#define AMDGPU_PTE_SYSTEM (1 << 1)
808#define AMDGPU_PTE_SNOOPED (1 << 2)
809
810/* VI only */
811#define AMDGPU_PTE_EXECUTABLE (1 << 4)
812
813#define AMDGPU_PTE_READABLE (1 << 5)
814#define AMDGPU_PTE_WRITEABLE (1 << 6)
815
1303c73c 816#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
97b2e202 817
d9c13156
CK		 818/* How to programm VM fault handling */
819#define AMDGPU_VM_FAULT_STOP_NEVER 0
820#define AMDGPU_VM_FAULT_STOP_FIRST 1
821#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
822
97b2e202 823struct amdgpu_vm_pt {
ee1782c3
CK		 824 struct amdgpu_bo_list_entry entry;
825 uint64_t addr;
6557e3d2 826 uint64_t shadow_addr;
97b2e202
AD		 827};
828
97b2e202 829struct amdgpu_vm {
25cfc3c2 830 /* tree of virtual addresses mapped */
97b2e202
AD		 831 struct rb_root va;
832
7fc11959 833 /* protecting invalidated */
97b2e202
AD		 834 spinlock_t status_lock;
835
836 /* BOs moved, but not yet updated in the PT */
837 struct list_head invalidated;
838
7fc11959
CK		 839 /* BOs cleared in the PT because of a move */
840 struct list_head cleared;
841
842 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 843 struct list_head freed;
844
845 /* contains the page directory */
846 struct amdgpu_bo *page_directory;
847 unsigned max_pde_used;
05906dec 848 struct fence *page_directory_fence;
5a712a87 849 uint64_t last_eviction_counter;
97b2e202
AD		 850
851 /* array of page tables, one for each page directory entry */
852 struct amdgpu_vm_pt *page_tables;
853
854 /* for id and flush management per ring */
bcb1ba35 855 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
25cfc3c2 856
81d75a30 857 /* protecting freed */
858 spinlock_t freed_lock;
2bd9ccfa
CK		 859
860 /* Scheduler entity for page table updates */
861 struct amd_sched_entity entity;
031e2983
CZ		 862
863 /* client id */
864 u64 client_id;
97b2e202
AD		 865};
866
bcb1ba35 867struct amdgpu_vm_id {
a9a78b32 868 struct list_head list;
832a902f
CK		 869 struct fence *first;
870 struct amdgpu_sync active;
41d9eb2c 871 struct fence *last_flush;
0ea54b9b 872 atomic64_t owner;
971fe9a9 873
bcb1ba35
CK		 874 uint64_t pd_gpu_addr;
875 /* last flushed PD/PT update */
876 struct fence *flushed_updates;
877
6adb0513
CZ		 878 uint32_t current_gpu_reset_count;
879
971fe9a9
CK		 880 uint32_t gds_base;
881 uint32_t gds_size;
882 uint32_t gws_base;
883 uint32_t gws_size;
884 uint32_t oa_base;
885 uint32_t oa_size;
a9a78b32
CK		 886};
887
97b2e202 888struct amdgpu_vm_manager {
a9a78b32 889 /* Handling of VMIDs */
8d0a7cea 890 struct mutex lock;
a9a78b32
CK		 891 unsigned num_ids;
892 struct list_head ids_lru;
bcb1ba35 893 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
1c16c0a7 894
1fbb2e92
CK		 895 /* Handling of VM fences */
896 u64 fence_context;
897 unsigned seqno[AMDGPU_MAX_RINGS];
898
8b4fb00b 899 uint32_t max_pfn;
97b2e202 900 /* vram base address for page table entry */
8b4fb00b 901 u64 vram_base_offset;
97b2e202 902 /* is vm enabled? */
8b4fb00b 903 bool enabled;
97b2e202
AD		 904 /* vm pte handling */
905 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 906 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
907 unsigned vm_pte_num_rings;
908 atomic_t vm_pte_next_ring;
031e2983
CZ		 909 /* client id counter */
910 atomic64_t client_counter;
97b2e202
AD		 911};
912
a9a78b32 913void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 914void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 915int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
916void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 917void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
918 struct list_head *validated,
919 struct amdgpu_bo_list_entry *entry);
5a712a87
CK		 920void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
921 struct list_head *duplicates);
eceb8a15
CK		 922void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
923 struct amdgpu_vm *vm);
8b4fb00b 924int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83 925 struct amdgpu_sync *sync, struct fence *fence,
fd53be30
CZ		 926 struct amdgpu_job *job);
927int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
971fe9a9 928void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
8b4fb00b
CK		 929int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
930 struct amdgpu_vm *vm);
931int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
932 struct amdgpu_vm *vm);
933int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
934 struct amdgpu_sync *sync);
935int amdgpu_vm_bo_update(struct amdgpu_device *adev,
936 struct amdgpu_bo_va *bo_va,
99e124f4 937 bool clear);
8b4fb00b
CK		 938void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
939 struct amdgpu_bo *bo);
940struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
941 struct amdgpu_bo *bo);
942struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
943 struct amdgpu_vm *vm,
944 struct amdgpu_bo *bo);
945int amdgpu_vm_bo_map(struct amdgpu_device *adev,
946 struct amdgpu_bo_va *bo_va,
947 uint64_t addr, uint64_t offset,
948 uint64_t size, uint32_t flags);
949int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
950 struct amdgpu_bo_va *bo_va,
951 uint64_t addr);
952void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
953 struct amdgpu_bo_va *bo_va);
8b4fb00b 954
97b2e202
AD		 955/*
956 * context related structures
957 */
958
21c16bf6 959struct amdgpu_ctx_ring {
91404fb2 960 uint64_t sequence;
37cd0ca2 961 struct fence **fences;
91404fb2 962 struct amd_sched_entity entity;
21c16bf6
CK		 963};
964
97b2e202 965struct amdgpu_ctx {
0b492a4c 966 struct kref refcount;
9cb7e5a9 967 struct amdgpu_device *adev;
0b492a4c 968 unsigned reset_counter;
21c16bf6 969 spinlock_t ring_lock;
37cd0ca2 970 struct fence **fences;
21c16bf6 971 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 972 bool preamble_presented;
97b2e202
AD		 973};
974
975struct amdgpu_ctx_mgr {
0b492a4c
AD		 976 struct amdgpu_device *adev;
977 struct mutex lock;
978 /* protected by lock */
979 struct idr ctx_handles;
97b2e202
AD		 980};
981
0b492a4c
AD		 982struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
983int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
984
21c16bf6 985uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 986 struct fence *fence);
21c16bf6
CK		 987struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
988 struct amdgpu_ring *ring, uint64_t seq);
989
0b492a4c
AD		 990int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *filp);
992
efd4ccb5
CK		 993void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
994void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 995
97b2e202
AD		 996/*
997 * file private structure
998 */
999
1000struct amdgpu_fpriv {
1001 struct amdgpu_vm vm;
1002 struct mutex bo_list_lock;
1003 struct idr bo_list_handles;
0b492a4c 1004 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1005};
1006
1007/*
1008 * residency list
1009 */
1010
1011struct amdgpu_bo_list {
1012 struct mutex lock;
1013 struct amdgpu_bo *gds_obj;
1014 struct amdgpu_bo *gws_obj;
1015 struct amdgpu_bo *oa_obj;
211dff55 1016 unsigned first_userptr;
97b2e202
AD		 1017 unsigned num_entries;
1018 struct amdgpu_bo_list_entry *array;
1019};
1020
1021struct amdgpu_bo_list *
1022amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1023void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1024 struct list_head *validated);
97b2e202
AD		 1025void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1026void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1027
1028/*
1029 * GFX stuff
1030 */
1031#include "clearstate_defs.h"
1032
79e5412c
AD		 1033struct amdgpu_rlc_funcs {
1034 void (*enter_safe_mode)(struct amdgpu_device *adev);
1035 void (*exit_safe_mode)(struct amdgpu_device *adev);
1036};
1037
97b2e202
AD		 1038struct amdgpu_rlc {
1039 /* for power gating */
1040 struct amdgpu_bo *save_restore_obj;
1041 uint64_t save_restore_gpu_addr;
1042 volatile uint32_t *sr_ptr;
1043 const u32 *reg_list;
1044 u32 reg_list_size;
1045 /* for clear state */
1046 struct amdgpu_bo *clear_state_obj;
1047 uint64_t clear_state_gpu_addr;
1048 volatile uint32_t *cs_ptr;
1049 const struct cs_section_def *cs_data;
1050 u32 clear_state_size;
1051 /* for cp tables */
1052 struct amdgpu_bo *cp_table_obj;
1053 uint64_t cp_table_gpu_addr;
1054 volatile uint32_t *cp_table_ptr;
1055 u32 cp_table_size;
79e5412c
AD		 1056
1057 /* safe mode for updating CG/PG state */
1058 bool in_safe_mode;
1059 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 1060
1061 /* for firmware data */
1062 u32 save_and_restore_offset;
1063 u32 clear_state_descriptor_offset;
1064 u32 avail_scratch_ram_locations;
1065 u32 reg_restore_list_size;
1066 u32 reg_list_format_start;
1067 u32 reg_list_format_separate_start;
1068 u32 starting_offsets_start;
1069 u32 reg_list_format_size_bytes;
1070 u32 reg_list_size_bytes;
1071
1072 u32 *register_list_format;
1073 u32 *register_restore;
97b2e202
AD		 1074};
1075
1076struct amdgpu_mec {
1077 struct amdgpu_bo *hpd_eop_obj;
1078 u64 hpd_eop_gpu_addr;
1079 u32 num_pipe;
1080 u32 num_mec;
1081 u32 num_queue;
1082};
1083
1084/*
1085 * GPU scratch registers structures, functions & helpers
1086 */
1087struct amdgpu_scratch {
1088 unsigned num_reg;
1089 uint32_t reg_base;
1090 bool free[32];
1091 uint32_t reg[32];
1092};
1093
1094/*
1095 * GFX configurations
1096 */
1097struct amdgpu_gca_config {
1098 unsigned max_shader_engines;
1099 unsigned max_tile_pipes;
1100 unsigned max_cu_per_sh;
1101 unsigned max_sh_per_se;
1102 unsigned max_backends_per_se;
1103 unsigned max_texture_channel_caches;
1104 unsigned max_gprs;
1105 unsigned max_gs_threads;
1106 unsigned max_hw_contexts;
1107 unsigned sc_prim_fifo_size_frontend;
1108 unsigned sc_prim_fifo_size_backend;
1109 unsigned sc_hiz_tile_fifo_size;
1110 unsigned sc_earlyz_tile_fifo_size;
1111
1112 unsigned num_tile_pipes;
1113 unsigned backend_enable_mask;
1114 unsigned mem_max_burst_length_bytes;
1115 unsigned mem_row_size_in_kb;
1116 unsigned shader_engine_tile_size;
1117 unsigned num_gpus;
1118 unsigned multi_gpu_tile_size;
1119 unsigned mc_arb_ramcfg;
1120 unsigned gb_addr_config;
8f8e00c1 1121 unsigned num_rbs;
97b2e202
AD		 1122
1123 uint32_t tile_mode_array[32];
1124 uint32_t macrotile_mode_array[16];
1125};
1126
7dae69a2
AD		 1127struct amdgpu_cu_info {
1128 uint32_t number; /* total active CU number */
1129 uint32_t ao_cu_mask;
1130 uint32_t bitmap[4][4];
1131};
1132
b95e31fd
AD		 1133struct amdgpu_gfx_funcs {
1134 /* get the gpu clock counter */
1135 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 1136 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
b95e31fd
AD		 1137};
1138
97b2e202
AD		 1139struct amdgpu_gfx {
1140 struct mutex gpu_clock_mutex;
1141 struct amdgpu_gca_config config;
1142 struct amdgpu_rlc rlc;
1143 struct amdgpu_mec mec;
1144 struct amdgpu_scratch scratch;
1145 const struct firmware *me_fw; /* ME firmware */
1146 uint32_t me_fw_version;
1147 const struct firmware *pfp_fw; /* PFP firmware */
1148 uint32_t pfp_fw_version;
1149 const struct firmware *ce_fw; /* CE firmware */
1150 uint32_t ce_fw_version;
1151 const struct firmware *rlc_fw; /* RLC firmware */
1152 uint32_t rlc_fw_version;
1153 const struct firmware *mec_fw; /* MEC firmware */
1154 uint32_t mec_fw_version;
1155 const struct firmware *mec2_fw; /* MEC2 firmware */
1156 uint32_t mec2_fw_version;
02558a00
KW		 1157 uint32_t me_feature_version;
1158 uint32_t ce_feature_version;
1159 uint32_t pfp_feature_version;
351643d7
JZ		 1160 uint32_t rlc_feature_version;
1161 uint32_t mec_feature_version;
1162 uint32_t mec2_feature_version;
97b2e202
AD		 1163 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1164 unsigned num_gfx_rings;
1165 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1166 unsigned num_compute_rings;
1167 struct amdgpu_irq_src eop_irq;
1168 struct amdgpu_irq_src priv_reg_irq;
1169 struct amdgpu_irq_src priv_inst_irq;
1170 /* gfx status */
7dae69a2 1171 uint32_t gfx_current_status;
a101a899 1172 /* ce ram size*/
7dae69a2
AD		 1173 unsigned ce_ram_size;
1174 struct amdgpu_cu_info cu_info;
b95e31fd 1175 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1176
1177 /* reset mask */
1178 uint32_t grbm_soft_reset;
1179 uint32_t srbm_soft_reset;
97b2e202
AD		 1180};
1181
b07c60c0 1182int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1183 unsigned size, struct amdgpu_ib *ib);
4d9c514d
CK		 1184void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1185 struct fence *f);
b07c60c0 1186int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1187 struct amdgpu_ib *ib, struct fence *last_vm_update,
c5637837 1188 struct amdgpu_job *job, struct fence **f);
97b2e202
AD		 1189int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1190void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1191int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1192int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1193void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1194void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1195void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1196void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1197int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1198 unsigned ring_size, u32 nop, u32 align_mask,
1199 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1200 enum amdgpu_ring_type ring_type);
1201void amdgpu_ring_fini(struct amdgpu_ring *ring);
1202
1203/*
1204 * CS.
1205 */
1206struct amdgpu_cs_chunk {
1207 uint32_t chunk_id;
1208 uint32_t length_dw;
758ac17f 1209 void *kdata;
97b2e202
AD		 1210};
1211
1212struct amdgpu_cs_parser {
1213 struct amdgpu_device *adev;
1214 struct drm_file *filp;
3cb485f3 1215 struct amdgpu_ctx *ctx;
c3cca41e 1216
97b2e202
AD		 1217 /* chunks */
1218 unsigned nchunks;
1219 struct amdgpu_cs_chunk *chunks;
97b2e202 1220
50838c8c
CK		 1221 /* scheduler job object */
1222 struct amdgpu_job *job;
97b2e202 1223
c3cca41e
CK		 1224 /* buffer objects */
1225 struct ww_acquire_ctx ticket;
1226 struct amdgpu_bo_list *bo_list;
1227 struct amdgpu_bo_list_entry vm_pd;
1228 struct list_head validated;
1229 struct fence *fence;
1230 uint64_t bytes_moved_threshold;
1231 uint64_t bytes_moved;
662bfa61 1232 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1233
1234 /* user fence */
91acbeb6 1235 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1236};
1237
753ad49c
ML		 1238#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1239#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1240#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1241
bb977d37
CZ		 1242struct amdgpu_job {
1243 struct amd_sched_job base;
1244 struct amdgpu_device *adev;
edf600da 1245 struct amdgpu_vm *vm;
b07c60c0 1246 struct amdgpu_ring *ring;
e86f9cee 1247 struct amdgpu_sync sync;
bb977d37 1248 struct amdgpu_ib *ibs;
73cfa5f5 1249 struct fence *fence; /* the hw fence */
753ad49c 1250 uint32_t preamble_status;
bb977d37 1251 uint32_t num_ibs;
e2840221 1252 void *owner;
3aecd24c 1253 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1254 bool vm_needs_flush;
d88bf583
CK		 1255 unsigned vm_id;
1256 uint64_t vm_pd_addr;
1257 uint32_t gds_base, gds_size;
1258 uint32_t gws_base, gws_size;
1259 uint32_t oa_base, oa_size;
758ac17f
CK		 1260
1261 /* user fence handling */
b5f5acbc 1262 uint64_t uf_addr;
758ac17f
CK		 1263 uint64_t uf_sequence;
1264
bb977d37 1265};
a6db8a33
JZ		 1266#define to_amdgpu_job(sched_job) \
1267 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1268
7270f839
CK		 1269static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1270 uint32_t ib_idx, int idx)
97b2e202 1271{
50838c8c 1272 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1273}
1274
7270f839
CK		 1275static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1276 uint32_t ib_idx, int idx,
1277 uint32_t value)
1278{
50838c8c 1279 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1280}
1281
97b2e202
AD		 1282/*
1283 * Writeback
1284 */
1285#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1286
1287struct amdgpu_wb {
1288 struct amdgpu_bo *wb_obj;
1289 volatile uint32_t *wb;
1290 uint64_t gpu_addr;
1291 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1292 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1293};
1294
1295int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1296void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1297
97b2e202 1298
97b2e202
AD		 1299
1300enum amdgpu_int_thermal_type {
1301 THERMAL_TYPE_NONE,
1302 THERMAL_TYPE_EXTERNAL,
1303 THERMAL_TYPE_EXTERNAL_GPIO,
1304 THERMAL_TYPE_RV6XX,
1305 THERMAL_TYPE_RV770,
1306 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1307 THERMAL_TYPE_EVERGREEN,
1308 THERMAL_TYPE_SUMO,
1309 THERMAL_TYPE_NI,
1310 THERMAL_TYPE_SI,
1311 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1312 THERMAL_TYPE_CI,
1313 THERMAL_TYPE_KV,
1314};
1315
1316enum amdgpu_dpm_auto_throttle_src {
1317 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1318 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1319};
1320
1321enum amdgpu_dpm_event_src {
1322 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1323 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1324 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1325 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1326 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1327};
1328
1329#define AMDGPU_MAX_VCE_LEVELS 6
1330
1331enum amdgpu_vce_level {
1332 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1333 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1334 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1335 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1336 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1337 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1338};
1339
1340struct amdgpu_ps {
1341 u32 caps; /* vbios flags */
1342 u32 class; /* vbios flags */
1343 u32 class2; /* vbios flags */
1344 /* UVD clocks */
1345 u32 vclk;
1346 u32 dclk;
1347 /* VCE clocks */
1348 u32 evclk;
1349 u32 ecclk;
1350 bool vce_active;
1351 enum amdgpu_vce_level vce_level;
1352 /* asic priv */
1353 void *ps_priv;
1354};
1355
1356struct amdgpu_dpm_thermal {
1357 /* thermal interrupt work */
1358 struct work_struct work;
1359 /* low temperature threshold */
1360 int min_temp;
1361 /* high temperature threshold */
1362 int max_temp;
1363 /* was last interrupt low to high or high to low */
1364 bool high_to_low;
1365 /* interrupt source */
1366 struct amdgpu_irq_src irq;
1367};
1368
1369enum amdgpu_clk_action
1370{
1371 AMDGPU_SCLK_UP = 1,
1372 AMDGPU_SCLK_DOWN
1373};
1374
1375struct amdgpu_blacklist_clocks
1376{
1377 u32 sclk;
1378 u32 mclk;
1379 enum amdgpu_clk_action action;
1380};
1381
1382struct amdgpu_clock_and_voltage_limits {
1383 u32 sclk;
1384 u32 mclk;
1385 u16 vddc;
1386 u16 vddci;
1387};
1388
1389struct amdgpu_clock_array {
1390 u32 count;
1391 u32 *values;
1392};
1393
1394struct amdgpu_clock_voltage_dependency_entry {
1395 u32 clk;
1396 u16 v;
1397};
1398
1399struct amdgpu_clock_voltage_dependency_table {
1400 u32 count;
1401 struct amdgpu_clock_voltage_dependency_entry *entries;
1402};
1403
1404union amdgpu_cac_leakage_entry {
1405 struct {
1406 u16 vddc;
1407 u32 leakage;
1408 };
1409 struct {
1410 u16 vddc1;
1411 u16 vddc2;
1412 u16 vddc3;
1413 };
1414};
1415
1416struct amdgpu_cac_leakage_table {
1417 u32 count;
1418 union amdgpu_cac_leakage_entry *entries;
1419};
1420
1421struct amdgpu_phase_shedding_limits_entry {
1422 u16 voltage;
1423 u32 sclk;
1424 u32 mclk;
1425};
1426
1427struct amdgpu_phase_shedding_limits_table {
1428 u32 count;
1429 struct amdgpu_phase_shedding_limits_entry *entries;
1430};
1431
1432struct amdgpu_uvd_clock_voltage_dependency_entry {
1433 u32 vclk;
1434 u32 dclk;
1435 u16 v;
1436};
1437
1438struct amdgpu_uvd_clock_voltage_dependency_table {
1439 u8 count;
1440 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1441};
1442
1443struct amdgpu_vce_clock_voltage_dependency_entry {
1444 u32 ecclk;
1445 u32 evclk;
1446 u16 v;
1447};
1448
1449struct amdgpu_vce_clock_voltage_dependency_table {
1450 u8 count;
1451 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1452};
1453
1454struct amdgpu_ppm_table {
1455 u8 ppm_design;
1456 u16 cpu_core_number;
1457 u32 platform_tdp;
1458 u32 small_ac_platform_tdp;
1459 u32 platform_tdc;
1460 u32 small_ac_platform_tdc;
1461 u32 apu_tdp;
1462 u32 dgpu_tdp;
1463 u32 dgpu_ulv_power;
1464 u32 tj_max;
1465};
1466
1467struct amdgpu_cac_tdp_table {
1468 u16 tdp;
1469 u16 configurable_tdp;
1470 u16 tdc;
1471 u16 battery_power_limit;
1472 u16 small_power_limit;
1473 u16 low_cac_leakage;
1474 u16 high_cac_leakage;
1475 u16 maximum_power_delivery_limit;
1476};
1477
1478struct amdgpu_dpm_dynamic_state {
1479 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1480 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1481 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1482 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1483 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1484 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1485 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1486 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1487 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1488 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1489 struct amdgpu_clock_array valid_sclk_values;
1490 struct amdgpu_clock_array valid_mclk_values;
1491 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1492 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1493 u32 mclk_sclk_ratio;
1494 u32 sclk_mclk_delta;
1495 u16 vddc_vddci_delta;
1496 u16 min_vddc_for_pcie_gen2;
1497 struct amdgpu_cac_leakage_table cac_leakage_table;
1498 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1499 struct amdgpu_ppm_table *ppm_table;
1500 struct amdgpu_cac_tdp_table *cac_tdp_table;
1501};
1502
1503struct amdgpu_dpm_fan {
1504 u16 t_min;
1505 u16 t_med;
1506 u16 t_high;
1507 u16 pwm_min;
1508 u16 pwm_med;
1509 u16 pwm_high;
1510 u8 t_hyst;
1511 u32 cycle_delay;
1512 u16 t_max;
1513 u8 control_mode;
1514 u16 default_max_fan_pwm;
1515 u16 default_fan_output_sensitivity;
1516 u16 fan_output_sensitivity;
1517 bool ucode_fan_control;
1518};
1519
1520enum amdgpu_pcie_gen {
1521 AMDGPU_PCIE_GEN1 = 0,
1522 AMDGPU_PCIE_GEN2 = 1,
1523 AMDGPU_PCIE_GEN3 = 2,
1524 AMDGPU_PCIE_GEN_INVALID = 0xffff
1525};
1526
1527enum amdgpu_dpm_forced_level {
1528 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1529 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1530 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1531 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1532};
1533
1534struct amdgpu_vce_state {
1535 /* vce clocks */
1536 u32 evclk;
1537 u32 ecclk;
1538 /* gpu clocks */
1539 u32 sclk;
1540 u32 mclk;
1541 u8 clk_idx;
1542 u8 pstate;
1543};
1544
1545struct amdgpu_dpm_funcs {
1546 int (*get_temperature)(struct amdgpu_device *adev);
1547 int (*pre_set_power_state)(struct amdgpu_device *adev);
1548 int (*set_power_state)(struct amdgpu_device *adev);
1549 void (*post_set_power_state)(struct amdgpu_device *adev);
1550 void (*display_configuration_changed)(struct amdgpu_device *adev);
1551 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1552 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1553 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1554 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1555 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1556 bool (*vblank_too_short)(struct amdgpu_device *adev);
1557 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1558 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1559 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1560 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1561 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1562 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1563 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
c85e299f
EH		 1564 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1565 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
8b2e574d
EH		 1566 int (*get_sclk_od)(struct amdgpu_device *adev);
1567 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
f2bdc05f
EH		 1568 int (*get_mclk_od)(struct amdgpu_device *adev);
1569 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
97b2e202
AD		 1570};
1571
1572struct amdgpu_dpm {
1573 struct amdgpu_ps *ps;
1574 /* number of valid power states */
1575 int num_ps;
1576 /* current power state that is active */
1577 struct amdgpu_ps *current_ps;
1578 /* requested power state */
1579 struct amdgpu_ps *requested_ps;
1580 /* boot up power state */
1581 struct amdgpu_ps *boot_ps;
1582 /* default uvd power state */
1583 struct amdgpu_ps *uvd_ps;
1584 /* vce requirements */
1585 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1586 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1587 enum amd_pm_state_type state;
1588 enum amd_pm_state_type user_state;
97b2e202
AD		 1589 u32 platform_caps;
1590 u32 voltage_response_time;
1591 u32 backbias_response_time;
1592 void *priv;
1593 u32 new_active_crtcs;
1594 int new_active_crtc_count;
1595 u32 current_active_crtcs;
1596 int current_active_crtc_count;
1597 struct amdgpu_dpm_dynamic_state dyn_state;
1598 struct amdgpu_dpm_fan fan;
1599 u32 tdp_limit;
1600 u32 near_tdp_limit;
1601 u32 near_tdp_limit_adjusted;
1602 u32 sq_ramping_threshold;
1603 u32 cac_leakage;
1604 u16 tdp_od_limit;
1605 u32 tdp_adjustment;
1606 u16 load_line_slope;
1607 bool power_control;
1608 bool ac_power;
1609 /* special states active */
1610 bool thermal_active;
1611 bool uvd_active;
1612 bool vce_active;
1613 /* thermal handling */
1614 struct amdgpu_dpm_thermal thermal;
1615 /* forced levels */
1616 enum amdgpu_dpm_forced_level forced_level;
1617};
1618
1619struct amdgpu_pm {
1620 struct mutex mutex;
97b2e202
AD		 1621 u32 current_sclk;
1622 u32 current_mclk;
1623 u32 default_sclk;
1624 u32 default_mclk;
1625 struct amdgpu_i2c_chan *i2c_bus;
1626 /* internal thermal controller on rv6xx+ */
1627 enum amdgpu_int_thermal_type int_thermal_type;
1628 struct device *int_hwmon_dev;
1629 /* fan control parameters */
1630 bool no_fan;
1631 u8 fan_pulses_per_revolution;
1632 u8 fan_min_rpm;
1633 u8 fan_max_rpm;
1634 /* dpm */
1635 bool dpm_enabled;
c86f5ebf 1636 bool sysfs_initialized;
97b2e202
AD		 1637 struct amdgpu_dpm dpm;
1638 const struct firmware *fw; /* SMC firmware */
1639 uint32_t fw_version;
1640 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1641 uint32_t pcie_gen_mask;
1642 uint32_t pcie_mlw_mask;
7fb72a1f 1643 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1644};
1645
d0dd7f0c
AD		 1646void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1647
97b2e202
AD		 1648/*
1649 * UVD
1650 */
c0365541
AN		 1651#define AMDGPU_DEFAULT_UVD_HANDLES 10
1652#define AMDGPU_MAX_UVD_HANDLES 40
1653#define AMDGPU_UVD_STACK_SIZE (200*1024)
1654#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1655#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1656#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1657
1658struct amdgpu_uvd {
1659 struct amdgpu_bo *vcpu_bo;
1660 void *cpu_addr;
1661 uint64_t gpu_addr;
562e2689 1662 unsigned fw_version;
3f99dd81 1663 void *saved_bo;
c0365541 1664 unsigned max_handles;
97b2e202
AD		 1665 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1666 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1667 struct delayed_work idle_work;
1668 const struct firmware *fw; /* UVD firmware */
1669 struct amdgpu_ring ring;
1670 struct amdgpu_irq_src irq;
1671 bool address_64_bit;
4cb5877c 1672 bool use_ctx_buf;
ead833ec 1673 struct amd_sched_entity entity;
fc0b3b90 1674 uint32_t srbm_soft_reset;
97b2e202
AD		 1675};
1676
1677/*
1678 * VCE
1679 */
1680#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1681#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1682
6a585777
AD		 1683#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1684#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1685
97b2e202
AD		 1686struct amdgpu_vce {
1687 struct amdgpu_bo *vcpu_bo;
1688 uint64_t gpu_addr;
1689 unsigned fw_version;
1690 unsigned fb_version;
1691 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1692 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1693 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202 1694 struct delayed_work idle_work;
ebff485e 1695 struct mutex idle_mutex;
97b2e202
AD		 1696 const struct firmware *fw; /* VCE firmware */
1697 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1698 struct amdgpu_irq_src irq;
6a585777 1699 unsigned harvest_config;
c594989c 1700 struct amd_sched_entity entity;
115933a5 1701 uint32_t srbm_soft_reset;
75c65480 1702 unsigned num_rings;
97b2e202
AD		 1703};
1704
1705/*
1706 * SDMA
1707 */
c113ea1c 1708struct amdgpu_sdma_instance {
97b2e202
AD		 1709 /* SDMA firmware */
1710 const struct firmware *fw;
1711 uint32_t fw_version;
cfa2104f 1712 uint32_t feature_version;
97b2e202
AD		 1713
1714 struct amdgpu_ring ring;
18111de0 1715 bool burst_nop;
97b2e202
AD		 1716};
1717
c113ea1c
AD		 1718struct amdgpu_sdma {
1719 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1720#ifdef CONFIG_DRM_AMDGPU_SI
1721 //SI DMA has a difference trap irq number for the second engine
1722 struct amdgpu_irq_src trap_irq_1;
1723#endif
c113ea1c
AD		 1724 struct amdgpu_irq_src trap_irq;
1725 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1726 int num_instances;
e702a680 1727 uint32_t srbm_soft_reset;
c113ea1c
AD		 1728};
1729
97b2e202
AD		 1730/*
1731 * Firmware
1732 */
1733struct amdgpu_firmware {
1734 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1735 bool smu_load;
1736 struct amdgpu_bo *fw_buf;
1737 unsigned int fw_size;
1738};
1739
1740/*
1741 * Benchmarking
1742 */
1743void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1744
1745
1746/*
1747 * Testing
1748 */
1749void amdgpu_test_moves(struct amdgpu_device *adev);
1750void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1751 struct amdgpu_ring *cpA,
1752 struct amdgpu_ring *cpB);
1753void amdgpu_test_syncing(struct amdgpu_device *adev);
1754
1755/*
1756 * MMU Notifier
1757 */
1758#if defined(CONFIG_MMU_NOTIFIER)
1759int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1760void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1761#else
1d1106b0 1762static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1763{
1764 return -ENODEV;
1765}
1d1106b0 1766static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1767#endif
1768
1769/*
1770 * Debugfs
1771 */
1772struct amdgpu_debugfs {
06ab6832 1773 const struct drm_info_list *files;
97b2e202
AD		 1774 unsigned num_files;
1775};
1776
1777int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1778 const struct drm_info_list *files,
97b2e202
AD		 1779 unsigned nfiles);
1780int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1781
1782#if defined(CONFIG_DEBUG_FS)
1783int amdgpu_debugfs_init(struct drm_minor *minor);
1784void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1785#endif
1786
50ab2533
HR		 1787int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1788
97b2e202
AD		 1789/*
1790 * amdgpu smumgr functions
1791 */
1792struct amdgpu_smumgr_funcs {
1793 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1794 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1795 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1796};
1797
1798/*
1799 * amdgpu smumgr
1800 */
1801struct amdgpu_smumgr {
1802 struct amdgpu_bo *toc_buf;
1803 struct amdgpu_bo *smu_buf;
1804 /* asic priv smu data */
1805 void *priv;
1806 spinlock_t smu_lock;
1807 /* smumgr functions */
1808 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1809 /* ucode loading complete flag */
1810 uint32_t fw_flags;
1811};
1812
1813/*
1814 * ASIC specific register table accessible by UMD
1815 */
1816struct amdgpu_allowed_register_entry {
1817 uint32_t reg_offset;
1818 bool untouched;
1819 bool grbm_indexed;
1820};
1821
97b2e202
AD		 1822/*
1823 * ASIC specific functions.
1824 */
1825struct amdgpu_asic_funcs {
1826 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1827 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1828 u8 *bios, u32 length_bytes);
4e99a44e 1829 void (*detect_hw_virtualization) (struct amdgpu_device *adev);
97b2e202
AD		 1830 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1831 u32 sh_num, u32 reg_offset, u32 *value);
1832 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1833 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1834 /* get the reference clock */
1835 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1836 /* MM block clocks */
1837 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1838 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1839 /* static power management */
1840 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1841 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
97b2e202
AD		 1842};
1843
1844/*
1845 * IOCTL.
1846 */
1847int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851
1852int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *filp);
1858int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1865int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1866
1867int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1868 struct drm_file *filp);
1869
1870/* VRAM scratch page for HDP bug, default vram page */
1871struct amdgpu_vram_scratch {
1872 struct amdgpu_bo *robj;
1873 volatile uint32_t *ptr;
1874 u64 gpu_addr;
1875};
1876
1877/*
1878 * ACPI
1879 */
1880struct amdgpu_atif_notification_cfg {
1881 bool enabled;
1882 int command_code;
1883};
1884
1885struct amdgpu_atif_notifications {
1886 bool display_switch;
1887 bool expansion_mode_change;
1888 bool thermal_state;
1889 bool forced_power_state;
1890 bool system_power_state;
1891 bool display_conf_change;
1892 bool px_gfx_switch;
1893 bool brightness_change;
1894 bool dgpu_display_event;
1895};
1896
1897struct amdgpu_atif_functions {
1898 bool system_params;
1899 bool sbios_requests;
1900 bool select_active_disp;
1901 bool lid_state;
1902 bool get_tv_standard;
1903 bool set_tv_standard;
1904 bool get_panel_expansion_mode;
1905 bool set_panel_expansion_mode;
1906 bool temperature_change;
1907 bool graphics_device_types;
1908};
1909
1910struct amdgpu_atif {
1911 struct amdgpu_atif_notifications notifications;
1912 struct amdgpu_atif_functions functions;
1913 struct amdgpu_atif_notification_cfg notification_cfg;
1914 struct amdgpu_encoder *encoder_for_bl;
1915};
1916
1917struct amdgpu_atcs_functions {
1918 bool get_ext_state;
1919 bool pcie_perf_req;
1920 bool pcie_dev_rdy;
1921 bool pcie_bus_width;
1922};
1923
1924struct amdgpu_atcs {
1925 struct amdgpu_atcs_functions functions;
1926};
1927
d03846af
CZ		 1928/*
1929 * CGS
1930 */
110e6f26
DA		 1931struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1932void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1933
97b2e202
AD		 1934/*
1935 * Core structure, functions and helpers.
1936 */
1937typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1938typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1939
1940typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1941typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1942
8faf0e08
AD		 1943struct amdgpu_ip_block_status {
1944 bool valid;
1945 bool sw;
1946 bool hw;
8a2eef1d 1947 bool late_initialized;
63fbf42f 1948 bool hang;
8faf0e08
AD		 1949};
1950
97b2e202
AD		 1951struct amdgpu_device {
1952 struct device *dev;
1953 struct drm_device *ddev;
1954 struct pci_dev *pdev;
97b2e202 1955
a8fe58ce
MB		 1956#ifdef CONFIG_DRM_AMD_ACP
1957 struct amdgpu_acp acp;
1958#endif
1959
97b2e202 1960 /* ASIC */
2f7d10b3 1961 enum amd_asic_type asic_type;
97b2e202
AD		 1962 uint32_t family;
1963 uint32_t rev_id;
1964 uint32_t external_rev_id;
1965 unsigned long flags;
1966 int usec_timeout;
1967 const struct amdgpu_asic_funcs *asic_funcs;
1968 bool shutdown;
97b2e202
AD		 1969 bool need_dma32;
1970 bool accel_working;
edf600da 1971 struct work_struct reset_work;
97b2e202
AD		 1972 struct notifier_block acpi_nb;
1973 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1974 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1975 unsigned debugfs_count;
97b2e202 1976#if defined(CONFIG_DEBUG_FS)
adcec288 1977 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1978#endif
1979 struct amdgpu_atif atif;
1980 struct amdgpu_atcs atcs;
1981 struct mutex srbm_mutex;
1982 /* GRBM index mutex. Protects concurrent access to GRBM index */
1983 struct mutex grbm_idx_mutex;
1984 struct dev_pm_domain vga_pm_domain;
1985 bool have_disp_power_ref;
1986
1987 /* BIOS */
1988 uint8_t *bios;
1989 bool is_atom_bios;
97b2e202
AD		 1990 struct amdgpu_bo *stollen_vga_memory;
1991 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1992
1993 /* Register/doorbell mmio */
1994 resource_size_t rmmio_base;
1995 resource_size_t rmmio_size;
1996 void __iomem *rmmio;
1997 /* protects concurrent MM_INDEX/DATA based register access */
1998 spinlock_t mmio_idx_lock;
1999 /* protects concurrent SMC based register access */
2000 spinlock_t smc_idx_lock;
2001 amdgpu_rreg_t smc_rreg;
2002 amdgpu_wreg_t smc_wreg;
2003 /* protects concurrent PCIE register access */
2004 spinlock_t pcie_idx_lock;
2005 amdgpu_rreg_t pcie_rreg;
2006 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 2007 amdgpu_rreg_t pciep_rreg;
2008 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 2009 /* protects concurrent UVD register access */
2010 spinlock_t uvd_ctx_idx_lock;
2011 amdgpu_rreg_t uvd_ctx_rreg;
2012 amdgpu_wreg_t uvd_ctx_wreg;
2013 /* protects concurrent DIDT register access */
2014 spinlock_t didt_idx_lock;
2015 amdgpu_rreg_t didt_rreg;
2016 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 2017 /* protects concurrent gc_cac register access */
2018 spinlock_t gc_cac_idx_lock;
2019 amdgpu_rreg_t gc_cac_rreg;
2020 amdgpu_wreg_t gc_cac_wreg;
97b2e202
AD		 2021 /* protects concurrent ENDPOINT (audio) register access */
2022 spinlock_t audio_endpt_idx_lock;
2023 amdgpu_block_rreg_t audio_endpt_rreg;
2024 amdgpu_block_wreg_t audio_endpt_wreg;
2025 void __iomem *rio_mem;
2026 resource_size_t rio_mem_size;
2027 struct amdgpu_doorbell doorbell;
2028
2029 /* clock/pll info */
2030 struct amdgpu_clock clock;
2031
2032 /* MC */
2033 struct amdgpu_mc mc;
2034 struct amdgpu_gart gart;
2035 struct amdgpu_dummy_page dummy_page;
2036 struct amdgpu_vm_manager vm_manager;
2037
2038 /* memory management */
2039 struct amdgpu_mman mman;
97b2e202
AD		 2040 struct amdgpu_vram_scratch vram_scratch;
2041 struct amdgpu_wb wb;
2042 atomic64_t vram_usage;
2043 atomic64_t vram_vis_usage;
2044 atomic64_t gtt_usage;
2045 atomic64_t num_bytes_moved;
dbd5ed60 2046 atomic64_t num_evictions;
d94aed5a 2047 atomic_t gpu_reset_counter;
97b2e202 2048
95844d20
MO		 2049 /* data for buffer migration throttling */
2050 struct {
2051 spinlock_t lock;
2052 s64 last_update_us;
2053 s64 accum_us; /* accumulated microseconds */
2054 u32 log2_max_MBps;
2055 } mm_stats;
2056
97b2e202 2057 /* display */
9accf2fd 2058 bool enable_virtual_display;
97b2e202
AD		 2059 struct amdgpu_mode_info mode_info;
2060 struct work_struct hotplug_work;
2061 struct amdgpu_irq_src crtc_irq;
2062 struct amdgpu_irq_src pageflip_irq;
2063 struct amdgpu_irq_src hpd_irq;
2064
2065 /* rings */
76bf0db5 2066 u64 fence_context;
97b2e202
AD		 2067 unsigned num_rings;
2068 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2069 bool ib_pool_ready;
2070 struct amdgpu_sa_manager ring_tmp_bo;
2071
2072 /* interrupts */
2073 struct amdgpu_irq irq;
2074
1f7371b2
AD		 2075 /* powerplay */
2076 struct amd_powerplay powerplay;
e61710c5 2077 bool pp_enabled;
f3898ea1 2078 bool pp_force_state_enabled;
1f7371b2 2079
97b2e202
AD		 2080 /* dpm */
2081 struct amdgpu_pm pm;
2082 u32 cg_flags;
2083 u32 pg_flags;
2084
2085 /* amdgpu smumgr */
2086 struct amdgpu_smumgr smu;
2087
2088 /* gfx */
2089 struct amdgpu_gfx gfx;
2090
2091 /* sdma */
c113ea1c 2092 struct amdgpu_sdma sdma;
97b2e202
AD		 2093
2094 /* uvd */
97b2e202
AD		 2095 struct amdgpu_uvd uvd;
2096
2097 /* vce */
2098 struct amdgpu_vce vce;
2099
2100 /* firmwares */
2101 struct amdgpu_firmware firmware;
2102
2103 /* GDS */
2104 struct amdgpu_gds gds;
2105
2106 const struct amdgpu_ip_block_version *ip_blocks;
2107 int num_ip_blocks;
8faf0e08 2108 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2109 struct mutex mn_lock;
2110 DECLARE_HASHTABLE(mn_hash, 7);
2111
2112 /* tracking pinned memory */
2113 u64 vram_pin_size;
e131b914 2114 u64 invisible_pin_size;
97b2e202 2115 u64 gart_pin_size;
130e0371
OG		 2116
2117 /* amdkfd interface */
2118 struct kfd_dev *kfd;
23ca0e4e 2119
7e471e6f 2120 struct amdgpu_virtualization virtualization;
0c4e7fa5
CZ		 2121
2122 /* link all shadow bo */
2123 struct list_head shadow_list;
2124 struct mutex shadow_list_lock;
5c1354bd
CZ		 2125 /* link all gtt */
2126 spinlock_t gtt_list_lock;
2127 struct list_head gtt_list;
2128
97b2e202
AD		 2129};
2130
2131bool amdgpu_device_is_px(struct drm_device *dev);
2132int amdgpu_device_init(struct amdgpu_device *adev,
2133 struct drm_device *ddev,
2134 struct pci_dev *pdev,
2135 uint32_t flags);
2136void amdgpu_device_fini(struct amdgpu_device *adev);
2137int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2138
2139uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2140 bool always_indirect);
2141void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2142 bool always_indirect);
2143u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2144void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2145
2146u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2147void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2148
97b2e202
AD		 2149/*
2150 * Registers read & write functions.
2151 */
2152#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2153#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2154#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2155#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2156#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2157#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2158#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2159#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2160#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 2161#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
2162#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 2163#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2164#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2165#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2166#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2167#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2168#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 2169#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2170#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
97b2e202
AD		 2171#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2172#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2173#define WREG32_P(reg, val, mask) \
2174 do { \
2175 uint32_t tmp_ = RREG32(reg); \
2176 tmp_ &= (mask); \
2177 tmp_ |= ((val) & ~(mask)); \
2178 WREG32(reg, tmp_); \
2179 } while (0)
2180#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2181#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2182#define WREG32_PLL_P(reg, val, mask) \
2183 do { \
2184 uint32_t tmp_ = RREG32_PLL(reg); \
2185 tmp_ &= (mask); \
2186 tmp_ |= ((val) & ~(mask)); \
2187 WREG32_PLL(reg, tmp_); \
2188 } while (0)
2189#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2190#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2191#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2192
2193#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2194#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2195
2196#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2197#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2198
2199#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2200 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2201 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2202
2203#define REG_GET_FIELD(value, reg, field) \
2204 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 2205
2206#define WREG32_FIELD(reg, field, val) \
2207 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202
AD		 2208
2209/*
2210 * BIOS helpers.
2211 */
2212#define RBIOS8(i) (adev->bios[i])
2213#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2214#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2215
2216/*
2217 * RING helpers.
2218 */
2219static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2220{
2221 if (ring->count_dw <= 0)
86c2b790 2222 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2223 ring->ring[ring->wptr++] = v;
2224 ring->wptr &= ring->ptr_mask;
2225 ring->count_dw--;
97b2e202
AD		 2226}
2227
c113ea1c
AD		 2228static inline struct amdgpu_sdma_instance *
2229amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2230{
2231 struct amdgpu_device *adev = ring->adev;
2232 int i;
2233
c113ea1c
AD		 2234 for (i = 0; i < adev->sdma.num_instances; i++)
2235 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2236 break;
2237
2238 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2239 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2240 else
2241 return NULL;
2242}
2243
97b2e202
AD		 2244/*
2245 * ASICs macro.
2246 */
2247#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2248#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 2249#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2250#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2251#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 2252#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
2253#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
2254#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 2255#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2256#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
4e99a44e 2257#define amdgpu_asic_detect_hw_virtualization(adev) (adev)->asic_funcs->detect_hw_virtualization((adev))
97b2e202 2258#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
97b2e202
AD		 2259#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2260#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2261#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 2262#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 2263#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2264#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2265#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 2266#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 2267#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2268#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2269#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 2270#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 2271#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2272#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2273#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2274#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2275#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2276#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 2277#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 2278#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
9e5d5309 2279#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 2280#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2281#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
b6384ff5
AD		 2282#define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r))
2283#define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r))
97b2e202
AD		 2284#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2285#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2286#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2287#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2288#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2289#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2290#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2291#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2292#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2293#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2294#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2295#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2296#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 2297#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 2298#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2299#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2300#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2301#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2302#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2303#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2304#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2305#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2306#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2307#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2308#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2309#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2310#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2311#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
b95e31fd 2312#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 2313#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
3af76f23 2314
3de4ec57
TSD		 2315#define amdgpu_dpm_read_sensor(adev, idx, value) \
2316 ((adev)->pp_enabled ? \
2317 (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
2318 -EINVAL)
2319
3af76f23 2320#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2321 ((adev)->pp_enabled ? \
e61710c5 2322 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2323 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2324
2325#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2326 ((adev)->pp_enabled ? \
e61710c5 2327 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2328 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2329
2330#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2331 ((adev)->pp_enabled ? \
e61710c5 2332 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2333 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2334
2335#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2336 ((adev)->pp_enabled ? \
e61710c5 2337 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2338 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2339
2340#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2341 ((adev)->pp_enabled ? \
e61710c5 2342 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2343 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2344
1b5708ff 2345#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2346 ((adev)->pp_enabled ? \
e61710c5 2347 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2348 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2349
2350#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2351 ((adev)->pp_enabled ? \
e61710c5 2352 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2353 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2354
2355
2356#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2357 ((adev)->pp_enabled ? \
e61710c5 2358 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2359 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2360
2361#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2362 ((adev)->pp_enabled ? \
e61710c5 2363 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2364 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2365
2366#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2367 ((adev)->pp_enabled ? \
e61710c5 2368 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2369 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff 2370
1b5708ff 2371#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2372 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2373
2374#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2375 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2376
f3898ea1
EH		 2377#define amdgpu_dpm_get_pp_num_states(adev, data) \
2378 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2379
2380#define amdgpu_dpm_get_pp_table(adev, table) \
2381 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2382
2383#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2384 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2385
2386#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2387 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2388
2389#define amdgpu_dpm_force_clock_level(adev, type, level) \
2390 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2391
428bafa8
EH		 2392#define amdgpu_dpm_get_sclk_od(adev) \
2393 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2394
2395#define amdgpu_dpm_set_sclk_od(adev, value) \
2396 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2397
f2bdc05f
EH		 2398#define amdgpu_dpm_get_mclk_od(adev) \
2399 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2400
2401#define amdgpu_dpm_set_mclk_od(adev, value) \
2402 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2403
e61710c5 2404#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2405 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2406
2407#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2408
2409/* Common functions */
2410int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 2411bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202
AD		 2412void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2413bool amdgpu_card_posted(struct amdgpu_device *adev);
2414void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2415
97b2e202
AD		 2416int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2417int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2418 u32 ip_instance, u32 ring,
2419 struct amdgpu_ring **out_ring);
765e7fbf 2420void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 2421bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2422int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2423int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2424 uint32_t flags);
2425bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 2426struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2427bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2428 unsigned long end);
2f568dbd
CK		 2429bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2430 int *last_invalidated);
97b2e202
AD		 2431bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2432uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2433 struct ttm_mem_reg *mem);
2434void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2435void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2436void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
a693e050
KW		 2437u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
2438int amdgpu_ttm_global_init(struct amdgpu_device *adev);
9f31a0b0
BX		 2439int amdgpu_ttm_init(struct amdgpu_device *adev);
2440void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 2441void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2442 const u32 *registers,
2443 const u32 array_size);
2444
2445bool amdgpu_device_is_px(struct drm_device *dev);
2446/* atpx handler */
2447#if defined(CONFIG_VGA_SWITCHEROO)
2448void amdgpu_register_atpx_handler(void);
2449void amdgpu_unregister_atpx_handler(void);
a78fe133 2450bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 2451bool amdgpu_is_atpx_hybrid(void);
efc83cf4 2452bool amdgpu_atpx_dgpu_req_power_for_displays(void);
97b2e202
AD		 2453#else
2454static inline void amdgpu_register_atpx_handler(void) {}
2455static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 2456static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 2457static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 2458static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
97b2e202
AD		 2459#endif
2460
2461/*
2462 * KMS
2463 */
2464extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 2465extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 2466
2467int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2468int amdgpu_driver_unload_kms(struct drm_device *dev);
2469void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2470int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2471void amdgpu_driver_postclose_kms(struct drm_device *dev,
2472 struct drm_file *file_priv);
2473void amdgpu_driver_preclose_kms(struct drm_device *dev,
2474 struct drm_file *file_priv);
810ddc3a
AD		 2475int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
2476int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2477u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2478int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2479void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2480int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2481 int *max_error,
2482 struct timeval *vblank_time,
2483 unsigned flags);
2484long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2485 unsigned long arg);
2486
97b2e202
AD		 2487/*
2488 * functions used by amdgpu_encoder.c
2489 */
2490struct amdgpu_afmt_acr {
2491 u32 clock;
2492
2493 int n_32khz;
2494 int cts_32khz;
2495
2496 int n_44_1khz;
2497 int cts_44_1khz;
2498
2499 int n_48khz;
2500 int cts_48khz;
2501
2502};
2503
2504struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2505
2506/* amdgpu_acpi.c */
2507#if defined(CONFIG_ACPI)
2508int amdgpu_acpi_init(struct amdgpu_device *adev);
2509void amdgpu_acpi_fini(struct amdgpu_device *adev);
2510bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2511int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2512 u8 perf_req, bool advertise);
2513int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2514#else
2515static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2516static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2517#endif
2518
2519struct amdgpu_bo_va_mapping *
2520amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2521 uint64_t addr, struct amdgpu_bo **bo);
c855e250 2522int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
97b2e202
AD		 2523
2524#include "amdgpu_object.h"
97b2e202 2525#endif
Linux 6.x block layer and io_uring tree(s)