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drm/amdgpu: Add new ring interface preempt_ib
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
8290268f
CK		 31#include "amdgpu_ctx.h"
32
97b2e202
AD		 33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
a9f87f64 37#include <linux/rbtree.h>
97b2e202 38#include <linux/hashtable.h>
f54d1867 39#include <linux/dma-fence.h>
97b2e202 40
248a1d6f
MY		 41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 46
d03846af 47#include <drm/drmP.h>
97b2e202 48#include <drm/drm_gem.h>
7e5a547f 49#include <drm/amdgpu_drm.h>
1b1f42d8 50#include <drm/gpu_scheduler.h>
97b2e202 51
78c16834 52#include <kgd_kfd_interface.h>
c79563a3
RZ		 53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
78c16834 55
5fc3aeeb 56#include "amd_shared.h"
97b2e202
AD		 57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
c632d799 61#include "amdgpu_ttm.h"
0e5ca0d1 62#include "amdgpu_psp.h"
97b2e202 63#include "amdgpu_gds.h"
56113504 64#include "amdgpu_sync.h"
78023016 65#include "amdgpu_ring.h"
073440d2 66#include "amdgpu_vm.h"
cf097881 67#include "amdgpu_dpm.h"
a8fe58ce 68#include "amdgpu_acp.h"
4df654d2 69#include "amdgpu_uvd.h"
5e568178 70#include "amdgpu_vce.h"
95aa13f6 71#include "amdgpu_vcn.h"
9a189996 72#include "amdgpu_mn.h"
770d13b1 73#include "amdgpu_gmc.h"
448fe192 74#include "amdgpu_gfx.h"
bb7743bc 75#include "amdgpu_sdma.h"
4562236b 76#include "amdgpu_dm.h"
ceeb50ed 77#include "amdgpu_virt.h"
7946340f 78#include "amdgpu_csa.h"
3490bdb5 79#include "amdgpu_gart.h"
75758255 80#include "amdgpu_debugfs.h"
050d9d43 81#include "amdgpu_job.h"
4a8c21a1 82#include "amdgpu_bo_list.h"
2cddc50e 83#include "amdgpu_gem.h"
cde577bd 84#include "amdgpu_doorbell.h"
611736d8 85#include "amdgpu_amdkfd.h"
137d63ab 86#include "amdgpu_smu.h"
c79563a3 87
62d73fbc
EQ		 88#define MAX_GPU_INSTANCE 16
89
90struct amdgpu_gpu_instance
91{
92 struct amdgpu_device *adev;
93 int mgpu_fan_enabled;
94};
95
96struct amdgpu_mgpu_info
97{
98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
99 struct mutex mutex;
100 uint32_t num_gpu;
101 uint32_t num_dgpu;
102 uint32_t num_apu;
103};
104
97b2e202
AD		 105/*
106 * Modules parameters.
107 */
108extern int amdgpu_modeset;
109extern int amdgpu_vram_limit;
218b5dcd 110extern int amdgpu_vis_vram_limit;
83e74db6 111extern int amdgpu_gart_size;
36d38372 112extern int amdgpu_gtt_size;
95844d20 113extern int amdgpu_moverate;
97b2e202
AD		 114extern int amdgpu_benchmarking;
115extern int amdgpu_testing;
116extern int amdgpu_audio;
117extern int amdgpu_disp_priority;
118extern int amdgpu_hw_i2c;
119extern int amdgpu_pcie_gen2;
120extern int amdgpu_msi;
97b2e202 121extern int amdgpu_dpm;
e635ee07 122extern int amdgpu_fw_load_type;
97b2e202
AD		 123extern int amdgpu_aspm;
124extern int amdgpu_runtime_pm;
0b693f0b 125extern uint amdgpu_ip_block_mask;
97b2e202
AD		 126extern int amdgpu_bapm;
127extern int amdgpu_deep_color;
128extern int amdgpu_vm_size;
129extern int amdgpu_vm_block_size;
d07f14be 130extern int amdgpu_vm_fragment_size;
d9c13156 131extern int amdgpu_vm_fault_stop;
b495bd3a 132extern int amdgpu_vm_debug;
9a4b7d4c 133extern int amdgpu_vm_update_mode;
4562236b 134extern int amdgpu_dc;
1333f723 135extern int amdgpu_sched_jobs;
4afcb303 136extern int amdgpu_sched_hw_submission;
0b693f0b
RZ		 137extern uint amdgpu_pcie_gen_cap;
138extern uint amdgpu_pcie_lane_cap;
139extern uint amdgpu_cg_mask;
140extern uint amdgpu_pg_mask;
141extern uint amdgpu_sdma_phase_quantum;
6f8941a2 142extern char *amdgpu_disable_cu;
9accf2fd 143extern char *amdgpu_virtual_display;
0b693f0b 144extern uint amdgpu_pp_feature_mask;
bce23e00
AD		 145extern int amdgpu_ngg;
146extern int amdgpu_prim_buf_per_se;
147extern int amdgpu_pos_buf_per_se;
148extern int amdgpu_cntl_sb_buf_per_se;
149extern int amdgpu_param_buf_per_se;
65781c78 150extern int amdgpu_job_hang_limit;
e8835e0e 151extern int amdgpu_lbpw;
4a75aefe 152extern int amdgpu_compute_multipipe;
dcebf026 153extern int amdgpu_gpu_recovery;
bfca0289 154extern int amdgpu_emu_mode;
7951e376 155extern uint amdgpu_smu_memory_pool_size;
7875a226 156extern uint amdgpu_dc_feature_mask;
ad4de27f 157extern uint amdgpu_dm_abm_level;
62d73fbc 158extern struct amdgpu_mgpu_info mgpu_info;
1218252f 159extern int amdgpu_ras_enable;
160extern uint amdgpu_ras_mask;
51bcce46 161extern int amdgpu_async_gfx_ring;
97b2e202 162
6dd13096
FK		 163#ifdef CONFIG_DRM_AMDGPU_SI
164extern int amdgpu_si_support;
165#endif
7df28986
FK		 166#ifdef CONFIG_DRM_AMDGPU_CIK
167extern int amdgpu_cik_support;
168#endif
97b2e202 169
08d1bdd4 170#define AMDGPU_VM_MAX_NUM_CTX 4096
6c8d74ca 171#define AMDGPU_SG_THRESHOLD (256*1024*1024)
55ed8caf 172#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 173#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202 174#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
8c5e13ec 175#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
97b2e202
AD		 176/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
177#define AMDGPU_IB_POOL_SIZE 16
178#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
179#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 180#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 181
97b2e202
AD		 182/* hard reset data */
183#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
184
185/* reset flags */
186#define AMDGPU_RESET_GFX (1 << 0)
187#define AMDGPU_RESET_COMPUTE (1 << 1)
188#define AMDGPU_RESET_DMA (1 << 2)
189#define AMDGPU_RESET_CP (1 << 3)
190#define AMDGPU_RESET_GRBM (1 << 4)
191#define AMDGPU_RESET_DMA1 (1 << 5)
192#define AMDGPU_RESET_RLC (1 << 6)
193#define AMDGPU_RESET_SEM (1 << 7)
194#define AMDGPU_RESET_IH (1 << 8)
195#define AMDGPU_RESET_VMC (1 << 9)
196#define AMDGPU_RESET_MC (1 << 10)
197#define AMDGPU_RESET_DISPLAY (1 << 11)
198#define AMDGPU_RESET_UVD (1 << 12)
199#define AMDGPU_RESET_VCE (1 << 13)
200#define AMDGPU_RESET_VCE1 (1 << 14)
201
97b2e202
AD		 202/* max cursor sizes (in pixels) */
203#define CIK_CURSOR_WIDTH 128
204#define CIK_CURSOR_HEIGHT 128
205
206struct amdgpu_device;
97b2e202 207struct amdgpu_ib;
97b2e202 208struct amdgpu_cs_parser;
bb977d37 209struct amdgpu_job;
97b2e202 210struct amdgpu_irq_src;
0b492a4c 211struct amdgpu_fpriv;
9cca0b8e 212struct amdgpu_bo_va_mapping;
102c16a0 213struct amdgpu_atif;
992af942 214struct kfd_vm_fault_info;
97b2e202
AD		 215
216enum amdgpu_cp_irq {
53b2fe41
HZ		 217 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
218 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
97b2e202
AD		 219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
221 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
222 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
225 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
226 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
227
228 AMDGPU_CP_IRQ_LAST
229};
230
97b2e202
AD		 231enum amdgpu_thermal_irq {
232 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
233 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
234
235 AMDGPU_THERMAL_IRQ_LAST
236};
237
4e638ae9
XY		 238enum amdgpu_kiq_irq {
239 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
240 AMDGPU_CP_KIQ_IRQ_LAST
241};
242
3890d111
ED		 243#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
244#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
4944af67 245#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
3890d111 246
43fa561f 247int amdgpu_device_ip_set_clockgating_state(void *dev,
2990a1fc
AD		 248 enum amd_ip_block_type block_type,
249 enum amd_clockgating_state state);
43fa561f 250int amdgpu_device_ip_set_powergating_state(void *dev,
2990a1fc
AD		 251 enum amd_ip_block_type block_type,
252 enum amd_powergating_state state);
253void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
254 u32 *flags);
255int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
256 enum amd_ip_block_type block_type);
257bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
258 enum amd_ip_block_type block_type);
97b2e202 259
a1255107
AD		 260#define AMDGPU_MAX_IP_NUM 16
261
262struct amdgpu_ip_block_status {
263 bool valid;
264 bool sw;
265 bool hw;
266 bool late_initialized;
267 bool hang;
268};
269
97b2e202 270struct amdgpu_ip_block_version {
a1255107
AD		 271 const enum amd_ip_block_type type;
272 const u32 major;
273 const u32 minor;
274 const u32 rev;
5fc3aeeb 275 const struct amd_ip_funcs *funcs;
97b2e202
AD		 276};
277
a1255107
AD		 278struct amdgpu_ip_block {
279 struct amdgpu_ip_block_status status;
280 const struct amdgpu_ip_block_version *version;
281};
282
2990a1fc
AD		 283int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
284 enum amd_ip_block_type type,
285 u32 major, u32 minor);
97b2e202 286
2990a1fc
AD		 287struct amdgpu_ip_block *
288amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
289 enum amd_ip_block_type type);
a1255107 290
2990a1fc
AD		 291int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
292 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202 293
97b2e202
AD		 294/*
295 * BIOS.
296 */
297bool amdgpu_get_bios(struct amdgpu_device *adev);
298bool amdgpu_read_bios(struct amdgpu_device *adev);
299
97b2e202
AD		 300/*
301 * Clocks
302 */
303
304#define AMDGPU_MAX_PPLL 3
305
306struct amdgpu_clock {
307 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
308 struct amdgpu_pll spll;
309 struct amdgpu_pll mpll;
310 /* 10 Khz units */
311 uint32_t default_mclk;
312 uint32_t default_sclk;
313 uint32_t default_dispclk;
314 uint32_t current_dispclk;
315 uint32_t dp_extclk;
316 uint32_t max_pixel_clock;
317};
318
97b2e202
AD		 319/* sub-allocation manager, it has to be protected by another lock.
320 * By conception this is an helper for other part of the driver
321 * like the indirect buffer or semaphore, which both have their
322 * locking.
323 *
324 * Principe is simple, we keep a list of sub allocation in offset
325 * order (first entry has offset == 0, last entry has the highest
326 * offset).
327 *
328 * When allocating new object we first check if there is room at
329 * the end total_size - (last_object_offset + last_object_size) >=
330 * alloc_size. If so we allocate new object there.
331 *
332 * When there is not enough room at the end, we start waiting for
333 * each sub object until we reach object_offset+object_size >=
334 * alloc_size, this object then become the sub object we return.
335 *
336 * Alignment can't be bigger than page size.
337 *
338 * Hole are not considered for allocation to keep things simple.
339 * Assumption is that there won't be hole (all object on same
340 * alignment).
341 */
6ba60b89
CK		 342
343#define AMDGPU_SA_NUM_FENCE_LISTS 32
344
97b2e202
AD		 345struct amdgpu_sa_manager {
346 wait_queue_head_t wq;
347 struct amdgpu_bo *bo;
348 struct list_head *hole;
6ba60b89 349 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 350 struct list_head olist;
351 unsigned size;
352 uint64_t gpu_addr;
353 void *cpu_ptr;
354 uint32_t domain;
355 uint32_t align;
356};
357
97b2e202
AD		 358/* sub-allocation buffer */
359struct amdgpu_sa_bo {
360 struct list_head olist;
361 struct list_head flist;
362 struct amdgpu_sa_manager *manager;
363 unsigned soffset;
364 unsigned eoffset;
f54d1867 365 struct dma_fence *fence;
97b2e202
AD		 366};
367
d573de2d
RZ		 368int amdgpu_fence_slab_init(void);
369void amdgpu_fence_slab_fini(void);
97b2e202 370
97b2e202
AD		 371/*
372 * IRQS.
373 */
374
375struct amdgpu_flip_work {
325cbba1 376 struct delayed_work flip_work;
97b2e202
AD		 377 struct work_struct unpin_work;
378 struct amdgpu_device *adev;
379 int crtc_id;
325cbba1 380 u32 target_vblank;
97b2e202
AD		 381 uint64_t base;
382 struct drm_pending_vblank_event *event;
765e7fbf 383 struct amdgpu_bo *old_abo;
f54d1867 384 struct dma_fence *excl;
1ffd2652 385 unsigned shared_count;
f54d1867
CW		 386 struct dma_fence **shared;
387 struct dma_fence_cb cb;
cb9e59d7 388 bool async;
97b2e202
AD		 389};
390
391
392/*
393 * CP & rings.
394 */
395
396struct amdgpu_ib {
397 struct amdgpu_sa_bo *sa_bo;
398 uint32_t length_dw;
399 uint64_t gpu_addr;
400 uint32_t *ptr;
de807f81 401 uint32_t flags;
97b2e202
AD		 402};
403
1b1f42d8 404extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 405
97b2e202
AD		 406/*
407 * file private structure
408 */
409
410struct amdgpu_fpriv {
411 struct amdgpu_vm vm;
b85891bd 412 struct amdgpu_bo_va *prt_va;
0f4b3c68 413 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 414 struct mutex bo_list_lock;
415 struct idr bo_list_handles;
0b492a4c 416 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 417};
418
021830d2 419int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
912dfc84 420int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
021830d2 421
b07c60c0 422int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 423 unsigned size, struct amdgpu_ib *ib);
4d9c514d 424void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 425 struct dma_fence *f);
b07c60c0 426int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 427 struct amdgpu_ib *ibs, struct amdgpu_job *job,
428 struct dma_fence **f);
97b2e202
AD		 429int amdgpu_ib_pool_init(struct amdgpu_device *adev);
430void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
431int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 432
433/*
434 * CS.
435 */
436struct amdgpu_cs_chunk {
437 uint32_t chunk_id;
438 uint32_t length_dw;
758ac17f 439 void *kdata;
97b2e202
AD		 440};
441
2624dd15
CZ		 442struct amdgpu_cs_post_dep {
443 struct drm_syncobj *syncobj;
444 struct dma_fence_chain *chain;
445 u64 point;
446};
447
97b2e202
AD		 448struct amdgpu_cs_parser {
449 struct amdgpu_device *adev;
450 struct drm_file *filp;
3cb485f3 451 struct amdgpu_ctx *ctx;
c3cca41e 452
97b2e202
AD		 453 /* chunks */
454 unsigned nchunks;
455 struct amdgpu_cs_chunk *chunks;
97b2e202 456
50838c8c
CK		 457 /* scheduler job object */
458 struct amdgpu_job *job;
0d346a14 459 struct drm_sched_entity *entity;
97b2e202 460
c3cca41e
CK		 461 /* buffer objects */
462 struct ww_acquire_ctx ticket;
463 struct amdgpu_bo_list *bo_list;
3fe89771 464 struct amdgpu_mn *mn;
c3cca41e
CK		 465 struct amdgpu_bo_list_entry vm_pd;
466 struct list_head validated;
f54d1867 467 struct dma_fence *fence;
c3cca41e 468 uint64_t bytes_moved_threshold;
00f06b24 469 uint64_t bytes_moved_vis_threshold;
c3cca41e 470 uint64_t bytes_moved;
00f06b24 471 uint64_t bytes_moved_vis;
662bfa61 472 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 473
474 /* user fence */
91acbeb6 475 struct amdgpu_bo_list_entry uf_entry;
660e8558 476
2624dd15
CZ		 477 unsigned num_post_deps;
478 struct amdgpu_cs_post_dep *post_deps;
97b2e202
AD		 479};
480
7270f839
CK		 481static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
482 uint32_t ib_idx, int idx)
97b2e202 483{
50838c8c 484 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 485}
486
7270f839
CK		 487static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
488 uint32_t ib_idx, int idx,
489 uint32_t value)
490{
50838c8c 491 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 492}
493
97b2e202
AD		 494/*
495 * Writeback
496 */
73469585 497#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
97b2e202
AD		 498
499struct amdgpu_wb {
500 struct amdgpu_bo *wb_obj;
501 volatile uint32_t *wb;
502 uint64_t gpu_addr;
503 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
504 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
505};
506
131b4b36
AD		 507int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
508void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 509
97b2e202
AD		 510/*
511 * Benchmarking
512 */
513void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
514
515
516/*
517 * Testing
518 */
519void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 520
97b2e202
AD		 521/*
522 * ASIC specific register table accessible by UMD
523 */
524struct amdgpu_allowed_register_entry {
525 uint32_t reg_offset;
97b2e202
AD		 526 bool grbm_indexed;
527};
528
97b2e202
AD		 529/*
530 * ASIC specific functions.
531 */
532struct amdgpu_asic_funcs {
533 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 534 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
535 u8 *bios, u32 length_bytes);
97b2e202
AD		 536 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
537 u32 sh_num, u32 reg_offset, u32 *value);
538 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
539 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 540 /* get the reference clock */
541 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 542 /* MM block clocks */
543 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
544 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 545 /* static power management */
546 int (*get_pcie_lanes)(struct amdgpu_device *adev);
547 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 548 /* get config memsize register */
549 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6 550 /* flush hdp write queue */
69882565 551 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
2df1b8b6 552 /* invalidate hdp read cache */
69882565
CK		 553 void (*invalidate_hdp)(struct amdgpu_device *adev,
554 struct amdgpu_ring *ring);
69070690
AD		 555 /* check if the asic needs a full reset of if soft reset will work */
556 bool (*need_full_reset)(struct amdgpu_device *adev);
5253163a
OZ		 557 /* initialize doorbell layout for specific asic*/
558 void (*init_doorbell_index)(struct amdgpu_device *adev);
b45e18ac
KR		 559 /* PCIe bandwidth usage */
560 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
561 uint64_t *count1);
44401889
AD		 562 /* do we need to reset the asic at init time (e.g., kexec) */
563 bool (*need_reset_on_init)(struct amdgpu_device *adev);
dcea6e65
KR		 564 /* PCIe replay counter */
565 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
97b2e202
AD		 566};
567
568/*
569 * IOCTL.
570 */
97b2e202
AD		 571int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
572 struct drm_file *filp);
573
97b2e202 574int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 575int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *filp);
97b2e202 577int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 578int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
579 struct drm_file *filp);
97b2e202 580
97b2e202
AD		 581/* VRAM scratch page for HDP bug, default vram page */
582struct amdgpu_vram_scratch {
583 struct amdgpu_bo *robj;
584 volatile uint32_t *ptr;
585 u64 gpu_addr;
586};
587
588/*
589 * ACPI
590 */
97b2e202
AD		 591struct amdgpu_atcs_functions {
592 bool get_ext_state;
593 bool pcie_perf_req;
594 bool pcie_dev_rdy;
595 bool pcie_bus_width;
596};
597
598struct amdgpu_atcs {
599 struct amdgpu_atcs_functions functions;
600};
601
a05502e5
HC		 602/*
603 * Firmware VRAM reservation
604 */
605struct amdgpu_fw_vram_usage {
606 u64 start_offset;
607 u64 size;
608 struct amdgpu_bo *reserved_bo;
609 void *va;
610};
611
d03846af
CZ		 612/*
613 * CGS
614 */
110e6f26
DA		 615struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
616void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 617
97b2e202
AD		 618/*
619 * Core structure, functions and helpers.
620 */
621typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
622typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
623
624typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
625typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
626
946a4d5b
SL		 627
628/*
629 * amdgpu nbio functions
630 *
946a4d5b 631 */
bf383fb6
AD		 632struct nbio_hdp_flush_reg {
633 u32 ref_and_mask_cp0;
634 u32 ref_and_mask_cp1;
635 u32 ref_and_mask_cp2;
636 u32 ref_and_mask_cp3;
637 u32 ref_and_mask_cp4;
638 u32 ref_and_mask_cp5;
639 u32 ref_and_mask_cp6;
640 u32 ref_and_mask_cp7;
641 u32 ref_and_mask_cp8;
642 u32 ref_and_mask_cp9;
643 u32 ref_and_mask_sdma0;
644 u32 ref_and_mask_sdma1;
645};
946a4d5b 646
88807dc8
OZ		 647struct amdgpu_mmio_remap {
648 u32 reg_offset;
649 resource_size_t bus_addr;
650};
651
946a4d5b 652struct amdgpu_nbio_funcs {
bf383fb6
AD		 653 const struct nbio_hdp_flush_reg *hdp_flush_reg;
654 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
655 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
656 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
657 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
658 u32 (*get_rev_id)(struct amdgpu_device *adev);
bf383fb6 659 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
69882565 660 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
bf383fb6
AD		 661 u32 (*get_memsize)(struct amdgpu_device *adev);
662 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
8987e2e2 663 bool use_doorbell, int doorbell_index, int doorbell_size);
b45ddfe8
LL		 664 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
665 int doorbell_index);
bf383fb6
AD		 666 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
667 bool enable);
668 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
669 bool enable);
670 void (*ih_doorbell_range)(struct amdgpu_device *adev,
671 bool use_doorbell, int doorbell_index);
672 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
673 bool enable);
674 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
675 bool enable);
676 void (*get_clockgating_state)(struct amdgpu_device *adev,
677 u32 *flags);
678 void (*ih_control)(struct amdgpu_device *adev);
679 void (*init_registers)(struct amdgpu_device *adev);
680 void (*detect_hw_virt)(struct amdgpu_device *adev);
88807dc8 681 void (*remap_hdp_registers)(struct amdgpu_device *adev);
946a4d5b
SL		 682};
683
634c96e3
HZ		 684struct amdgpu_df_funcs {
685 void (*init)(struct amdgpu_device *adev);
e4cf4bf5 686 void (*sw_init)(struct amdgpu_device *adev);
634c96e3
HZ		 687 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
688 bool enable);
689 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
690 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
691 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
692 bool enable);
693 void (*get_clockgating_state)(struct amdgpu_device *adev,
694 u32 *flags);
8f9b2e50
AD		 695 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
696 bool enable);
992af942
JK		 697 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
698 int is_enable);
699 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
700 int is_disable);
701 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
702 uint64_t *count);
634c96e3 703};
4522824c
SL		 704/* Define the HW IP blocks will be used in driver , add more if necessary */
705enum amd_hw_ip_block_type {
706 GC_HWIP = 1,
707 HDP_HWIP,
708 SDMA0_HWIP,
709 SDMA1_HWIP,
710 MMHUB_HWIP,
711 ATHUB_HWIP,
712 NBIO_HWIP,
713 MP0_HWIP,
e6636ae1 714 MP1_HWIP,
4522824c
SL		 715 UVD_HWIP,
716 VCN_HWIP = UVD_HWIP,
717 VCE_HWIP,
718 DF_HWIP,
719 DCE_HWIP,
720 OSSSYS_HWIP,
721 SMUIO_HWIP,
722 PWR_HWIP,
723 NBIF_HWIP,
e6636ae1 724 THM_HWIP,
73b19174 725 CLK_HWIP,
4522824c
SL		 726 MAX_HWIP
727};
728
729#define HWIP_MAX_INSTANCE 6
730
11dc9364 731struct amd_powerplay {
11dc9364 732 void *pp_handle;
11dc9364
RZ		 733 const struct amd_pm_funcs *pp_funcs;
734};
735
0c49e0b8 736#define AMDGPU_RESET_MAGIC_NUM 64
e4cf4bf5 737#define AMDGPU_MAX_DF_PERFMONS 4
97b2e202
AD		 738struct amdgpu_device {
739 struct device *dev;
740 struct drm_device *ddev;
741 struct pci_dev *pdev;
97b2e202 742
a8fe58ce
MB		 743#ifdef CONFIG_DRM_AMD_ACP
744 struct amdgpu_acp acp;
745#endif
746
97b2e202 747 /* ASIC */
2f7d10b3 748 enum amd_asic_type asic_type;
97b2e202
AD		 749 uint32_t family;
750 uint32_t rev_id;
751 uint32_t external_rev_id;
752 unsigned long flags;
753 int usec_timeout;
754 const struct amdgpu_asic_funcs *asic_funcs;
755 bool shutdown;
97b2e202 756 bool need_dma32;
fd5fd480 757 bool need_swiotlb;
97b2e202 758 bool accel_working;
97b2e202
AD		 759 struct notifier_block acpi_nb;
760 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
761 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 762 unsigned debugfs_count;
97b2e202 763#if defined(CONFIG_DEBUG_FS)
adcec288 764 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202 765#endif
102c16a0 766 struct amdgpu_atif *atif;
97b2e202
AD		 767 struct amdgpu_atcs atcs;
768 struct mutex srbm_mutex;
769 /* GRBM index mutex. Protects concurrent access to GRBM index */
770 struct mutex grbm_idx_mutex;
771 struct dev_pm_domain vga_pm_domain;
772 bool have_disp_power_ref;
773
774 /* BIOS */
0cdd5005 775 bool is_atom_fw;
97b2e202 776 uint8_t *bios;
a9f5db9c 777 uint32_t bios_size;
5af2c10d 778 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 779 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 780 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
781
782 /* Register/doorbell mmio */
783 resource_size_t rmmio_base;
784 resource_size_t rmmio_size;
785 void __iomem *rmmio;
786 /* protects concurrent MM_INDEX/DATA based register access */
787 spinlock_t mmio_idx_lock;
88807dc8 788 struct amdgpu_mmio_remap rmmio_remap;
97b2e202
AD		 789 /* protects concurrent SMC based register access */
790 spinlock_t smc_idx_lock;
791 amdgpu_rreg_t smc_rreg;
792 amdgpu_wreg_t smc_wreg;
793 /* protects concurrent PCIE register access */
794 spinlock_t pcie_idx_lock;
795 amdgpu_rreg_t pcie_rreg;
796 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 797 amdgpu_rreg_t pciep_rreg;
798 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 799 /* protects concurrent UVD register access */
800 spinlock_t uvd_ctx_idx_lock;
801 amdgpu_rreg_t uvd_ctx_rreg;
802 amdgpu_wreg_t uvd_ctx_wreg;
803 /* protects concurrent DIDT register access */
804 spinlock_t didt_idx_lock;
805 amdgpu_rreg_t didt_rreg;
806 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 807 /* protects concurrent gc_cac register access */
808 spinlock_t gc_cac_idx_lock;
809 amdgpu_rreg_t gc_cac_rreg;
810 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 811 /* protects concurrent se_cac register access */
812 spinlock_t se_cac_idx_lock;
813 amdgpu_rreg_t se_cac_rreg;
814 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 815 /* protects concurrent ENDPOINT (audio) register access */
816 spinlock_t audio_endpt_idx_lock;
817 amdgpu_block_rreg_t audio_endpt_rreg;
818 amdgpu_block_wreg_t audio_endpt_wreg;
819 void __iomem *rio_mem;
820 resource_size_t rio_mem_size;
821 struct amdgpu_doorbell doorbell;
822
823 /* clock/pll info */
824 struct amdgpu_clock clock;
825
826 /* MC */
770d13b1 827 struct amdgpu_gmc gmc;
97b2e202 828 struct amdgpu_gart gart;
92e71b06 829 dma_addr_t dummy_page_addr;
97b2e202 830 struct amdgpu_vm_manager vm_manager;
e60f8db5 831 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 832
833 /* memory management */
834 struct amdgpu_mman mman;
97b2e202
AD		 835 struct amdgpu_vram_scratch vram_scratch;
836 struct amdgpu_wb wb;
97b2e202 837 atomic64_t num_bytes_moved;
dbd5ed60 838 atomic64_t num_evictions;
68e2c5ff 839 atomic64_t num_vram_cpu_page_faults;
d94aed5a 840 atomic_t gpu_reset_counter;
f1892138 841 atomic_t vram_lost_counter;
97b2e202 842
95844d20
MO		 843 /* data for buffer migration throttling */
844 struct {
845 spinlock_t lock;
846 s64 last_update_us;
847 s64 accum_us; /* accumulated microseconds */
00f06b24 848 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 849 u32 log2_max_MBps;
850 } mm_stats;
851
97b2e202 852 /* display */
9accf2fd 853 bool enable_virtual_display;
97b2e202 854 struct amdgpu_mode_info mode_info;
4562236b 855 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 856 struct work_struct hotplug_work;
857 struct amdgpu_irq_src crtc_irq;
d2574c33 858 struct amdgpu_irq_src vupdate_irq;
97b2e202
AD		 859 struct amdgpu_irq_src pageflip_irq;
860 struct amdgpu_irq_src hpd_irq;
861
862 /* rings */
76bf0db5 863 u64 fence_context;
97b2e202
AD		 864 unsigned num_rings;
865 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
866 bool ib_pool_ready;
867 struct amdgpu_sa_manager ring_tmp_bo;
868
869 /* interrupts */
870 struct amdgpu_irq irq;
871
1f7371b2
AD		 872 /* powerplay */
873 struct amd_powerplay powerplay;
f3898ea1 874 bool pp_force_state_enabled;
1f7371b2 875
137d63ab
HR		 876 /* smu */
877 struct smu_context smu;
878
97b2e202
AD		 879 /* dpm */
880 struct amdgpu_pm pm;
881 u32 cg_flags;
882 u32 pg_flags;
883
97b2e202
AD		 884 /* gfx */
885 struct amdgpu_gfx gfx;
886
887 /* sdma */
c113ea1c 888 struct amdgpu_sdma sdma;
97b2e202 889
b43aaee6
LL		 890 /* uvd */
891 struct amdgpu_uvd uvd;
892
893 /* vce */
894 struct amdgpu_vce vce;
895
896 /* vcn */
897 struct amdgpu_vcn vcn;
97b2e202
AD		 898
899 /* firmwares */
900 struct amdgpu_firmware firmware;
901
0e5ca0d1
HR		 902 /* PSP */
903 struct psp_context psp;
904
97b2e202
AD		 905 /* GDS */
906 struct amdgpu_gds gds;
907
611736d8
FK		 908 /* KFD */
909 struct amdgpu_kfd_dev kfd;
910
4562236b
HW		 911 /* display related functionality */
912 struct amdgpu_display_manager dm;
913
a1255107 914 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 915 int num_ip_blocks;
97b2e202
AD		 916 struct mutex mn_lock;
917 DECLARE_HASHTABLE(mn_hash, 7);
918
919 /* tracking pinned memory */
a5ccfe5c
MD		 920 atomic64_t vram_pin_size;
921 atomic64_t visible_pin_size;
922 atomic64_t gart_pin_size;
130e0371 923
4522824c
SL		 924 /* soc15 register offset based on ip, instance and segment */
925 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
926
946a4d5b 927 const struct amdgpu_nbio_funcs *nbio_funcs;
634c96e3 928 const struct amdgpu_df_funcs *df_funcs;
946a4d5b 929
2dc80b00 930 /* delayed work_func for deferring clockgating during resume */
beff74bc 931 struct delayed_work delayed_init_work;
2dc80b00 932
5a5099cb 933 struct amdgpu_virt virt;
a05502e5
HC		 934 /* firmware VRAM reservation */
935 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 936
937 /* link all shadow bo */
938 struct list_head shadow_list;
939 struct mutex shadow_list_lock;
795f2813
AR		 940 /* keep an lru list of rings by HW IP */
941 struct list_head ring_lru_list;
942 spinlock_t ring_lru_list_lock;
5c1354bd 943
c836fec5
JQ		 944 /* record hw reset is performed */
945 bool has_hw_reset;
0c49e0b8 946 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 947
44779b43
RZ		 948 /* s3/s4 mask */
949 bool in_suspend;
950
47ed4e1c
KW		 951 /* record last mm index being written through WREG32*/
952 unsigned long last_mm_index;
13a752e3
ML		 953 bool in_gpu_reset;
954 struct mutex lock_reset;
409c5191 955 struct amdgpu_doorbell_index doorbell_index;
d4535e2c 956
26bc5340 957 int asic_reset_res;
d4535e2c 958 struct work_struct xgmi_reset_work;
9b638f97 959
0c5ccf14 960 bool in_baco_reset;
912dfc84
EQ		 961
962 long gfx_timeout;
963 long sdma_timeout;
964 long video_timeout;
965 long compute_timeout;
fb2dbfd2
KR		 966
967 uint64_t unique_id;
e4cf4bf5 968 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
97b2e202
AD		 969};
970
a7d64de6
CK		 971static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
972{
973 return container_of(bdev, struct amdgpu_device, mman.bdev);
974}
975
97b2e202
AD		 976int amdgpu_device_init(struct amdgpu_device *adev,
977 struct drm_device *ddev,
978 struct pci_dev *pdev,
979 uint32_t flags);
980void amdgpu_device_fini(struct amdgpu_device *adev);
981int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
982
983uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 984 uint32_t acc_flags);
97b2e202 985void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 986 uint32_t acc_flags);
421a2a30
ML		 987void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
988uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
989
97b2e202
AD		 990u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
991void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
992
4562236b
HW		 993bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
994bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
995
9475a943
SL		 996int emu_soc_asic_init(struct amdgpu_device *adev);
997
97b2e202
AD		 998/*
999 * Registers read & write functions.
1000 */
15d72fd7
ML		 1001
1002#define AMDGPU_REGS_IDX (1<<0)
1003#define AMDGPU_REGS_NO_KIQ (1<<1)
1004
1005#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1006#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1007
421a2a30
ML		 1008#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1009#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1010
15d72fd7
ML		 1011#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1012#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1013#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1014#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1015#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1016#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1017#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1018#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1019#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1020#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1021#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1022#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1023#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1024#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1025#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1026#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1027#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1028#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1029#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1030#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1031#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1032#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1033#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1034#define WREG32_P(reg, val, mask) \
1035 do { \
1036 uint32_t tmp_ = RREG32(reg); \
1037 tmp_ &= (mask); \
1038 tmp_ |= ((val) & ~(mask)); \
1039 WREG32(reg, tmp_); \
1040 } while (0)
1041#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1042#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1043#define WREG32_PLL_P(reg, val, mask) \
1044 do { \
1045 uint32_t tmp_ = RREG32_PLL(reg); \
1046 tmp_ &= (mask); \
1047 tmp_ |= ((val) & ~(mask)); \
1048 WREG32_PLL(reg, tmp_); \
1049 } while (0)
1050#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1051#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1052#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1053
97b2e202
AD		 1054#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1055#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1056
1057#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1058 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1059 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1060
1061#define REG_GET_FIELD(value, reg, field) \
1062 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1063
1064#define WREG32_FIELD(reg, field, val) \
1065 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1066
ccaf3574
TSD		 1067#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1068 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1069
97b2e202
AD		 1070/*
1071 * BIOS helpers.
1072 */
1073#define RBIOS8(i) (adev->bios[i])
1074#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1075#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1076
97b2e202
AD		 1077/*
1078 * ASICs macro.
1079 */
1080#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1081#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1082#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1083#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1084#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1085#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1086#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1087#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1088#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1089#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1090#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1091#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
69882565
CK		 1092#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1093#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
69070690 1094#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
5253163a 1095#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
b45e18ac 1096#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
44401889 1097#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
dcea6e65 1098#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
97b2e202
AD		 1099
1100/* Common functions */
12938fad 1101bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
5f152b5e 1102int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12938fad 1103 struct amdgpu_job* job);
8111c387 1104void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1105bool amdgpu_device_need_post(struct amdgpu_device *adev);
d5fc5e82 1106
00f06b24
JB		 1107void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1108 u64 num_vis_bytes);
d6895ad3 1109int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
9c3f2b54 1110void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1111 const u32 *registers,
1112 const u32 array_size);
1113
1114bool amdgpu_device_is_px(struct drm_device *dev);
992af942
JK		 1115bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1116 struct amdgpu_device *peer_adev);
1117
97b2e202
AD		 1118/* atpx handler */
1119#if defined(CONFIG_VGA_SWITCHEROO)
1120void amdgpu_register_atpx_handler(void);
1121void amdgpu_unregister_atpx_handler(void);
a78fe133 1122bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1123bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1124bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1125bool amdgpu_has_atpx(void);
97b2e202
AD		 1126#else
1127static inline void amdgpu_register_atpx_handler(void) {}
1128static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1129static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1130static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1131static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1132static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1133#endif
1134
24aeefcd
LP		 1135#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1136void *amdgpu_atpx_get_dhandle(void);
1137#else
1138static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1139#endif
1140
97b2e202
AD		 1141/*
1142 * KMS
1143 */
1144extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1145extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1146
1147int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1148void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1149void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1150int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1151void amdgpu_driver_postclose_kms(struct drm_device *dev,
1152 struct drm_file *file_priv);
cdd61df6 1153int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1154int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1155int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1156u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1157int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1158void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1159long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1160 unsigned long arg);
1161
97b2e202
AD		 1162/*
1163 * functions used by amdgpu_encoder.c
1164 */
1165struct amdgpu_afmt_acr {
1166 u32 clock;
1167
1168 int n_32khz;
1169 int cts_32khz;
1170
1171 int n_44_1khz;
1172 int cts_44_1khz;
1173
1174 int n_48khz;
1175 int cts_48khz;
1176
1177};
1178
1179struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1180
1181/* amdgpu_acpi.c */
1182#if defined(CONFIG_ACPI)
1183int amdgpu_acpi_init(struct amdgpu_device *adev);
1184void amdgpu_acpi_fini(struct amdgpu_device *adev);
1185bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1186int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1187 u8 perf_req, bool advertise);
1188int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
206bbafe
DF		 1189
1190void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1191 struct amdgpu_dm_backlight_caps *caps);
97b2e202
AD		 1192#else
1193static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1194static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1195#endif
1196
9cca0b8e
CK		 1197int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1198 uint64_t addr, struct amdgpu_bo **bo,
1199 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1200
4562236b
HW		 1201#if defined(CONFIG_DRM_AMD_DC)
1202int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1203#else
1204static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1205#endif
1206
97b2e202 1207#include "amdgpu_object.h"
e4cf4bf5
JK		 1208
1209/* used by df_v3_6.c and amdgpu_pmu.c */
1210#define AMDGPU_PMU_ATTR(_name, _object) \
1211static ssize_t \
1212_name##_show(struct device *dev, \
1213 struct device_attribute *attr, \
1214 char *page) \
1215{ \
1216 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1217 return sprintf(page, _object "\n"); \
1218} \
1219 \
1220static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1221
97b2e202 1222#endif
e4cf4bf5 1223
Linux 6.x block layer and io_uring tree(s)