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drm/amd/powerplay: add helper function to get smu firmware & if version
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
8290268f
CK		 31#include "amdgpu_ctx.h"
32
97b2e202
AD		 33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
a9f87f64 37#include <linux/rbtree.h>
97b2e202 38#include <linux/hashtable.h>
f54d1867 39#include <linux/dma-fence.h>
97b2e202 40
248a1d6f
MY		 41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 46
d03846af 47#include <drm/drmP.h>
97b2e202 48#include <drm/drm_gem.h>
7e5a547f 49#include <drm/amdgpu_drm.h>
1b1f42d8 50#include <drm/gpu_scheduler.h>
97b2e202 51
78c16834 52#include <kgd_kfd_interface.h>
c79563a3
RZ		 53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
78c16834 55
5fc3aeeb 56#include "amd_shared.h"
97b2e202
AD		 57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
c632d799 61#include "amdgpu_ttm.h"
0e5ca0d1 62#include "amdgpu_psp.h"
97b2e202 63#include "amdgpu_gds.h"
56113504 64#include "amdgpu_sync.h"
78023016 65#include "amdgpu_ring.h"
073440d2 66#include "amdgpu_vm.h"
cf097881 67#include "amdgpu_dpm.h"
a8fe58ce 68#include "amdgpu_acp.h"
4df654d2 69#include "amdgpu_uvd.h"
5e568178 70#include "amdgpu_vce.h"
95aa13f6 71#include "amdgpu_vcn.h"
9a189996 72#include "amdgpu_mn.h"
770d13b1 73#include "amdgpu_gmc.h"
448fe192 74#include "amdgpu_gfx.h"
bb7743bc 75#include "amdgpu_sdma.h"
4562236b 76#include "amdgpu_dm.h"
ceeb50ed 77#include "amdgpu_virt.h"
7946340f 78#include "amdgpu_csa.h"
3490bdb5 79#include "amdgpu_gart.h"
75758255 80#include "amdgpu_debugfs.h"
050d9d43 81#include "amdgpu_job.h"
4a8c21a1 82#include "amdgpu_bo_list.h"
2cddc50e 83#include "amdgpu_gem.h"
cde577bd 84#include "amdgpu_doorbell.h"
611736d8 85#include "amdgpu_amdkfd.h"
137d63ab 86#include "amdgpu_smu.h"
c79563a3 87
62d73fbc
EQ		 88#define MAX_GPU_INSTANCE 16
89
90struct amdgpu_gpu_instance
91{
92 struct amdgpu_device *adev;
93 int mgpu_fan_enabled;
94};
95
96struct amdgpu_mgpu_info
97{
98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
99 struct mutex mutex;
100 uint32_t num_gpu;
101 uint32_t num_dgpu;
102 uint32_t num_apu;
103};
104
97b2e202
AD		 105/*
106 * Modules parameters.
107 */
108extern int amdgpu_modeset;
109extern int amdgpu_vram_limit;
218b5dcd 110extern int amdgpu_vis_vram_limit;
83e74db6 111extern int amdgpu_gart_size;
36d38372 112extern int amdgpu_gtt_size;
95844d20 113extern int amdgpu_moverate;
97b2e202
AD		 114extern int amdgpu_benchmarking;
115extern int amdgpu_testing;
116extern int amdgpu_audio;
117extern int amdgpu_disp_priority;
118extern int amdgpu_hw_i2c;
119extern int amdgpu_pcie_gen2;
120extern int amdgpu_msi;
121extern int amdgpu_lockup_timeout;
122extern int amdgpu_dpm;
e635ee07 123extern int amdgpu_fw_load_type;
97b2e202
AD		 124extern int amdgpu_aspm;
125extern int amdgpu_runtime_pm;
0b693f0b 126extern uint amdgpu_ip_block_mask;
97b2e202
AD		 127extern int amdgpu_bapm;
128extern int amdgpu_deep_color;
129extern int amdgpu_vm_size;
130extern int amdgpu_vm_block_size;
d07f14be 131extern int amdgpu_vm_fragment_size;
d9c13156 132extern int amdgpu_vm_fault_stop;
b495bd3a 133extern int amdgpu_vm_debug;
9a4b7d4c 134extern int amdgpu_vm_update_mode;
4562236b 135extern int amdgpu_dc;
1333f723 136extern int amdgpu_sched_jobs;
4afcb303 137extern int amdgpu_sched_hw_submission;
0b693f0b
RZ		 138extern uint amdgpu_pcie_gen_cap;
139extern uint amdgpu_pcie_lane_cap;
140extern uint amdgpu_cg_mask;
141extern uint amdgpu_pg_mask;
142extern uint amdgpu_sdma_phase_quantum;
6f8941a2 143extern char *amdgpu_disable_cu;
9accf2fd 144extern char *amdgpu_virtual_display;
0b693f0b 145extern uint amdgpu_pp_feature_mask;
6a7f76e7 146extern int amdgpu_vram_page_split;
bce23e00
AD		 147extern int amdgpu_ngg;
148extern int amdgpu_prim_buf_per_se;
149extern int amdgpu_pos_buf_per_se;
150extern int amdgpu_cntl_sb_buf_per_se;
151extern int amdgpu_param_buf_per_se;
65781c78 152extern int amdgpu_job_hang_limit;
e8835e0e 153extern int amdgpu_lbpw;
4a75aefe 154extern int amdgpu_compute_multipipe;
dcebf026 155extern int amdgpu_gpu_recovery;
bfca0289 156extern int amdgpu_emu_mode;
7951e376 157extern uint amdgpu_smu_memory_pool_size;
7875a226 158extern uint amdgpu_dc_feature_mask;
62d73fbc 159extern struct amdgpu_mgpu_info mgpu_info;
1218252f 160extern int amdgpu_ras_enable;
161extern uint amdgpu_ras_mask;
97b2e202 162
6dd13096
FK		 163#ifdef CONFIG_DRM_AMDGPU_SI
164extern int amdgpu_si_support;
165#endif
7df28986
FK		 166#ifdef CONFIG_DRM_AMDGPU_CIK
167extern int amdgpu_cik_support;
168#endif
97b2e202 169
08d1bdd4 170#define AMDGPU_VM_MAX_NUM_CTX 4096
6c8d74ca 171#define AMDGPU_SG_THRESHOLD (256*1024*1024)
55ed8caf 172#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 173#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202 174#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
8c5e13ec 175#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
97b2e202
AD		 176/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
177#define AMDGPU_IB_POOL_SIZE 16
178#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
179#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 180#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 181
97b2e202
AD		 182/* hard reset data */
183#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
184
185/* reset flags */
186#define AMDGPU_RESET_GFX (1 << 0)
187#define AMDGPU_RESET_COMPUTE (1 << 1)
188#define AMDGPU_RESET_DMA (1 << 2)
189#define AMDGPU_RESET_CP (1 << 3)
190#define AMDGPU_RESET_GRBM (1 << 4)
191#define AMDGPU_RESET_DMA1 (1 << 5)
192#define AMDGPU_RESET_RLC (1 << 6)
193#define AMDGPU_RESET_SEM (1 << 7)
194#define AMDGPU_RESET_IH (1 << 8)
195#define AMDGPU_RESET_VMC (1 << 9)
196#define AMDGPU_RESET_MC (1 << 10)
197#define AMDGPU_RESET_DISPLAY (1 << 11)
198#define AMDGPU_RESET_UVD (1 << 12)
199#define AMDGPU_RESET_VCE (1 << 13)
200#define AMDGPU_RESET_VCE1 (1 << 14)
201
97b2e202
AD		 202/* max cursor sizes (in pixels) */
203#define CIK_CURSOR_WIDTH 128
204#define CIK_CURSOR_HEIGHT 128
205
206struct amdgpu_device;
97b2e202 207struct amdgpu_ib;
97b2e202 208struct amdgpu_cs_parser;
bb977d37 209struct amdgpu_job;
97b2e202 210struct amdgpu_irq_src;
0b492a4c 211struct amdgpu_fpriv;
9cca0b8e 212struct amdgpu_bo_va_mapping;
102c16a0 213struct amdgpu_atif;
97b2e202
AD		 214
215enum amdgpu_cp_irq {
216 AMDGPU_CP_IRQ_GFX_EOP = 0,
217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
218 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
222 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
225
226 AMDGPU_CP_IRQ_LAST
227};
228
97b2e202
AD		 229enum amdgpu_thermal_irq {
230 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
231 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
232
233 AMDGPU_THERMAL_IRQ_LAST
234};
235
4e638ae9
XY		 236enum amdgpu_kiq_irq {
237 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
238 AMDGPU_CP_KIQ_IRQ_LAST
239};
240
3890d111
ED		 241#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
242#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
4944af67 243#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
3890d111 244
43fa561f 245int amdgpu_device_ip_set_clockgating_state(void *dev,
2990a1fc
AD		 246 enum amd_ip_block_type block_type,
247 enum amd_clockgating_state state);
43fa561f 248int amdgpu_device_ip_set_powergating_state(void *dev,
2990a1fc
AD		 249 enum amd_ip_block_type block_type,
250 enum amd_powergating_state state);
251void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
252 u32 *flags);
253int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
254 enum amd_ip_block_type block_type);
255bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
256 enum amd_ip_block_type block_type);
97b2e202 257
a1255107
AD		 258#define AMDGPU_MAX_IP_NUM 16
259
260struct amdgpu_ip_block_status {
261 bool valid;
262 bool sw;
263 bool hw;
264 bool late_initialized;
265 bool hang;
266};
267
97b2e202 268struct amdgpu_ip_block_version {
a1255107
AD		 269 const enum amd_ip_block_type type;
270 const u32 major;
271 const u32 minor;
272 const u32 rev;
5fc3aeeb 273 const struct amd_ip_funcs *funcs;
97b2e202
AD		 274};
275
a1255107
AD		 276struct amdgpu_ip_block {
277 struct amdgpu_ip_block_status status;
278 const struct amdgpu_ip_block_version *version;
279};
280
2990a1fc
AD		 281int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
282 enum amd_ip_block_type type,
283 u32 major, u32 minor);
97b2e202 284
2990a1fc
AD		 285struct amdgpu_ip_block *
286amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
287 enum amd_ip_block_type type);
a1255107 288
2990a1fc
AD		 289int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
290 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202 291
97b2e202
AD		 292/*
293 * BIOS.
294 */
295bool amdgpu_get_bios(struct amdgpu_device *adev);
296bool amdgpu_read_bios(struct amdgpu_device *adev);
297
97b2e202
AD		 298/*
299 * Clocks
300 */
301
302#define AMDGPU_MAX_PPLL 3
303
304struct amdgpu_clock {
305 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
306 struct amdgpu_pll spll;
307 struct amdgpu_pll mpll;
308 /* 10 Khz units */
309 uint32_t default_mclk;
310 uint32_t default_sclk;
311 uint32_t default_dispclk;
312 uint32_t current_dispclk;
313 uint32_t dp_extclk;
314 uint32_t max_pixel_clock;
315};
316
97b2e202
AD		 317/* sub-allocation manager, it has to be protected by another lock.
318 * By conception this is an helper for other part of the driver
319 * like the indirect buffer or semaphore, which both have their
320 * locking.
321 *
322 * Principe is simple, we keep a list of sub allocation in offset
323 * order (first entry has offset == 0, last entry has the highest
324 * offset).
325 *
326 * When allocating new object we first check if there is room at
327 * the end total_size - (last_object_offset + last_object_size) >=
328 * alloc_size. If so we allocate new object there.
329 *
330 * When there is not enough room at the end, we start waiting for
331 * each sub object until we reach object_offset+object_size >=
332 * alloc_size, this object then become the sub object we return.
333 *
334 * Alignment can't be bigger than page size.
335 *
336 * Hole are not considered for allocation to keep things simple.
337 * Assumption is that there won't be hole (all object on same
338 * alignment).
339 */
6ba60b89
CK		 340
341#define AMDGPU_SA_NUM_FENCE_LISTS 32
342
97b2e202
AD		 343struct amdgpu_sa_manager {
344 wait_queue_head_t wq;
345 struct amdgpu_bo *bo;
346 struct list_head *hole;
6ba60b89 347 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 348 struct list_head olist;
349 unsigned size;
350 uint64_t gpu_addr;
351 void *cpu_ptr;
352 uint32_t domain;
353 uint32_t align;
354};
355
97b2e202
AD		 356/* sub-allocation buffer */
357struct amdgpu_sa_bo {
358 struct list_head olist;
359 struct list_head flist;
360 struct amdgpu_sa_manager *manager;
361 unsigned soffset;
362 unsigned eoffset;
f54d1867 363 struct dma_fence *fence;
97b2e202
AD		 364};
365
d573de2d
RZ		 366int amdgpu_fence_slab_init(void);
367void amdgpu_fence_slab_fini(void);
97b2e202 368
97b2e202
AD		 369/*
370 * IRQS.
371 */
372
373struct amdgpu_flip_work {
325cbba1 374 struct delayed_work flip_work;
97b2e202
AD		 375 struct work_struct unpin_work;
376 struct amdgpu_device *adev;
377 int crtc_id;
325cbba1 378 u32 target_vblank;
97b2e202
AD		 379 uint64_t base;
380 struct drm_pending_vblank_event *event;
765e7fbf 381 struct amdgpu_bo *old_abo;
f54d1867 382 struct dma_fence *excl;
1ffd2652 383 unsigned shared_count;
f54d1867
CW		 384 struct dma_fence **shared;
385 struct dma_fence_cb cb;
cb9e59d7 386 bool async;
97b2e202
AD		 387};
388
389
390/*
391 * CP & rings.
392 */
393
394struct amdgpu_ib {
395 struct amdgpu_sa_bo *sa_bo;
396 uint32_t length_dw;
397 uint64_t gpu_addr;
398 uint32_t *ptr;
de807f81 399 uint32_t flags;
97b2e202
AD		 400};
401
1b1f42d8 402extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 403
97b2e202
AD		 404/*
405 * file private structure
406 */
407
408struct amdgpu_fpriv {
409 struct amdgpu_vm vm;
b85891bd 410 struct amdgpu_bo_va *prt_va;
0f4b3c68 411 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 412 struct mutex bo_list_lock;
413 struct idr bo_list_handles;
0b492a4c 414 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 415};
416
021830d2
BN		 417int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
418
b07c60c0 419int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 420 unsigned size, struct amdgpu_ib *ib);
4d9c514d 421void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 422 struct dma_fence *f);
b07c60c0 423int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 424 struct amdgpu_ib *ibs, struct amdgpu_job *job,
425 struct dma_fence **f);
97b2e202
AD		 426int amdgpu_ib_pool_init(struct amdgpu_device *adev);
427void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
428int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 429
430/*
431 * CS.
432 */
433struct amdgpu_cs_chunk {
434 uint32_t chunk_id;
435 uint32_t length_dw;
758ac17f 436 void *kdata;
97b2e202
AD		 437};
438
2624dd15
CZ		 439struct amdgpu_cs_post_dep {
440 struct drm_syncobj *syncobj;
441 struct dma_fence_chain *chain;
442 u64 point;
443};
444
97b2e202
AD		 445struct amdgpu_cs_parser {
446 struct amdgpu_device *adev;
447 struct drm_file *filp;
3cb485f3 448 struct amdgpu_ctx *ctx;
c3cca41e 449
97b2e202
AD		 450 /* chunks */
451 unsigned nchunks;
452 struct amdgpu_cs_chunk *chunks;
97b2e202 453
50838c8c
CK		 454 /* scheduler job object */
455 struct amdgpu_job *job;
0d346a14 456 struct drm_sched_entity *entity;
97b2e202 457
c3cca41e
CK		 458 /* buffer objects */
459 struct ww_acquire_ctx ticket;
460 struct amdgpu_bo_list *bo_list;
3fe89771 461 struct amdgpu_mn *mn;
c3cca41e
CK		 462 struct amdgpu_bo_list_entry vm_pd;
463 struct list_head validated;
f54d1867 464 struct dma_fence *fence;
c3cca41e 465 uint64_t bytes_moved_threshold;
00f06b24 466 uint64_t bytes_moved_vis_threshold;
c3cca41e 467 uint64_t bytes_moved;
00f06b24 468 uint64_t bytes_moved_vis;
662bfa61 469 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 470
471 /* user fence */
91acbeb6 472 struct amdgpu_bo_list_entry uf_entry;
660e8558 473
2624dd15
CZ		 474 unsigned num_post_deps;
475 struct amdgpu_cs_post_dep *post_deps;
97b2e202
AD		 476};
477
7270f839
CK		 478static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
479 uint32_t ib_idx, int idx)
97b2e202 480{
50838c8c 481 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 482}
483
7270f839
CK		 484static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
485 uint32_t ib_idx, int idx,
486 uint32_t value)
487{
50838c8c 488 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 489}
490
97b2e202
AD		 491/*
492 * Writeback
493 */
73469585 494#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
97b2e202
AD		 495
496struct amdgpu_wb {
497 struct amdgpu_bo *wb_obj;
498 volatile uint32_t *wb;
499 uint64_t gpu_addr;
500 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
501 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
502};
503
131b4b36
AD		 504int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
505void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 506
97b2e202
AD		 507/*
508 * Benchmarking
509 */
510void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
511
512
513/*
514 * Testing
515 */
516void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 517
97b2e202
AD		 518/*
519 * ASIC specific register table accessible by UMD
520 */
521struct amdgpu_allowed_register_entry {
522 uint32_t reg_offset;
97b2e202
AD		 523 bool grbm_indexed;
524};
525
97b2e202
AD		 526/*
527 * ASIC specific functions.
528 */
529struct amdgpu_asic_funcs {
530 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 531 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
532 u8 *bios, u32 length_bytes);
97b2e202
AD		 533 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
534 u32 sh_num, u32 reg_offset, u32 *value);
535 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
536 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 537 /* get the reference clock */
538 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 539 /* MM block clocks */
540 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
541 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 542 /* static power management */
543 int (*get_pcie_lanes)(struct amdgpu_device *adev);
544 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 545 /* get config memsize register */
546 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6 547 /* flush hdp write queue */
69882565 548 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
2df1b8b6 549 /* invalidate hdp read cache */
69882565
CK		 550 void (*invalidate_hdp)(struct amdgpu_device *adev,
551 struct amdgpu_ring *ring);
69070690
AD		 552 /* check if the asic needs a full reset of if soft reset will work */
553 bool (*need_full_reset)(struct amdgpu_device *adev);
5253163a
OZ		 554 /* initialize doorbell layout for specific asic*/
555 void (*init_doorbell_index)(struct amdgpu_device *adev);
b45e18ac
KR		 556 /* PCIe bandwidth usage */
557 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
558 uint64_t *count1);
44401889
AD		 559 /* do we need to reset the asic at init time (e.g., kexec) */
560 bool (*need_reset_on_init)(struct amdgpu_device *adev);
97b2e202
AD		 561};
562
563/*
564 * IOCTL.
565 */
97b2e202
AD		 566int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
567 struct drm_file *filp);
568
97b2e202 569int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 570int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
571 struct drm_file *filp);
97b2e202 572int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 573int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *filp);
97b2e202 575
97b2e202
AD		 576/* VRAM scratch page for HDP bug, default vram page */
577struct amdgpu_vram_scratch {
578 struct amdgpu_bo *robj;
579 volatile uint32_t *ptr;
580 u64 gpu_addr;
581};
582
583/*
584 * ACPI
585 */
97b2e202
AD		 586struct amdgpu_atcs_functions {
587 bool get_ext_state;
588 bool pcie_perf_req;
589 bool pcie_dev_rdy;
590 bool pcie_bus_width;
591};
592
593struct amdgpu_atcs {
594 struct amdgpu_atcs_functions functions;
595};
596
a05502e5
HC		 597/*
598 * Firmware VRAM reservation
599 */
600struct amdgpu_fw_vram_usage {
601 u64 start_offset;
602 u64 size;
603 struct amdgpu_bo *reserved_bo;
604 void *va;
605};
606
d03846af
CZ		 607/*
608 * CGS
609 */
110e6f26
DA		 610struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
611void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 612
97b2e202
AD		 613/*
614 * Core structure, functions and helpers.
615 */
616typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
617typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
618
619typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
620typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
621
946a4d5b
SL		 622
623/*
624 * amdgpu nbio functions
625 *
946a4d5b 626 */
bf383fb6
AD		 627struct nbio_hdp_flush_reg {
628 u32 ref_and_mask_cp0;
629 u32 ref_and_mask_cp1;
630 u32 ref_and_mask_cp2;
631 u32 ref_and_mask_cp3;
632 u32 ref_and_mask_cp4;
633 u32 ref_and_mask_cp5;
634 u32 ref_and_mask_cp6;
635 u32 ref_and_mask_cp7;
636 u32 ref_and_mask_cp8;
637 u32 ref_and_mask_cp9;
638 u32 ref_and_mask_sdma0;
639 u32 ref_and_mask_sdma1;
640};
946a4d5b
SL		 641
642struct amdgpu_nbio_funcs {
bf383fb6
AD		 643 const struct nbio_hdp_flush_reg *hdp_flush_reg;
644 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
645 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
646 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
647 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
648 u32 (*get_rev_id)(struct amdgpu_device *adev);
bf383fb6 649 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
69882565 650 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
bf383fb6
AD		 651 u32 (*get_memsize)(struct amdgpu_device *adev);
652 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
8987e2e2 653 bool use_doorbell, int doorbell_index, int doorbell_size);
bf383fb6
AD		 654 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
655 bool enable);
656 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
657 bool enable);
658 void (*ih_doorbell_range)(struct amdgpu_device *adev,
659 bool use_doorbell, int doorbell_index);
660 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
661 bool enable);
662 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
663 bool enable);
664 void (*get_clockgating_state)(struct amdgpu_device *adev,
665 u32 *flags);
666 void (*ih_control)(struct amdgpu_device *adev);
667 void (*init_registers)(struct amdgpu_device *adev);
668 void (*detect_hw_virt)(struct amdgpu_device *adev);
946a4d5b
SL		 669};
670
634c96e3
HZ		 671struct amdgpu_df_funcs {
672 void (*init)(struct amdgpu_device *adev);
673 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
674 bool enable);
675 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
676 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
677 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
678 bool enable);
679 void (*get_clockgating_state)(struct amdgpu_device *adev,
680 u32 *flags);
8f9b2e50
AD		 681 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
682 bool enable);
634c96e3 683};
4522824c
SL		 684/* Define the HW IP blocks will be used in driver , add more if necessary */
685enum amd_hw_ip_block_type {
686 GC_HWIP = 1,
687 HDP_HWIP,
688 SDMA0_HWIP,
689 SDMA1_HWIP,
690 MMHUB_HWIP,
691 ATHUB_HWIP,
692 NBIO_HWIP,
693 MP0_HWIP,
e6636ae1 694 MP1_HWIP,
4522824c
SL		 695 UVD_HWIP,
696 VCN_HWIP = UVD_HWIP,
697 VCE_HWIP,
698 DF_HWIP,
699 DCE_HWIP,
700 OSSSYS_HWIP,
701 SMUIO_HWIP,
702 PWR_HWIP,
703 NBIF_HWIP,
e6636ae1 704 THM_HWIP,
73b19174 705 CLK_HWIP,
4522824c
SL		 706 MAX_HWIP
707};
708
709#define HWIP_MAX_INSTANCE 6
710
11dc9364 711struct amd_powerplay {
11dc9364 712 void *pp_handle;
11dc9364
RZ		 713 const struct amd_pm_funcs *pp_funcs;
714};
715
0c49e0b8 716#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 717struct amdgpu_device {
718 struct device *dev;
719 struct drm_device *ddev;
720 struct pci_dev *pdev;
97b2e202 721
a8fe58ce
MB		 722#ifdef CONFIG_DRM_AMD_ACP
723 struct amdgpu_acp acp;
724#endif
725
97b2e202 726 /* ASIC */
2f7d10b3 727 enum amd_asic_type asic_type;
97b2e202
AD		 728 uint32_t family;
729 uint32_t rev_id;
730 uint32_t external_rev_id;
731 unsigned long flags;
732 int usec_timeout;
733 const struct amdgpu_asic_funcs *asic_funcs;
734 bool shutdown;
97b2e202 735 bool need_dma32;
fd5fd480 736 bool need_swiotlb;
97b2e202 737 bool accel_working;
97b2e202
AD		 738 struct notifier_block acpi_nb;
739 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
740 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 741 unsigned debugfs_count;
97b2e202 742#if defined(CONFIG_DEBUG_FS)
adcec288 743 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202 744#endif
102c16a0 745 struct amdgpu_atif *atif;
97b2e202
AD		 746 struct amdgpu_atcs atcs;
747 struct mutex srbm_mutex;
748 /* GRBM index mutex. Protects concurrent access to GRBM index */
749 struct mutex grbm_idx_mutex;
750 struct dev_pm_domain vga_pm_domain;
751 bool have_disp_power_ref;
752
753 /* BIOS */
0cdd5005 754 bool is_atom_fw;
97b2e202 755 uint8_t *bios;
a9f5db9c 756 uint32_t bios_size;
5af2c10d 757 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 758 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 759 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
760
761 /* Register/doorbell mmio */
762 resource_size_t rmmio_base;
763 resource_size_t rmmio_size;
764 void __iomem *rmmio;
765 /* protects concurrent MM_INDEX/DATA based register access */
766 spinlock_t mmio_idx_lock;
767 /* protects concurrent SMC based register access */
768 spinlock_t smc_idx_lock;
769 amdgpu_rreg_t smc_rreg;
770 amdgpu_wreg_t smc_wreg;
771 /* protects concurrent PCIE register access */
772 spinlock_t pcie_idx_lock;
773 amdgpu_rreg_t pcie_rreg;
774 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 775 amdgpu_rreg_t pciep_rreg;
776 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 777 /* protects concurrent UVD register access */
778 spinlock_t uvd_ctx_idx_lock;
779 amdgpu_rreg_t uvd_ctx_rreg;
780 amdgpu_wreg_t uvd_ctx_wreg;
781 /* protects concurrent DIDT register access */
782 spinlock_t didt_idx_lock;
783 amdgpu_rreg_t didt_rreg;
784 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 785 /* protects concurrent gc_cac register access */
786 spinlock_t gc_cac_idx_lock;
787 amdgpu_rreg_t gc_cac_rreg;
788 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 789 /* protects concurrent se_cac register access */
790 spinlock_t se_cac_idx_lock;
791 amdgpu_rreg_t se_cac_rreg;
792 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 793 /* protects concurrent ENDPOINT (audio) register access */
794 spinlock_t audio_endpt_idx_lock;
795 amdgpu_block_rreg_t audio_endpt_rreg;
796 amdgpu_block_wreg_t audio_endpt_wreg;
797 void __iomem *rio_mem;
798 resource_size_t rio_mem_size;
799 struct amdgpu_doorbell doorbell;
800
801 /* clock/pll info */
802 struct amdgpu_clock clock;
803
804 /* MC */
770d13b1 805 struct amdgpu_gmc gmc;
97b2e202 806 struct amdgpu_gart gart;
92e71b06 807 dma_addr_t dummy_page_addr;
97b2e202 808 struct amdgpu_vm_manager vm_manager;
e60f8db5 809 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 810
811 /* memory management */
812 struct amdgpu_mman mman;
97b2e202
AD		 813 struct amdgpu_vram_scratch vram_scratch;
814 struct amdgpu_wb wb;
97b2e202 815 atomic64_t num_bytes_moved;
dbd5ed60 816 atomic64_t num_evictions;
68e2c5ff 817 atomic64_t num_vram_cpu_page_faults;
d94aed5a 818 atomic_t gpu_reset_counter;
f1892138 819 atomic_t vram_lost_counter;
97b2e202 820
95844d20
MO		 821 /* data for buffer migration throttling */
822 struct {
823 spinlock_t lock;
824 s64 last_update_us;
825 s64 accum_us; /* accumulated microseconds */
00f06b24 826 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 827 u32 log2_max_MBps;
828 } mm_stats;
829
97b2e202 830 /* display */
9accf2fd 831 bool enable_virtual_display;
97b2e202 832 struct amdgpu_mode_info mode_info;
4562236b 833 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 834 struct work_struct hotplug_work;
835 struct amdgpu_irq_src crtc_irq;
d2574c33 836 struct amdgpu_irq_src vupdate_irq;
97b2e202
AD		 837 struct amdgpu_irq_src pageflip_irq;
838 struct amdgpu_irq_src hpd_irq;
839
840 /* rings */
76bf0db5 841 u64 fence_context;
97b2e202
AD		 842 unsigned num_rings;
843 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
844 bool ib_pool_ready;
845 struct amdgpu_sa_manager ring_tmp_bo;
846
847 /* interrupts */
848 struct amdgpu_irq irq;
849
1f7371b2
AD		 850 /* powerplay */
851 struct amd_powerplay powerplay;
f3898ea1 852 bool pp_force_state_enabled;
1f7371b2 853
137d63ab
HR		 854 /* smu */
855 struct smu_context smu;
856
97b2e202
AD		 857 /* dpm */
858 struct amdgpu_pm pm;
859 u32 cg_flags;
860 u32 pg_flags;
861
97b2e202
AD		 862 /* gfx */
863 struct amdgpu_gfx gfx;
864
865 /* sdma */
c113ea1c 866 struct amdgpu_sdma sdma;
97b2e202 867
b43aaee6
LL		 868 /* uvd */
869 struct amdgpu_uvd uvd;
870
871 /* vce */
872 struct amdgpu_vce vce;
873
874 /* vcn */
875 struct amdgpu_vcn vcn;
97b2e202
AD		 876
877 /* firmwares */
878 struct amdgpu_firmware firmware;
879
0e5ca0d1
HR		 880 /* PSP */
881 struct psp_context psp;
882
97b2e202
AD		 883 /* GDS */
884 struct amdgpu_gds gds;
885
611736d8
FK		 886 /* KFD */
887 struct amdgpu_kfd_dev kfd;
888
4562236b
HW		 889 /* display related functionality */
890 struct amdgpu_display_manager dm;
891
a1255107 892 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 893 int num_ip_blocks;
97b2e202
AD		 894 struct mutex mn_lock;
895 DECLARE_HASHTABLE(mn_hash, 7);
896
897 /* tracking pinned memory */
a5ccfe5c
MD		 898 atomic64_t vram_pin_size;
899 atomic64_t visible_pin_size;
900 atomic64_t gart_pin_size;
130e0371 901
4522824c
SL		 902 /* soc15 register offset based on ip, instance and segment */
903 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
904
946a4d5b 905 const struct amdgpu_nbio_funcs *nbio_funcs;
634c96e3 906 const struct amdgpu_df_funcs *df_funcs;
946a4d5b 907
2dc80b00
S		 908 /* delayed work_func for deferring clockgating during resume */
909 struct delayed_work late_init_work;
910
5a5099cb 911 struct amdgpu_virt virt;
a05502e5
HC		 912 /* firmware VRAM reservation */
913 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 914
915 /* link all shadow bo */
916 struct list_head shadow_list;
917 struct mutex shadow_list_lock;
795f2813
AR		 918 /* keep an lru list of rings by HW IP */
919 struct list_head ring_lru_list;
920 spinlock_t ring_lru_list_lock;
5c1354bd 921
c836fec5
JQ		 922 /* record hw reset is performed */
923 bool has_hw_reset;
0c49e0b8 924 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 925
44779b43
RZ		 926 /* s3/s4 mask */
927 bool in_suspend;
928
47ed4e1c
KW		 929 /* record last mm index being written through WREG32*/
930 unsigned long last_mm_index;
13a752e3
ML		 931 bool in_gpu_reset;
932 struct mutex lock_reset;
409c5191 933 struct amdgpu_doorbell_index doorbell_index;
d4535e2c 934
26bc5340 935 int asic_reset_res;
d4535e2c 936 struct work_struct xgmi_reset_work;
9b638f97 937
0c5ccf14 938 bool in_baco_reset;
97b2e202
AD		 939};
940
a7d64de6
CK		 941static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
942{
943 return container_of(bdev, struct amdgpu_device, mman.bdev);
944}
945
97b2e202
AD		 946int amdgpu_device_init(struct amdgpu_device *adev,
947 struct drm_device *ddev,
948 struct pci_dev *pdev,
949 uint32_t flags);
950void amdgpu_device_fini(struct amdgpu_device *adev);
951int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
952
953uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 954 uint32_t acc_flags);
97b2e202 955void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 956 uint32_t acc_flags);
421a2a30
ML		 957void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
958uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
959
97b2e202
AD		 960u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
961void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
962
4562236b
HW		 963bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
964bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
965
9475a943
SL		 966int emu_soc_asic_init(struct amdgpu_device *adev);
967
97b2e202
AD		 968/*
969 * Registers read & write functions.
970 */
15d72fd7
ML		 971
972#define AMDGPU_REGS_IDX (1<<0)
973#define AMDGPU_REGS_NO_KIQ (1<<1)
974
975#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
976#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
977
421a2a30
ML		 978#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
979#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
980
15d72fd7
ML		 981#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
982#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
983#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
984#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
985#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 986#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
987#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
988#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
989#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 990#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
991#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 992#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
993#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
994#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
995#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
996#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
997#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 998#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
999#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1000#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1001#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1002#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1003#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1004#define WREG32_P(reg, val, mask) \
1005 do { \
1006 uint32_t tmp_ = RREG32(reg); \
1007 tmp_ &= (mask); \
1008 tmp_ |= ((val) & ~(mask)); \
1009 WREG32(reg, tmp_); \
1010 } while (0)
1011#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1012#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1013#define WREG32_PLL_P(reg, val, mask) \
1014 do { \
1015 uint32_t tmp_ = RREG32_PLL(reg); \
1016 tmp_ &= (mask); \
1017 tmp_ |= ((val) & ~(mask)); \
1018 WREG32_PLL(reg, tmp_); \
1019 } while (0)
1020#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1021#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1022#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1023
97b2e202
AD		 1024#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1025#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1026
1027#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1028 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1029 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1030
1031#define REG_GET_FIELD(value, reg, field) \
1032 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1033
1034#define WREG32_FIELD(reg, field, val) \
1035 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1036
ccaf3574
TSD		 1037#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1038 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1039
97b2e202
AD		 1040/*
1041 * BIOS helpers.
1042 */
1043#define RBIOS8(i) (adev->bios[i])
1044#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1045#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1046
97b2e202
AD		 1047/*
1048 * ASICs macro.
1049 */
1050#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1051#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1052#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1053#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1054#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1055#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1056#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1057#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1058#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1059#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1060#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1061#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
69882565
CK		 1062#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1063#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
69070690 1064#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
5253163a 1065#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
b45e18ac 1066#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
44401889 1067#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
97b2e202
AD		 1068
1069/* Common functions */
12938fad 1070bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
5f152b5e 1071int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12938fad 1072 struct amdgpu_job* job);
8111c387 1073void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1074bool amdgpu_device_need_post(struct amdgpu_device *adev);
d5fc5e82 1075
00f06b24
JB		 1076void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1077 u64 num_vis_bytes);
d6895ad3 1078int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
9c3f2b54 1079void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1080 const u32 *registers,
1081 const u32 array_size);
1082
1083bool amdgpu_device_is_px(struct drm_device *dev);
1084/* atpx handler */
1085#if defined(CONFIG_VGA_SWITCHEROO)
1086void amdgpu_register_atpx_handler(void);
1087void amdgpu_unregister_atpx_handler(void);
a78fe133 1088bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1089bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1090bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1091bool amdgpu_has_atpx(void);
97b2e202
AD		 1092#else
1093static inline void amdgpu_register_atpx_handler(void) {}
1094static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1095static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1096static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1097static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1098static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1099#endif
1100
24aeefcd
LP		 1101#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1102void *amdgpu_atpx_get_dhandle(void);
1103#else
1104static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1105#endif
1106
97b2e202
AD		 1107/*
1108 * KMS
1109 */
1110extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1111extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1112
1113int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1114void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1115void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1116int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1117void amdgpu_driver_postclose_kms(struct drm_device *dev,
1118 struct drm_file *file_priv);
cdd61df6 1119int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1120int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1121int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1122u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1123int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1124void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1125long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1126 unsigned long arg);
1127
97b2e202
AD		 1128/*
1129 * functions used by amdgpu_encoder.c
1130 */
1131struct amdgpu_afmt_acr {
1132 u32 clock;
1133
1134 int n_32khz;
1135 int cts_32khz;
1136
1137 int n_44_1khz;
1138 int cts_44_1khz;
1139
1140 int n_48khz;
1141 int cts_48khz;
1142
1143};
1144
1145struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1146
1147/* amdgpu_acpi.c */
1148#if defined(CONFIG_ACPI)
1149int amdgpu_acpi_init(struct amdgpu_device *adev);
1150void amdgpu_acpi_fini(struct amdgpu_device *adev);
1151bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1152int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1153 u8 perf_req, bool advertise);
1154int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
206bbafe
DF		 1155
1156void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1157 struct amdgpu_dm_backlight_caps *caps);
97b2e202
AD		 1158#else
1159static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1160static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1161#endif
1162
9cca0b8e
CK		 1163int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1164 uint64_t addr, struct amdgpu_bo **bo,
1165 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1166
4562236b
HW		 1167#if defined(CONFIG_DRM_AMD_DC)
1168int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1169#else
1170static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1171#endif
1172
97b2e202 1173#include "amdgpu_object.h"
97b2e202 1174#endif
Linux 6.x block layer and io_uring tree(s)