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drm/amdgpu: two minor 80 char fixes
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
cd474ba0
AD		 88extern unsigned amdgpu_pcie_gen_cap;
89extern unsigned amdgpu_pcie_lane_cap;
97b2e202 90
4b559c90 91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95#define AMDGPU_IB_POOL_SIZE 16
96#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97#define AMDGPUFB_CONN_LIMIT 4
98#define AMDGPU_BIOS_NUM_SCRATCH 8
99
97b2e202
AD		 100/* max number of rings */
101#define AMDGPU_MAX_RINGS 16
102#define AMDGPU_MAX_GFX_RINGS 1
103#define AMDGPU_MAX_COMPUTE_RINGS 8
104#define AMDGPU_MAX_VCE_RINGS 2
105
36f523a7
JZ		 106/* max number of IP instances */
107#define AMDGPU_MAX_SDMA_INSTANCES 2
108
97b2e202
AD		 109/* hardcode that limit for now */
110#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112/* hard reset data */
113#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115/* reset flags */
116#define AMDGPU_RESET_GFX (1 << 0)
117#define AMDGPU_RESET_COMPUTE (1 << 1)
118#define AMDGPU_RESET_DMA (1 << 2)
119#define AMDGPU_RESET_CP (1 << 3)
120#define AMDGPU_RESET_GRBM (1 << 4)
121#define AMDGPU_RESET_DMA1 (1 << 5)
122#define AMDGPU_RESET_RLC (1 << 6)
123#define AMDGPU_RESET_SEM (1 << 7)
124#define AMDGPU_RESET_IH (1 << 8)
125#define AMDGPU_RESET_VMC (1 << 9)
126#define AMDGPU_RESET_MC (1 << 10)
127#define AMDGPU_RESET_DISPLAY (1 << 11)
128#define AMDGPU_RESET_UVD (1 << 12)
129#define AMDGPU_RESET_VCE (1 << 13)
130#define AMDGPU_RESET_VCE1 (1 << 14)
131
97b2e202
AD		 132/* GFX current status */
133#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
134#define AMDGPU_GFX_SAFE_MODE 0x00000001L
135#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
136#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
137#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
138
139/* max cursor sizes (in pixels) */
140#define CIK_CURSOR_WIDTH 128
141#define CIK_CURSOR_HEIGHT 128
142
143struct amdgpu_device;
97b2e202
AD		 144struct amdgpu_ib;
145struct amdgpu_vm;
146struct amdgpu_ring;
97b2e202 147struct amdgpu_cs_parser;
bb977d37 148struct amdgpu_job;
97b2e202 149struct amdgpu_irq_src;
0b492a4c 150struct amdgpu_fpriv;
97b2e202
AD		 151
152enum amdgpu_cp_irq {
153 AMDGPU_CP_IRQ_GFX_EOP = 0,
154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
162
163 AMDGPU_CP_IRQ_LAST
164};
165
166enum amdgpu_sdma_irq {
167 AMDGPU_SDMA_IRQ_TRAP0 = 0,
168 AMDGPU_SDMA_IRQ_TRAP1,
169
170 AMDGPU_SDMA_IRQ_LAST
171};
172
173enum amdgpu_thermal_irq {
174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
176
177 AMDGPU_THERMAL_IRQ_LAST
178};
179
97b2e202 180int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 181 enum amd_ip_block_type block_type,
182 enum amd_clockgating_state state);
97b2e202 183int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 184 enum amd_ip_block_type block_type,
185 enum amd_powergating_state state);
97b2e202
AD		 186
187struct amdgpu_ip_block_version {
5fc3aeeb 188 enum amd_ip_block_type type;
97b2e202
AD		 189 u32 major;
190 u32 minor;
191 u32 rev;
5fc3aeeb 192 const struct amd_ip_funcs *funcs;
97b2e202
AD		 193};
194
195int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 196 enum amd_ip_block_type type,
97b2e202
AD		 197 u32 major, u32 minor);
198
199const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
200 struct amdgpu_device *adev,
5fc3aeeb 201 enum amd_ip_block_type type);
97b2e202
AD		 202
203/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
204struct amdgpu_buffer_funcs {
205 /* maximum bytes in a single operation */
206 uint32_t copy_max_bytes;
207
208 /* number of dw to reserve per operation */
209 unsigned copy_num_dw;
210
211 /* used for buffer migration */
c7ae72c0 212 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 213 /* src addr in bytes */
214 uint64_t src_offset,
215 /* dst addr in bytes */
216 uint64_t dst_offset,
217 /* number of byte to transfer */
218 uint32_t byte_count);
219
220 /* maximum bytes in a single operation */
221 uint32_t fill_max_bytes;
222
223 /* number of dw to reserve per operation */
224 unsigned fill_num_dw;
225
226 /* used for buffer clearing */
6e7a3840 227 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 228 /* value to write to memory */
229 uint32_t src_data,
230 /* dst addr in bytes */
231 uint64_t dst_offset,
232 /* number of byte to fill */
233 uint32_t byte_count);
234};
235
236/* provided by hw blocks that can write ptes, e.g., sdma */
237struct amdgpu_vm_pte_funcs {
238 /* copy pte entries from GART */
239 void (*copy_pte)(struct amdgpu_ib *ib,
240 uint64_t pe, uint64_t src,
241 unsigned count);
242 /* write pte one entry at a time with addr mapping */
243 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 244 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 245 uint64_t addr, unsigned count,
246 uint32_t incr, uint32_t flags);
247 /* for linear pte/pde updates without addr mapping */
248 void (*set_pte_pde)(struct amdgpu_ib *ib,
249 uint64_t pe,
250 uint64_t addr, unsigned count,
251 uint32_t incr, uint32_t flags);
97b2e202
AD		 252};
253
254/* provided by the gmc block */
255struct amdgpu_gart_funcs {
256 /* flush the vm tlb via mmio */
257 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
258 uint32_t vmid);
259 /* write pte/pde updates using the cpu */
260 int (*set_pte_pde)(struct amdgpu_device *adev,
261 void *cpu_pt_addr, /* cpu addr of page table */
262 uint32_t gpu_page_idx, /* pte/pde to update */
263 uint64_t addr, /* addr to write into pte/pde */
264 uint32_t flags); /* access flags */
265};
266
267/* provided by the ih block */
268struct amdgpu_ih_funcs {
269 /* ring read/write ptr handling, called from interrupt context */
270 u32 (*get_wptr)(struct amdgpu_device *adev);
271 void (*decode_iv)(struct amdgpu_device *adev,
272 struct amdgpu_iv_entry *entry);
273 void (*set_rptr)(struct amdgpu_device *adev);
274};
275
276/* provided by hw blocks that expose a ring buffer for commands */
277struct amdgpu_ring_funcs {
278 /* ring read/write ptr handling */
279 u32 (*get_rptr)(struct amdgpu_ring *ring);
280 u32 (*get_wptr)(struct amdgpu_ring *ring);
281 void (*set_wptr)(struct amdgpu_ring *ring);
282 /* validating and patching of IBs */
283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
284 /* command emit functions */
285 void (*emit_ib)(struct amdgpu_ring *ring,
286 struct amdgpu_ib *ib);
287 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 288 uint64_t seq, unsigned flags);
b8c7b39e 289 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
291 uint64_t pd_addr);
d2edb07b 292 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 293 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 294 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
295 uint32_t gds_base, uint32_t gds_size,
296 uint32_t gws_base, uint32_t gws_size,
297 uint32_t oa_base, uint32_t oa_size);
298 /* testing functions */
299 int (*test_ring)(struct amdgpu_ring *ring);
300 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 301 /* insert NOP packets */
302 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 303 /* pad the indirect buffer to the necessary number of dw */
304 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
03ccf481
ML		 305 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
306 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
97b2e202
AD		 307};
308
309/*
310 * BIOS.
311 */
312bool amdgpu_get_bios(struct amdgpu_device *adev);
313bool amdgpu_read_bios(struct amdgpu_device *adev);
314
315/*
316 * Dummy page
317 */
318struct amdgpu_dummy_page {
319 struct page *page;
320 dma_addr_t addr;
321};
322int amdgpu_dummy_page_init(struct amdgpu_device *adev);
323void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
324
325
326/*
327 * Clocks
328 */
329
330#define AMDGPU_MAX_PPLL 3
331
332struct amdgpu_clock {
333 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
334 struct amdgpu_pll spll;
335 struct amdgpu_pll mpll;
336 /* 10 Khz units */
337 uint32_t default_mclk;
338 uint32_t default_sclk;
339 uint32_t default_dispclk;
340 uint32_t current_dispclk;
341 uint32_t dp_extclk;
342 uint32_t max_pixel_clock;
343};
344
345/*
346 * Fences.
347 */
348struct amdgpu_fence_driver {
97b2e202
AD		 349 uint64_t gpu_addr;
350 volatile uint32_t *cpu_addr;
351 /* sync_seq is protected by ring emission lock */
742c085f
CK		 352 uint32_t sync_seq;
353 atomic_t last_seq;
97b2e202 354 bool initialized;
97b2e202
AD		 355 struct amdgpu_irq_src *irq_src;
356 unsigned irq_type;
c2776afe 357 struct timer_list fallback_timer;
c89377d1 358 unsigned num_fences_mask;
4a7d74f1 359 spinlock_t lock;
c89377d1 360 struct fence **fences;
97b2e202
AD		 361};
362
363/* some special values for the owner field */
364#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
365#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
031e2983 366#define AMDGPU_CLIENT_ID_RESERVED 2
97b2e202 367
890ee23f
CZ		 368#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
369#define AMDGPU_FENCE_FLAG_INT (1 << 1)
370
97b2e202
AD		 371struct amdgpu_user_fence {
372 /* write-back bo */
373 struct amdgpu_bo *bo;
374 /* write-back address offset to bo start */
375 uint32_t offset;
376};
377
378int amdgpu_fence_driver_init(struct amdgpu_device *adev);
379void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
380void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
381
e6151a08
CK		 382int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
383 unsigned num_hw_submission);
97b2e202
AD		 384int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
385 struct amdgpu_irq_src *irq_src,
386 unsigned irq_type);
5ceb54c6
AD		 387void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
388void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 389int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202 390void amdgpu_fence_process(struct amdgpu_ring *ring);
97b2e202
AD		 391int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
392unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
393
97b2e202
AD		 394/*
395 * TTM.
396 */
29b3259a
CK		 397
398#define AMDGPU_TTM_LRU_SIZE 20
399
400struct amdgpu_mman_lru {
401 struct list_head *lru[TTM_NUM_MEM_TYPES];
402 struct list_head *swap_lru;
403};
404
97b2e202
AD		 405struct amdgpu_mman {
406 struct ttm_bo_global_ref bo_global_ref;
407 struct drm_global_reference mem_global_ref;
408 struct ttm_bo_device bdev;
409 bool mem_global_referenced;
410 bool initialized;
411
412#if defined(CONFIG_DEBUG_FS)
413 struct dentry *vram;
414 struct dentry *gtt;
415#endif
416
417 /* buffer handling */
418 const struct amdgpu_buffer_funcs *buffer_funcs;
419 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 420 /* Scheduler entity for buffer moves */
421 struct amd_sched_entity entity;
29b3259a
CK		 422
423 /* custom LRU management */
424 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
97b2e202
AD		 425};
426
427int amdgpu_copy_buffer(struct amdgpu_ring *ring,
428 uint64_t src_offset,
429 uint64_t dst_offset,
430 uint32_t byte_count,
431 struct reservation_object *resv,
c7ae72c0 432 struct fence **fence);
97b2e202
AD		 433int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
434
435struct amdgpu_bo_list_entry {
436 struct amdgpu_bo *robj;
437 struct ttm_validate_buffer tv;
438 struct amdgpu_bo_va *bo_va;
97b2e202 439 uint32_t priority;
2f568dbd
CK		 440 struct page **user_pages;
441 int user_invalidated;
97b2e202
AD		 442};
443
444struct amdgpu_bo_va_mapping {
445 struct list_head list;
446 struct interval_tree_node it;
447 uint64_t offset;
448 uint32_t flags;
449};
450
451/* bo virtual addresses in a specific vm */
452struct amdgpu_bo_va {
453 /* protected by bo being reserved */
454 struct list_head bo_list;
bb1e38a4 455 struct fence *last_pt_update;
97b2e202
AD		 456 unsigned ref_count;
457
7fc11959 458 /* protected by vm mutex and spinlock */
97b2e202
AD		 459 struct list_head vm_status;
460
7fc11959
CK		 461 /* mappings for this bo_va */
462 struct list_head invalids;
463 struct list_head valids;
464
97b2e202
AD		 465 /* constant after initialization */
466 struct amdgpu_vm *vm;
467 struct amdgpu_bo *bo;
468};
469
7e5a547f
CZ		 470#define AMDGPU_GEM_DOMAIN_MAX 0x3
471
97b2e202
AD		 472struct amdgpu_bo {
473 /* Protected by gem.mutex */
474 struct list_head list;
475 /* Protected by tbo.reserved */
1ea863fd
CK		 476 u32 prefered_domains;
477 u32 allowed_domains;
7e5a547f 478 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 479 struct ttm_placement placement;
480 struct ttm_buffer_object tbo;
481 struct ttm_bo_kmap_obj kmap;
482 u64 flags;
483 unsigned pin_count;
484 void *kptr;
485 u64 tiling_flags;
486 u64 metadata_flags;
487 void *metadata;
488 u32 metadata_size;
489 /* list of all virtual address to which this bo
490 * is associated to
491 */
492 struct list_head va;
493 /* Constant after initialization */
494 struct amdgpu_device *adev;
495 struct drm_gem_object gem_base;
82b9c55b 496 struct amdgpu_bo *parent;
97b2e202
AD		 497
498 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 499 struct amdgpu_mn *mn;
500 struct list_head mn_list;
501};
502#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
503
504void amdgpu_gem_object_free(struct drm_gem_object *obj);
505int amdgpu_gem_object_open(struct drm_gem_object *obj,
506 struct drm_file *file_priv);
507void amdgpu_gem_object_close(struct drm_gem_object *obj,
508 struct drm_file *file_priv);
509unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
510struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 511struct drm_gem_object *
512amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
513 struct dma_buf_attachment *attach,
514 struct sg_table *sg);
97b2e202
AD		 515struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
516 struct drm_gem_object *gobj,
517 int flags);
518int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
519void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
520struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
521void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
522void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
523int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
524
525/* sub-allocation manager, it has to be protected by another lock.
526 * By conception this is an helper for other part of the driver
527 * like the indirect buffer or semaphore, which both have their
528 * locking.
529 *
530 * Principe is simple, we keep a list of sub allocation in offset
531 * order (first entry has offset == 0, last entry has the highest
532 * offset).
533 *
534 * When allocating new object we first check if there is room at
535 * the end total_size - (last_object_offset + last_object_size) >=
536 * alloc_size. If so we allocate new object there.
537 *
538 * When there is not enough room at the end, we start waiting for
539 * each sub object until we reach object_offset+object_size >=
540 * alloc_size, this object then become the sub object we return.
541 *
542 * Alignment can't be bigger than page size.
543 *
544 * Hole are not considered for allocation to keep things simple.
545 * Assumption is that there won't be hole (all object on same
546 * alignment).
547 */
6ba60b89
CK		 548
549#define AMDGPU_SA_NUM_FENCE_LISTS 32
550
97b2e202
AD		 551struct amdgpu_sa_manager {
552 wait_queue_head_t wq;
553 struct amdgpu_bo *bo;
554 struct list_head *hole;
6ba60b89 555 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 556 struct list_head olist;
557 unsigned size;
558 uint64_t gpu_addr;
559 void *cpu_ptr;
560 uint32_t domain;
561 uint32_t align;
562};
563
97b2e202
AD		 564/* sub-allocation buffer */
565struct amdgpu_sa_bo {
566 struct list_head olist;
567 struct list_head flist;
568 struct amdgpu_sa_manager *manager;
569 unsigned soffset;
570 unsigned eoffset;
4ce9891e 571 struct fence *fence;
97b2e202
AD		 572};
573
574/*
575 * GEM objects.
576 */
418aa0c2 577void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 578int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
579 int alignment, u32 initial_domain,
580 u64 flags, bool kernel,
581 struct drm_gem_object **obj);
582
583int amdgpu_mode_dumb_create(struct drm_file *file_priv,
584 struct drm_device *dev,
585 struct drm_mode_create_dumb *args);
586int amdgpu_mode_dumb_mmap(struct drm_file *filp,
587 struct drm_device *dev,
588 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 589/*
590 * Synchronization
591 */
592struct amdgpu_sync {
f91b3a69 593 DECLARE_HASHTABLE(fences, 4);
3c62338c 594 struct fence *last_vm_update;
97b2e202
AD		 595};
596
597void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 598int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
599 struct fence *f);
97b2e202
AD		 600int amdgpu_sync_resv(struct amdgpu_device *adev,
601 struct amdgpu_sync *sync,
602 struct reservation_object *resv,
603 void *owner);
832a902f
CK		 604bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);
605int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
606 struct fence *fence);
e61235db 607struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 608int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 609void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 610int amdgpu_sync_init(void);
611void amdgpu_sync_fini(void);
97b2e202
AD		 612
613/*
614 * GART structures, functions & helpers
615 */
616struct amdgpu_mc;
617
618#define AMDGPU_GPU_PAGE_SIZE 4096
619#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
620#define AMDGPU_GPU_PAGE_SHIFT 12
621#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
622
623struct amdgpu_gart {
624 dma_addr_t table_addr;
625 struct amdgpu_bo *robj;
626 void *ptr;
627 unsigned num_gpu_pages;
628 unsigned num_cpu_pages;
629 unsigned table_size;
a1d29476 630#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 631 struct page **pages;
a1d29476 632#endif
97b2e202
AD		 633 bool ready;
634 const struct amdgpu_gart_funcs *gart_funcs;
635};
636
637int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
638void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
639int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
640void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
641int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
642void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
643int amdgpu_gart_init(struct amdgpu_device *adev);
644void amdgpu_gart_fini(struct amdgpu_device *adev);
645void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
646 int pages);
647int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
648 int pages, struct page **pagelist,
649 dma_addr_t *dma_addr, uint32_t flags);
650
651/*
652 * GPU MC structures, functions & helpers
653 */
654struct amdgpu_mc {
655 resource_size_t aper_size;
656 resource_size_t aper_base;
657 resource_size_t agp_base;
658 /* for some chips with <= 32MB we need to lie
659 * about vram size near mc fb location */
660 u64 mc_vram_size;
661 u64 visible_vram_size;
662 u64 gtt_size;
663 u64 gtt_start;
664 u64 gtt_end;
665 u64 vram_start;
666 u64 vram_end;
667 unsigned vram_width;
668 u64 real_vram_size;
669 int vram_mtrr;
670 u64 gtt_base_align;
671 u64 mc_mask;
672 const struct firmware *fw; /* MC firmware */
673 uint32_t fw_version;
674 struct amdgpu_irq_src vm_fault;
81c59f54 675 uint32_t vram_type;
97b2e202
AD		 676};
677
678/*
679 * GPU doorbell structures, functions & helpers
680 */
681typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
682{
683 AMDGPU_DOORBELL_KIQ = 0x000,
684 AMDGPU_DOORBELL_HIQ = 0x001,
685 AMDGPU_DOORBELL_DIQ = 0x002,
686 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
687 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
688 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
689 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
690 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
691 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
692 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
693 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
694 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
695 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
696 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
697 AMDGPU_DOORBELL_IH = 0x1E8,
698 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
699 AMDGPU_DOORBELL_INVALID = 0xFFFF
700} AMDGPU_DOORBELL_ASSIGNMENT;
701
702struct amdgpu_doorbell {
703 /* doorbell mmio */
704 resource_size_t base;
705 resource_size_t size;
706 u32 __iomem *ptr;
707 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
708};
709
710void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
711 phys_addr_t *aperture_base,
712 size_t *aperture_size,
713 size_t *start_offset);
714
715/*
716 * IRQS.
717 */
718
719struct amdgpu_flip_work {
720 struct work_struct flip_work;
721 struct work_struct unpin_work;
722 struct amdgpu_device *adev;
723 int crtc_id;
724 uint64_t base;
725 struct drm_pending_vblank_event *event;
726 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 727 struct fence *excl;
728 unsigned shared_count;
729 struct fence **shared;
c3874b75 730 struct fence_cb cb;
97b2e202
AD		 731};
732
733
734/*
735 * CP & rings.
736 */
737
738struct amdgpu_ib {
739 struct amdgpu_sa_bo *sa_bo;
740 uint32_t length_dw;
741 uint64_t gpu_addr;
742 uint32_t *ptr;
97b2e202 743 struct amdgpu_user_fence *user;
4ff37a83
CK		 744 unsigned vm_id;
745 uint64_t vm_pd_addr;
3cb485f3 746 struct amdgpu_ctx *ctx;
97b2e202
AD		 747 uint32_t gds_base, gds_size;
748 uint32_t gws_base, gws_size;
749 uint32_t oa_base, oa_size;
de807f81 750 uint32_t flags;
5430a3ff
CK		 751 /* resulting sequence number */
752 uint64_t sequence;
97b2e202
AD		 753};
754
755enum amdgpu_ring_type {
756 AMDGPU_RING_TYPE_GFX,
757 AMDGPU_RING_TYPE_COMPUTE,
758 AMDGPU_RING_TYPE_SDMA,
759 AMDGPU_RING_TYPE_UVD,
760 AMDGPU_RING_TYPE_VCE
761};
762
62250a91 763extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 764
50838c8c 765int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 766 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 767int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
768 struct amdgpu_job **job);
b6723c8d 769
50838c8c 770void amdgpu_job_free(struct amdgpu_job *job);
b6723c8d 771void amdgpu_job_free_func(struct kref *refcount);
d71518b5 772int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 773 struct amd_sched_entity *entity, void *owner,
774 struct fence **f);
0de2479c 775void amdgpu_job_timeout_func(struct work_struct *work);
3c704e93 776
97b2e202
AD		 777struct amdgpu_ring {
778 struct amdgpu_device *adev;
779 const struct amdgpu_ring_funcs *funcs;
780 struct amdgpu_fence_driver fence_drv;
4f839a24 781 struct amd_gpu_scheduler sched;
97b2e202 782
176e1ab1 783 spinlock_t fence_lock;
97b2e202
AD		 784 struct amdgpu_bo *ring_obj;
785 volatile uint32_t *ring;
786 unsigned rptr_offs;
787 u64 next_rptr_gpu_addr;
788 volatile u32 *next_rptr_cpu_addr;
789 unsigned wptr;
790 unsigned wptr_old;
791 unsigned ring_size;
c7e6be23 792 unsigned max_dw;
97b2e202 793 int count_dw;
97b2e202
AD		 794 uint64_t gpu_addr;
795 uint32_t align_mask;
796 uint32_t ptr_mask;
797 bool ready;
798 u32 nop;
799 u32 idx;
97b2e202
AD		 800 u32 me;
801 u32 pipe;
802 u32 queue;
803 struct amdgpu_bo *mqd_obj;
804 u32 doorbell_index;
805 bool use_doorbell;
806 unsigned wptr_offs;
807 unsigned next_rptr_offs;
808 unsigned fence_offs;
3cb485f3 809 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 810 enum amdgpu_ring_type type;
811 char name[16];
128cff1a
ML		 812 unsigned cond_exe_offs;
813 u64 cond_exe_gpu_addr;
814 volatile u32 *cond_exe_cpu_addr;
97b2e202
AD		 815};
816
817/*
818 * VM
819 */
820
821/* maximum number of VMIDs */
822#define AMDGPU_NUM_VM 16
823
824/* number of entries in page table */
825#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
826
827/* PTBs (Page Table Blocks) need to be aligned to 32K */
828#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
829#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
830#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
831
832#define AMDGPU_PTE_VALID (1 << 0)
833#define AMDGPU_PTE_SYSTEM (1 << 1)
834#define AMDGPU_PTE_SNOOPED (1 << 2)
835
836/* VI only */
837#define AMDGPU_PTE_EXECUTABLE (1 << 4)
838
839#define AMDGPU_PTE_READABLE (1 << 5)
840#define AMDGPU_PTE_WRITEABLE (1 << 6)
841
842/* PTE (Page Table Entry) fragment field for different page sizes */
843#define AMDGPU_PTE_FRAG_4KB (0 << 7)
844#define AMDGPU_PTE_FRAG_64KB (4 << 7)
845#define AMDGPU_LOG2_PAGES_PER_FRAG 4
846
d9c13156
CK		 847/* How to programm VM fault handling */
848#define AMDGPU_VM_FAULT_STOP_NEVER 0
849#define AMDGPU_VM_FAULT_STOP_FIRST 1
850#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
851
97b2e202 852struct amdgpu_vm_pt {
ee1782c3
CK		 853 struct amdgpu_bo_list_entry entry;
854 uint64_t addr;
97b2e202
AD		 855};
856
97b2e202 857struct amdgpu_vm {
25cfc3c2 858 /* tree of virtual addresses mapped */
97b2e202
AD		 859 struct rb_root va;
860
7fc11959 861 /* protecting invalidated */
97b2e202
AD		 862 spinlock_t status_lock;
863
864 /* BOs moved, but not yet updated in the PT */
865 struct list_head invalidated;
866
7fc11959
CK		 867 /* BOs cleared in the PT because of a move */
868 struct list_head cleared;
869
870 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 871 struct list_head freed;
872
873 /* contains the page directory */
874 struct amdgpu_bo *page_directory;
875 unsigned max_pde_used;
05906dec 876 struct fence *page_directory_fence;
97b2e202
AD		 877
878 /* array of page tables, one for each page directory entry */
879 struct amdgpu_vm_pt *page_tables;
880
881 /* for id and flush management per ring */
bcb1ba35 882 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
25cfc3c2 883
81d75a30 884 /* protecting freed */
885 spinlock_t freed_lock;
2bd9ccfa
CK		 886
887 /* Scheduler entity for page table updates */
888 struct amd_sched_entity entity;
031e2983
CZ		 889
890 /* client id */
891 u64 client_id;
97b2e202
AD		 892};
893
bcb1ba35 894struct amdgpu_vm_id {
a9a78b32 895 struct list_head list;
832a902f
CK		 896 struct fence *first;
897 struct amdgpu_sync active;
41d9eb2c 898 struct fence *last_flush;
68befebe 899 struct amdgpu_ring *last_user;
a9a78b32 900 atomic_long_t owner;
971fe9a9 901
bcb1ba35
CK		 902 uint64_t pd_gpu_addr;
903 /* last flushed PD/PT update */
904 struct fence *flushed_updates;
905
971fe9a9
CK		 906 uint32_t gds_base;
907 uint32_t gds_size;
908 uint32_t gws_base;
909 uint32_t gws_size;
910 uint32_t oa_base;
911 uint32_t oa_size;
a9a78b32
CK		 912};
913
97b2e202 914struct amdgpu_vm_manager {
a9a78b32 915 /* Handling of VMIDs */
8d0a7cea 916 struct mutex lock;
a9a78b32
CK		 917 unsigned num_ids;
918 struct list_head ids_lru;
bcb1ba35 919 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
1c16c0a7 920
8b4fb00b 921 uint32_t max_pfn;
97b2e202 922 /* vram base address for page table entry */
8b4fb00b 923 u64 vram_base_offset;
97b2e202 924 /* is vm enabled? */
8b4fb00b 925 bool enabled;
97b2e202
AD		 926 /* vm pte handling */
927 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 928 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
929 unsigned vm_pte_num_rings;
930 atomic_t vm_pte_next_ring;
031e2983
CZ		 931 /* client id counter */
932 atomic64_t client_counter;
97b2e202
AD		 933};
934
a9a78b32 935void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 936void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 937int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
938void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 939void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
940 struct list_head *validated,
941 struct amdgpu_bo_list_entry *entry);
ee1782c3 942void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 943void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
944 struct amdgpu_vm *vm);
8b4fb00b 945int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83
CK		 946 struct amdgpu_sync *sync, struct fence *fence,
947 unsigned *vm_id, uint64_t *vm_pd_addr);
41d9eb2c
CK		 948int amdgpu_vm_flush(struct amdgpu_ring *ring,
949 unsigned vm_id, uint64_t pd_addr,
950 uint32_t gds_base, uint32_t gds_size,
951 uint32_t gws_base, uint32_t gws_size,
952 uint32_t oa_base, uint32_t oa_size);
971fe9a9 953void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
b07c9d2a 954uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 955int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
956 struct amdgpu_vm *vm);
957int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
958 struct amdgpu_vm *vm);
959int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
960 struct amdgpu_sync *sync);
961int amdgpu_vm_bo_update(struct amdgpu_device *adev,
962 struct amdgpu_bo_va *bo_va,
963 struct ttm_mem_reg *mem);
964void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
965 struct amdgpu_bo *bo);
966struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
967 struct amdgpu_bo *bo);
968struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
969 struct amdgpu_vm *vm,
970 struct amdgpu_bo *bo);
971int amdgpu_vm_bo_map(struct amdgpu_device *adev,
972 struct amdgpu_bo_va *bo_va,
973 uint64_t addr, uint64_t offset,
974 uint64_t size, uint32_t flags);
975int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
976 struct amdgpu_bo_va *bo_va,
977 uint64_t addr);
978void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
979 struct amdgpu_bo_va *bo_va);
8b4fb00b 980
97b2e202
AD		 981/*
982 * context related structures
983 */
984
21c16bf6 985struct amdgpu_ctx_ring {
91404fb2 986 uint64_t sequence;
37cd0ca2 987 struct fence **fences;
91404fb2 988 struct amd_sched_entity entity;
21c16bf6
CK		 989};
990
97b2e202 991struct amdgpu_ctx {
0b492a4c 992 struct kref refcount;
9cb7e5a9 993 struct amdgpu_device *adev;
0b492a4c 994 unsigned reset_counter;
21c16bf6 995 spinlock_t ring_lock;
37cd0ca2 996 struct fence **fences;
21c16bf6 997 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 998};
999
1000struct amdgpu_ctx_mgr {
0b492a4c
AD		 1001 struct amdgpu_device *adev;
1002 struct mutex lock;
1003 /* protected by lock */
1004 struct idr ctx_handles;
97b2e202
AD		 1005};
1006
0b492a4c
AD		 1007struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1008int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1009
21c16bf6 1010uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1011 struct fence *fence);
21c16bf6
CK		 1012struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1013 struct amdgpu_ring *ring, uint64_t seq);
1014
0b492a4c
AD		 1015int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1016 struct drm_file *filp);
1017
efd4ccb5
CK		 1018void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1019void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1020
97b2e202
AD		 1021/*
1022 * file private structure
1023 */
1024
1025struct amdgpu_fpriv {
1026 struct amdgpu_vm vm;
1027 struct mutex bo_list_lock;
1028 struct idr bo_list_handles;
0b492a4c 1029 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1030};
1031
1032/*
1033 * residency list
1034 */
1035
1036struct amdgpu_bo_list {
1037 struct mutex lock;
1038 struct amdgpu_bo *gds_obj;
1039 struct amdgpu_bo *gws_obj;
1040 struct amdgpu_bo *oa_obj;
211dff55 1041 unsigned first_userptr;
97b2e202
AD		 1042 unsigned num_entries;
1043 struct amdgpu_bo_list_entry *array;
1044};
1045
1046struct amdgpu_bo_list *
1047amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1048void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1049 struct list_head *validated);
97b2e202
AD		 1050void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1051void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1052
1053/*
1054 * GFX stuff
1055 */
1056#include "clearstate_defs.h"
1057
79e5412c
AD		 1058struct amdgpu_rlc_funcs {
1059 void (*enter_safe_mode)(struct amdgpu_device *adev);
1060 void (*exit_safe_mode)(struct amdgpu_device *adev);
1061};
1062
97b2e202
AD		 1063struct amdgpu_rlc {
1064 /* for power gating */
1065 struct amdgpu_bo *save_restore_obj;
1066 uint64_t save_restore_gpu_addr;
1067 volatile uint32_t *sr_ptr;
1068 const u32 *reg_list;
1069 u32 reg_list_size;
1070 /* for clear state */
1071 struct amdgpu_bo *clear_state_obj;
1072 uint64_t clear_state_gpu_addr;
1073 volatile uint32_t *cs_ptr;
1074 const struct cs_section_def *cs_data;
1075 u32 clear_state_size;
1076 /* for cp tables */
1077 struct amdgpu_bo *cp_table_obj;
1078 uint64_t cp_table_gpu_addr;
1079 volatile uint32_t *cp_table_ptr;
1080 u32 cp_table_size;
79e5412c
AD		 1081
1082 /* safe mode for updating CG/PG state */
1083 bool in_safe_mode;
1084 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 1085
1086 /* for firmware data */
1087 u32 save_and_restore_offset;
1088 u32 clear_state_descriptor_offset;
1089 u32 avail_scratch_ram_locations;
1090 u32 reg_restore_list_size;
1091 u32 reg_list_format_start;
1092 u32 reg_list_format_separate_start;
1093 u32 starting_offsets_start;
1094 u32 reg_list_format_size_bytes;
1095 u32 reg_list_size_bytes;
1096
1097 u32 *register_list_format;
1098 u32 *register_restore;
97b2e202
AD		 1099};
1100
1101struct amdgpu_mec {
1102 struct amdgpu_bo *hpd_eop_obj;
1103 u64 hpd_eop_gpu_addr;
1104 u32 num_pipe;
1105 u32 num_mec;
1106 u32 num_queue;
1107};
1108
1109/*
1110 * GPU scratch registers structures, functions & helpers
1111 */
1112struct amdgpu_scratch {
1113 unsigned num_reg;
1114 uint32_t reg_base;
1115 bool free[32];
1116 uint32_t reg[32];
1117};
1118
1119/*
1120 * GFX configurations
1121 */
1122struct amdgpu_gca_config {
1123 unsigned max_shader_engines;
1124 unsigned max_tile_pipes;
1125 unsigned max_cu_per_sh;
1126 unsigned max_sh_per_se;
1127 unsigned max_backends_per_se;
1128 unsigned max_texture_channel_caches;
1129 unsigned max_gprs;
1130 unsigned max_gs_threads;
1131 unsigned max_hw_contexts;
1132 unsigned sc_prim_fifo_size_frontend;
1133 unsigned sc_prim_fifo_size_backend;
1134 unsigned sc_hiz_tile_fifo_size;
1135 unsigned sc_earlyz_tile_fifo_size;
1136
1137 unsigned num_tile_pipes;
1138 unsigned backend_enable_mask;
1139 unsigned mem_max_burst_length_bytes;
1140 unsigned mem_row_size_in_kb;
1141 unsigned shader_engine_tile_size;
1142 unsigned num_gpus;
1143 unsigned multi_gpu_tile_size;
1144 unsigned mc_arb_ramcfg;
1145 unsigned gb_addr_config;
8f8e00c1 1146 unsigned num_rbs;
97b2e202
AD		 1147
1148 uint32_t tile_mode_array[32];
1149 uint32_t macrotile_mode_array[16];
1150};
1151
1152struct amdgpu_gfx {
1153 struct mutex gpu_clock_mutex;
1154 struct amdgpu_gca_config config;
1155 struct amdgpu_rlc rlc;
1156 struct amdgpu_mec mec;
1157 struct amdgpu_scratch scratch;
1158 const struct firmware *me_fw; /* ME firmware */
1159 uint32_t me_fw_version;
1160 const struct firmware *pfp_fw; /* PFP firmware */
1161 uint32_t pfp_fw_version;
1162 const struct firmware *ce_fw; /* CE firmware */
1163 uint32_t ce_fw_version;
1164 const struct firmware *rlc_fw; /* RLC firmware */
1165 uint32_t rlc_fw_version;
1166 const struct firmware *mec_fw; /* MEC firmware */
1167 uint32_t mec_fw_version;
1168 const struct firmware *mec2_fw; /* MEC2 firmware */
1169 uint32_t mec2_fw_version;
02558a00
KW		 1170 uint32_t me_feature_version;
1171 uint32_t ce_feature_version;
1172 uint32_t pfp_feature_version;
351643d7
JZ		 1173 uint32_t rlc_feature_version;
1174 uint32_t mec_feature_version;
1175 uint32_t mec2_feature_version;
97b2e202
AD		 1176 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1177 unsigned num_gfx_rings;
1178 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1179 unsigned num_compute_rings;
1180 struct amdgpu_irq_src eop_irq;
1181 struct amdgpu_irq_src priv_reg_irq;
1182 struct amdgpu_irq_src priv_inst_irq;
1183 /* gfx status */
1184 uint32_t gfx_current_status;
a101a899
KW		 1185 /* ce ram size*/
1186 unsigned ce_ram_size;
97b2e202
AD		 1187};
1188
b07c60c0 1189int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1190 unsigned size, struct amdgpu_ib *ib);
4d9c514d
CK		 1191void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1192 struct fence *f);
b07c60c0 1193int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1194 struct amdgpu_ib *ib, struct fence *last_vm_update,
c5637837 1195 struct amdgpu_job *job, struct fence **f);
97b2e202
AD		 1196int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1197void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1198int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1199int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1200void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1201void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1202void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1203void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1204unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1205 uint32_t **data);
1206int amdgpu_ring_restore(struct amdgpu_ring *ring,
1207 unsigned size, uint32_t *data);
1208int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1209 unsigned ring_size, u32 nop, u32 align_mask,
1210 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1211 enum amdgpu_ring_type ring_type);
1212void amdgpu_ring_fini(struct amdgpu_ring *ring);
1213
1214/*
1215 * CS.
1216 */
1217struct amdgpu_cs_chunk {
1218 uint32_t chunk_id;
1219 uint32_t length_dw;
1220 uint32_t *kdata;
97b2e202
AD		 1221};
1222
1223struct amdgpu_cs_parser {
1224 struct amdgpu_device *adev;
1225 struct drm_file *filp;
3cb485f3 1226 struct amdgpu_ctx *ctx;
c3cca41e 1227
97b2e202
AD		 1228 /* chunks */
1229 unsigned nchunks;
1230 struct amdgpu_cs_chunk *chunks;
97b2e202 1231
50838c8c
CK		 1232 /* scheduler job object */
1233 struct amdgpu_job *job;
97b2e202 1234
c3cca41e
CK		 1235 /* buffer objects */
1236 struct ww_acquire_ctx ticket;
1237 struct amdgpu_bo_list *bo_list;
1238 struct amdgpu_bo_list_entry vm_pd;
1239 struct list_head validated;
1240 struct fence *fence;
1241 uint64_t bytes_moved_threshold;
1242 uint64_t bytes_moved;
97b2e202
AD		 1243
1244 /* user fence */
91acbeb6 1245 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1246};
1247
bb977d37
CZ		 1248struct amdgpu_job {
1249 struct amd_sched_job base;
1250 struct amdgpu_device *adev;
c5637837 1251 struct amdgpu_vm *vm;
b07c60c0 1252 struct amdgpu_ring *ring;
e86f9cee 1253 struct amdgpu_sync sync;
bb977d37 1254 struct amdgpu_ib *ibs;
73cfa5f5 1255 struct fence *fence; /* the hw fence */
bb977d37 1256 uint32_t num_ibs;
e2840221 1257 void *owner;
bb977d37 1258 struct amdgpu_user_fence uf;
bb977d37 1259};
a6db8a33
JZ		 1260#define to_amdgpu_job(sched_job) \
1261 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1262
7270f839
CK		 1263static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1264 uint32_t ib_idx, int idx)
97b2e202 1265{
50838c8c 1266 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1267}
1268
7270f839
CK		 1269static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1270 uint32_t ib_idx, int idx,
1271 uint32_t value)
1272{
50838c8c 1273 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1274}
1275
97b2e202
AD		 1276/*
1277 * Writeback
1278 */
1279#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1280
1281struct amdgpu_wb {
1282 struct amdgpu_bo *wb_obj;
1283 volatile uint32_t *wb;
1284 uint64_t gpu_addr;
1285 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1286 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1287};
1288
1289int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1290void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1291
97b2e202 1292
97b2e202
AD		 1293
1294enum amdgpu_int_thermal_type {
1295 THERMAL_TYPE_NONE,
1296 THERMAL_TYPE_EXTERNAL,
1297 THERMAL_TYPE_EXTERNAL_GPIO,
1298 THERMAL_TYPE_RV6XX,
1299 THERMAL_TYPE_RV770,
1300 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1301 THERMAL_TYPE_EVERGREEN,
1302 THERMAL_TYPE_SUMO,
1303 THERMAL_TYPE_NI,
1304 THERMAL_TYPE_SI,
1305 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1306 THERMAL_TYPE_CI,
1307 THERMAL_TYPE_KV,
1308};
1309
1310enum amdgpu_dpm_auto_throttle_src {
1311 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1312 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1313};
1314
1315enum amdgpu_dpm_event_src {
1316 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1317 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1318 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1319 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1320 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1321};
1322
1323#define AMDGPU_MAX_VCE_LEVELS 6
1324
1325enum amdgpu_vce_level {
1326 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1327 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1328 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1329 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1330 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1331 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1332};
1333
1334struct amdgpu_ps {
1335 u32 caps; /* vbios flags */
1336 u32 class; /* vbios flags */
1337 u32 class2; /* vbios flags */
1338 /* UVD clocks */
1339 u32 vclk;
1340 u32 dclk;
1341 /* VCE clocks */
1342 u32 evclk;
1343 u32 ecclk;
1344 bool vce_active;
1345 enum amdgpu_vce_level vce_level;
1346 /* asic priv */
1347 void *ps_priv;
1348};
1349
1350struct amdgpu_dpm_thermal {
1351 /* thermal interrupt work */
1352 struct work_struct work;
1353 /* low temperature threshold */
1354 int min_temp;
1355 /* high temperature threshold */
1356 int max_temp;
1357 /* was last interrupt low to high or high to low */
1358 bool high_to_low;
1359 /* interrupt source */
1360 struct amdgpu_irq_src irq;
1361};
1362
1363enum amdgpu_clk_action
1364{
1365 AMDGPU_SCLK_UP = 1,
1366 AMDGPU_SCLK_DOWN
1367};
1368
1369struct amdgpu_blacklist_clocks
1370{
1371 u32 sclk;
1372 u32 mclk;
1373 enum amdgpu_clk_action action;
1374};
1375
1376struct amdgpu_clock_and_voltage_limits {
1377 u32 sclk;
1378 u32 mclk;
1379 u16 vddc;
1380 u16 vddci;
1381};
1382
1383struct amdgpu_clock_array {
1384 u32 count;
1385 u32 *values;
1386};
1387
1388struct amdgpu_clock_voltage_dependency_entry {
1389 u32 clk;
1390 u16 v;
1391};
1392
1393struct amdgpu_clock_voltage_dependency_table {
1394 u32 count;
1395 struct amdgpu_clock_voltage_dependency_entry *entries;
1396};
1397
1398union amdgpu_cac_leakage_entry {
1399 struct {
1400 u16 vddc;
1401 u32 leakage;
1402 };
1403 struct {
1404 u16 vddc1;
1405 u16 vddc2;
1406 u16 vddc3;
1407 };
1408};
1409
1410struct amdgpu_cac_leakage_table {
1411 u32 count;
1412 union amdgpu_cac_leakage_entry *entries;
1413};
1414
1415struct amdgpu_phase_shedding_limits_entry {
1416 u16 voltage;
1417 u32 sclk;
1418 u32 mclk;
1419};
1420
1421struct amdgpu_phase_shedding_limits_table {
1422 u32 count;
1423 struct amdgpu_phase_shedding_limits_entry *entries;
1424};
1425
1426struct amdgpu_uvd_clock_voltage_dependency_entry {
1427 u32 vclk;
1428 u32 dclk;
1429 u16 v;
1430};
1431
1432struct amdgpu_uvd_clock_voltage_dependency_table {
1433 u8 count;
1434 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1435};
1436
1437struct amdgpu_vce_clock_voltage_dependency_entry {
1438 u32 ecclk;
1439 u32 evclk;
1440 u16 v;
1441};
1442
1443struct amdgpu_vce_clock_voltage_dependency_table {
1444 u8 count;
1445 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1446};
1447
1448struct amdgpu_ppm_table {
1449 u8 ppm_design;
1450 u16 cpu_core_number;
1451 u32 platform_tdp;
1452 u32 small_ac_platform_tdp;
1453 u32 platform_tdc;
1454 u32 small_ac_platform_tdc;
1455 u32 apu_tdp;
1456 u32 dgpu_tdp;
1457 u32 dgpu_ulv_power;
1458 u32 tj_max;
1459};
1460
1461struct amdgpu_cac_tdp_table {
1462 u16 tdp;
1463 u16 configurable_tdp;
1464 u16 tdc;
1465 u16 battery_power_limit;
1466 u16 small_power_limit;
1467 u16 low_cac_leakage;
1468 u16 high_cac_leakage;
1469 u16 maximum_power_delivery_limit;
1470};
1471
1472struct amdgpu_dpm_dynamic_state {
1473 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1474 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1475 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1476 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1477 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1478 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1479 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1480 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1481 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1482 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1483 struct amdgpu_clock_array valid_sclk_values;
1484 struct amdgpu_clock_array valid_mclk_values;
1485 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1486 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1487 u32 mclk_sclk_ratio;
1488 u32 sclk_mclk_delta;
1489 u16 vddc_vddci_delta;
1490 u16 min_vddc_for_pcie_gen2;
1491 struct amdgpu_cac_leakage_table cac_leakage_table;
1492 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1493 struct amdgpu_ppm_table *ppm_table;
1494 struct amdgpu_cac_tdp_table *cac_tdp_table;
1495};
1496
1497struct amdgpu_dpm_fan {
1498 u16 t_min;
1499 u16 t_med;
1500 u16 t_high;
1501 u16 pwm_min;
1502 u16 pwm_med;
1503 u16 pwm_high;
1504 u8 t_hyst;
1505 u32 cycle_delay;
1506 u16 t_max;
1507 u8 control_mode;
1508 u16 default_max_fan_pwm;
1509 u16 default_fan_output_sensitivity;
1510 u16 fan_output_sensitivity;
1511 bool ucode_fan_control;
1512};
1513
1514enum amdgpu_pcie_gen {
1515 AMDGPU_PCIE_GEN1 = 0,
1516 AMDGPU_PCIE_GEN2 = 1,
1517 AMDGPU_PCIE_GEN3 = 2,
1518 AMDGPU_PCIE_GEN_INVALID = 0xffff
1519};
1520
1521enum amdgpu_dpm_forced_level {
1522 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1523 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1524 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1525 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1526};
1527
1528struct amdgpu_vce_state {
1529 /* vce clocks */
1530 u32 evclk;
1531 u32 ecclk;
1532 /* gpu clocks */
1533 u32 sclk;
1534 u32 mclk;
1535 u8 clk_idx;
1536 u8 pstate;
1537};
1538
1539struct amdgpu_dpm_funcs {
1540 int (*get_temperature)(struct amdgpu_device *adev);
1541 int (*pre_set_power_state)(struct amdgpu_device *adev);
1542 int (*set_power_state)(struct amdgpu_device *adev);
1543 void (*post_set_power_state)(struct amdgpu_device *adev);
1544 void (*display_configuration_changed)(struct amdgpu_device *adev);
1545 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1546 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1547 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1548 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1549 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1550 bool (*vblank_too_short)(struct amdgpu_device *adev);
1551 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1552 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1553 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1554 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1555 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1556 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1557 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1558};
1559
1560struct amdgpu_dpm {
1561 struct amdgpu_ps *ps;
1562 /* number of valid power states */
1563 int num_ps;
1564 /* current power state that is active */
1565 struct amdgpu_ps *current_ps;
1566 /* requested power state */
1567 struct amdgpu_ps *requested_ps;
1568 /* boot up power state */
1569 struct amdgpu_ps *boot_ps;
1570 /* default uvd power state */
1571 struct amdgpu_ps *uvd_ps;
1572 /* vce requirements */
1573 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1574 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1575 enum amd_pm_state_type state;
1576 enum amd_pm_state_type user_state;
97b2e202
AD		 1577 u32 platform_caps;
1578 u32 voltage_response_time;
1579 u32 backbias_response_time;
1580 void *priv;
1581 u32 new_active_crtcs;
1582 int new_active_crtc_count;
1583 u32 current_active_crtcs;
1584 int current_active_crtc_count;
1585 struct amdgpu_dpm_dynamic_state dyn_state;
1586 struct amdgpu_dpm_fan fan;
1587 u32 tdp_limit;
1588 u32 near_tdp_limit;
1589 u32 near_tdp_limit_adjusted;
1590 u32 sq_ramping_threshold;
1591 u32 cac_leakage;
1592 u16 tdp_od_limit;
1593 u32 tdp_adjustment;
1594 u16 load_line_slope;
1595 bool power_control;
1596 bool ac_power;
1597 /* special states active */
1598 bool thermal_active;
1599 bool uvd_active;
1600 bool vce_active;
1601 /* thermal handling */
1602 struct amdgpu_dpm_thermal thermal;
1603 /* forced levels */
1604 enum amdgpu_dpm_forced_level forced_level;
1605};
1606
1607struct amdgpu_pm {
1608 struct mutex mutex;
97b2e202
AD		 1609 u32 current_sclk;
1610 u32 current_mclk;
1611 u32 default_sclk;
1612 u32 default_mclk;
1613 struct amdgpu_i2c_chan *i2c_bus;
1614 /* internal thermal controller on rv6xx+ */
1615 enum amdgpu_int_thermal_type int_thermal_type;
1616 struct device *int_hwmon_dev;
1617 /* fan control parameters */
1618 bool no_fan;
1619 u8 fan_pulses_per_revolution;
1620 u8 fan_min_rpm;
1621 u8 fan_max_rpm;
1622 /* dpm */
1623 bool dpm_enabled;
c86f5ebf 1624 bool sysfs_initialized;
97b2e202
AD		 1625 struct amdgpu_dpm dpm;
1626 const struct firmware *fw; /* SMC firmware */
1627 uint32_t fw_version;
1628 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1629 uint32_t pcie_gen_mask;
1630 uint32_t pcie_mlw_mask;
7fb72a1f 1631 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1632};
1633
d0dd7f0c
AD		 1634void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1635
97b2e202
AD		 1636/*
1637 * UVD
1638 */
c0365541
AN		 1639#define AMDGPU_DEFAULT_UVD_HANDLES 10
1640#define AMDGPU_MAX_UVD_HANDLES 40
1641#define AMDGPU_UVD_STACK_SIZE (200*1024)
1642#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1643#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1644#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1645
1646struct amdgpu_uvd {
1647 struct amdgpu_bo *vcpu_bo;
1648 void *cpu_addr;
1649 uint64_t gpu_addr;
562e2689 1650 unsigned fw_version;
3f99dd81 1651 void *saved_bo;
c0365541 1652 unsigned max_handles;
97b2e202
AD		 1653 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1654 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1655 struct delayed_work idle_work;
1656 const struct firmware *fw; /* UVD firmware */
1657 struct amdgpu_ring ring;
1658 struct amdgpu_irq_src irq;
1659 bool address_64_bit;
ead833ec 1660 struct amd_sched_entity entity;
97b2e202
AD		 1661};
1662
1663/*
1664 * VCE
1665 */
1666#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1667#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1668
6a585777
AD		 1669#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1670#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1671
97b2e202
AD		 1672struct amdgpu_vce {
1673 struct amdgpu_bo *vcpu_bo;
1674 uint64_t gpu_addr;
1675 unsigned fw_version;
1676 unsigned fb_version;
1677 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1678 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1679 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1680 struct delayed_work idle_work;
1681 const struct firmware *fw; /* VCE firmware */
1682 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1683 struct amdgpu_irq_src irq;
6a585777 1684 unsigned harvest_config;
c594989c 1685 struct amd_sched_entity entity;
97b2e202
AD		 1686};
1687
1688/*
1689 * SDMA
1690 */
c113ea1c 1691struct amdgpu_sdma_instance {
97b2e202
AD		 1692 /* SDMA firmware */
1693 const struct firmware *fw;
1694 uint32_t fw_version;
cfa2104f 1695 uint32_t feature_version;
97b2e202
AD		 1696
1697 struct amdgpu_ring ring;
18111de0 1698 bool burst_nop;
97b2e202
AD		 1699};
1700
c113ea1c
AD		 1701struct amdgpu_sdma {
1702 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1703 struct amdgpu_irq_src trap_irq;
1704 struct amdgpu_irq_src illegal_inst_irq;
1705 int num_instances;
1706};
1707
97b2e202
AD		 1708/*
1709 * Firmware
1710 */
1711struct amdgpu_firmware {
1712 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1713 bool smu_load;
1714 struct amdgpu_bo *fw_buf;
1715 unsigned int fw_size;
1716};
1717
1718/*
1719 * Benchmarking
1720 */
1721void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1722
1723
1724/*
1725 * Testing
1726 */
1727void amdgpu_test_moves(struct amdgpu_device *adev);
1728void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1729 struct amdgpu_ring *cpA,
1730 struct amdgpu_ring *cpB);
1731void amdgpu_test_syncing(struct amdgpu_device *adev);
1732
1733/*
1734 * MMU Notifier
1735 */
1736#if defined(CONFIG_MMU_NOTIFIER)
1737int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1738void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1739#else
1d1106b0 1740static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1741{
1742 return -ENODEV;
1743}
1d1106b0 1744static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1745#endif
1746
1747/*
1748 * Debugfs
1749 */
1750struct amdgpu_debugfs {
06ab6832 1751 const struct drm_info_list *files;
97b2e202
AD		 1752 unsigned num_files;
1753};
1754
1755int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1756 const struct drm_info_list *files,
97b2e202
AD		 1757 unsigned nfiles);
1758int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1759
1760#if defined(CONFIG_DEBUG_FS)
1761int amdgpu_debugfs_init(struct drm_minor *minor);
1762void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1763#endif
1764
1765/*
1766 * amdgpu smumgr functions
1767 */
1768struct amdgpu_smumgr_funcs {
1769 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1770 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1771 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1772};
1773
1774/*
1775 * amdgpu smumgr
1776 */
1777struct amdgpu_smumgr {
1778 struct amdgpu_bo *toc_buf;
1779 struct amdgpu_bo *smu_buf;
1780 /* asic priv smu data */
1781 void *priv;
1782 spinlock_t smu_lock;
1783 /* smumgr functions */
1784 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1785 /* ucode loading complete flag */
1786 uint32_t fw_flags;
1787};
1788
1789/*
1790 * ASIC specific register table accessible by UMD
1791 */
1792struct amdgpu_allowed_register_entry {
1793 uint32_t reg_offset;
1794 bool untouched;
1795 bool grbm_indexed;
1796};
1797
1798struct amdgpu_cu_info {
1799 uint32_t number; /* total active CU number */
1800 uint32_t ao_cu_mask;
1801 uint32_t bitmap[4][4];
1802};
1803
1804
1805/*
1806 * ASIC specific functions.
1807 */
1808struct amdgpu_asic_funcs {
1809 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1810 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1811 u8 *bios, u32 length_bytes);
97b2e202
AD		 1812 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1813 u32 sh_num, u32 reg_offset, u32 *value);
1814 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1815 int (*reset)(struct amdgpu_device *adev);
1816 /* wait for mc_idle */
1817 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1818 /* get the reference clock */
1819 u32 (*get_xclk)(struct amdgpu_device *adev);
1820 /* get the gpu clock counter */
1821 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1822 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1823 /* MM block clocks */
1824 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1825 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1826};
1827
1828/*
1829 * IOCTL.
1830 */
1831int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1833int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1834 struct drm_file *filp);
1835
1836int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *filp);
1838int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1839 struct drm_file *filp);
1840int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1847 struct drm_file *filp);
1848int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1849int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1850
1851int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1852 struct drm_file *filp);
1853
1854/* VRAM scratch page for HDP bug, default vram page */
1855struct amdgpu_vram_scratch {
1856 struct amdgpu_bo *robj;
1857 volatile uint32_t *ptr;
1858 u64 gpu_addr;
1859};
1860
1861/*
1862 * ACPI
1863 */
1864struct amdgpu_atif_notification_cfg {
1865 bool enabled;
1866 int command_code;
1867};
1868
1869struct amdgpu_atif_notifications {
1870 bool display_switch;
1871 bool expansion_mode_change;
1872 bool thermal_state;
1873 bool forced_power_state;
1874 bool system_power_state;
1875 bool display_conf_change;
1876 bool px_gfx_switch;
1877 bool brightness_change;
1878 bool dgpu_display_event;
1879};
1880
1881struct amdgpu_atif_functions {
1882 bool system_params;
1883 bool sbios_requests;
1884 bool select_active_disp;
1885 bool lid_state;
1886 bool get_tv_standard;
1887 bool set_tv_standard;
1888 bool get_panel_expansion_mode;
1889 bool set_panel_expansion_mode;
1890 bool temperature_change;
1891 bool graphics_device_types;
1892};
1893
1894struct amdgpu_atif {
1895 struct amdgpu_atif_notifications notifications;
1896 struct amdgpu_atif_functions functions;
1897 struct amdgpu_atif_notification_cfg notification_cfg;
1898 struct amdgpu_encoder *encoder_for_bl;
1899};
1900
1901struct amdgpu_atcs_functions {
1902 bool get_ext_state;
1903 bool pcie_perf_req;
1904 bool pcie_dev_rdy;
1905 bool pcie_bus_width;
1906};
1907
1908struct amdgpu_atcs {
1909 struct amdgpu_atcs_functions functions;
1910};
1911
d03846af
CZ		 1912/*
1913 * CGS
1914 */
110e6f26
DA		 1915struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1916void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce
MB		 1917
1918
7e471e6f
AD		 1919/* GPU virtualization */
1920struct amdgpu_virtualization {
1921 bool supports_sr_iov;
1922};
1923
97b2e202
AD		 1924/*
1925 * Core structure, functions and helpers.
1926 */
1927typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1928typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1929
1930typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1931typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1932
8faf0e08
AD		 1933struct amdgpu_ip_block_status {
1934 bool valid;
1935 bool sw;
1936 bool hw;
1937};
1938
97b2e202
AD		 1939struct amdgpu_device {
1940 struct device *dev;
1941 struct drm_device *ddev;
1942 struct pci_dev *pdev;
97b2e202 1943
a8fe58ce
MB		 1944#ifdef CONFIG_DRM_AMD_ACP
1945 struct amdgpu_acp acp;
1946#endif
1947
97b2e202 1948 /* ASIC */
2f7d10b3 1949 enum amd_asic_type asic_type;
97b2e202
AD		 1950 uint32_t family;
1951 uint32_t rev_id;
1952 uint32_t external_rev_id;
1953 unsigned long flags;
1954 int usec_timeout;
1955 const struct amdgpu_asic_funcs *asic_funcs;
1956 bool shutdown;
97b2e202
AD		 1957 bool need_dma32;
1958 bool accel_working;
97b2e202
AD		 1959 struct work_struct reset_work;
1960 struct notifier_block acpi_nb;
1961 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1962 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1963 unsigned debugfs_count;
1964#if defined(CONFIG_DEBUG_FS)
adcec288 1965 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1966#endif
1967 struct amdgpu_atif atif;
1968 struct amdgpu_atcs atcs;
1969 struct mutex srbm_mutex;
1970 /* GRBM index mutex. Protects concurrent access to GRBM index */
1971 struct mutex grbm_idx_mutex;
1972 struct dev_pm_domain vga_pm_domain;
1973 bool have_disp_power_ref;
1974
1975 /* BIOS */
1976 uint8_t *bios;
1977 bool is_atom_bios;
97b2e202
AD		 1978 struct amdgpu_bo *stollen_vga_memory;
1979 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1980
1981 /* Register/doorbell mmio */
1982 resource_size_t rmmio_base;
1983 resource_size_t rmmio_size;
1984 void __iomem *rmmio;
1985 /* protects concurrent MM_INDEX/DATA based register access */
1986 spinlock_t mmio_idx_lock;
1987 /* protects concurrent SMC based register access */
1988 spinlock_t smc_idx_lock;
1989 amdgpu_rreg_t smc_rreg;
1990 amdgpu_wreg_t smc_wreg;
1991 /* protects concurrent PCIE register access */
1992 spinlock_t pcie_idx_lock;
1993 amdgpu_rreg_t pcie_rreg;
1994 amdgpu_wreg_t pcie_wreg;
1995 /* protects concurrent UVD register access */
1996 spinlock_t uvd_ctx_idx_lock;
1997 amdgpu_rreg_t uvd_ctx_rreg;
1998 amdgpu_wreg_t uvd_ctx_wreg;
1999 /* protects concurrent DIDT register access */
2000 spinlock_t didt_idx_lock;
2001 amdgpu_rreg_t didt_rreg;
2002 amdgpu_wreg_t didt_wreg;
2003 /* protects concurrent ENDPOINT (audio) register access */
2004 spinlock_t audio_endpt_idx_lock;
2005 amdgpu_block_rreg_t audio_endpt_rreg;
2006 amdgpu_block_wreg_t audio_endpt_wreg;
2007 void __iomem *rio_mem;
2008 resource_size_t rio_mem_size;
2009 struct amdgpu_doorbell doorbell;
2010
2011 /* clock/pll info */
2012 struct amdgpu_clock clock;
2013
2014 /* MC */
2015 struct amdgpu_mc mc;
2016 struct amdgpu_gart gart;
2017 struct amdgpu_dummy_page dummy_page;
2018 struct amdgpu_vm_manager vm_manager;
2019
2020 /* memory management */
2021 struct amdgpu_mman mman;
97b2e202
AD		 2022 struct amdgpu_vram_scratch vram_scratch;
2023 struct amdgpu_wb wb;
2024 atomic64_t vram_usage;
2025 atomic64_t vram_vis_usage;
2026 atomic64_t gtt_usage;
2027 atomic64_t num_bytes_moved;
d94aed5a 2028 atomic_t gpu_reset_counter;
97b2e202
AD		 2029
2030 /* display */
2031 struct amdgpu_mode_info mode_info;
2032 struct work_struct hotplug_work;
2033 struct amdgpu_irq_src crtc_irq;
2034 struct amdgpu_irq_src pageflip_irq;
2035 struct amdgpu_irq_src hpd_irq;
2036
2037 /* rings */
97b2e202 2038 unsigned fence_context;
97b2e202
AD		 2039 unsigned num_rings;
2040 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2041 bool ib_pool_ready;
2042 struct amdgpu_sa_manager ring_tmp_bo;
2043
2044 /* interrupts */
2045 struct amdgpu_irq irq;
2046
1f7371b2
AD		 2047 /* powerplay */
2048 struct amd_powerplay powerplay;
e61710c5 2049 bool pp_enabled;
f3898ea1 2050 bool pp_force_state_enabled;
1f7371b2 2051
97b2e202
AD		 2052 /* dpm */
2053 struct amdgpu_pm pm;
2054 u32 cg_flags;
2055 u32 pg_flags;
2056
2057 /* amdgpu smumgr */
2058 struct amdgpu_smumgr smu;
2059
2060 /* gfx */
2061 struct amdgpu_gfx gfx;
2062
2063 /* sdma */
c113ea1c 2064 struct amdgpu_sdma sdma;
97b2e202
AD		 2065
2066 /* uvd */
97b2e202
AD		 2067 struct amdgpu_uvd uvd;
2068
2069 /* vce */
2070 struct amdgpu_vce vce;
2071
2072 /* firmwares */
2073 struct amdgpu_firmware firmware;
2074
2075 /* GDS */
2076 struct amdgpu_gds gds;
2077
2078 const struct amdgpu_ip_block_version *ip_blocks;
2079 int num_ip_blocks;
8faf0e08 2080 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2081 struct mutex mn_lock;
2082 DECLARE_HASHTABLE(mn_hash, 7);
2083
2084 /* tracking pinned memory */
2085 u64 vram_pin_size;
e131b914 2086 u64 invisible_pin_size;
97b2e202 2087 u64 gart_pin_size;
130e0371
OG		 2088
2089 /* amdkfd interface */
2090 struct kfd_dev *kfd;
23ca0e4e 2091
7e471e6f 2092 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2093};
2094
2095bool amdgpu_device_is_px(struct drm_device *dev);
2096int amdgpu_device_init(struct amdgpu_device *adev,
2097 struct drm_device *ddev,
2098 struct pci_dev *pdev,
2099 uint32_t flags);
2100void amdgpu_device_fini(struct amdgpu_device *adev);
2101int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2102
2103uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2104 bool always_indirect);
2105void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2106 bool always_indirect);
2107u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2108void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2109
2110u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2111void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2112
97b2e202
AD		 2113/*
2114 * Registers read & write functions.
2115 */
2116#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2117#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2118#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2119#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2120#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2121#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2122#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2123#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2124#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2125#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2126#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2127#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2128#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2129#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2130#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2131#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2132#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2133#define WREG32_P(reg, val, mask) \
2134 do { \
2135 uint32_t tmp_ = RREG32(reg); \
2136 tmp_ &= (mask); \
2137 tmp_ |= ((val) & ~(mask)); \
2138 WREG32(reg, tmp_); \
2139 } while (0)
2140#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2141#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2142#define WREG32_PLL_P(reg, val, mask) \
2143 do { \
2144 uint32_t tmp_ = RREG32_PLL(reg); \
2145 tmp_ &= (mask); \
2146 tmp_ |= ((val) & ~(mask)); \
2147 WREG32_PLL(reg, tmp_); \
2148 } while (0)
2149#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2150#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2151#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2152
2153#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2154#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2155
2156#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2157#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2158
2159#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2160 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2161 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2162
2163#define REG_GET_FIELD(value, reg, field) \
2164 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2165
2166/*
2167 * BIOS helpers.
2168 */
2169#define RBIOS8(i) (adev->bios[i])
2170#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2171#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2172
2173/*
2174 * RING helpers.
2175 */
2176static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2177{
2178 if (ring->count_dw <= 0)
86c2b790 2179 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2180 ring->ring[ring->wptr++] = v;
2181 ring->wptr &= ring->ptr_mask;
2182 ring->count_dw--;
97b2e202
AD		 2183}
2184
c113ea1c
AD		 2185static inline struct amdgpu_sdma_instance *
2186amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2187{
2188 struct amdgpu_device *adev = ring->adev;
2189 int i;
2190
c113ea1c
AD		 2191 for (i = 0; i < adev->sdma.num_instances; i++)
2192 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2193 break;
2194
2195 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2196 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2197 else
2198 return NULL;
2199}
2200
97b2e202
AD		 2201/*
2202 * ASICs macro.
2203 */
2204#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2205#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2206#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2207#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2208#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2209#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2210#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2211#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2212#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2213#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2214#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2215#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2216#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2217#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2218#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2219#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2220#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2221#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2222#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2223#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2224#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2225#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2226#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
b8c7b39e 2227#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2228#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2229#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2230#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2231#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2232#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2233#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 2234#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2235#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 2236#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2237#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2238#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2239#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2240#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2241#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2242#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2243#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2244#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2245#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2246#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2247#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2248#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2249#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2250#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2251#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2252#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2253#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2254#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2255#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2256#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2257#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2258#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2259#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2260#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2261#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2262#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2263#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2264
2265#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2266 ((adev)->pp_enabled ? \
e61710c5 2267 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2268 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2269
2270#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2271 ((adev)->pp_enabled ? \
e61710c5 2272 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2273 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2274
2275#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2276 ((adev)->pp_enabled ? \
e61710c5 2277 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2278 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2279
2280#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2281 ((adev)->pp_enabled ? \
e61710c5 2282 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2283 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2284
2285#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2286 ((adev)->pp_enabled ? \
e61710c5 2287 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2288 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2289
1b5708ff 2290#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2291 ((adev)->pp_enabled ? \
e61710c5 2292 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2293 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2294
2295#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2296 ((adev)->pp_enabled ? \
e61710c5 2297 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2298 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2299
2300
2301#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2302 ((adev)->pp_enabled ? \
e61710c5 2303 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2304 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2305
2306#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2307 ((adev)->pp_enabled ? \
e61710c5 2308 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2309 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2310
2311#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2312 ((adev)->pp_enabled ? \
e61710c5 2313 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2314 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2315
2316#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2317 ((adev)->pp_enabled ? \
e61710c5 2318 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2319 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2320
2321#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2322 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2323
2324#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2325 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2326
f3898ea1
EH		 2327#define amdgpu_dpm_get_pp_num_states(adev, data) \
2328 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2329
2330#define amdgpu_dpm_get_pp_table(adev, table) \
2331 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2332
2333#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2334 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2335
2336#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2337 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2338
2339#define amdgpu_dpm_force_clock_level(adev, type, level) \
2340 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2341
e61710c5 2342#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2343 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2344
2345#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2346
2347/* Common functions */
2348int amdgpu_gpu_reset(struct amdgpu_device *adev);
2349void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2350bool amdgpu_card_posted(struct amdgpu_device *adev);
2351void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2352
97b2e202
AD		 2353int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2354int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2355 u32 ip_instance, u32 ring,
2356 struct amdgpu_ring **out_ring);
2357void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2358bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2359int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2360int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2361 uint32_t flags);
2362bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 2363struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2364bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2365 unsigned long end);
2f568dbd
CK		 2366bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2367 int *last_invalidated);
97b2e202
AD		 2368bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2369uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2370 struct ttm_mem_reg *mem);
2371void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2372void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2373void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2374void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2375 const u32 *registers,
2376 const u32 array_size);
2377
2378bool amdgpu_device_is_px(struct drm_device *dev);
2379/* atpx handler */
2380#if defined(CONFIG_VGA_SWITCHEROO)
2381void amdgpu_register_atpx_handler(void);
2382void amdgpu_unregister_atpx_handler(void);
2383#else
2384static inline void amdgpu_register_atpx_handler(void) {}
2385static inline void amdgpu_unregister_atpx_handler(void) {}
2386#endif
2387
2388/*
2389 * KMS
2390 */
2391extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 2392extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 2393
2394int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2395int amdgpu_driver_unload_kms(struct drm_device *dev);
2396void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2397int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2398void amdgpu_driver_postclose_kms(struct drm_device *dev,
2399 struct drm_file *file_priv);
2400void amdgpu_driver_preclose_kms(struct drm_device *dev,
2401 struct drm_file *file_priv);
2402int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2403int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2404u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2405int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2406void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2407int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2408 int *max_error,
2409 struct timeval *vblank_time,
2410 unsigned flags);
2411long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2412 unsigned long arg);
2413
97b2e202
AD		 2414/*
2415 * functions used by amdgpu_encoder.c
2416 */
2417struct amdgpu_afmt_acr {
2418 u32 clock;
2419
2420 int n_32khz;
2421 int cts_32khz;
2422
2423 int n_44_1khz;
2424 int cts_44_1khz;
2425
2426 int n_48khz;
2427 int cts_48khz;
2428
2429};
2430
2431struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2432
2433/* amdgpu_acpi.c */
2434#if defined(CONFIG_ACPI)
2435int amdgpu_acpi_init(struct amdgpu_device *adev);
2436void amdgpu_acpi_fini(struct amdgpu_device *adev);
2437bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2438int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2439 u8 perf_req, bool advertise);
2440int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2441#else
2442static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2443static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2444#endif
2445
2446struct amdgpu_bo_va_mapping *
2447amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2448 uint64_t addr, struct amdgpu_bo **bo);
2449
2450#include "amdgpu_object.h"
97b2e202 2451#endif
Linux 6.x block layer and io_uring tree(s)