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drm/amdgpu/atombios: add function for whether we need asic_init
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834
AR		 49#include <kgd_kfd_interface.h>
50
5fc3aeeb 51#include "amd_shared.h"
97b2e202
AD		 52#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
c632d799 56#include "amdgpu_ttm.h"
0e5ca0d1 57#include "amdgpu_psp.h"
97b2e202 58#include "amdgpu_gds.h"
56113504 59#include "amdgpu_sync.h"
78023016 60#include "amdgpu_ring.h"
073440d2 61#include "amdgpu_vm.h"
1f7371b2 62#include "amd_powerplay.h"
cf097881 63#include "amdgpu_dpm.h"
a8fe58ce 64#include "amdgpu_acp.h"
4df654d2 65#include "amdgpu_uvd.h"
5e568178 66#include "amdgpu_vce.h"
95aa13f6 67#include "amdgpu_vcn.h"
97b2e202 68
b80d8475 69#include "gpu_scheduler.h"
ceeb50ed 70#include "amdgpu_virt.h"
b80d8475 71
97b2e202
AD		 72/*
73 * Modules parameters.
74 */
75extern int amdgpu_modeset;
76extern int amdgpu_vram_limit;
77extern int amdgpu_gart_size;
95844d20 78extern int amdgpu_moverate;
97b2e202
AD		 79extern int amdgpu_benchmarking;
80extern int amdgpu_testing;
81extern int amdgpu_audio;
82extern int amdgpu_disp_priority;
83extern int amdgpu_hw_i2c;
84extern int amdgpu_pcie_gen2;
85extern int amdgpu_msi;
86extern int amdgpu_lockup_timeout;
87extern int amdgpu_dpm;
e635ee07 88extern int amdgpu_fw_load_type;
97b2e202
AD		 89extern int amdgpu_aspm;
90extern int amdgpu_runtime_pm;
97b2e202
AD		 91extern unsigned amdgpu_ip_block_mask;
92extern int amdgpu_bapm;
93extern int amdgpu_deep_color;
94extern int amdgpu_vm_size;
95extern int amdgpu_vm_block_size;
d9c13156 96extern int amdgpu_vm_fault_stop;
b495bd3a 97extern int amdgpu_vm_debug;
9a4b7d4c 98extern int amdgpu_vm_update_mode;
1333f723 99extern int amdgpu_sched_jobs;
4afcb303 100extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 101extern int amdgpu_no_evict;
102extern int amdgpu_direct_gma_size;
cd474ba0
AD		 103extern unsigned amdgpu_pcie_gen_cap;
104extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 105extern unsigned amdgpu_cg_mask;
106extern unsigned amdgpu_pg_mask;
6f8941a2 107extern char *amdgpu_disable_cu;
9accf2fd 108extern char *amdgpu_virtual_display;
5141e9d2 109extern unsigned amdgpu_pp_feature_mask;
6a7f76e7 110extern int amdgpu_vram_page_split;
bce23e00
AD		 111extern int amdgpu_ngg;
112extern int amdgpu_prim_buf_per_se;
113extern int amdgpu_pos_buf_per_se;
114extern int amdgpu_cntl_sb_buf_per_se;
115extern int amdgpu_param_buf_per_se;
65781c78 116extern int amdgpu_job_hang_limit;
e8835e0e 117extern int amdgpu_lbpw;
97b2e202 118
6dd13096
FK		 119#ifdef CONFIG_DRM_AMDGPU_SI
120extern int amdgpu_si_support;
121#endif
7df28986
FK		 122#ifdef CONFIG_DRM_AMDGPU_CIK
123extern int amdgpu_cik_support;
124#endif
97b2e202 125
55ed8caf 126#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 127#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 128#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
129#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
130/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
131#define AMDGPU_IB_POOL_SIZE 16
132#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
133#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 134#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 135
36f523a7
JZ		 136/* max number of IP instances */
137#define AMDGPU_MAX_SDMA_INSTANCES 2
138
97b2e202
AD		 139/* hard reset data */
140#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
141
142/* reset flags */
143#define AMDGPU_RESET_GFX (1 << 0)
144#define AMDGPU_RESET_COMPUTE (1 << 1)
145#define AMDGPU_RESET_DMA (1 << 2)
146#define AMDGPU_RESET_CP (1 << 3)
147#define AMDGPU_RESET_GRBM (1 << 4)
148#define AMDGPU_RESET_DMA1 (1 << 5)
149#define AMDGPU_RESET_RLC (1 << 6)
150#define AMDGPU_RESET_SEM (1 << 7)
151#define AMDGPU_RESET_IH (1 << 8)
152#define AMDGPU_RESET_VMC (1 << 9)
153#define AMDGPU_RESET_MC (1 << 10)
154#define AMDGPU_RESET_DISPLAY (1 << 11)
155#define AMDGPU_RESET_UVD (1 << 12)
156#define AMDGPU_RESET_VCE (1 << 13)
157#define AMDGPU_RESET_VCE1 (1 << 14)
158
97b2e202
AD		 159/* GFX current status */
160#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
161#define AMDGPU_GFX_SAFE_MODE 0x00000001L
162#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
163#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
164#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
165
166/* max cursor sizes (in pixels) */
167#define CIK_CURSOR_WIDTH 128
168#define CIK_CURSOR_HEIGHT 128
169
170struct amdgpu_device;
97b2e202 171struct amdgpu_ib;
97b2e202 172struct amdgpu_cs_parser;
bb977d37 173struct amdgpu_job;
97b2e202 174struct amdgpu_irq_src;
0b492a4c 175struct amdgpu_fpriv;
97b2e202
AD		 176
177enum amdgpu_cp_irq {
178 AMDGPU_CP_IRQ_GFX_EOP = 0,
179 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
180 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
181 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
182 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
183 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
184 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
185 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
187
188 AMDGPU_CP_IRQ_LAST
189};
190
191enum amdgpu_sdma_irq {
192 AMDGPU_SDMA_IRQ_TRAP0 = 0,
193 AMDGPU_SDMA_IRQ_TRAP1,
194
195 AMDGPU_SDMA_IRQ_LAST
196};
197
198enum amdgpu_thermal_irq {
199 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
200 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
201
202 AMDGPU_THERMAL_IRQ_LAST
203};
204
4e638ae9
XY		 205enum amdgpu_kiq_irq {
206 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
207 AMDGPU_CP_KIQ_IRQ_LAST
208};
209
97b2e202 210int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 211 enum amd_ip_block_type block_type,
212 enum amd_clockgating_state state);
97b2e202 213int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 214 enum amd_ip_block_type block_type,
215 enum amd_powergating_state state);
6cb2d4e4 216void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 217int amdgpu_wait_for_idle(struct amdgpu_device *adev,
218 enum amd_ip_block_type block_type);
219bool amdgpu_is_idle(struct amdgpu_device *adev,
220 enum amd_ip_block_type block_type);
97b2e202 221
a1255107
AD		 222#define AMDGPU_MAX_IP_NUM 16
223
224struct amdgpu_ip_block_status {
225 bool valid;
226 bool sw;
227 bool hw;
228 bool late_initialized;
229 bool hang;
230};
231
97b2e202 232struct amdgpu_ip_block_version {
a1255107
AD		 233 const enum amd_ip_block_type type;
234 const u32 major;
235 const u32 minor;
236 const u32 rev;
5fc3aeeb 237 const struct amd_ip_funcs *funcs;
97b2e202
AD		 238};
239
a1255107
AD		 240struct amdgpu_ip_block {
241 struct amdgpu_ip_block_status status;
242 const struct amdgpu_ip_block_version *version;
243};
244
97b2e202 245int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 246 enum amd_ip_block_type type,
97b2e202
AD		 247 u32 major, u32 minor);
248
a1255107
AD		 249struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
250 enum amd_ip_block_type type);
251
252int amdgpu_ip_block_add(struct amdgpu_device *adev,
253 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 254
255/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
256struct amdgpu_buffer_funcs {
257 /* maximum bytes in a single operation */
258 uint32_t copy_max_bytes;
259
260 /* number of dw to reserve per operation */
261 unsigned copy_num_dw;
262
263 /* used for buffer migration */
c7ae72c0 264 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 265 /* src addr in bytes */
266 uint64_t src_offset,
267 /* dst addr in bytes */
268 uint64_t dst_offset,
269 /* number of byte to transfer */
270 uint32_t byte_count);
271
272 /* maximum bytes in a single operation */
273 uint32_t fill_max_bytes;
274
275 /* number of dw to reserve per operation */
276 unsigned fill_num_dw;
277
278 /* used for buffer clearing */
6e7a3840 279 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 280 /* value to write to memory */
281 uint32_t src_data,
282 /* dst addr in bytes */
283 uint64_t dst_offset,
284 /* number of byte to fill */
285 uint32_t byte_count);
286};
287
288/* provided by hw blocks that can write ptes, e.g., sdma */
289struct amdgpu_vm_pte_funcs {
290 /* copy pte entries from GART */
291 void (*copy_pte)(struct amdgpu_ib *ib,
292 uint64_t pe, uint64_t src,
293 unsigned count);
294 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 295 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
296 uint64_t value, unsigned count,
297 uint32_t incr);
97b2e202
AD		 298 /* for linear pte/pde updates without addr mapping */
299 void (*set_pte_pde)(struct amdgpu_ib *ib,
300 uint64_t pe,
301 uint64_t addr, unsigned count,
6b777607 302 uint32_t incr, uint64_t flags);
97b2e202
AD		 303};
304
305/* provided by the gmc block */
306struct amdgpu_gart_funcs {
307 /* flush the vm tlb via mmio */
308 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
309 uint32_t vmid);
310 /* write pte/pde updates using the cpu */
311 int (*set_pte_pde)(struct amdgpu_device *adev,
312 void *cpu_pt_addr, /* cpu addr of page table */
313 uint32_t gpu_page_idx, /* pte/pde to update */
314 uint64_t addr, /* addr to write into pte/pde */
6b777607 315 uint64_t flags); /* access flags */
284710fa
CK		 316 /* enable/disable PRT support */
317 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 318 /* set pte flags based per asic */
319 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
320 uint32_t flags);
b1166325
CK		 321 /* get the pde for a given mc addr */
322 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 323 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 324};
325
97b2e202
AD		 326/* provided by the ih block */
327struct amdgpu_ih_funcs {
328 /* ring read/write ptr handling, called from interrupt context */
329 u32 (*get_wptr)(struct amdgpu_device *adev);
330 void (*decode_iv)(struct amdgpu_device *adev,
331 struct amdgpu_iv_entry *entry);
332 void (*set_rptr)(struct amdgpu_device *adev);
333};
334
97b2e202
AD		 335/*
336 * BIOS.
337 */
338bool amdgpu_get_bios(struct amdgpu_device *adev);
339bool amdgpu_read_bios(struct amdgpu_device *adev);
340
341/*
342 * Dummy page
343 */
344struct amdgpu_dummy_page {
345 struct page *page;
346 dma_addr_t addr;
347};
348int amdgpu_dummy_page_init(struct amdgpu_device *adev);
349void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
350
351
352/*
353 * Clocks
354 */
355
356#define AMDGPU_MAX_PPLL 3
357
358struct amdgpu_clock {
359 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
360 struct amdgpu_pll spll;
361 struct amdgpu_pll mpll;
362 /* 10 Khz units */
363 uint32_t default_mclk;
364 uint32_t default_sclk;
365 uint32_t default_dispclk;
366 uint32_t current_dispclk;
367 uint32_t dp_extclk;
368 uint32_t max_pixel_clock;
369};
370
97b2e202 371/*
c632d799 372 * BO.
97b2e202 373 */
97b2e202
AD		 374struct amdgpu_bo_list_entry {
375 struct amdgpu_bo *robj;
376 struct ttm_validate_buffer tv;
377 struct amdgpu_bo_va *bo_va;
97b2e202 378 uint32_t priority;
2f568dbd
CK		 379 struct page **user_pages;
380 int user_invalidated;
97b2e202
AD		 381};
382
383struct amdgpu_bo_va_mapping {
384 struct list_head list;
a9f87f64
CK		 385 struct rb_node rb;
386 uint64_t start;
387 uint64_t last;
388 uint64_t __subtree_last;
97b2e202 389 uint64_t offset;
268c3001 390 uint64_t flags;
97b2e202
AD		 391};
392
393/* bo virtual addresses in a specific vm */
394struct amdgpu_bo_va {
395 /* protected by bo being reserved */
396 struct list_head bo_list;
f54d1867 397 struct dma_fence *last_pt_update;
97b2e202
AD		 398 unsigned ref_count;
399
7fc11959 400 /* protected by vm mutex and spinlock */
97b2e202
AD		 401 struct list_head vm_status;
402
7fc11959
CK		 403 /* mappings for this bo_va */
404 struct list_head invalids;
405 struct list_head valids;
406
97b2e202
AD		 407 /* constant after initialization */
408 struct amdgpu_vm *vm;
409 struct amdgpu_bo *bo;
410};
411
7e5a547f
CZ		 412#define AMDGPU_GEM_DOMAIN_MAX 0x3
413
97b2e202 414struct amdgpu_bo {
97b2e202 415 /* Protected by tbo.reserved */
1ea863fd
CK		 416 u32 prefered_domains;
417 u32 allowed_domains;
7e5a547f 418 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 419 struct ttm_placement placement;
420 struct ttm_buffer_object tbo;
421 struct ttm_bo_kmap_obj kmap;
422 u64 flags;
423 unsigned pin_count;
424 void *kptr;
425 u64 tiling_flags;
426 u64 metadata_flags;
427 void *metadata;
428 u32 metadata_size;
8e94a46c 429 unsigned prime_shared_count;
97b2e202
AD		 430 /* list of all virtual address to which this bo
431 * is associated to
432 */
433 struct list_head va;
434 /* Constant after initialization */
97b2e202 435 struct drm_gem_object gem_base;
82b9c55b 436 struct amdgpu_bo *parent;
e7893c4b 437 struct amdgpu_bo *shadow;
97b2e202
AD		 438
439 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 440 struct amdgpu_mn *mn;
441 struct list_head mn_list;
0c4e7fa5 442 struct list_head shadow_list;
97b2e202
AD		 443};
444#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
445
446void amdgpu_gem_object_free(struct drm_gem_object *obj);
447int amdgpu_gem_object_open(struct drm_gem_object *obj,
448 struct drm_file *file_priv);
449void amdgpu_gem_object_close(struct drm_gem_object *obj,
450 struct drm_file *file_priv);
451unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
452struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 453struct drm_gem_object *
454amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
455 struct dma_buf_attachment *attach,
456 struct sg_table *sg);
97b2e202
AD		 457struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
458 struct drm_gem_object *gobj,
459 int flags);
460int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
461void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
462struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
463void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
464void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
465int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
466
467/* sub-allocation manager, it has to be protected by another lock.
468 * By conception this is an helper for other part of the driver
469 * like the indirect buffer or semaphore, which both have their
470 * locking.
471 *
472 * Principe is simple, we keep a list of sub allocation in offset
473 * order (first entry has offset == 0, last entry has the highest
474 * offset).
475 *
476 * When allocating new object we first check if there is room at
477 * the end total_size - (last_object_offset + last_object_size) >=
478 * alloc_size. If so we allocate new object there.
479 *
480 * When there is not enough room at the end, we start waiting for
481 * each sub object until we reach object_offset+object_size >=
482 * alloc_size, this object then become the sub object we return.
483 *
484 * Alignment can't be bigger than page size.
485 *
486 * Hole are not considered for allocation to keep things simple.
487 * Assumption is that there won't be hole (all object on same
488 * alignment).
489 */
6ba60b89
CK		 490
491#define AMDGPU_SA_NUM_FENCE_LISTS 32
492
97b2e202
AD		 493struct amdgpu_sa_manager {
494 wait_queue_head_t wq;
495 struct amdgpu_bo *bo;
496 struct list_head *hole;
6ba60b89 497 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 498 struct list_head olist;
499 unsigned size;
500 uint64_t gpu_addr;
501 void *cpu_ptr;
502 uint32_t domain;
503 uint32_t align;
504};
505
97b2e202
AD		 506/* sub-allocation buffer */
507struct amdgpu_sa_bo {
508 struct list_head olist;
509 struct list_head flist;
510 struct amdgpu_sa_manager *manager;
511 unsigned soffset;
512 unsigned eoffset;
f54d1867 513 struct dma_fence *fence;
97b2e202
AD		 514};
515
516/*
517 * GEM objects.
518 */
418aa0c2 519void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 520int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
521 int alignment, u32 initial_domain,
522 u64 flags, bool kernel,
523 struct drm_gem_object **obj);
524
525int amdgpu_mode_dumb_create(struct drm_file *file_priv,
526 struct drm_device *dev,
527 struct drm_mode_create_dumb *args);
528int amdgpu_mode_dumb_mmap(struct drm_file *filp,
529 struct drm_device *dev,
530 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 531int amdgpu_fence_slab_init(void);
532void amdgpu_fence_slab_fini(void);
97b2e202
AD		 533
534/*
535 * GART structures, functions & helpers
536 */
537struct amdgpu_mc;
538
539#define AMDGPU_GPU_PAGE_SIZE 4096
540#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
541#define AMDGPU_GPU_PAGE_SHIFT 12
542#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
543
544struct amdgpu_gart {
545 dma_addr_t table_addr;
546 struct amdgpu_bo *robj;
547 void *ptr;
548 unsigned num_gpu_pages;
549 unsigned num_cpu_pages;
550 unsigned table_size;
a1d29476 551#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 552 struct page **pages;
a1d29476 553#endif
97b2e202 554 bool ready;
4b98e0c4
AX		 555
556 /* Asic default pte flags */
557 uint64_t gart_pte_flags;
558
97b2e202
AD		 559 const struct amdgpu_gart_funcs *gart_funcs;
560};
561
011d4bbe 562void amdgpu_gart_set_defaults(struct amdgpu_device *adev);
97b2e202
AD		 563int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
564void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
565int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
566void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
567int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
568void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
569int amdgpu_gart_init(struct amdgpu_device *adev);
570void amdgpu_gart_fini(struct amdgpu_device *adev);
738f64cc 571int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 572 int pages);
cab0b8d5 573int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 574 int pages, struct page **pagelist,
6b777607 575 dma_addr_t *dma_addr, uint64_t flags);
2c0d7318 576int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
97b2e202 577
e60f8db5
AX		 578/*
579 * VMHUB structures, functions & helpers
580 */
581struct amdgpu_vmhub {
582 uint32_t ctx0_ptb_addr_lo32;
583 uint32_t ctx0_ptb_addr_hi32;
584 uint32_t vm_inv_eng0_req;
585 uint32_t vm_inv_eng0_ack;
586 uint32_t vm_context0_cntl;
587 uint32_t vm_l2_pro_fault_status;
588 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 589};
590
97b2e202
AD		 591/*
592 * GPU MC structures, functions & helpers
593 */
594struct amdgpu_mc {
595 resource_size_t aper_size;
596 resource_size_t aper_base;
597 resource_size_t agp_base;
598 /* for some chips with <= 32MB we need to lie
599 * about vram size near mc fb location */
600 u64 mc_vram_size;
601 u64 visible_vram_size;
602 u64 gtt_size;
603 u64 gtt_start;
604 u64 gtt_end;
605 u64 vram_start;
606 u64 vram_end;
607 unsigned vram_width;
608 u64 real_vram_size;
609 int vram_mtrr;
610 u64 gtt_base_align;
611 u64 mc_mask;
612 const struct firmware *fw; /* MC firmware */
613 uint32_t fw_version;
614 struct amdgpu_irq_src vm_fault;
81c59f54 615 uint32_t vram_type;
50b0197a 616 uint32_t srbm_soft_reset;
f7c35abe 617 bool prt_warning;
916910ad 618 uint64_t stolen_size;
8fe73328
JZ		 619 /* apertures */
620 u64 shared_aperture_start;
621 u64 shared_aperture_end;
622 u64 private_aperture_start;
623 u64 private_aperture_end;
e60f8db5
AX		 624 /* protects concurrent invalidation */
625 spinlock_t invalidate_lock;
97b2e202
AD		 626};
627
628/*
629 * GPU doorbell structures, functions & helpers
630 */
631typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
632{
633 AMDGPU_DOORBELL_KIQ = 0x000,
634 AMDGPU_DOORBELL_HIQ = 0x001,
635 AMDGPU_DOORBELL_DIQ = 0x002,
636 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
637 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
638 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
639 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
640 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
641 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
642 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
643 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
644 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
645 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
646 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
647 AMDGPU_DOORBELL_IH = 0x1E8,
648 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
649 AMDGPU_DOORBELL_INVALID = 0xFFFF
650} AMDGPU_DOORBELL_ASSIGNMENT;
651
652struct amdgpu_doorbell {
653 /* doorbell mmio */
654 resource_size_t base;
655 resource_size_t size;
656 u32 __iomem *ptr;
657 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
658};
659
39807b93
KW		 660/*
661 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
662 */
663typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
664{
665 /*
666 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
667 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
668 * Compute related doorbells are allocated from 0x00 to 0x8a
669 */
670
671
672 /* kernel scheduling */
673 AMDGPU_DOORBELL64_KIQ = 0x00,
674
675 /* HSA interface queue and debug queue */
676 AMDGPU_DOORBELL64_HIQ = 0x01,
677 AMDGPU_DOORBELL64_DIQ = 0x02,
678
679 /* Compute engines */
680 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
681 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
682 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
683 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
684 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
685 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
686 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
687 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
688
689 /* User queue doorbell range (128 doorbells) */
690 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
691 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
692
693 /* Graphics engine */
694 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
695
696 /*
697 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
698 * Graphics voltage island aperture 1
699 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
700 */
701
702 /* sDMA engines */
703 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
704 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
705 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
706 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
707
708 /* Interrupt handler */
709 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
710 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
711 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
712
e6b3ecb4
ML		 713 /* VCN engine use 32 bits doorbell */
714 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
715 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
716 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
717 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
718
719 /* overlap the doorbell assignment with VCN as they are mutually exclusive
720 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
721 */
722 AMDGPU_DOORBELL64_RING0_1 = 0xF8,
723 AMDGPU_DOORBELL64_RING2_3 = 0xF9,
724 AMDGPU_DOORBELL64_RING4_5 = 0xFA,
725 AMDGPU_DOORBELL64_RING6_7 = 0xFB,
726
727 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
728 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
729 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
730 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
39807b93
KW		 731
732 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
733 AMDGPU_DOORBELL64_INVALID = 0xFFFF
734} AMDGPU_DOORBELL64_ASSIGNMENT;
735
736
97b2e202
AD		 737void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
738 phys_addr_t *aperture_base,
739 size_t *aperture_size,
740 size_t *start_offset);
741
742/*
743 * IRQS.
744 */
745
746struct amdgpu_flip_work {
325cbba1 747 struct delayed_work flip_work;
97b2e202
AD		 748 struct work_struct unpin_work;
749 struct amdgpu_device *adev;
750 int crtc_id;
325cbba1 751 u32 target_vblank;
97b2e202
AD		 752 uint64_t base;
753 struct drm_pending_vblank_event *event;
765e7fbf 754 struct amdgpu_bo *old_abo;
f54d1867 755 struct dma_fence *excl;
1ffd2652 756 unsigned shared_count;
f54d1867
CW		 757 struct dma_fence **shared;
758 struct dma_fence_cb cb;
cb9e59d7 759 bool async;
97b2e202
AD		 760};
761
762
763/*
764 * CP & rings.
765 */
766
767struct amdgpu_ib {
768 struct amdgpu_sa_bo *sa_bo;
769 uint32_t length_dw;
770 uint64_t gpu_addr;
771 uint32_t *ptr;
de807f81 772 uint32_t flags;
97b2e202
AD		 773};
774
62250a91 775extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 776
50838c8c 777int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 778 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 779int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
780 struct amdgpu_job **job);
b6723c8d 781
a5fb4ec2 782void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 783void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 784int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 785 struct amd_sched_entity *entity, void *owner,
f54d1867 786 struct dma_fence **f);
8b4fb00b 787
effd924d
AR		 788/*
789 * Queue manager
790 */
791struct amdgpu_queue_mapper {
792 int hw_ip;
793 struct mutex lock;
794 /* protected by lock */
795 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
796};
797
798struct amdgpu_queue_mgr {
799 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
800};
801
802int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
803 struct amdgpu_queue_mgr *mgr);
804int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
805 struct amdgpu_queue_mgr *mgr);
806int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
807 struct amdgpu_queue_mgr *mgr,
808 int hw_ip, int instance, int ring,
809 struct amdgpu_ring **out_ring);
810
97b2e202
AD		 811/*
812 * context related structures
813 */
814
21c16bf6 815struct amdgpu_ctx_ring {
91404fb2 816 uint64_t sequence;
f54d1867 817 struct dma_fence **fences;
91404fb2 818 struct amd_sched_entity entity;
21c16bf6
CK		 819};
820
97b2e202 821struct amdgpu_ctx {
0b492a4c 822 struct kref refcount;
9cb7e5a9 823 struct amdgpu_device *adev;
effd924d 824 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 825 unsigned reset_counter;
21c16bf6 826 spinlock_t ring_lock;
f54d1867 827 struct dma_fence **fences;
21c16bf6 828 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
753ad49c 829 bool preamble_presented;
97b2e202
AD		 830};
831
832struct amdgpu_ctx_mgr {
0b492a4c
AD		 833 struct amdgpu_device *adev;
834 struct mutex lock;
835 /* protected by lock */
836 struct idr ctx_handles;
97b2e202
AD		 837};
838
0b492a4c
AD		 839struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
840int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
841
21c16bf6 842uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
f54d1867
CW		 843 struct dma_fence *fence);
844struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6
CK		 845 struct amdgpu_ring *ring, uint64_t seq);
846
0b492a4c
AD		 847int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
848 struct drm_file *filp);
849
efd4ccb5
CK		 850void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
851void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 852
97b2e202
AD		 853/*
854 * file private structure
855 */
856
857struct amdgpu_fpriv {
858 struct amdgpu_vm vm;
b85891bd 859 struct amdgpu_bo_va *prt_va;
97b2e202
AD		 860 struct mutex bo_list_lock;
861 struct idr bo_list_handles;
0b492a4c 862 struct amdgpu_ctx_mgr ctx_mgr;
f1892138 863 u32 vram_lost_counter;
97b2e202
AD		 864};
865
866/*
867 * residency list
868 */
869
870struct amdgpu_bo_list {
871 struct mutex lock;
5ac55629
AX		 872 struct rcu_head rhead;
873 struct kref refcount;
97b2e202
AD		 874 struct amdgpu_bo *gds_obj;
875 struct amdgpu_bo *gws_obj;
876 struct amdgpu_bo *oa_obj;
211dff55 877 unsigned first_userptr;
97b2e202
AD		 878 unsigned num_entries;
879 struct amdgpu_bo_list_entry *array;
880};
881
882struct amdgpu_bo_list *
883amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 884void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
885 struct list_head *validated);
97b2e202
AD		 886void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
887void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
888
889/*
890 * GFX stuff
891 */
892#include "clearstate_defs.h"
893
79e5412c
AD		 894struct amdgpu_rlc_funcs {
895 void (*enter_safe_mode)(struct amdgpu_device *adev);
896 void (*exit_safe_mode)(struct amdgpu_device *adev);
897};
898
97b2e202
AD		 899struct amdgpu_rlc {
900 /* for power gating */
901 struct amdgpu_bo *save_restore_obj;
902 uint64_t save_restore_gpu_addr;
903 volatile uint32_t *sr_ptr;
904 const u32 *reg_list;
905 u32 reg_list_size;
906 /* for clear state */
907 struct amdgpu_bo *clear_state_obj;
908 uint64_t clear_state_gpu_addr;
909 volatile uint32_t *cs_ptr;
910 const struct cs_section_def *cs_data;
911 u32 clear_state_size;
912 /* for cp tables */
913 struct amdgpu_bo *cp_table_obj;
914 uint64_t cp_table_gpu_addr;
915 volatile uint32_t *cp_table_ptr;
916 u32 cp_table_size;
79e5412c
AD		 917
918 /* safe mode for updating CG/PG state */
919 bool in_safe_mode;
920 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 921
922 /* for firmware data */
923 u32 save_and_restore_offset;
924 u32 clear_state_descriptor_offset;
925 u32 avail_scratch_ram_locations;
926 u32 reg_restore_list_size;
927 u32 reg_list_format_start;
928 u32 reg_list_format_separate_start;
929 u32 starting_offsets_start;
930 u32 reg_list_format_size_bytes;
931 u32 reg_list_size_bytes;
932
933 u32 *register_list_format;
934 u32 *register_restore;
97b2e202
AD		 935};
936
78c16834
AR		 937#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
938
97b2e202
AD		 939struct amdgpu_mec {
940 struct amdgpu_bo *hpd_eop_obj;
941 u64 hpd_eop_gpu_addr;
b1023571
KW		 942 struct amdgpu_bo *mec_fw_obj;
943 u64 mec_fw_gpu_addr;
97b2e202 944 u32 num_mec;
42794b27
AR		 945 u32 num_pipe_per_mec;
946 u32 num_queue_per_pipe;
59a82d7d 947 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 948
949 /* These are the resources for which amdgpu takes ownership */
950 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 951};
952
4e638ae9
XY		 953struct amdgpu_kiq {
954 u64 eop_gpu_addr;
955 struct amdgpu_bo *eop_obj;
cdf6adb2 956 struct mutex ring_mutex;
4e638ae9
XY		 957 struct amdgpu_ring ring;
958 struct amdgpu_irq_src irq;
959};
960
97b2e202
AD		 961/*
962 * GPU scratch registers structures, functions & helpers
963 */
964struct amdgpu_scratch {
965 unsigned num_reg;
966 uint32_t reg_base;
50261151 967 uint32_t free_mask;
97b2e202
AD		 968};
969
970/*
971 * GFX configurations
972 */
e3fa7630
AD		 973#define AMDGPU_GFX_MAX_SE 4
974#define AMDGPU_GFX_MAX_SH_PER_SE 2
975
976struct amdgpu_rb_config {
977 uint32_t rb_backend_disable;
978 uint32_t user_rb_backend_disable;
979 uint32_t raster_config;
980 uint32_t raster_config_1;
981};
982
d0e95758
AG		 983struct gb_addr_config {
984 uint16_t pipe_interleave_size;
985 uint8_t num_pipes;
986 uint8_t max_compress_frags;
987 uint8_t num_banks;
988 uint8_t num_se;
989 uint8_t num_rb_per_se;
990};
991
ea323f88 992struct amdgpu_gfx_config {
97b2e202
AD		 993 unsigned max_shader_engines;
994 unsigned max_tile_pipes;
995 unsigned max_cu_per_sh;
996 unsigned max_sh_per_se;
997 unsigned max_backends_per_se;
998 unsigned max_texture_channel_caches;
999 unsigned max_gprs;
1000 unsigned max_gs_threads;
1001 unsigned max_hw_contexts;
1002 unsigned sc_prim_fifo_size_frontend;
1003 unsigned sc_prim_fifo_size_backend;
1004 unsigned sc_hiz_tile_fifo_size;
1005 unsigned sc_earlyz_tile_fifo_size;
1006
1007 unsigned num_tile_pipes;
1008 unsigned backend_enable_mask;
1009 unsigned mem_max_burst_length_bytes;
1010 unsigned mem_row_size_in_kb;
1011 unsigned shader_engine_tile_size;
1012 unsigned num_gpus;
1013 unsigned multi_gpu_tile_size;
1014 unsigned mc_arb_ramcfg;
1015 unsigned gb_addr_config;
8f8e00c1 1016 unsigned num_rbs;
408bfe7c
JZ		 1017 unsigned gs_vgt_table_depth;
1018 unsigned gs_prim_buffer_depth;
97b2e202
AD		 1019
1020 uint32_t tile_mode_array[32];
1021 uint32_t macrotile_mode_array[16];
e3fa7630 1022
d0e95758 1023 struct gb_addr_config gb_addr_config_fields;
e3fa7630 1024 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 1025
1026 /* gfx configure feature */
1027 uint32_t double_offchip_lds_buf;
97b2e202
AD		 1028};
1029
7dae69a2 1030struct amdgpu_cu_info {
51fd0370 1031 uint32_t max_waves_per_simd;
408bfe7c 1032 uint32_t wave_front_size;
51fd0370
HZ		 1033 uint32_t max_scratch_slots_per_cu;
1034 uint32_t lds_size;
dbfe85ea
FC		 1035
1036 /* total active CU number */
1037 uint32_t number;
1038 uint32_t ao_cu_mask;
1039 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 1040 uint32_t bitmap[4][4];
1041};
1042
b95e31fd
AD		 1043struct amdgpu_gfx_funcs {
1044 /* get the gpu clock counter */
1045 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 1046 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 1047 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 1048 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
1049 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 1050};
1051
bce23e00
AD		 1052struct amdgpu_ngg_buf {
1053 struct amdgpu_bo *bo;
1054 uint64_t gpu_addr;
1055 uint32_t size;
1056 uint32_t bo_size;
1057};
1058
1059enum {
af8baf15
GR		 1060 NGG_PRIM = 0,
1061 NGG_POS,
1062 NGG_CNTL,
1063 NGG_PARAM,
bce23e00
AD		 1064 NGG_BUF_MAX
1065};
1066
1067struct amdgpu_ngg {
1068 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1069 uint32_t gds_reserve_addr;
1070 uint32_t gds_reserve_size;
1071 bool init;
1072};
1073
97b2e202
AD		 1074struct amdgpu_gfx {
1075 struct mutex gpu_clock_mutex;
ea323f88 1076 struct amdgpu_gfx_config config;
97b2e202
AD		 1077 struct amdgpu_rlc rlc;
1078 struct amdgpu_mec mec;
4e638ae9 1079 struct amdgpu_kiq kiq;
97b2e202
AD		 1080 struct amdgpu_scratch scratch;
1081 const struct firmware *me_fw; /* ME firmware */
1082 uint32_t me_fw_version;
1083 const struct firmware *pfp_fw; /* PFP firmware */
1084 uint32_t pfp_fw_version;
1085 const struct firmware *ce_fw; /* CE firmware */
1086 uint32_t ce_fw_version;
1087 const struct firmware *rlc_fw; /* RLC firmware */
1088 uint32_t rlc_fw_version;
1089 const struct firmware *mec_fw; /* MEC firmware */
1090 uint32_t mec_fw_version;
1091 const struct firmware *mec2_fw; /* MEC2 firmware */
1092 uint32_t mec2_fw_version;
02558a00
KW		 1093 uint32_t me_feature_version;
1094 uint32_t ce_feature_version;
1095 uint32_t pfp_feature_version;
351643d7
JZ		 1096 uint32_t rlc_feature_version;
1097 uint32_t mec_feature_version;
1098 uint32_t mec2_feature_version;
97b2e202
AD		 1099 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1100 unsigned num_gfx_rings;
1101 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1102 unsigned num_compute_rings;
1103 struct amdgpu_irq_src eop_irq;
1104 struct amdgpu_irq_src priv_reg_irq;
1105 struct amdgpu_irq_src priv_inst_irq;
1106 /* gfx status */
7dae69a2 1107 uint32_t gfx_current_status;
a101a899 1108 /* ce ram size*/
7dae69a2
AD		 1109 unsigned ce_ram_size;
1110 struct amdgpu_cu_info cu_info;
b95e31fd 1111 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1112
1113 /* reset mask */
1114 uint32_t grbm_soft_reset;
1115 uint32_t srbm_soft_reset;
223049cd 1116 bool in_reset;
b4e40676
DP		 1117 /* s3/s4 mask */
1118 bool in_suspend;
bce23e00
AD		 1119 /* NGG */
1120 struct amdgpu_ngg ngg;
97b2e202
AD		 1121};
1122
b07c60c0 1123int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1124 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1125void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1126 struct dma_fence *f);
b07c60c0 1127int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1128 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1129 struct dma_fence **f);
97b2e202
AD		 1130int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1131void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1132int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1133
1134/*
1135 * CS.
1136 */
1137struct amdgpu_cs_chunk {
1138 uint32_t chunk_id;
1139 uint32_t length_dw;
758ac17f 1140 void *kdata;
97b2e202
AD		 1141};
1142
1143struct amdgpu_cs_parser {
1144 struct amdgpu_device *adev;
1145 struct drm_file *filp;
3cb485f3 1146 struct amdgpu_ctx *ctx;
c3cca41e 1147
97b2e202
AD		 1148 /* chunks */
1149 unsigned nchunks;
1150 struct amdgpu_cs_chunk *chunks;
97b2e202 1151
50838c8c
CK		 1152 /* scheduler job object */
1153 struct amdgpu_job *job;
97b2e202 1154
c3cca41e
CK		 1155 /* buffer objects */
1156 struct ww_acquire_ctx ticket;
1157 struct amdgpu_bo_list *bo_list;
1158 struct amdgpu_bo_list_entry vm_pd;
1159 struct list_head validated;
f54d1867 1160 struct dma_fence *fence;
c3cca41e
CK		 1161 uint64_t bytes_moved_threshold;
1162 uint64_t bytes_moved;
662bfa61 1163 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1164
1165 /* user fence */
91acbeb6 1166 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1167
1168 unsigned num_post_dep_syncobjs;
1169 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1170};
1171
753ad49c
ML		 1172#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1173#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1174#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1175
bb977d37
CZ		 1176struct amdgpu_job {
1177 struct amd_sched_job base;
1178 struct amdgpu_device *adev;
edf600da 1179 struct amdgpu_vm *vm;
b07c60c0 1180 struct amdgpu_ring *ring;
e86f9cee 1181 struct amdgpu_sync sync;
a340c7bc 1182 struct amdgpu_sync dep_sync;
df83d1eb 1183 struct amdgpu_sync sched_sync;
bb977d37 1184 struct amdgpu_ib *ibs;
f54d1867 1185 struct dma_fence *fence; /* the hw fence */
753ad49c 1186 uint32_t preamble_status;
bb977d37 1187 uint32_t num_ibs;
e2840221 1188 void *owner;
3aecd24c 1189 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1190 bool vm_needs_flush;
d88bf583
CK		 1191 unsigned vm_id;
1192 uint64_t vm_pd_addr;
1193 uint32_t gds_base, gds_size;
1194 uint32_t gws_base, gws_size;
1195 uint32_t oa_base, oa_size;
758ac17f
CK		 1196
1197 /* user fence handling */
b5f5acbc 1198 uint64_t uf_addr;
758ac17f
CK		 1199 uint64_t uf_sequence;
1200
bb977d37 1201};
a6db8a33
JZ		 1202#define to_amdgpu_job(sched_job) \
1203 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1204
7270f839
CK		 1205static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1206 uint32_t ib_idx, int idx)
97b2e202 1207{
50838c8c 1208 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1209}
1210
7270f839
CK		 1211static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1212 uint32_t ib_idx, int idx,
1213 uint32_t value)
1214{
50838c8c 1215 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1216}
1217
97b2e202
AD		 1218/*
1219 * Writeback
1220 */
1221#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1222
1223struct amdgpu_wb {
1224 struct amdgpu_bo *wb_obj;
1225 volatile uint32_t *wb;
1226 uint64_t gpu_addr;
1227 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1228 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1229};
1230
1231int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1232void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
7014285a
KW		 1233int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1234void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
97b2e202 1235
d0dd7f0c
AD		 1236void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1237
97b2e202
AD		 1238/*
1239 * SDMA
1240 */
c113ea1c 1241struct amdgpu_sdma_instance {
97b2e202
AD		 1242 /* SDMA firmware */
1243 const struct firmware *fw;
1244 uint32_t fw_version;
cfa2104f 1245 uint32_t feature_version;
97b2e202
AD		 1246
1247 struct amdgpu_ring ring;
18111de0 1248 bool burst_nop;
97b2e202
AD		 1249};
1250
c113ea1c
AD		 1251struct amdgpu_sdma {
1252 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1253#ifdef CONFIG_DRM_AMDGPU_SI
1254 //SI DMA has a difference trap irq number for the second engine
1255 struct amdgpu_irq_src trap_irq_1;
1256#endif
c113ea1c
AD		 1257 struct amdgpu_irq_src trap_irq;
1258 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1259 int num_instances;
e702a680 1260 uint32_t srbm_soft_reset;
c113ea1c
AD		 1261};
1262
97b2e202
AD		 1263/*
1264 * Firmware
1265 */
e635ee07
HR		 1266enum amdgpu_firmware_load_type {
1267 AMDGPU_FW_LOAD_DIRECT = 0,
1268 AMDGPU_FW_LOAD_SMU,
1269 AMDGPU_FW_LOAD_PSP,
1270};
1271
97b2e202
AD		 1272struct amdgpu_firmware {
1273 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1274 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1275 struct amdgpu_bo *fw_buf;
1276 unsigned int fw_size;
2445b227 1277 unsigned int max_ucodes;
0e5ca0d1
HR		 1278 /* firmwares are loaded by psp instead of smu from vega10 */
1279 const struct amdgpu_psp_funcs *funcs;
1280 struct amdgpu_bo *rbuf;
1281 struct mutex mutex;
ab4fe3e1
HR		 1282
1283 /* gpu info firmware data pointer */
1284 const struct firmware *gpu_info_fw;
97b2e202
AD		 1285};
1286
1287/*
1288 * Benchmarking
1289 */
1290void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1291
1292
1293/*
1294 * Testing
1295 */
1296void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202
AD		 1297
1298/*
1299 * MMU Notifier
1300 */
1301#if defined(CONFIG_MMU_NOTIFIER)
1302int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1303void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1304#else
1d1106b0 1305static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1306{
1307 return -ENODEV;
1308}
1d1106b0 1309static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1310#endif
1311
1312/*
1313 * Debugfs
1314 */
1315struct amdgpu_debugfs {
06ab6832 1316 const struct drm_info_list *files;
97b2e202
AD		 1317 unsigned num_files;
1318};
1319
1320int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1321 const struct drm_info_list *files,
97b2e202
AD		 1322 unsigned nfiles);
1323int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1324
1325#if defined(CONFIG_DEBUG_FS)
1326int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1327#endif
1328
50ab2533
HR		 1329int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1330
97b2e202
AD		 1331/*
1332 * amdgpu smumgr functions
1333 */
1334struct amdgpu_smumgr_funcs {
1335 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1336 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1337 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1338};
1339
1340/*
1341 * amdgpu smumgr
1342 */
1343struct amdgpu_smumgr {
1344 struct amdgpu_bo *toc_buf;
1345 struct amdgpu_bo *smu_buf;
1346 /* asic priv smu data */
1347 void *priv;
1348 spinlock_t smu_lock;
1349 /* smumgr functions */
1350 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1351 /* ucode loading complete flag */
1352 uint32_t fw_flags;
1353};
1354
1355/*
1356 * ASIC specific register table accessible by UMD
1357 */
1358struct amdgpu_allowed_register_entry {
1359 uint32_t reg_offset;
97b2e202
AD		 1360 bool grbm_indexed;
1361};
1362
97b2e202
AD		 1363/*
1364 * ASIC specific functions.
1365 */
1366struct amdgpu_asic_funcs {
1367 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1368 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1369 u8 *bios, u32 length_bytes);
97b2e202
AD		 1370 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1371 u32 sh_num, u32 reg_offset, u32 *value);
1372 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1373 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1374 /* get the reference clock */
1375 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1376 /* MM block clocks */
1377 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1378 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1379 /* static power management */
1380 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1381 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1382 /* get config memsize register */
1383 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1384};
1385
1386/*
1387 * IOCTL.
1388 */
1389int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1390 struct drm_file *filp);
1391int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *filp);
1393
1394int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *filp);
1396int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1397 struct drm_file *filp);
1398int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1399 struct drm_file *filp);
1400int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1401 struct drm_file *filp);
1402int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1403 struct drm_file *filp);
1404int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1405 struct drm_file *filp);
1406int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1407int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1408int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1409 struct drm_file *filp);
97b2e202
AD		 1410
1411int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *filp);
1413
1414/* VRAM scratch page for HDP bug, default vram page */
1415struct amdgpu_vram_scratch {
1416 struct amdgpu_bo *robj;
1417 volatile uint32_t *ptr;
1418 u64 gpu_addr;
1419};
1420
1421/*
1422 * ACPI
1423 */
1424struct amdgpu_atif_notification_cfg {
1425 bool enabled;
1426 int command_code;
1427};
1428
1429struct amdgpu_atif_notifications {
1430 bool display_switch;
1431 bool expansion_mode_change;
1432 bool thermal_state;
1433 bool forced_power_state;
1434 bool system_power_state;
1435 bool display_conf_change;
1436 bool px_gfx_switch;
1437 bool brightness_change;
1438 bool dgpu_display_event;
1439};
1440
1441struct amdgpu_atif_functions {
1442 bool system_params;
1443 bool sbios_requests;
1444 bool select_active_disp;
1445 bool lid_state;
1446 bool get_tv_standard;
1447 bool set_tv_standard;
1448 bool get_panel_expansion_mode;
1449 bool set_panel_expansion_mode;
1450 bool temperature_change;
1451 bool graphics_device_types;
1452};
1453
1454struct amdgpu_atif {
1455 struct amdgpu_atif_notifications notifications;
1456 struct amdgpu_atif_functions functions;
1457 struct amdgpu_atif_notification_cfg notification_cfg;
1458 struct amdgpu_encoder *encoder_for_bl;
1459};
1460
1461struct amdgpu_atcs_functions {
1462 bool get_ext_state;
1463 bool pcie_perf_req;
1464 bool pcie_dev_rdy;
1465 bool pcie_bus_width;
1466};
1467
1468struct amdgpu_atcs {
1469 struct amdgpu_atcs_functions functions;
1470};
1471
d03846af
CZ		 1472/*
1473 * CGS
1474 */
110e6f26
DA		 1475struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1476void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1477
97b2e202
AD		 1478/*
1479 * Core structure, functions and helpers.
1480 */
1481typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1482typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1483
1484typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1485typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1486
0c49e0b8 1487#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1488struct amdgpu_device {
1489 struct device *dev;
1490 struct drm_device *ddev;
1491 struct pci_dev *pdev;
97b2e202 1492
a8fe58ce
MB		 1493#ifdef CONFIG_DRM_AMD_ACP
1494 struct amdgpu_acp acp;
1495#endif
1496
97b2e202 1497 /* ASIC */
2f7d10b3 1498 enum amd_asic_type asic_type;
97b2e202
AD		 1499 uint32_t family;
1500 uint32_t rev_id;
1501 uint32_t external_rev_id;
1502 unsigned long flags;
1503 int usec_timeout;
1504 const struct amdgpu_asic_funcs *asic_funcs;
1505 bool shutdown;
97b2e202
AD		 1506 bool need_dma32;
1507 bool accel_working;
edf600da 1508 struct work_struct reset_work;
97b2e202
AD		 1509 struct notifier_block acpi_nb;
1510 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1511 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1512 unsigned debugfs_count;
97b2e202 1513#if defined(CONFIG_DEBUG_FS)
adcec288 1514 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1515#endif
1516 struct amdgpu_atif atif;
1517 struct amdgpu_atcs atcs;
1518 struct mutex srbm_mutex;
1519 /* GRBM index mutex. Protects concurrent access to GRBM index */
1520 struct mutex grbm_idx_mutex;
1521 struct dev_pm_domain vga_pm_domain;
1522 bool have_disp_power_ref;
1523
1524 /* BIOS */
0cdd5005 1525 bool is_atom_fw;
97b2e202 1526 uint8_t *bios;
a9f5db9c 1527 uint32_t bios_size;
97b2e202 1528 struct amdgpu_bo *stollen_vga_memory;
a5bde2f9 1529 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1530 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1531
1532 /* Register/doorbell mmio */
1533 resource_size_t rmmio_base;
1534 resource_size_t rmmio_size;
1535 void __iomem *rmmio;
1536 /* protects concurrent MM_INDEX/DATA based register access */
1537 spinlock_t mmio_idx_lock;
1538 /* protects concurrent SMC based register access */
1539 spinlock_t smc_idx_lock;
1540 amdgpu_rreg_t smc_rreg;
1541 amdgpu_wreg_t smc_wreg;
1542 /* protects concurrent PCIE register access */
1543 spinlock_t pcie_idx_lock;
1544 amdgpu_rreg_t pcie_rreg;
1545 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1546 amdgpu_rreg_t pciep_rreg;
1547 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1548 /* protects concurrent UVD register access */
1549 spinlock_t uvd_ctx_idx_lock;
1550 amdgpu_rreg_t uvd_ctx_rreg;
1551 amdgpu_wreg_t uvd_ctx_wreg;
1552 /* protects concurrent DIDT register access */
1553 spinlock_t didt_idx_lock;
1554 amdgpu_rreg_t didt_rreg;
1555 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1556 /* protects concurrent gc_cac register access */
1557 spinlock_t gc_cac_idx_lock;
1558 amdgpu_rreg_t gc_cac_rreg;
1559 amdgpu_wreg_t gc_cac_wreg;
97b2e202
AD		 1560 /* protects concurrent ENDPOINT (audio) register access */
1561 spinlock_t audio_endpt_idx_lock;
1562 amdgpu_block_rreg_t audio_endpt_rreg;
1563 amdgpu_block_wreg_t audio_endpt_wreg;
1564 void __iomem *rio_mem;
1565 resource_size_t rio_mem_size;
1566 struct amdgpu_doorbell doorbell;
1567
1568 /* clock/pll info */
1569 struct amdgpu_clock clock;
1570
1571 /* MC */
1572 struct amdgpu_mc mc;
1573 struct amdgpu_gart gart;
1574 struct amdgpu_dummy_page dummy_page;
1575 struct amdgpu_vm_manager vm_manager;
e60f8db5 1576 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1577
1578 /* memory management */
1579 struct amdgpu_mman mman;
97b2e202
AD		 1580 struct amdgpu_vram_scratch vram_scratch;
1581 struct amdgpu_wb wb;
1582 atomic64_t vram_usage;
1583 atomic64_t vram_vis_usage;
1584 atomic64_t gtt_usage;
1585 atomic64_t num_bytes_moved;
dbd5ed60 1586 atomic64_t num_evictions;
68e2c5ff 1587 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1588 atomic_t gpu_reset_counter;
f1892138 1589 atomic_t vram_lost_counter;
97b2e202 1590
95844d20
MO		 1591 /* data for buffer migration throttling */
1592 struct {
1593 spinlock_t lock;
1594 s64 last_update_us;
1595 s64 accum_us; /* accumulated microseconds */
1596 u32 log2_max_MBps;
1597 } mm_stats;
1598
97b2e202 1599 /* display */
9accf2fd 1600 bool enable_virtual_display;
97b2e202
AD		 1601 struct amdgpu_mode_info mode_info;
1602 struct work_struct hotplug_work;
1603 struct amdgpu_irq_src crtc_irq;
1604 struct amdgpu_irq_src pageflip_irq;
1605 struct amdgpu_irq_src hpd_irq;
1606
1607 /* rings */
76bf0db5 1608 u64 fence_context;
97b2e202
AD		 1609 unsigned num_rings;
1610 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1611 bool ib_pool_ready;
1612 struct amdgpu_sa_manager ring_tmp_bo;
1613
1614 /* interrupts */
1615 struct amdgpu_irq irq;
1616
1f7371b2
AD		 1617 /* powerplay */
1618 struct amd_powerplay powerplay;
e61710c5 1619 bool pp_enabled;
f3898ea1 1620 bool pp_force_state_enabled;
1f7371b2 1621
97b2e202
AD		 1622 /* dpm */
1623 struct amdgpu_pm pm;
1624 u32 cg_flags;
1625 u32 pg_flags;
1626
1627 /* amdgpu smumgr */
1628 struct amdgpu_smumgr smu;
1629
1630 /* gfx */
1631 struct amdgpu_gfx gfx;
1632
1633 /* sdma */
c113ea1c 1634 struct amdgpu_sdma sdma;
97b2e202 1635
95d0906f
LL		 1636 union {
1637 struct {
1638 /* uvd */
1639 struct amdgpu_uvd uvd;
1640
1641 /* vce */
1642 struct amdgpu_vce vce;
1643 };
97b2e202 1644
95d0906f
LL		 1645 /* vcn */
1646 struct amdgpu_vcn vcn;
1647 };
97b2e202
AD		 1648
1649 /* firmwares */
1650 struct amdgpu_firmware firmware;
1651
0e5ca0d1
HR		 1652 /* PSP */
1653 struct psp_context psp;
1654
97b2e202
AD		 1655 /* GDS */
1656 struct amdgpu_gds gds;
1657
a1255107 1658 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1659 int num_ip_blocks;
97b2e202
AD		 1660 struct mutex mn_lock;
1661 DECLARE_HASHTABLE(mn_hash, 7);
1662
1663 /* tracking pinned memory */
1664 u64 vram_pin_size;
e131b914 1665 u64 invisible_pin_size;
97b2e202 1666 u64 gart_pin_size;
130e0371
OG		 1667
1668 /* amdkfd interface */
1669 struct kfd_dev *kfd;
23ca0e4e 1670
2dc80b00
S		 1671 /* delayed work_func for deferring clockgating during resume */
1672 struct delayed_work late_init_work;
1673
5a5099cb 1674 struct amdgpu_virt virt;
0c4e7fa5
CZ		 1675
1676 /* link all shadow bo */
1677 struct list_head shadow_list;
1678 struct mutex shadow_list_lock;
5c1354bd
CZ		 1679 /* link all gtt */
1680 spinlock_t gtt_list_lock;
1681 struct list_head gtt_list;
795f2813
AR		 1682 /* keep an lru list of rings by HW IP */
1683 struct list_head ring_lru_list;
1684 spinlock_t ring_lru_list_lock;
5c1354bd 1685
c836fec5
JQ		 1686 /* record hw reset is performed */
1687 bool has_hw_reset;
0c49e0b8 1688 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1689
97b2e202
AD		 1690};
1691
a7d64de6
CK		 1692static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1693{
1694 return container_of(bdev, struct amdgpu_device, mman.bdev);
1695}
1696
97b2e202
AD		 1697int amdgpu_device_init(struct amdgpu_device *adev,
1698 struct drm_device *ddev,
1699 struct pci_dev *pdev,
1700 uint32_t flags);
1701void amdgpu_device_fini(struct amdgpu_device *adev);
1702int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1703
1704uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1705 uint32_t acc_flags);
97b2e202 1706void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1707 uint32_t acc_flags);
97b2e202
AD		 1708u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1709void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1710
1711u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1712void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1713u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1714void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1715
97b2e202
AD		 1716/*
1717 * Registers read & write functions.
1718 */
15d72fd7
ML		 1719
1720#define AMDGPU_REGS_IDX (1<<0)
1721#define AMDGPU_REGS_NO_KIQ (1<<1)
1722
1723#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1724#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1725
1726#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1727#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1728#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1729#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1730#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1731#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1732#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1733#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1734#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1735#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1736#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1737#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1738#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1739#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1740#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1741#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1742#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1743#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1744#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1745#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1746#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1747#define WREG32_P(reg, val, mask) \
1748 do { \
1749 uint32_t tmp_ = RREG32(reg); \
1750 tmp_ &= (mask); \
1751 tmp_ |= ((val) & ~(mask)); \
1752 WREG32(reg, tmp_); \
1753 } while (0)
1754#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1755#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1756#define WREG32_PLL_P(reg, val, mask) \
1757 do { \
1758 uint32_t tmp_ = RREG32_PLL(reg); \
1759 tmp_ &= (mask); \
1760 tmp_ |= ((val) & ~(mask)); \
1761 WREG32_PLL(reg, tmp_); \
1762 } while (0)
1763#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1764#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1765#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1766
1767#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1768#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1769#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1770#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1771
1772#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1773#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1774
1775#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1776 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1777 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1778
1779#define REG_GET_FIELD(value, reg, field) \
1780 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1781
1782#define WREG32_FIELD(reg, field, val) \
1783 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1784
ccaf3574
TSD		 1785#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1786 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1787
97b2e202
AD		 1788/*
1789 * BIOS helpers.
1790 */
1791#define RBIOS8(i) (adev->bios[i])
1792#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1793#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1794
c113ea1c
AD		 1795static inline struct amdgpu_sdma_instance *
1796amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1797{
1798 struct amdgpu_device *adev = ring->adev;
1799 int i;
1800
c113ea1c
AD		 1801 for (i = 0; i < adev->sdma.num_instances; i++)
1802 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1803 break;
1804
1805 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1806 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1807 else
1808 return NULL;
1809}
1810
97b2e202
AD		 1811/*
1812 * ASICs macro.
1813 */
1814#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1815#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1816#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1817#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1818#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1819#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1820#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1821#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1822#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1823#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1824#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1825#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1826#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1827#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1828#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1829#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1830#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1831#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1832#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1833#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1834#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1835#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1836#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1837#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1838#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1839#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1840#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1841#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1842#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1843#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1844#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1845#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1846#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1847#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1848#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1849#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1850#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1851#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1852#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1853#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 1854#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1855#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1856#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1857#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1858#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1859#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1860#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1861#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1862#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1863#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1864#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1865#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1866#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1867#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1868#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1869#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1870#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1871#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1872#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1873#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1874#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1875
1876/* Common functions */
1877int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1878bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1879void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1880bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1881void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1882
fad06127 1883void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
765e7fbf 1884void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1885bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 1886int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 1887int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1888 uint32_t flags);
1889bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 1890struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 1891bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1892 unsigned long end);
2f568dbd
CK		 1893bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1894 int *last_invalidated);
97b2e202 1895bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
6b777607 1896uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
97b2e202
AD		 1897 struct ttm_mem_reg *mem);
1898void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1899void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1900void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1901int amdgpu_ttm_init(struct amdgpu_device *adev);
1902void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1903void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1904 const u32 *registers,
1905 const u32 array_size);
1906
1907bool amdgpu_device_is_px(struct drm_device *dev);
1908/* atpx handler */
1909#if defined(CONFIG_VGA_SWITCHEROO)
1910void amdgpu_register_atpx_handler(void);
1911void amdgpu_unregister_atpx_handler(void);
a78fe133 1912bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1913bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1914bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1915bool amdgpu_has_atpx(void);
97b2e202
AD		 1916#else
1917static inline void amdgpu_register_atpx_handler(void) {}
1918static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1919static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1920static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1921static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1922static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1923#endif
1924
1925/*
1926 * KMS
1927 */
1928extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1929extern const int amdgpu_max_kms_ioctl;
97b2e202 1930
f1892138
CZ		 1931bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1932 struct amdgpu_fpriv *fpriv);
97b2e202 1933int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1934void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1935void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1936int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1937void amdgpu_driver_postclose_kms(struct drm_device *dev,
1938 struct drm_file *file_priv);
faefba95 1939int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1940int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1941int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1942u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1943int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1944void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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AD		 1945long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1946 unsigned long arg);
1947
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AD		 1948/*
1949 * functions used by amdgpu_encoder.c
1950 */
1951struct amdgpu_afmt_acr {
1952 u32 clock;
1953
1954 int n_32khz;
1955 int cts_32khz;
1956
1957 int n_44_1khz;
1958 int cts_44_1khz;
1959
1960 int n_48khz;
1961 int cts_48khz;
1962
1963};
1964
1965struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1966
1967/* amdgpu_acpi.c */
1968#if defined(CONFIG_ACPI)
1969int amdgpu_acpi_init(struct amdgpu_device *adev);
1970void amdgpu_acpi_fini(struct amdgpu_device *adev);
1971bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1972int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1973 u8 perf_req, bool advertise);
1974int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1975#else
1976static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1977static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1978#endif
1979
1980struct amdgpu_bo_va_mapping *
1981amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1982 uint64_t addr, struct amdgpu_bo **bo);
c855e250 1983int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
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AD		 1984
1985#include "amdgpu_object.h"
97b2e202 1986#endif
Linux 6.x block layer and io_uring tree(s)