projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/pp: Add update_avfs call when set_power_state
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
1b1f42d8 48#include <drm/gpu_scheduler.h>
97b2e202 49
78c16834 50#include <kgd_kfd_interface.h>
c79563a3
RZ		 51#include "dm_pp_interface.h"
52#include "kgd_pp_interface.h"
78c16834 53
5fc3aeeb 54#include "amd_shared.h"
97b2e202
AD		 55#include "amdgpu_mode.h"
56#include "amdgpu_ih.h"
57#include "amdgpu_irq.h"
58#include "amdgpu_ucode.h"
c632d799 59#include "amdgpu_ttm.h"
0e5ca0d1 60#include "amdgpu_psp.h"
97b2e202 61#include "amdgpu_gds.h"
56113504 62#include "amdgpu_sync.h"
78023016 63#include "amdgpu_ring.h"
073440d2 64#include "amdgpu_vm.h"
cf097881 65#include "amdgpu_dpm.h"
a8fe58ce 66#include "amdgpu_acp.h"
4df654d2 67#include "amdgpu_uvd.h"
5e568178 68#include "amdgpu_vce.h"
95aa13f6 69#include "amdgpu_vcn.h"
9a189996 70#include "amdgpu_mn.h"
770d13b1 71#include "amdgpu_gmc.h"
4562236b 72#include "amdgpu_dm.h"
ceeb50ed 73#include "amdgpu_virt.h"
3490bdb5 74#include "amdgpu_gart.h"
75758255 75#include "amdgpu_debugfs.h"
c79563a3 76
97b2e202
AD		 77/*
78 * Modules parameters.
79 */
80extern int amdgpu_modeset;
81extern int amdgpu_vram_limit;
218b5dcd 82extern int amdgpu_vis_vram_limit;
83e74db6 83extern int amdgpu_gart_size;
36d38372 84extern int amdgpu_gtt_size;
95844d20 85extern int amdgpu_moverate;
97b2e202
AD		 86extern int amdgpu_benchmarking;
87extern int amdgpu_testing;
88extern int amdgpu_audio;
89extern int amdgpu_disp_priority;
90extern int amdgpu_hw_i2c;
91extern int amdgpu_pcie_gen2;
92extern int amdgpu_msi;
93extern int amdgpu_lockup_timeout;
94extern int amdgpu_dpm;
e635ee07 95extern int amdgpu_fw_load_type;
97b2e202
AD		 96extern int amdgpu_aspm;
97extern int amdgpu_runtime_pm;
0b693f0b 98extern uint amdgpu_ip_block_mask;
97b2e202
AD		 99extern int amdgpu_bapm;
100extern int amdgpu_deep_color;
101extern int amdgpu_vm_size;
102extern int amdgpu_vm_block_size;
d07f14be 103extern int amdgpu_vm_fragment_size;
d9c13156 104extern int amdgpu_vm_fault_stop;
b495bd3a 105extern int amdgpu_vm_debug;
9a4b7d4c 106extern int amdgpu_vm_update_mode;
4562236b 107extern int amdgpu_dc;
02e749dc 108extern int amdgpu_dc_log;
1333f723 109extern int amdgpu_sched_jobs;
4afcb303 110extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 111extern int amdgpu_no_evict;
112extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 113extern uint amdgpu_pcie_gen_cap;
114extern uint amdgpu_pcie_lane_cap;
115extern uint amdgpu_cg_mask;
116extern uint amdgpu_pg_mask;
117extern uint amdgpu_sdma_phase_quantum;
6f8941a2 118extern char *amdgpu_disable_cu;
9accf2fd 119extern char *amdgpu_virtual_display;
0b693f0b 120extern uint amdgpu_pp_feature_mask;
6a7f76e7 121extern int amdgpu_vram_page_split;
bce23e00
AD		 122extern int amdgpu_ngg;
123extern int amdgpu_prim_buf_per_se;
124extern int amdgpu_pos_buf_per_se;
125extern int amdgpu_cntl_sb_buf_per_se;
126extern int amdgpu_param_buf_per_se;
65781c78 127extern int amdgpu_job_hang_limit;
e8835e0e 128extern int amdgpu_lbpw;
4a75aefe 129extern int amdgpu_compute_multipipe;
dcebf026 130extern int amdgpu_gpu_recovery;
97b2e202 131
6dd13096
FK		 132#ifdef CONFIG_DRM_AMDGPU_SI
133extern int amdgpu_si_support;
134#endif
7df28986
FK		 135#ifdef CONFIG_DRM_AMDGPU_CIK
136extern int amdgpu_cik_support;
137#endif
97b2e202 138
55ed8caf 139#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 140#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 141#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
142#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
143/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
144#define AMDGPU_IB_POOL_SIZE 16
145#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
146#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 147#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 148
36f523a7
JZ		 149/* max number of IP instances */
150#define AMDGPU_MAX_SDMA_INSTANCES 2
151
97b2e202
AD		 152/* hard reset data */
153#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
154
155/* reset flags */
156#define AMDGPU_RESET_GFX (1 << 0)
157#define AMDGPU_RESET_COMPUTE (1 << 1)
158#define AMDGPU_RESET_DMA (1 << 2)
159#define AMDGPU_RESET_CP (1 << 3)
160#define AMDGPU_RESET_GRBM (1 << 4)
161#define AMDGPU_RESET_DMA1 (1 << 5)
162#define AMDGPU_RESET_RLC (1 << 6)
163#define AMDGPU_RESET_SEM (1 << 7)
164#define AMDGPU_RESET_IH (1 << 8)
165#define AMDGPU_RESET_VMC (1 << 9)
166#define AMDGPU_RESET_MC (1 << 10)
167#define AMDGPU_RESET_DISPLAY (1 << 11)
168#define AMDGPU_RESET_UVD (1 << 12)
169#define AMDGPU_RESET_VCE (1 << 13)
170#define AMDGPU_RESET_VCE1 (1 << 14)
171
97b2e202
AD		 172/* GFX current status */
173#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
174#define AMDGPU_GFX_SAFE_MODE 0x00000001L
175#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
176#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
177#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
178
179/* max cursor sizes (in pixels) */
180#define CIK_CURSOR_WIDTH 128
181#define CIK_CURSOR_HEIGHT 128
182
5740682e
ML		 183/* GPU RESET flags */
184#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0)
185#define AMDGPU_RESET_INFO_FULLRESET (1 << 1)
186
97b2e202 187struct amdgpu_device;
97b2e202 188struct amdgpu_ib;
97b2e202 189struct amdgpu_cs_parser;
bb977d37 190struct amdgpu_job;
97b2e202 191struct amdgpu_irq_src;
0b492a4c 192struct amdgpu_fpriv;
9cca0b8e 193struct amdgpu_bo_va_mapping;
97b2e202
AD		 194
195enum amdgpu_cp_irq {
196 AMDGPU_CP_IRQ_GFX_EOP = 0,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
205
206 AMDGPU_CP_IRQ_LAST
207};
208
209enum amdgpu_sdma_irq {
210 AMDGPU_SDMA_IRQ_TRAP0 = 0,
211 AMDGPU_SDMA_IRQ_TRAP1,
212
213 AMDGPU_SDMA_IRQ_LAST
214};
215
216enum amdgpu_thermal_irq {
217 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
218 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
219
220 AMDGPU_THERMAL_IRQ_LAST
221};
222
4e638ae9
XY		 223enum amdgpu_kiq_irq {
224 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
225 AMDGPU_CP_KIQ_IRQ_LAST
226};
227
2990a1fc
AD		 228int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
229 enum amd_ip_block_type block_type,
230 enum amd_clockgating_state state);
231int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
232 enum amd_ip_block_type block_type,
233 enum amd_powergating_state state);
234void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
235 u32 *flags);
236int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
237 enum amd_ip_block_type block_type);
238bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
239 enum amd_ip_block_type block_type);
97b2e202 240
a1255107
AD		 241#define AMDGPU_MAX_IP_NUM 16
242
243struct amdgpu_ip_block_status {
244 bool valid;
245 bool sw;
246 bool hw;
247 bool late_initialized;
248 bool hang;
249};
250
97b2e202 251struct amdgpu_ip_block_version {
a1255107
AD		 252 const enum amd_ip_block_type type;
253 const u32 major;
254 const u32 minor;
255 const u32 rev;
5fc3aeeb 256 const struct amd_ip_funcs *funcs;
97b2e202
AD		 257};
258
a1255107
AD		 259struct amdgpu_ip_block {
260 struct amdgpu_ip_block_status status;
261 const struct amdgpu_ip_block_version *version;
262};
263
2990a1fc
AD		 264int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
265 enum amd_ip_block_type type,
266 u32 major, u32 minor);
97b2e202 267
2990a1fc
AD		 268struct amdgpu_ip_block *
269amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
270 enum amd_ip_block_type type);
a1255107 271
2990a1fc
AD		 272int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
273 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 274
275/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
276struct amdgpu_buffer_funcs {
277 /* maximum bytes in a single operation */
278 uint32_t copy_max_bytes;
279
280 /* number of dw to reserve per operation */
281 unsigned copy_num_dw;
282
283 /* used for buffer migration */
c7ae72c0 284 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 285 /* src addr in bytes */
286 uint64_t src_offset,
287 /* dst addr in bytes */
288 uint64_t dst_offset,
289 /* number of byte to transfer */
290 uint32_t byte_count);
291
292 /* maximum bytes in a single operation */
293 uint32_t fill_max_bytes;
294
295 /* number of dw to reserve per operation */
296 unsigned fill_num_dw;
297
298 /* used for buffer clearing */
6e7a3840 299 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 300 /* value to write to memory */
301 uint32_t src_data,
302 /* dst addr in bytes */
303 uint64_t dst_offset,
304 /* number of byte to fill */
305 uint32_t byte_count);
306};
307
308/* provided by hw blocks that can write ptes, e.g., sdma */
309struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 310 /* number of dw to reserve per operation */
311 unsigned copy_pte_num_dw;
312
97b2e202
AD		 313 /* copy pte entries from GART */
314 void (*copy_pte)(struct amdgpu_ib *ib,
315 uint64_t pe, uint64_t src,
316 unsigned count);
e6d92197 317
97b2e202 318 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 319 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
320 uint64_t value, unsigned count,
321 uint32_t incr);
7bdc53f9
YZ		 322
323 /* maximum nums of PTEs/PDEs in a single operation */
324 uint32_t set_max_nums_pte_pde;
325
326 /* number of dw to reserve per operation */
327 unsigned set_pte_pde_num_dw;
328
97b2e202
AD		 329 /* for linear pte/pde updates without addr mapping */
330 void (*set_pte_pde)(struct amdgpu_ib *ib,
331 uint64_t pe,
332 uint64_t addr, unsigned count,
6b777607 333 uint32_t incr, uint64_t flags);
97b2e202
AD		 334};
335
97b2e202
AD		 336/* provided by the ih block */
337struct amdgpu_ih_funcs {
338 /* ring read/write ptr handling, called from interrupt context */
339 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 340 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 341 void (*decode_iv)(struct amdgpu_device *adev,
342 struct amdgpu_iv_entry *entry);
343 void (*set_rptr)(struct amdgpu_device *adev);
344};
345
97b2e202
AD		 346/*
347 * BIOS.
348 */
349bool amdgpu_get_bios(struct amdgpu_device *adev);
350bool amdgpu_read_bios(struct amdgpu_device *adev);
351
352/*
353 * Dummy page
354 */
355struct amdgpu_dummy_page {
356 struct page *page;
357 dma_addr_t addr;
358};
97b2e202
AD		 359
360/*
361 * Clocks
362 */
363
364#define AMDGPU_MAX_PPLL 3
365
366struct amdgpu_clock {
367 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
368 struct amdgpu_pll spll;
369 struct amdgpu_pll mpll;
370 /* 10 Khz units */
371 uint32_t default_mclk;
372 uint32_t default_sclk;
373 uint32_t default_dispclk;
374 uint32_t current_dispclk;
375 uint32_t dp_extclk;
376 uint32_t max_pixel_clock;
377};
378
97b2e202 379/*
9124a398 380 * GEM.
97b2e202 381 */
97b2e202 382
7e5a547f 383#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 384#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
385
386void amdgpu_gem_object_free(struct drm_gem_object *obj);
387int amdgpu_gem_object_open(struct drm_gem_object *obj,
388 struct drm_file *file_priv);
389void amdgpu_gem_object_close(struct drm_gem_object *obj,
390 struct drm_file *file_priv);
391unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
392struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 393struct drm_gem_object *
394amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
395 struct dma_buf_attachment *attach,
396 struct sg_table *sg);
97b2e202
AD		 397struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
398 struct drm_gem_object *gobj,
399 int flags);
09052fc3
SL		 400struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
401 struct dma_buf *dma_buf);
97b2e202
AD		 402int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
403void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
404struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
405void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
406void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 407int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 408
409/* sub-allocation manager, it has to be protected by another lock.
410 * By conception this is an helper for other part of the driver
411 * like the indirect buffer or semaphore, which both have their
412 * locking.
413 *
414 * Principe is simple, we keep a list of sub allocation in offset
415 * order (first entry has offset == 0, last entry has the highest
416 * offset).
417 *
418 * When allocating new object we first check if there is room at
419 * the end total_size - (last_object_offset + last_object_size) >=
420 * alloc_size. If so we allocate new object there.
421 *
422 * When there is not enough room at the end, we start waiting for
423 * each sub object until we reach object_offset+object_size >=
424 * alloc_size, this object then become the sub object we return.
425 *
426 * Alignment can't be bigger than page size.
427 *
428 * Hole are not considered for allocation to keep things simple.
429 * Assumption is that there won't be hole (all object on same
430 * alignment).
431 */
6ba60b89
CK		 432
433#define AMDGPU_SA_NUM_FENCE_LISTS 32
434
97b2e202
AD		 435struct amdgpu_sa_manager {
436 wait_queue_head_t wq;
437 struct amdgpu_bo *bo;
438 struct list_head *hole;
6ba60b89 439 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 440 struct list_head olist;
441 unsigned size;
442 uint64_t gpu_addr;
443 void *cpu_ptr;
444 uint32_t domain;
445 uint32_t align;
446};
447
97b2e202
AD		 448/* sub-allocation buffer */
449struct amdgpu_sa_bo {
450 struct list_head olist;
451 struct list_head flist;
452 struct amdgpu_sa_manager *manager;
453 unsigned soffset;
454 unsigned eoffset;
f54d1867 455 struct dma_fence *fence;
97b2e202
AD		 456};
457
458/*
459 * GEM objects.
460 */
418aa0c2 461void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 462int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 463 int alignment, u32 initial_domain,
464 u64 flags, bool kernel,
465 struct reservation_object *resv,
466 struct drm_gem_object **obj);
97b2e202
AD		 467
468int amdgpu_mode_dumb_create(struct drm_file *file_priv,
469 struct drm_device *dev,
470 struct drm_mode_create_dumb *args);
471int amdgpu_mode_dumb_mmap(struct drm_file *filp,
472 struct drm_device *dev,
473 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 474int amdgpu_fence_slab_init(void);
475void amdgpu_fence_slab_fini(void);
97b2e202 476
97b2e202
AD		 477/*
478 * GPU doorbell structures, functions & helpers
479 */
480typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
481{
482 AMDGPU_DOORBELL_KIQ = 0x000,
483 AMDGPU_DOORBELL_HIQ = 0x001,
484 AMDGPU_DOORBELL_DIQ = 0x002,
485 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
486 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
487 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
488 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
489 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
490 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
491 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
492 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
493 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
494 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
495 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
496 AMDGPU_DOORBELL_IH = 0x1E8,
497 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
498 AMDGPU_DOORBELL_INVALID = 0xFFFF
499} AMDGPU_DOORBELL_ASSIGNMENT;
500
501struct amdgpu_doorbell {
502 /* doorbell mmio */
503 resource_size_t base;
504 resource_size_t size;
505 u32 __iomem *ptr;
506 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
507};
508
39807b93
KW		 509/*
510 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
511 */
512typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
513{
514 /*
515 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
516 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
517 * Compute related doorbells are allocated from 0x00 to 0x8a
518 */
519
520
521 /* kernel scheduling */
522 AMDGPU_DOORBELL64_KIQ = 0x00,
523
524 /* HSA interface queue and debug queue */
525 AMDGPU_DOORBELL64_HIQ = 0x01,
526 AMDGPU_DOORBELL64_DIQ = 0x02,
527
528 /* Compute engines */
529 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
530 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
531 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
532 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
533 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
534 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
535 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
536 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
537
538 /* User queue doorbell range (128 doorbells) */
539 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
540 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
541
542 /* Graphics engine */
543 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
544
545 /*
546 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
547 * Graphics voltage island aperture 1
548 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
549 */
550
551 /* sDMA engines */
552 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
553 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
554 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
555 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
556
557 /* Interrupt handler */
558 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
559 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
560 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
561
e6b3ecb4
ML		 562 /* VCN engine use 32 bits doorbell */
563 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
564 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
565 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
566 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
567
568 /* overlap the doorbell assignment with VCN as they are mutually exclusive
569 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
570 */
4ed11d79
FM		 571 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
572 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
573 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
574 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
575
576 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
577 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
578 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
579 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 580
581 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
582 AMDGPU_DOORBELL64_INVALID = 0xFFFF
583} AMDGPU_DOORBELL64_ASSIGNMENT;
584
97b2e202
AD		 585/*
586 * IRQS.
587 */
588
589struct amdgpu_flip_work {
325cbba1 590 struct delayed_work flip_work;
97b2e202
AD		 591 struct work_struct unpin_work;
592 struct amdgpu_device *adev;
593 int crtc_id;
325cbba1 594 u32 target_vblank;
97b2e202
AD		 595 uint64_t base;
596 struct drm_pending_vblank_event *event;
765e7fbf 597 struct amdgpu_bo *old_abo;
f54d1867 598 struct dma_fence *excl;
1ffd2652 599 unsigned shared_count;
f54d1867
CW		 600 struct dma_fence **shared;
601 struct dma_fence_cb cb;
cb9e59d7 602 bool async;
97b2e202
AD		 603};
604
605
606/*
607 * CP & rings.
608 */
609
610struct amdgpu_ib {
611 struct amdgpu_sa_bo *sa_bo;
612 uint32_t length_dw;
613 uint64_t gpu_addr;
614 uint32_t *ptr;
de807f81 615 uint32_t flags;
97b2e202
AD		 616};
617
1b1f42d8 618extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 619
50838c8c 620int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 621 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 622int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
623 struct amdgpu_job **job);
b6723c8d 624
a5fb4ec2 625void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 626void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 627int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
1b1f42d8 628 struct drm_sched_entity *entity, void *owner,
f54d1867 629 struct dma_fence **f);
8b4fb00b 630
effd924d
AR		 631/*
632 * Queue manager
633 */
634struct amdgpu_queue_mapper {
635 int hw_ip;
636 struct mutex lock;
637 /* protected by lock */
638 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
639};
640
641struct amdgpu_queue_mgr {
642 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
643};
644
645int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
646 struct amdgpu_queue_mgr *mgr);
647int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
648 struct amdgpu_queue_mgr *mgr);
649int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
650 struct amdgpu_queue_mgr *mgr,
fa7c7939 651 u32 hw_ip, u32 instance, u32 ring,
effd924d
AR		 652 struct amdgpu_ring **out_ring);
653
97b2e202
AD		 654/*
655 * context related structures
656 */
657
21c16bf6 658struct amdgpu_ctx_ring {
91404fb2 659 uint64_t sequence;
f54d1867 660 struct dma_fence **fences;
1b1f42d8 661 struct drm_sched_entity entity;
21c16bf6
CK		 662};
663
97b2e202 664struct amdgpu_ctx {
0b492a4c 665 struct kref refcount;
9cb7e5a9 666 struct amdgpu_device *adev;
effd924d 667 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 668 unsigned reset_counter;
668ca1b4 669 unsigned reset_counter_query;
e55f2b64 670 uint32_t vram_lost_counter;
21c16bf6 671 spinlock_t ring_lock;
f54d1867 672 struct dma_fence **fences;
21c16bf6 673 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
e55f2b64 674 bool preamble_presented;
1b1f42d8
LS		 675 enum drm_sched_priority init_priority;
676 enum drm_sched_priority override_priority;
0ae94444 677 struct mutex lock;
1102900d 678 atomic_t guilty;
97b2e202
AD		 679};
680
681struct amdgpu_ctx_mgr {
0b492a4c
AD		 682 struct amdgpu_device *adev;
683 struct mutex lock;
684 /* protected by lock */
685 struct idr ctx_handles;
97b2e202
AD		 686};
687
0b492a4c
AD		 688struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
689int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
690
eb01abc7
ML		 691int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
692 struct dma_fence *fence, uint64_t *seq);
f54d1867 693struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 694 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae 695void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
1b1f42d8 696 enum drm_sched_priority priority);
21c16bf6 697
0b492a4c
AD		 698int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
699 struct drm_file *filp);
700
0ae94444
AG		 701int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
702
efd4ccb5
CK		 703void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
704void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 705
0ae94444 706
97b2e202
AD		 707/*
708 * file private structure
709 */
710
711struct amdgpu_fpriv {
712 struct amdgpu_vm vm;
b85891bd 713 struct amdgpu_bo_va *prt_va;
0f4b3c68 714 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 715 struct mutex bo_list_lock;
716 struct idr bo_list_handles;
0b492a4c 717 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 718};
719
720/*
721 * residency list
722 */
9124a398
CK		 723struct amdgpu_bo_list_entry {
724 struct amdgpu_bo *robj;
725 struct ttm_validate_buffer tv;
726 struct amdgpu_bo_va *bo_va;
727 uint32_t priority;
728 struct page **user_pages;
729 int user_invalidated;
730};
97b2e202
AD		 731
732struct amdgpu_bo_list {
733 struct mutex lock;
5ac55629
AX		 734 struct rcu_head rhead;
735 struct kref refcount;
97b2e202
AD		 736 struct amdgpu_bo *gds_obj;
737 struct amdgpu_bo *gws_obj;
738 struct amdgpu_bo *oa_obj;
211dff55 739 unsigned first_userptr;
97b2e202
AD		 740 unsigned num_entries;
741 struct amdgpu_bo_list_entry *array;
742};
743
744struct amdgpu_bo_list *
745amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 746void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
747 struct list_head *validated);
97b2e202
AD		 748void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
749void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
750
751/*
752 * GFX stuff
753 */
754#include "clearstate_defs.h"
755
79e5412c
AD		 756struct amdgpu_rlc_funcs {
757 void (*enter_safe_mode)(struct amdgpu_device *adev);
758 void (*exit_safe_mode)(struct amdgpu_device *adev);
759};
760
97b2e202
AD		 761struct amdgpu_rlc {
762 /* for power gating */
763 struct amdgpu_bo *save_restore_obj;
764 uint64_t save_restore_gpu_addr;
765 volatile uint32_t *sr_ptr;
766 const u32 *reg_list;
767 u32 reg_list_size;
768 /* for clear state */
769 struct amdgpu_bo *clear_state_obj;
770 uint64_t clear_state_gpu_addr;
771 volatile uint32_t *cs_ptr;
772 const struct cs_section_def *cs_data;
773 u32 clear_state_size;
774 /* for cp tables */
775 struct amdgpu_bo *cp_table_obj;
776 uint64_t cp_table_gpu_addr;
777 volatile uint32_t *cp_table_ptr;
778 u32 cp_table_size;
79e5412c
AD		 779
780 /* safe mode for updating CG/PG state */
781 bool in_safe_mode;
782 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 783
784 /* for firmware data */
785 u32 save_and_restore_offset;
786 u32 clear_state_descriptor_offset;
787 u32 avail_scratch_ram_locations;
788 u32 reg_restore_list_size;
789 u32 reg_list_format_start;
790 u32 reg_list_format_separate_start;
791 u32 starting_offsets_start;
792 u32 reg_list_format_size_bytes;
793 u32 reg_list_size_bytes;
794
795 u32 *register_list_format;
796 u32 *register_restore;
97b2e202
AD		 797};
798
78c16834
AR		 799#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
800
97b2e202
AD		 801struct amdgpu_mec {
802 struct amdgpu_bo *hpd_eop_obj;
803 u64 hpd_eop_gpu_addr;
b1023571
KW		 804 struct amdgpu_bo *mec_fw_obj;
805 u64 mec_fw_gpu_addr;
97b2e202 806 u32 num_mec;
42794b27
AR		 807 u32 num_pipe_per_mec;
808 u32 num_queue_per_pipe;
59a82d7d 809 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 810
811 /* These are the resources for which amdgpu takes ownership */
812 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 813};
814
4e638ae9
XY		 815struct amdgpu_kiq {
816 u64 eop_gpu_addr;
817 struct amdgpu_bo *eop_obj;
43ca8efa 818 spinlock_t ring_lock;
4e638ae9
XY		 819 struct amdgpu_ring ring;
820 struct amdgpu_irq_src irq;
821};
822
97b2e202
AD		 823/*
824 * GPU scratch registers structures, functions & helpers
825 */
826struct amdgpu_scratch {
827 unsigned num_reg;
828 uint32_t reg_base;
50261151 829 uint32_t free_mask;
97b2e202
AD		 830};
831
832/*
833 * GFX configurations
834 */
e3fa7630
AD		 835#define AMDGPU_GFX_MAX_SE 4
836#define AMDGPU_GFX_MAX_SH_PER_SE 2
837
838struct amdgpu_rb_config {
839 uint32_t rb_backend_disable;
840 uint32_t user_rb_backend_disable;
841 uint32_t raster_config;
842 uint32_t raster_config_1;
843};
844
d0e95758
AG		 845struct gb_addr_config {
846 uint16_t pipe_interleave_size;
847 uint8_t num_pipes;
848 uint8_t max_compress_frags;
849 uint8_t num_banks;
850 uint8_t num_se;
851 uint8_t num_rb_per_se;
852};
853
ea323f88 854struct amdgpu_gfx_config {
97b2e202
AD		 855 unsigned max_shader_engines;
856 unsigned max_tile_pipes;
857 unsigned max_cu_per_sh;
858 unsigned max_sh_per_se;
859 unsigned max_backends_per_se;
860 unsigned max_texture_channel_caches;
861 unsigned max_gprs;
862 unsigned max_gs_threads;
863 unsigned max_hw_contexts;
864 unsigned sc_prim_fifo_size_frontend;
865 unsigned sc_prim_fifo_size_backend;
866 unsigned sc_hiz_tile_fifo_size;
867 unsigned sc_earlyz_tile_fifo_size;
868
869 unsigned num_tile_pipes;
870 unsigned backend_enable_mask;
871 unsigned mem_max_burst_length_bytes;
872 unsigned mem_row_size_in_kb;
873 unsigned shader_engine_tile_size;
874 unsigned num_gpus;
875 unsigned multi_gpu_tile_size;
876 unsigned mc_arb_ramcfg;
877 unsigned gb_addr_config;
8f8e00c1 878 unsigned num_rbs;
408bfe7c
JZ		 879 unsigned gs_vgt_table_depth;
880 unsigned gs_prim_buffer_depth;
97b2e202
AD		 881
882 uint32_t tile_mode_array[32];
883 uint32_t macrotile_mode_array[16];
e3fa7630 884
d0e95758 885 struct gb_addr_config gb_addr_config_fields;
e3fa7630 886 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 887
888 /* gfx configure feature */
889 uint32_t double_offchip_lds_buf;
97b2e202
AD		 890};
891
7dae69a2 892struct amdgpu_cu_info {
ebdebf42 893 uint32_t simd_per_cu;
51fd0370 894 uint32_t max_waves_per_simd;
408bfe7c 895 uint32_t wave_front_size;
51fd0370
HZ		 896 uint32_t max_scratch_slots_per_cu;
897 uint32_t lds_size;
dbfe85ea
FC		 898
899 /* total active CU number */
900 uint32_t number;
901 uint32_t ao_cu_mask;
902 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 903 uint32_t bitmap[4][4];
904};
905
b95e31fd
AD		 906struct amdgpu_gfx_funcs {
907 /* get the gpu clock counter */
908 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 909 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 910 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 911 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
912 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 913};
914
bce23e00
AD		 915struct amdgpu_ngg_buf {
916 struct amdgpu_bo *bo;
917 uint64_t gpu_addr;
918 uint32_t size;
919 uint32_t bo_size;
920};
921
922enum {
af8baf15
GR		 923 NGG_PRIM = 0,
924 NGG_POS,
925 NGG_CNTL,
926 NGG_PARAM,
bce23e00
AD		 927 NGG_BUF_MAX
928};
929
930struct amdgpu_ngg {
931 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
932 uint32_t gds_reserve_addr;
933 uint32_t gds_reserve_size;
934 bool init;
935};
936
97b2e202
AD		 937struct amdgpu_gfx {
938 struct mutex gpu_clock_mutex;
ea323f88 939 struct amdgpu_gfx_config config;
97b2e202
AD		 940 struct amdgpu_rlc rlc;
941 struct amdgpu_mec mec;
4e638ae9 942 struct amdgpu_kiq kiq;
97b2e202
AD		 943 struct amdgpu_scratch scratch;
944 const struct firmware *me_fw; /* ME firmware */
945 uint32_t me_fw_version;
946 const struct firmware *pfp_fw; /* PFP firmware */
947 uint32_t pfp_fw_version;
948 const struct firmware *ce_fw; /* CE firmware */
949 uint32_t ce_fw_version;
950 const struct firmware *rlc_fw; /* RLC firmware */
951 uint32_t rlc_fw_version;
952 const struct firmware *mec_fw; /* MEC firmware */
953 uint32_t mec_fw_version;
954 const struct firmware *mec2_fw; /* MEC2 firmware */
955 uint32_t mec2_fw_version;
02558a00
KW		 956 uint32_t me_feature_version;
957 uint32_t ce_feature_version;
958 uint32_t pfp_feature_version;
351643d7
JZ		 959 uint32_t rlc_feature_version;
960 uint32_t mec_feature_version;
961 uint32_t mec2_feature_version;
97b2e202
AD		 962 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
963 unsigned num_gfx_rings;
964 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
965 unsigned num_compute_rings;
966 struct amdgpu_irq_src eop_irq;
967 struct amdgpu_irq_src priv_reg_irq;
968 struct amdgpu_irq_src priv_inst_irq;
969 /* gfx status */
7dae69a2 970 uint32_t gfx_current_status;
a101a899 971 /* ce ram size*/
7dae69a2
AD		 972 unsigned ce_ram_size;
973 struct amdgpu_cu_info cu_info;
b95e31fd 974 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 975
976 /* reset mask */
977 uint32_t grbm_soft_reset;
978 uint32_t srbm_soft_reset;
b4e40676
DP		 979 /* s3/s4 mask */
980 bool in_suspend;
bce23e00
AD		 981 /* NGG */
982 struct amdgpu_ngg ngg;
b8866c26
AR		 983
984 /* pipe reservation */
985 struct mutex pipe_reserve_mutex;
986 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 987};
988
b07c60c0 989int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 990 unsigned size, struct amdgpu_ib *ib);
4d9c514d 991void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 992 struct dma_fence *f);
b07c60c0 993int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 994 struct amdgpu_ib *ibs, struct amdgpu_job *job,
995 struct dma_fence **f);
97b2e202
AD		 996int amdgpu_ib_pool_init(struct amdgpu_device *adev);
997void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
998int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 999
1000/*
1001 * CS.
1002 */
1003struct amdgpu_cs_chunk {
1004 uint32_t chunk_id;
1005 uint32_t length_dw;
758ac17f 1006 void *kdata;
97b2e202
AD		 1007};
1008
1009struct amdgpu_cs_parser {
1010 struct amdgpu_device *adev;
1011 struct drm_file *filp;
3cb485f3 1012 struct amdgpu_ctx *ctx;
c3cca41e 1013
97b2e202
AD		 1014 /* chunks */
1015 unsigned nchunks;
1016 struct amdgpu_cs_chunk *chunks;
97b2e202 1017
50838c8c
CK		 1018 /* scheduler job object */
1019 struct amdgpu_job *job;
97b2e202 1020
c3cca41e
CK		 1021 /* buffer objects */
1022 struct ww_acquire_ctx ticket;
1023 struct amdgpu_bo_list *bo_list;
3fe89771 1024 struct amdgpu_mn *mn;
c3cca41e
CK		 1025 struct amdgpu_bo_list_entry vm_pd;
1026 struct list_head validated;
f54d1867 1027 struct dma_fence *fence;
c3cca41e 1028 uint64_t bytes_moved_threshold;
00f06b24 1029 uint64_t bytes_moved_vis_threshold;
c3cca41e 1030 uint64_t bytes_moved;
00f06b24 1031 uint64_t bytes_moved_vis;
662bfa61 1032 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1033
1034 /* user fence */
91acbeb6 1035 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1036
1037 unsigned num_post_dep_syncobjs;
1038 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1039};
1040
753ad49c
ML		 1041#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1042#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1043#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1044
bb977d37 1045struct amdgpu_job {
1b1f42d8 1046 struct drm_sched_job base;
bb977d37 1047 struct amdgpu_device *adev;
edf600da 1048 struct amdgpu_vm *vm;
b07c60c0 1049 struct amdgpu_ring *ring;
e86f9cee 1050 struct amdgpu_sync sync;
df83d1eb 1051 struct amdgpu_sync sched_sync;
bb977d37 1052 struct amdgpu_ib *ibs;
f54d1867 1053 struct dma_fence *fence; /* the hw fence */
753ad49c 1054 uint32_t preamble_status;
bb977d37 1055 uint32_t num_ibs;
e2840221 1056 void *owner;
3aecd24c 1057 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1058 bool vm_needs_flush;
d88bf583 1059 uint64_t vm_pd_addr;
5a4633c4
CK		 1060 unsigned vmid;
1061 unsigned pasid;
d88bf583
CK		 1062 uint32_t gds_base, gds_size;
1063 uint32_t gws_base, gws_size;
1064 uint32_t oa_base, oa_size;
14e47f93 1065 uint32_t vram_lost_counter;
758ac17f
CK		 1066
1067 /* user fence handling */
b5f5acbc 1068 uint64_t uf_addr;
758ac17f
CK		 1069 uint64_t uf_sequence;
1070
bb977d37 1071};
a6db8a33
JZ		 1072#define to_amdgpu_job(sched_job) \
1073 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1074
7270f839
CK		 1075static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1076 uint32_t ib_idx, int idx)
97b2e202 1077{
50838c8c 1078 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1079}
1080
7270f839
CK		 1081static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1082 uint32_t ib_idx, int idx,
1083 uint32_t value)
1084{
50838c8c 1085 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1086}
1087
97b2e202
AD		 1088/*
1089 * Writeback
1090 */
896a664c 1091#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
97b2e202
AD		 1092
1093struct amdgpu_wb {
1094 struct amdgpu_bo *wb_obj;
1095 volatile uint32_t *wb;
1096 uint64_t gpu_addr;
1097 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1098 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1099};
1100
131b4b36
AD		 1101int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
1102void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 1103
041d9d93 1104void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
d0dd7f0c 1105
97b2e202
AD		 1106/*
1107 * SDMA
1108 */
c113ea1c 1109struct amdgpu_sdma_instance {
97b2e202
AD		 1110 /* SDMA firmware */
1111 const struct firmware *fw;
1112 uint32_t fw_version;
cfa2104f 1113 uint32_t feature_version;
97b2e202
AD		 1114
1115 struct amdgpu_ring ring;
18111de0 1116 bool burst_nop;
97b2e202
AD		 1117};
1118
c113ea1c
AD		 1119struct amdgpu_sdma {
1120 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1121#ifdef CONFIG_DRM_AMDGPU_SI
1122 //SI DMA has a difference trap irq number for the second engine
1123 struct amdgpu_irq_src trap_irq_1;
1124#endif
c113ea1c
AD		 1125 struct amdgpu_irq_src trap_irq;
1126 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1127 int num_instances;
e702a680 1128 uint32_t srbm_soft_reset;
c113ea1c
AD		 1129};
1130
97b2e202
AD		 1131/*
1132 * Firmware
1133 */
e635ee07
HR		 1134enum amdgpu_firmware_load_type {
1135 AMDGPU_FW_LOAD_DIRECT = 0,
1136 AMDGPU_FW_LOAD_SMU,
1137 AMDGPU_FW_LOAD_PSP,
1138};
1139
97b2e202
AD		 1140struct amdgpu_firmware {
1141 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1142 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1143 struct amdgpu_bo *fw_buf;
1144 unsigned int fw_size;
2445b227 1145 unsigned int max_ucodes;
0e5ca0d1
HR		 1146 /* firmwares are loaded by psp instead of smu from vega10 */
1147 const struct amdgpu_psp_funcs *funcs;
1148 struct amdgpu_bo *rbuf;
1149 struct mutex mutex;
ab4fe3e1
HR		 1150
1151 /* gpu info firmware data pointer */
1152 const struct firmware *gpu_info_fw;
d59c026b
ML		 1153
1154 void *fw_buf_ptr;
1155 uint64_t fw_buf_mc;
97b2e202
AD		 1156};
1157
1158/*
1159 * Benchmarking
1160 */
1161void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1162
1163
1164/*
1165 * Testing
1166 */
1167void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1168
50ab2533 1169
97b2e202
AD		 1170/*
1171 * amdgpu smumgr functions
1172 */
1173struct amdgpu_smumgr_funcs {
1174 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1175 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1176 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1177};
1178
1179/*
1180 * amdgpu smumgr
1181 */
1182struct amdgpu_smumgr {
1183 struct amdgpu_bo *toc_buf;
1184 struct amdgpu_bo *smu_buf;
1185 /* asic priv smu data */
1186 void *priv;
1187 spinlock_t smu_lock;
1188 /* smumgr functions */
1189 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1190 /* ucode loading complete flag */
1191 uint32_t fw_flags;
1192};
1193
1194/*
1195 * ASIC specific register table accessible by UMD
1196 */
1197struct amdgpu_allowed_register_entry {
1198 uint32_t reg_offset;
97b2e202
AD		 1199 bool grbm_indexed;
1200};
1201
97b2e202
AD		 1202/*
1203 * ASIC specific functions.
1204 */
1205struct amdgpu_asic_funcs {
1206 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1207 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1208 u8 *bios, u32 length_bytes);
97b2e202
AD		 1209 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1210 u32 sh_num, u32 reg_offset, u32 *value);
1211 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1212 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1213 /* get the reference clock */
1214 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1215 /* MM block clocks */
1216 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1217 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1218 /* static power management */
1219 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1220 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1221 /* get config memsize register */
1222 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6
AD		 1223 /* flush hdp write queue */
1224 void (*flush_hdp)(struct amdgpu_device *adev);
1225 /* invalidate hdp read cache */
1226 void (*invalidate_hdp)(struct amdgpu_device *adev);
97b2e202
AD		 1227};
1228
1229/*
1230 * IOCTL.
1231 */
1232int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1233 struct drm_file *filp);
1234int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1235 struct drm_file *filp);
1236
1237int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1238 struct drm_file *filp);
1239int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1240 struct drm_file *filp);
1241int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1242 struct drm_file *filp);
1243int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1244 struct drm_file *filp);
1245int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1246 struct drm_file *filp);
1247int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1248 struct drm_file *filp);
1249int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1250int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1251 struct drm_file *filp);
97b2e202 1252int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1253int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1254 struct drm_file *filp);
97b2e202
AD		 1255
1256int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1257 struct drm_file *filp);
1258
1259/* VRAM scratch page for HDP bug, default vram page */
1260struct amdgpu_vram_scratch {
1261 struct amdgpu_bo *robj;
1262 volatile uint32_t *ptr;
1263 u64 gpu_addr;
1264};
1265
1266/*
1267 * ACPI
1268 */
1269struct amdgpu_atif_notification_cfg {
1270 bool enabled;
1271 int command_code;
1272};
1273
1274struct amdgpu_atif_notifications {
1275 bool display_switch;
1276 bool expansion_mode_change;
1277 bool thermal_state;
1278 bool forced_power_state;
1279 bool system_power_state;
1280 bool display_conf_change;
1281 bool px_gfx_switch;
1282 bool brightness_change;
1283 bool dgpu_display_event;
1284};
1285
1286struct amdgpu_atif_functions {
1287 bool system_params;
1288 bool sbios_requests;
1289 bool select_active_disp;
1290 bool lid_state;
1291 bool get_tv_standard;
1292 bool set_tv_standard;
1293 bool get_panel_expansion_mode;
1294 bool set_panel_expansion_mode;
1295 bool temperature_change;
1296 bool graphics_device_types;
1297};
1298
1299struct amdgpu_atif {
1300 struct amdgpu_atif_notifications notifications;
1301 struct amdgpu_atif_functions functions;
1302 struct amdgpu_atif_notification_cfg notification_cfg;
1303 struct amdgpu_encoder *encoder_for_bl;
1304};
1305
1306struct amdgpu_atcs_functions {
1307 bool get_ext_state;
1308 bool pcie_perf_req;
1309 bool pcie_dev_rdy;
1310 bool pcie_bus_width;
1311};
1312
1313struct amdgpu_atcs {
1314 struct amdgpu_atcs_functions functions;
1315};
1316
a05502e5
HC		 1317/*
1318 * Firmware VRAM reservation
1319 */
1320struct amdgpu_fw_vram_usage {
1321 u64 start_offset;
1322 u64 size;
1323 struct amdgpu_bo *reserved_bo;
1324 void *va;
1325};
1326
d03846af
CZ		 1327/*
1328 * CGS
1329 */
110e6f26
DA		 1330struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1331void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1332
97b2e202
AD		 1333/*
1334 * Core structure, functions and helpers.
1335 */
1336typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1337typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1338
1339typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1340typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1341
946a4d5b
SL		 1342
1343/*
1344 * amdgpu nbio functions
1345 *
946a4d5b 1346 */
bf383fb6
AD		 1347struct nbio_hdp_flush_reg {
1348 u32 ref_and_mask_cp0;
1349 u32 ref_and_mask_cp1;
1350 u32 ref_and_mask_cp2;
1351 u32 ref_and_mask_cp3;
1352 u32 ref_and_mask_cp4;
1353 u32 ref_and_mask_cp5;
1354 u32 ref_and_mask_cp6;
1355 u32 ref_and_mask_cp7;
1356 u32 ref_and_mask_cp8;
1357 u32 ref_and_mask_cp9;
1358 u32 ref_and_mask_sdma0;
1359 u32 ref_and_mask_sdma1;
1360};
946a4d5b
SL		 1361
1362struct amdgpu_nbio_funcs {
bf383fb6
AD		 1363 const struct nbio_hdp_flush_reg *hdp_flush_reg;
1364 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
1365 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
1366 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
1367 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
1368 u32 (*get_rev_id)(struct amdgpu_device *adev);
bf383fb6
AD		 1369 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
1370 void (*hdp_flush)(struct amdgpu_device *adev);
1371 u32 (*get_memsize)(struct amdgpu_device *adev);
1372 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
1373 bool use_doorbell, int doorbell_index);
1374 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
1375 bool enable);
1376 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
1377 bool enable);
1378 void (*ih_doorbell_range)(struct amdgpu_device *adev,
1379 bool use_doorbell, int doorbell_index);
1380 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
1381 bool enable);
1382 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
1383 bool enable);
1384 void (*get_clockgating_state)(struct amdgpu_device *adev,
1385 u32 *flags);
1386 void (*ih_control)(struct amdgpu_device *adev);
1387 void (*init_registers)(struct amdgpu_device *adev);
1388 void (*detect_hw_virt)(struct amdgpu_device *adev);
946a4d5b
SL		 1389};
1390
1391
4522824c
SL		 1392/* Define the HW IP blocks will be used in driver , add more if necessary */
1393enum amd_hw_ip_block_type {
1394 GC_HWIP = 1,
1395 HDP_HWIP,
1396 SDMA0_HWIP,
1397 SDMA1_HWIP,
1398 MMHUB_HWIP,
1399 ATHUB_HWIP,
1400 NBIO_HWIP,
1401 MP0_HWIP,
1402 UVD_HWIP,
1403 VCN_HWIP = UVD_HWIP,
1404 VCE_HWIP,
1405 DF_HWIP,
1406 DCE_HWIP,
1407 OSSSYS_HWIP,
1408 SMUIO_HWIP,
1409 PWR_HWIP,
1410 NBIF_HWIP,
1411 MAX_HWIP
1412};
1413
1414#define HWIP_MAX_INSTANCE 6
1415
11dc9364
RZ		 1416struct amd_powerplay {
1417 struct cgs_device *cgs_device;
1418 void *pp_handle;
1419 const struct amd_ip_funcs *ip_funcs;
1420 const struct amd_pm_funcs *pp_funcs;
1421};
1422
0c49e0b8 1423#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1424struct amdgpu_device {
1425 struct device *dev;
1426 struct drm_device *ddev;
1427 struct pci_dev *pdev;
97b2e202 1428
a8fe58ce
MB		 1429#ifdef CONFIG_DRM_AMD_ACP
1430 struct amdgpu_acp acp;
1431#endif
1432
97b2e202 1433 /* ASIC */
2f7d10b3 1434 enum amd_asic_type asic_type;
97b2e202
AD		 1435 uint32_t family;
1436 uint32_t rev_id;
1437 uint32_t external_rev_id;
1438 unsigned long flags;
1439 int usec_timeout;
1440 const struct amdgpu_asic_funcs *asic_funcs;
1441 bool shutdown;
97b2e202 1442 bool need_dma32;
fd5fd480 1443 bool need_swiotlb;
97b2e202 1444 bool accel_working;
edf600da 1445 struct work_struct reset_work;
97b2e202
AD		 1446 struct notifier_block acpi_nb;
1447 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1448 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1449 unsigned debugfs_count;
97b2e202 1450#if defined(CONFIG_DEBUG_FS)
adcec288 1451 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1452#endif
1453 struct amdgpu_atif atif;
1454 struct amdgpu_atcs atcs;
1455 struct mutex srbm_mutex;
1456 /* GRBM index mutex. Protects concurrent access to GRBM index */
1457 struct mutex grbm_idx_mutex;
1458 struct dev_pm_domain vga_pm_domain;
1459 bool have_disp_power_ref;
1460
1461 /* BIOS */
0cdd5005 1462 bool is_atom_fw;
97b2e202 1463 uint8_t *bios;
a9f5db9c 1464 uint32_t bios_size;
5af2c10d 1465 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1466 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1467 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1468
1469 /* Register/doorbell mmio */
1470 resource_size_t rmmio_base;
1471 resource_size_t rmmio_size;
1472 void __iomem *rmmio;
1473 /* protects concurrent MM_INDEX/DATA based register access */
1474 spinlock_t mmio_idx_lock;
1475 /* protects concurrent SMC based register access */
1476 spinlock_t smc_idx_lock;
1477 amdgpu_rreg_t smc_rreg;
1478 amdgpu_wreg_t smc_wreg;
1479 /* protects concurrent PCIE register access */
1480 spinlock_t pcie_idx_lock;
1481 amdgpu_rreg_t pcie_rreg;
1482 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1483 amdgpu_rreg_t pciep_rreg;
1484 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1485 /* protects concurrent UVD register access */
1486 spinlock_t uvd_ctx_idx_lock;
1487 amdgpu_rreg_t uvd_ctx_rreg;
1488 amdgpu_wreg_t uvd_ctx_wreg;
1489 /* protects concurrent DIDT register access */
1490 spinlock_t didt_idx_lock;
1491 amdgpu_rreg_t didt_rreg;
1492 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1493 /* protects concurrent gc_cac register access */
1494 spinlock_t gc_cac_idx_lock;
1495 amdgpu_rreg_t gc_cac_rreg;
1496 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1497 /* protects concurrent se_cac register access */
1498 spinlock_t se_cac_idx_lock;
1499 amdgpu_rreg_t se_cac_rreg;
1500 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1501 /* protects concurrent ENDPOINT (audio) register access */
1502 spinlock_t audio_endpt_idx_lock;
1503 amdgpu_block_rreg_t audio_endpt_rreg;
1504 amdgpu_block_wreg_t audio_endpt_wreg;
1505 void __iomem *rio_mem;
1506 resource_size_t rio_mem_size;
1507 struct amdgpu_doorbell doorbell;
1508
1509 /* clock/pll info */
1510 struct amdgpu_clock clock;
1511
1512 /* MC */
770d13b1 1513 struct amdgpu_gmc gmc;
97b2e202
AD		 1514 struct amdgpu_gart gart;
1515 struct amdgpu_dummy_page dummy_page;
1516 struct amdgpu_vm_manager vm_manager;
e60f8db5 1517 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1518
1519 /* memory management */
1520 struct amdgpu_mman mman;
97b2e202
AD		 1521 struct amdgpu_vram_scratch vram_scratch;
1522 struct amdgpu_wb wb;
97b2e202 1523 atomic64_t num_bytes_moved;
dbd5ed60 1524 atomic64_t num_evictions;
68e2c5ff 1525 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1526 atomic_t gpu_reset_counter;
f1892138 1527 atomic_t vram_lost_counter;
97b2e202 1528
95844d20
MO		 1529 /* data for buffer migration throttling */
1530 struct {
1531 spinlock_t lock;
1532 s64 last_update_us;
1533 s64 accum_us; /* accumulated microseconds */
00f06b24 1534 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1535 u32 log2_max_MBps;
1536 } mm_stats;
1537
97b2e202 1538 /* display */
9accf2fd 1539 bool enable_virtual_display;
97b2e202 1540 struct amdgpu_mode_info mode_info;
4562236b 1541 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 1542 struct work_struct hotplug_work;
1543 struct amdgpu_irq_src crtc_irq;
1544 struct amdgpu_irq_src pageflip_irq;
1545 struct amdgpu_irq_src hpd_irq;
1546
1547 /* rings */
76bf0db5 1548 u64 fence_context;
97b2e202
AD		 1549 unsigned num_rings;
1550 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1551 bool ib_pool_ready;
1552 struct amdgpu_sa_manager ring_tmp_bo;
1553
1554 /* interrupts */
1555 struct amdgpu_irq irq;
1556
1f7371b2
AD		 1557 /* powerplay */
1558 struct amd_powerplay powerplay;
f3898ea1 1559 bool pp_force_state_enabled;
1f7371b2 1560
97b2e202
AD		 1561 /* dpm */
1562 struct amdgpu_pm pm;
1563 u32 cg_flags;
1564 u32 pg_flags;
1565
1566 /* amdgpu smumgr */
1567 struct amdgpu_smumgr smu;
1568
1569 /* gfx */
1570 struct amdgpu_gfx gfx;
1571
1572 /* sdma */
c113ea1c 1573 struct amdgpu_sdma sdma;
97b2e202 1574
b43aaee6
LL		 1575 /* uvd */
1576 struct amdgpu_uvd uvd;
1577
1578 /* vce */
1579 struct amdgpu_vce vce;
1580
1581 /* vcn */
1582 struct amdgpu_vcn vcn;
97b2e202
AD		 1583
1584 /* firmwares */
1585 struct amdgpu_firmware firmware;
1586
0e5ca0d1
HR		 1587 /* PSP */
1588 struct psp_context psp;
1589
97b2e202
AD		 1590 /* GDS */
1591 struct amdgpu_gds gds;
1592
4562236b
HW		 1593 /* display related functionality */
1594 struct amdgpu_display_manager dm;
1595
a1255107 1596 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1597 int num_ip_blocks;
97b2e202
AD		 1598 struct mutex mn_lock;
1599 DECLARE_HASHTABLE(mn_hash, 7);
1600
1601 /* tracking pinned memory */
1602 u64 vram_pin_size;
e131b914 1603 u64 invisible_pin_size;
97b2e202 1604 u64 gart_pin_size;
130e0371
OG		 1605
1606 /* amdkfd interface */
1607 struct kfd_dev *kfd;
23ca0e4e 1608
4522824c
SL		 1609 /* soc15 register offset based on ip, instance and segment */
1610 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1611
946a4d5b
SL		 1612 const struct amdgpu_nbio_funcs *nbio_funcs;
1613
2dc80b00
S		 1614 /* delayed work_func for deferring clockgating during resume */
1615 struct delayed_work late_init_work;
1616
5a5099cb 1617 struct amdgpu_virt virt;
a05502e5
HC		 1618 /* firmware VRAM reservation */
1619 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1620
1621 /* link all shadow bo */
1622 struct list_head shadow_list;
1623 struct mutex shadow_list_lock;
795f2813
AR		 1624 /* keep an lru list of rings by HW IP */
1625 struct list_head ring_lru_list;
1626 spinlock_t ring_lru_list_lock;
5c1354bd 1627
c836fec5
JQ		 1628 /* record hw reset is performed */
1629 bool has_hw_reset;
0c49e0b8 1630 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1631
47ed4e1c
KW		 1632 /* record last mm index being written through WREG32*/
1633 unsigned long last_mm_index;
13a752e3
ML		 1634 bool in_gpu_reset;
1635 struct mutex lock_reset;
97b2e202
AD		 1636};
1637
a7d64de6
CK		 1638static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1639{
1640 return container_of(bdev, struct amdgpu_device, mman.bdev);
1641}
1642
97b2e202
AD		 1643int amdgpu_device_init(struct amdgpu_device *adev,
1644 struct drm_device *ddev,
1645 struct pci_dev *pdev,
1646 uint32_t flags);
1647void amdgpu_device_fini(struct amdgpu_device *adev);
1648int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1649
1650uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1651 uint32_t acc_flags);
97b2e202 1652void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1653 uint32_t acc_flags);
97b2e202
AD		 1654u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1655void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1656
1657u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1658void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1659u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1660void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1661
4562236b
HW		 1662bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1663bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1664
97b2e202
AD		 1665/*
1666 * Registers read & write functions.
1667 */
15d72fd7
ML		 1668
1669#define AMDGPU_REGS_IDX (1<<0)
1670#define AMDGPU_REGS_NO_KIQ (1<<1)
1671
1672#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1673#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1674
1675#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1676#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1677#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1678#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1679#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1680#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1681#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1682#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1683#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1684#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1685#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1686#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1687#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1688#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1689#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1690#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1691#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1692#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1693#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1694#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1695#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1696#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1697#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1698#define WREG32_P(reg, val, mask) \
1699 do { \
1700 uint32_t tmp_ = RREG32(reg); \
1701 tmp_ &= (mask); \
1702 tmp_ |= ((val) & ~(mask)); \
1703 WREG32(reg, tmp_); \
1704 } while (0)
1705#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1706#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1707#define WREG32_PLL_P(reg, val, mask) \
1708 do { \
1709 uint32_t tmp_ = RREG32_PLL(reg); \
1710 tmp_ &= (mask); \
1711 tmp_ |= ((val) & ~(mask)); \
1712 WREG32_PLL(reg, tmp_); \
1713 } while (0)
1714#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1715#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1716#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1717
1718#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1719#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1720#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1721#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1722
1723#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1724#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1725
1726#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1727 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1728 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1729
1730#define REG_GET_FIELD(value, reg, field) \
1731 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1732
1733#define WREG32_FIELD(reg, field, val) \
1734 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1735
ccaf3574
TSD		 1736#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1737 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1738
97b2e202
AD		 1739/*
1740 * BIOS helpers.
1741 */
1742#define RBIOS8(i) (adev->bios[i])
1743#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1744#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1745
c113ea1c
AD		 1746static inline struct amdgpu_sdma_instance *
1747amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1748{
1749 struct amdgpu_device *adev = ring->adev;
1750 int i;
1751
c113ea1c
AD		 1752 for (i = 0; i < adev->sdma.num_instances; i++)
1753 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1754 break;
1755
1756 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1757 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1758 else
1759 return NULL;
1760}
1761
97b2e202
AD		 1762/*
1763 * ASICs macro.
1764 */
1765#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1766#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1767#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1768#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1769#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1770#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1771#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1772#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1773#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1774#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1775#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1776#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
2df1b8b6
AD		 1777#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
1778#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
132f34e4 1779#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
7ef11047 1780#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
132f34e4
CK		 1781#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1782#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
1783#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
97b2e202 1784#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1785#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1786#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 1787#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1788#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1789#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1790#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1791#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1792#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
c4f46f22 1793#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
b8c7b39e 1794#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
5a4633c4 1795#define amdgpu_ring_emit_vm_flush(r, vmid, pasid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (pasid), (addr))
890ee23f 1796#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1797#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1798#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1799#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1800#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1801#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1802#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1803#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1804#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1805#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1806#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1807#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1808#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1809#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1810#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1811#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1812#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1813#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1814#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1815#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1816#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1817#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1818#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1819#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1820#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1821#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1822#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1823#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1824#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1825#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1826#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1827#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1828#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1829#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1830
1831/* Common functions */
5f152b5e
AD		 1832int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1833 struct amdgpu_job* job, bool force);
8111c387 1834void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1835bool amdgpu_device_need_post(struct amdgpu_device *adev);
97b2e202 1836void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1837
00f06b24
JB		 1838void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1839 u64 num_vis_bytes);
765e7fbf 1840void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1841bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2543e28a 1842void amdgpu_device_vram_location(struct amdgpu_device *adev,
770d13b1 1843 struct amdgpu_gmc *mc, u64 base);
2543e28a 1844void amdgpu_device_gart_location(struct amdgpu_device *adev,
770d13b1 1845 struct amdgpu_gmc *mc);
d6895ad3 1846int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
97b2e202 1847void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1848int amdgpu_ttm_init(struct amdgpu_device *adev);
1849void amdgpu_ttm_fini(struct amdgpu_device *adev);
9c3f2b54 1850void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1851 const u32 *registers,
1852 const u32 array_size);
1853
1854bool amdgpu_device_is_px(struct drm_device *dev);
1855/* atpx handler */
1856#if defined(CONFIG_VGA_SWITCHEROO)
1857void amdgpu_register_atpx_handler(void);
1858void amdgpu_unregister_atpx_handler(void);
a78fe133 1859bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1860bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1861bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1862bool amdgpu_has_atpx(void);
97b2e202
AD		 1863#else
1864static inline void amdgpu_register_atpx_handler(void) {}
1865static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1866static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1867static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1868static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1869static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1870#endif
1871
1872/*
1873 * KMS
1874 */
1875extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1876extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1877
1878int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1879void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1880void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1881int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1882void amdgpu_driver_postclose_kms(struct drm_device *dev,
1883 struct drm_file *file_priv);
cdd61df6 1884int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1885int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1886int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1887u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1888int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1889void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1890long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1891 unsigned long arg);
1892
97b2e202
AD		 1893/*
1894 * functions used by amdgpu_encoder.c
1895 */
1896struct amdgpu_afmt_acr {
1897 u32 clock;
1898
1899 int n_32khz;
1900 int cts_32khz;
1901
1902 int n_44_1khz;
1903 int cts_44_1khz;
1904
1905 int n_48khz;
1906 int cts_48khz;
1907
1908};
1909
1910struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1911
1912/* amdgpu_acpi.c */
1913#if defined(CONFIG_ACPI)
1914int amdgpu_acpi_init(struct amdgpu_device *adev);
1915void amdgpu_acpi_fini(struct amdgpu_device *adev);
1916bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1917int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1918 u8 perf_req, bool advertise);
1919int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1920#else
1921static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1922static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1923#endif
1924
9cca0b8e
CK		 1925int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1926 uint64_t addr, struct amdgpu_bo **bo,
1927 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1928
4562236b
HW		 1929#if defined(CONFIG_DRM_AMD_DC)
1930int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1931#else
1932static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1933#endif
1934
97b2e202 1935#include "amdgpu_object.h"
97b2e202 1936#endif
Linux 6.x block layer and io_uring tree(s)