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drm/amdgpu: partial revert VRAM lost handling v2
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834
AR		 49#include <kgd_kfd_interface.h>
50
5fc3aeeb 51#include "amd_shared.h"
97b2e202
AD		 52#include "amdgpu_mode.h"
53#include "amdgpu_ih.h"
54#include "amdgpu_irq.h"
55#include "amdgpu_ucode.h"
c632d799 56#include "amdgpu_ttm.h"
0e5ca0d1 57#include "amdgpu_psp.h"
97b2e202 58#include "amdgpu_gds.h"
56113504 59#include "amdgpu_sync.h"
78023016 60#include "amdgpu_ring.h"
073440d2 61#include "amdgpu_vm.h"
1f7371b2 62#include "amd_powerplay.h"
cf097881 63#include "amdgpu_dpm.h"
a8fe58ce 64#include "amdgpu_acp.h"
4df654d2 65#include "amdgpu_uvd.h"
5e568178 66#include "amdgpu_vce.h"
95aa13f6 67#include "amdgpu_vcn.h"
9a189996 68#include "amdgpu_mn.h"
97b2e202 69
b80d8475 70#include "gpu_scheduler.h"
ceeb50ed 71#include "amdgpu_virt.h"
3490bdb5 72#include "amdgpu_gart.h"
b80d8475 73
97b2e202
AD		 74/*
75 * Modules parameters.
76 */
77extern int amdgpu_modeset;
78extern int amdgpu_vram_limit;
218b5dcd 79extern int amdgpu_vis_vram_limit;
83e74db6 80extern int amdgpu_gart_size;
36d38372 81extern int amdgpu_gtt_size;
95844d20 82extern int amdgpu_moverate;
97b2e202
AD		 83extern int amdgpu_benchmarking;
84extern int amdgpu_testing;
85extern int amdgpu_audio;
86extern int amdgpu_disp_priority;
87extern int amdgpu_hw_i2c;
88extern int amdgpu_pcie_gen2;
89extern int amdgpu_msi;
90extern int amdgpu_lockup_timeout;
91extern int amdgpu_dpm;
e635ee07 92extern int amdgpu_fw_load_type;
97b2e202
AD		 93extern int amdgpu_aspm;
94extern int amdgpu_runtime_pm;
0b693f0b 95extern uint amdgpu_ip_block_mask;
97b2e202
AD		 96extern int amdgpu_bapm;
97extern int amdgpu_deep_color;
98extern int amdgpu_vm_size;
99extern int amdgpu_vm_block_size;
d07f14be 100extern int amdgpu_vm_fragment_size;
d9c13156 101extern int amdgpu_vm_fault_stop;
b495bd3a 102extern int amdgpu_vm_debug;
9a4b7d4c 103extern int amdgpu_vm_update_mode;
1333f723 104extern int amdgpu_sched_jobs;
4afcb303 105extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 106extern int amdgpu_no_evict;
107extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 108extern uint amdgpu_pcie_gen_cap;
109extern uint amdgpu_pcie_lane_cap;
110extern uint amdgpu_cg_mask;
111extern uint amdgpu_pg_mask;
112extern uint amdgpu_sdma_phase_quantum;
6f8941a2 113extern char *amdgpu_disable_cu;
9accf2fd 114extern char *amdgpu_virtual_display;
0b693f0b 115extern uint amdgpu_pp_feature_mask;
6a7f76e7 116extern int amdgpu_vram_page_split;
bce23e00
AD		 117extern int amdgpu_ngg;
118extern int amdgpu_prim_buf_per_se;
119extern int amdgpu_pos_buf_per_se;
120extern int amdgpu_cntl_sb_buf_per_se;
121extern int amdgpu_param_buf_per_se;
65781c78 122extern int amdgpu_job_hang_limit;
e8835e0e 123extern int amdgpu_lbpw;
4a75aefe 124extern int amdgpu_compute_multipipe;
97b2e202 125
6dd13096
FK		 126#ifdef CONFIG_DRM_AMDGPU_SI
127extern int amdgpu_si_support;
128#endif
7df28986
FK		 129#ifdef CONFIG_DRM_AMDGPU_CIK
130extern int amdgpu_cik_support;
131#endif
97b2e202 132
55ed8caf 133#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 134#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 135#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
136#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
137/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
138#define AMDGPU_IB_POOL_SIZE 16
139#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
140#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 141#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 142
36f523a7
JZ		 143/* max number of IP instances */
144#define AMDGPU_MAX_SDMA_INSTANCES 2
145
97b2e202
AD		 146/* hard reset data */
147#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
148
149/* reset flags */
150#define AMDGPU_RESET_GFX (1 << 0)
151#define AMDGPU_RESET_COMPUTE (1 << 1)
152#define AMDGPU_RESET_DMA (1 << 2)
153#define AMDGPU_RESET_CP (1 << 3)
154#define AMDGPU_RESET_GRBM (1 << 4)
155#define AMDGPU_RESET_DMA1 (1 << 5)
156#define AMDGPU_RESET_RLC (1 << 6)
157#define AMDGPU_RESET_SEM (1 << 7)
158#define AMDGPU_RESET_IH (1 << 8)
159#define AMDGPU_RESET_VMC (1 << 9)
160#define AMDGPU_RESET_MC (1 << 10)
161#define AMDGPU_RESET_DISPLAY (1 << 11)
162#define AMDGPU_RESET_UVD (1 << 12)
163#define AMDGPU_RESET_VCE (1 << 13)
164#define AMDGPU_RESET_VCE1 (1 << 14)
165
97b2e202
AD		 166/* GFX current status */
167#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
168#define AMDGPU_GFX_SAFE_MODE 0x00000001L
169#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
170#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
171#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
172
173/* max cursor sizes (in pixels) */
174#define CIK_CURSOR_WIDTH 128
175#define CIK_CURSOR_HEIGHT 128
176
177struct amdgpu_device;
97b2e202 178struct amdgpu_ib;
97b2e202 179struct amdgpu_cs_parser;
bb977d37 180struct amdgpu_job;
97b2e202 181struct amdgpu_irq_src;
0b492a4c 182struct amdgpu_fpriv;
9cca0b8e 183struct amdgpu_bo_va_mapping;
97b2e202
AD		 184
185enum amdgpu_cp_irq {
186 AMDGPU_CP_IRQ_GFX_EOP = 0,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
195
196 AMDGPU_CP_IRQ_LAST
197};
198
199enum amdgpu_sdma_irq {
200 AMDGPU_SDMA_IRQ_TRAP0 = 0,
201 AMDGPU_SDMA_IRQ_TRAP1,
202
203 AMDGPU_SDMA_IRQ_LAST
204};
205
206enum amdgpu_thermal_irq {
207 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
208 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
209
210 AMDGPU_THERMAL_IRQ_LAST
211};
212
4e638ae9
XY		 213enum amdgpu_kiq_irq {
214 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
215 AMDGPU_CP_KIQ_IRQ_LAST
216};
217
97b2e202 218int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 219 enum amd_ip_block_type block_type,
220 enum amd_clockgating_state state);
97b2e202 221int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 222 enum amd_ip_block_type block_type,
223 enum amd_powergating_state state);
6cb2d4e4 224void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 225int amdgpu_wait_for_idle(struct amdgpu_device *adev,
226 enum amd_ip_block_type block_type);
227bool amdgpu_is_idle(struct amdgpu_device *adev,
228 enum amd_ip_block_type block_type);
97b2e202 229
a1255107
AD		 230#define AMDGPU_MAX_IP_NUM 16
231
232struct amdgpu_ip_block_status {
233 bool valid;
234 bool sw;
235 bool hw;
236 bool late_initialized;
237 bool hang;
238};
239
97b2e202 240struct amdgpu_ip_block_version {
a1255107
AD		 241 const enum amd_ip_block_type type;
242 const u32 major;
243 const u32 minor;
244 const u32 rev;
5fc3aeeb 245 const struct amd_ip_funcs *funcs;
97b2e202
AD		 246};
247
a1255107
AD		 248struct amdgpu_ip_block {
249 struct amdgpu_ip_block_status status;
250 const struct amdgpu_ip_block_version *version;
251};
252
97b2e202 253int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 254 enum amd_ip_block_type type,
97b2e202
AD		 255 u32 major, u32 minor);
256
a1255107
AD		 257struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
258 enum amd_ip_block_type type);
259
260int amdgpu_ip_block_add(struct amdgpu_device *adev,
261 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 262
263/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
264struct amdgpu_buffer_funcs {
265 /* maximum bytes in a single operation */
266 uint32_t copy_max_bytes;
267
268 /* number of dw to reserve per operation */
269 unsigned copy_num_dw;
270
271 /* used for buffer migration */
c7ae72c0 272 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 273 /* src addr in bytes */
274 uint64_t src_offset,
275 /* dst addr in bytes */
276 uint64_t dst_offset,
277 /* number of byte to transfer */
278 uint32_t byte_count);
279
280 /* maximum bytes in a single operation */
281 uint32_t fill_max_bytes;
282
283 /* number of dw to reserve per operation */
284 unsigned fill_num_dw;
285
286 /* used for buffer clearing */
6e7a3840 287 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 288 /* value to write to memory */
289 uint32_t src_data,
290 /* dst addr in bytes */
291 uint64_t dst_offset,
292 /* number of byte to fill */
293 uint32_t byte_count);
294};
295
296/* provided by hw blocks that can write ptes, e.g., sdma */
297struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 298 /* number of dw to reserve per operation */
299 unsigned copy_pte_num_dw;
300
97b2e202
AD		 301 /* copy pte entries from GART */
302 void (*copy_pte)(struct amdgpu_ib *ib,
303 uint64_t pe, uint64_t src,
304 unsigned count);
e6d92197 305
97b2e202 306 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 307 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
308 uint64_t value, unsigned count,
309 uint32_t incr);
7bdc53f9
YZ		 310
311 /* maximum nums of PTEs/PDEs in a single operation */
312 uint32_t set_max_nums_pte_pde;
313
314 /* number of dw to reserve per operation */
315 unsigned set_pte_pde_num_dw;
316
97b2e202
AD		 317 /* for linear pte/pde updates without addr mapping */
318 void (*set_pte_pde)(struct amdgpu_ib *ib,
319 uint64_t pe,
320 uint64_t addr, unsigned count,
6b777607 321 uint32_t incr, uint64_t flags);
97b2e202
AD		 322};
323
324/* provided by the gmc block */
325struct amdgpu_gart_funcs {
326 /* flush the vm tlb via mmio */
327 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
328 uint32_t vmid);
329 /* write pte/pde updates using the cpu */
330 int (*set_pte_pde)(struct amdgpu_device *adev,
331 void *cpu_pt_addr, /* cpu addr of page table */
332 uint32_t gpu_page_idx, /* pte/pde to update */
333 uint64_t addr, /* addr to write into pte/pde */
6b777607 334 uint64_t flags); /* access flags */
284710fa
CK		 335 /* enable/disable PRT support */
336 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 337 /* set pte flags based per asic */
338 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
339 uint32_t flags);
b1166325
CK		 340 /* get the pde for a given mc addr */
341 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 342 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 343};
344
97b2e202
AD		 345/* provided by the ih block */
346struct amdgpu_ih_funcs {
347 /* ring read/write ptr handling, called from interrupt context */
348 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 349 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 350 void (*decode_iv)(struct amdgpu_device *adev,
351 struct amdgpu_iv_entry *entry);
352 void (*set_rptr)(struct amdgpu_device *adev);
353};
354
97b2e202
AD		 355/*
356 * BIOS.
357 */
358bool amdgpu_get_bios(struct amdgpu_device *adev);
359bool amdgpu_read_bios(struct amdgpu_device *adev);
360
361/*
362 * Dummy page
363 */
364struct amdgpu_dummy_page {
365 struct page *page;
366 dma_addr_t addr;
367};
368int amdgpu_dummy_page_init(struct amdgpu_device *adev);
369void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
370
371
372/*
373 * Clocks
374 */
375
376#define AMDGPU_MAX_PPLL 3
377
378struct amdgpu_clock {
379 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
380 struct amdgpu_pll spll;
381 struct amdgpu_pll mpll;
382 /* 10 Khz units */
383 uint32_t default_mclk;
384 uint32_t default_sclk;
385 uint32_t default_dispclk;
386 uint32_t current_dispclk;
387 uint32_t dp_extclk;
388 uint32_t max_pixel_clock;
389};
390
97b2e202 391/*
9124a398 392 * GEM.
97b2e202 393 */
97b2e202 394
7e5a547f 395#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 396#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
397
398void amdgpu_gem_object_free(struct drm_gem_object *obj);
399int amdgpu_gem_object_open(struct drm_gem_object *obj,
400 struct drm_file *file_priv);
401void amdgpu_gem_object_close(struct drm_gem_object *obj,
402 struct drm_file *file_priv);
403unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
404struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 405struct drm_gem_object *
406amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
407 struct dma_buf_attachment *attach,
408 struct sg_table *sg);
97b2e202
AD		 409struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
410 struct drm_gem_object *gobj,
411 int flags);
412int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
413void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
414struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
415void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
416void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 417int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 418int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
419
420/* sub-allocation manager, it has to be protected by another lock.
421 * By conception this is an helper for other part of the driver
422 * like the indirect buffer or semaphore, which both have their
423 * locking.
424 *
425 * Principe is simple, we keep a list of sub allocation in offset
426 * order (first entry has offset == 0, last entry has the highest
427 * offset).
428 *
429 * When allocating new object we first check if there is room at
430 * the end total_size - (last_object_offset + last_object_size) >=
431 * alloc_size. If so we allocate new object there.
432 *
433 * When there is not enough room at the end, we start waiting for
434 * each sub object until we reach object_offset+object_size >=
435 * alloc_size, this object then become the sub object we return.
436 *
437 * Alignment can't be bigger than page size.
438 *
439 * Hole are not considered for allocation to keep things simple.
440 * Assumption is that there won't be hole (all object on same
441 * alignment).
442 */
6ba60b89
CK		 443
444#define AMDGPU_SA_NUM_FENCE_LISTS 32
445
97b2e202
AD		 446struct amdgpu_sa_manager {
447 wait_queue_head_t wq;
448 struct amdgpu_bo *bo;
449 struct list_head *hole;
6ba60b89 450 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 451 struct list_head olist;
452 unsigned size;
453 uint64_t gpu_addr;
454 void *cpu_ptr;
455 uint32_t domain;
456 uint32_t align;
457};
458
97b2e202
AD		 459/* sub-allocation buffer */
460struct amdgpu_sa_bo {
461 struct list_head olist;
462 struct list_head flist;
463 struct amdgpu_sa_manager *manager;
464 unsigned soffset;
465 unsigned eoffset;
f54d1867 466 struct dma_fence *fence;
97b2e202
AD		 467};
468
469/*
470 * GEM objects.
471 */
418aa0c2 472void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 473int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 474 int alignment, u32 initial_domain,
475 u64 flags, bool kernel,
476 struct reservation_object *resv,
477 struct drm_gem_object **obj);
97b2e202
AD		 478
479int amdgpu_mode_dumb_create(struct drm_file *file_priv,
480 struct drm_device *dev,
481 struct drm_mode_create_dumb *args);
482int amdgpu_mode_dumb_mmap(struct drm_file *filp,
483 struct drm_device *dev,
484 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 485int amdgpu_fence_slab_init(void);
486void amdgpu_fence_slab_fini(void);
97b2e202 487
e60f8db5
AX		 488/*
489 * VMHUB structures, functions & helpers
490 */
491struct amdgpu_vmhub {
492 uint32_t ctx0_ptb_addr_lo32;
493 uint32_t ctx0_ptb_addr_hi32;
494 uint32_t vm_inv_eng0_req;
495 uint32_t vm_inv_eng0_ack;
496 uint32_t vm_context0_cntl;
497 uint32_t vm_l2_pro_fault_status;
498 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 499};
500
97b2e202
AD		 501/*
502 * GPU MC structures, functions & helpers
503 */
504struct amdgpu_mc {
505 resource_size_t aper_size;
506 resource_size_t aper_base;
507 resource_size_t agp_base;
508 /* for some chips with <= 32MB we need to lie
509 * about vram size near mc fb location */
510 u64 mc_vram_size;
511 u64 visible_vram_size;
6f02a696
CK		 512 u64 gart_size;
513 u64 gart_start;
514 u64 gart_end;
97b2e202
AD		 515 u64 vram_start;
516 u64 vram_end;
517 unsigned vram_width;
518 u64 real_vram_size;
519 int vram_mtrr;
97b2e202
AD		 520 u64 mc_mask;
521 const struct firmware *fw; /* MC firmware */
522 uint32_t fw_version;
523 struct amdgpu_irq_src vm_fault;
81c59f54 524 uint32_t vram_type;
50b0197a 525 uint32_t srbm_soft_reset;
f7c35abe 526 bool prt_warning;
916910ad 527 uint64_t stolen_size;
8fe73328
JZ		 528 /* apertures */
529 u64 shared_aperture_start;
530 u64 shared_aperture_end;
531 u64 private_aperture_start;
532 u64 private_aperture_end;
e60f8db5
AX		 533 /* protects concurrent invalidation */
534 spinlock_t invalidate_lock;
97b2e202
AD		 535};
536
537/*
538 * GPU doorbell structures, functions & helpers
539 */
540typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
541{
542 AMDGPU_DOORBELL_KIQ = 0x000,
543 AMDGPU_DOORBELL_HIQ = 0x001,
544 AMDGPU_DOORBELL_DIQ = 0x002,
545 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
546 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
547 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
548 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
549 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
550 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
551 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
552 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
553 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
554 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
555 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
556 AMDGPU_DOORBELL_IH = 0x1E8,
557 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
558 AMDGPU_DOORBELL_INVALID = 0xFFFF
559} AMDGPU_DOORBELL_ASSIGNMENT;
560
561struct amdgpu_doorbell {
562 /* doorbell mmio */
563 resource_size_t base;
564 resource_size_t size;
565 u32 __iomem *ptr;
566 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
567};
568
39807b93
KW		 569/*
570 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
571 */
572typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
573{
574 /*
575 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
576 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
577 * Compute related doorbells are allocated from 0x00 to 0x8a
578 */
579
580
581 /* kernel scheduling */
582 AMDGPU_DOORBELL64_KIQ = 0x00,
583
584 /* HSA interface queue and debug queue */
585 AMDGPU_DOORBELL64_HIQ = 0x01,
586 AMDGPU_DOORBELL64_DIQ = 0x02,
587
588 /* Compute engines */
589 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
590 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
591 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
592 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
593 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
594 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
595 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
596 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
597
598 /* User queue doorbell range (128 doorbells) */
599 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
600 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
601
602 /* Graphics engine */
603 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
604
605 /*
606 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
607 * Graphics voltage island aperture 1
608 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
609 */
610
611 /* sDMA engines */
612 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
613 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
614 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
615 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
616
617 /* Interrupt handler */
618 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
619 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
620 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
621
e6b3ecb4
ML		 622 /* VCN engine use 32 bits doorbell */
623 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
624 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
625 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
626 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
627
628 /* overlap the doorbell assignment with VCN as they are mutually exclusive
629 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
630 */
4ed11d79
FM		 631 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
632 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
633 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
634 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
635
636 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
637 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
638 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
639 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 640
641 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
642 AMDGPU_DOORBELL64_INVALID = 0xFFFF
643} AMDGPU_DOORBELL64_ASSIGNMENT;
644
645
97b2e202
AD		 646void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
647 phys_addr_t *aperture_base,
648 size_t *aperture_size,
649 size_t *start_offset);
650
651/*
652 * IRQS.
653 */
654
655struct amdgpu_flip_work {
325cbba1 656 struct delayed_work flip_work;
97b2e202
AD		 657 struct work_struct unpin_work;
658 struct amdgpu_device *adev;
659 int crtc_id;
325cbba1 660 u32 target_vblank;
97b2e202
AD		 661 uint64_t base;
662 struct drm_pending_vblank_event *event;
765e7fbf 663 struct amdgpu_bo *old_abo;
f54d1867 664 struct dma_fence *excl;
1ffd2652 665 unsigned shared_count;
f54d1867
CW		 666 struct dma_fence **shared;
667 struct dma_fence_cb cb;
cb9e59d7 668 bool async;
97b2e202
AD		 669};
670
671
672/*
673 * CP & rings.
674 */
675
676struct amdgpu_ib {
677 struct amdgpu_sa_bo *sa_bo;
678 uint32_t length_dw;
679 uint64_t gpu_addr;
680 uint32_t *ptr;
de807f81 681 uint32_t flags;
97b2e202
AD		 682};
683
62250a91 684extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 685
50838c8c 686int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 687 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 688int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
689 struct amdgpu_job **job);
b6723c8d 690
a5fb4ec2 691void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 692void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 693int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 694 struct amd_sched_entity *entity, void *owner,
f54d1867 695 struct dma_fence **f);
8b4fb00b 696
effd924d
AR		 697/*
698 * Queue manager
699 */
700struct amdgpu_queue_mapper {
701 int hw_ip;
702 struct mutex lock;
703 /* protected by lock */
704 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
705};
706
707struct amdgpu_queue_mgr {
708 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
709};
710
711int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
712 struct amdgpu_queue_mgr *mgr);
713int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
714 struct amdgpu_queue_mgr *mgr);
715int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
716 struct amdgpu_queue_mgr *mgr,
717 int hw_ip, int instance, int ring,
718 struct amdgpu_ring **out_ring);
719
97b2e202
AD		 720/*
721 * context related structures
722 */
723
21c16bf6 724struct amdgpu_ctx_ring {
91404fb2 725 uint64_t sequence;
f54d1867 726 struct dma_fence **fences;
91404fb2 727 struct amd_sched_entity entity;
21c16bf6
CK		 728};
729
97b2e202 730struct amdgpu_ctx {
0b492a4c 731 struct kref refcount;
9cb7e5a9 732 struct amdgpu_device *adev;
effd924d 733 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 734 unsigned reset_counter;
21c16bf6 735 spinlock_t ring_lock;
f54d1867 736 struct dma_fence **fences;
21c16bf6 737 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
c23be4ae
AR		 738 bool preamble_presented;
739 enum amd_sched_priority init_priority;
740 enum amd_sched_priority override_priority;
0ae94444 741 struct mutex lock;
97b2e202
AD		 742};
743
744struct amdgpu_ctx_mgr {
0b492a4c
AD		 745 struct amdgpu_device *adev;
746 struct mutex lock;
747 /* protected by lock */
748 struct idr ctx_handles;
97b2e202
AD		 749};
750
0b492a4c
AD		 751struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
752int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
753
eb01abc7
ML		 754int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
755 struct dma_fence *fence, uint64_t *seq);
f54d1867 756struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 757 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae
AR		 758void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
759 enum amd_sched_priority priority);
21c16bf6 760
0b492a4c
AD		 761int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
762 struct drm_file *filp);
763
0ae94444
AG		 764int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
765
efd4ccb5
CK		 766void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
767void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 768
0ae94444 769
97b2e202
AD		 770/*
771 * file private structure
772 */
773
774struct amdgpu_fpriv {
775 struct amdgpu_vm vm;
b85891bd 776 struct amdgpu_bo_va *prt_va;
0f4b3c68 777 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 778 struct mutex bo_list_lock;
779 struct idr bo_list_handles;
0b492a4c 780 struct amdgpu_ctx_mgr ctx_mgr;
f1892138 781 u32 vram_lost_counter;
97b2e202
AD		 782};
783
784/*
785 * residency list
786 */
9124a398
CK		 787struct amdgpu_bo_list_entry {
788 struct amdgpu_bo *robj;
789 struct ttm_validate_buffer tv;
790 struct amdgpu_bo_va *bo_va;
791 uint32_t priority;
792 struct page **user_pages;
793 int user_invalidated;
794};
97b2e202
AD		 795
796struct amdgpu_bo_list {
797 struct mutex lock;
5ac55629
AX		 798 struct rcu_head rhead;
799 struct kref refcount;
97b2e202
AD		 800 struct amdgpu_bo *gds_obj;
801 struct amdgpu_bo *gws_obj;
802 struct amdgpu_bo *oa_obj;
211dff55 803 unsigned first_userptr;
97b2e202
AD		 804 unsigned num_entries;
805 struct amdgpu_bo_list_entry *array;
806};
807
808struct amdgpu_bo_list *
809amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 810void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
811 struct list_head *validated);
97b2e202
AD		 812void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
813void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
814
815/*
816 * GFX stuff
817 */
818#include "clearstate_defs.h"
819
79e5412c
AD		 820struct amdgpu_rlc_funcs {
821 void (*enter_safe_mode)(struct amdgpu_device *adev);
822 void (*exit_safe_mode)(struct amdgpu_device *adev);
823};
824
97b2e202
AD		 825struct amdgpu_rlc {
826 /* for power gating */
827 struct amdgpu_bo *save_restore_obj;
828 uint64_t save_restore_gpu_addr;
829 volatile uint32_t *sr_ptr;
830 const u32 *reg_list;
831 u32 reg_list_size;
832 /* for clear state */
833 struct amdgpu_bo *clear_state_obj;
834 uint64_t clear_state_gpu_addr;
835 volatile uint32_t *cs_ptr;
836 const struct cs_section_def *cs_data;
837 u32 clear_state_size;
838 /* for cp tables */
839 struct amdgpu_bo *cp_table_obj;
840 uint64_t cp_table_gpu_addr;
841 volatile uint32_t *cp_table_ptr;
842 u32 cp_table_size;
79e5412c
AD		 843
844 /* safe mode for updating CG/PG state */
845 bool in_safe_mode;
846 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 847
848 /* for firmware data */
849 u32 save_and_restore_offset;
850 u32 clear_state_descriptor_offset;
851 u32 avail_scratch_ram_locations;
852 u32 reg_restore_list_size;
853 u32 reg_list_format_start;
854 u32 reg_list_format_separate_start;
855 u32 starting_offsets_start;
856 u32 reg_list_format_size_bytes;
857 u32 reg_list_size_bytes;
858
859 u32 *register_list_format;
860 u32 *register_restore;
97b2e202
AD		 861};
862
78c16834
AR		 863#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
864
97b2e202
AD		 865struct amdgpu_mec {
866 struct amdgpu_bo *hpd_eop_obj;
867 u64 hpd_eop_gpu_addr;
b1023571
KW		 868 struct amdgpu_bo *mec_fw_obj;
869 u64 mec_fw_gpu_addr;
97b2e202 870 u32 num_mec;
42794b27
AR		 871 u32 num_pipe_per_mec;
872 u32 num_queue_per_pipe;
59a82d7d 873 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 874
875 /* These are the resources for which amdgpu takes ownership */
876 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 877};
878
4e638ae9
XY		 879struct amdgpu_kiq {
880 u64 eop_gpu_addr;
881 struct amdgpu_bo *eop_obj;
cdf6adb2 882 struct mutex ring_mutex;
4e638ae9
XY		 883 struct amdgpu_ring ring;
884 struct amdgpu_irq_src irq;
885};
886
97b2e202
AD		 887/*
888 * GPU scratch registers structures, functions & helpers
889 */
890struct amdgpu_scratch {
891 unsigned num_reg;
892 uint32_t reg_base;
50261151 893 uint32_t free_mask;
97b2e202
AD		 894};
895
896/*
897 * GFX configurations
898 */
e3fa7630
AD		 899#define AMDGPU_GFX_MAX_SE 4
900#define AMDGPU_GFX_MAX_SH_PER_SE 2
901
902struct amdgpu_rb_config {
903 uint32_t rb_backend_disable;
904 uint32_t user_rb_backend_disable;
905 uint32_t raster_config;
906 uint32_t raster_config_1;
907};
908
d0e95758
AG		 909struct gb_addr_config {
910 uint16_t pipe_interleave_size;
911 uint8_t num_pipes;
912 uint8_t max_compress_frags;
913 uint8_t num_banks;
914 uint8_t num_se;
915 uint8_t num_rb_per_se;
916};
917
ea323f88 918struct amdgpu_gfx_config {
97b2e202
AD		 919 unsigned max_shader_engines;
920 unsigned max_tile_pipes;
921 unsigned max_cu_per_sh;
922 unsigned max_sh_per_se;
923 unsigned max_backends_per_se;
924 unsigned max_texture_channel_caches;
925 unsigned max_gprs;
926 unsigned max_gs_threads;
927 unsigned max_hw_contexts;
928 unsigned sc_prim_fifo_size_frontend;
929 unsigned sc_prim_fifo_size_backend;
930 unsigned sc_hiz_tile_fifo_size;
931 unsigned sc_earlyz_tile_fifo_size;
932
933 unsigned num_tile_pipes;
934 unsigned backend_enable_mask;
935 unsigned mem_max_burst_length_bytes;
936 unsigned mem_row_size_in_kb;
937 unsigned shader_engine_tile_size;
938 unsigned num_gpus;
939 unsigned multi_gpu_tile_size;
940 unsigned mc_arb_ramcfg;
941 unsigned gb_addr_config;
8f8e00c1 942 unsigned num_rbs;
408bfe7c
JZ		 943 unsigned gs_vgt_table_depth;
944 unsigned gs_prim_buffer_depth;
97b2e202
AD		 945
946 uint32_t tile_mode_array[32];
947 uint32_t macrotile_mode_array[16];
e3fa7630 948
d0e95758 949 struct gb_addr_config gb_addr_config_fields;
e3fa7630 950 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 951
952 /* gfx configure feature */
953 uint32_t double_offchip_lds_buf;
97b2e202
AD		 954};
955
7dae69a2 956struct amdgpu_cu_info {
51fd0370 957 uint32_t max_waves_per_simd;
408bfe7c 958 uint32_t wave_front_size;
51fd0370
HZ		 959 uint32_t max_scratch_slots_per_cu;
960 uint32_t lds_size;
dbfe85ea
FC		 961
962 /* total active CU number */
963 uint32_t number;
964 uint32_t ao_cu_mask;
965 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 966 uint32_t bitmap[4][4];
967};
968
b95e31fd
AD		 969struct amdgpu_gfx_funcs {
970 /* get the gpu clock counter */
971 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 972 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 973 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 974 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
975 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 976};
977
bce23e00
AD		 978struct amdgpu_ngg_buf {
979 struct amdgpu_bo *bo;
980 uint64_t gpu_addr;
981 uint32_t size;
982 uint32_t bo_size;
983};
984
985enum {
af8baf15
GR		 986 NGG_PRIM = 0,
987 NGG_POS,
988 NGG_CNTL,
989 NGG_PARAM,
bce23e00
AD		 990 NGG_BUF_MAX
991};
992
993struct amdgpu_ngg {
994 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
995 uint32_t gds_reserve_addr;
996 uint32_t gds_reserve_size;
997 bool init;
998};
999
97b2e202
AD		 1000struct amdgpu_gfx {
1001 struct mutex gpu_clock_mutex;
ea323f88 1002 struct amdgpu_gfx_config config;
97b2e202
AD		 1003 struct amdgpu_rlc rlc;
1004 struct amdgpu_mec mec;
4e638ae9 1005 struct amdgpu_kiq kiq;
97b2e202
AD		 1006 struct amdgpu_scratch scratch;
1007 const struct firmware *me_fw; /* ME firmware */
1008 uint32_t me_fw_version;
1009 const struct firmware *pfp_fw; /* PFP firmware */
1010 uint32_t pfp_fw_version;
1011 const struct firmware *ce_fw; /* CE firmware */
1012 uint32_t ce_fw_version;
1013 const struct firmware *rlc_fw; /* RLC firmware */
1014 uint32_t rlc_fw_version;
1015 const struct firmware *mec_fw; /* MEC firmware */
1016 uint32_t mec_fw_version;
1017 const struct firmware *mec2_fw; /* MEC2 firmware */
1018 uint32_t mec2_fw_version;
02558a00
KW		 1019 uint32_t me_feature_version;
1020 uint32_t ce_feature_version;
1021 uint32_t pfp_feature_version;
351643d7
JZ		 1022 uint32_t rlc_feature_version;
1023 uint32_t mec_feature_version;
1024 uint32_t mec2_feature_version;
97b2e202
AD		 1025 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1026 unsigned num_gfx_rings;
1027 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1028 unsigned num_compute_rings;
1029 struct amdgpu_irq_src eop_irq;
1030 struct amdgpu_irq_src priv_reg_irq;
1031 struct amdgpu_irq_src priv_inst_irq;
1032 /* gfx status */
7dae69a2 1033 uint32_t gfx_current_status;
a101a899 1034 /* ce ram size*/
7dae69a2
AD		 1035 unsigned ce_ram_size;
1036 struct amdgpu_cu_info cu_info;
b95e31fd 1037 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1038
1039 /* reset mask */
1040 uint32_t grbm_soft_reset;
1041 uint32_t srbm_soft_reset;
b4e40676
DP		 1042 /* s3/s4 mask */
1043 bool in_suspend;
bce23e00
AD		 1044 /* NGG */
1045 struct amdgpu_ngg ngg;
b8866c26
AR		 1046
1047 /* pipe reservation */
1048 struct mutex pipe_reserve_mutex;
1049 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 1050};
1051
b07c60c0 1052int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1053 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1054void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1055 struct dma_fence *f);
b07c60c0 1056int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1057 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1058 struct dma_fence **f);
97b2e202
AD		 1059int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1060void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1061int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1062
1063/*
1064 * CS.
1065 */
1066struct amdgpu_cs_chunk {
1067 uint32_t chunk_id;
1068 uint32_t length_dw;
758ac17f 1069 void *kdata;
97b2e202
AD		 1070};
1071
1072struct amdgpu_cs_parser {
1073 struct amdgpu_device *adev;
1074 struct drm_file *filp;
3cb485f3 1075 struct amdgpu_ctx *ctx;
c3cca41e 1076
97b2e202
AD		 1077 /* chunks */
1078 unsigned nchunks;
1079 struct amdgpu_cs_chunk *chunks;
97b2e202 1080
50838c8c
CK		 1081 /* scheduler job object */
1082 struct amdgpu_job *job;
97b2e202 1083
c3cca41e
CK		 1084 /* buffer objects */
1085 struct ww_acquire_ctx ticket;
1086 struct amdgpu_bo_list *bo_list;
3fe89771 1087 struct amdgpu_mn *mn;
c3cca41e
CK		 1088 struct amdgpu_bo_list_entry vm_pd;
1089 struct list_head validated;
f54d1867 1090 struct dma_fence *fence;
c3cca41e 1091 uint64_t bytes_moved_threshold;
00f06b24 1092 uint64_t bytes_moved_vis_threshold;
c3cca41e 1093 uint64_t bytes_moved;
00f06b24 1094 uint64_t bytes_moved_vis;
662bfa61 1095 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1096
1097 /* user fence */
91acbeb6 1098 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1099
1100 unsigned num_post_dep_syncobjs;
1101 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1102};
1103
753ad49c
ML		 1104#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1105#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1106#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1107
bb977d37
CZ		 1108struct amdgpu_job {
1109 struct amd_sched_job base;
1110 struct amdgpu_device *adev;
edf600da 1111 struct amdgpu_vm *vm;
b07c60c0 1112 struct amdgpu_ring *ring;
e86f9cee 1113 struct amdgpu_sync sync;
a340c7bc 1114 struct amdgpu_sync dep_sync;
df83d1eb 1115 struct amdgpu_sync sched_sync;
bb977d37 1116 struct amdgpu_ib *ibs;
f54d1867 1117 struct dma_fence *fence; /* the hw fence */
753ad49c 1118 uint32_t preamble_status;
bb977d37 1119 uint32_t num_ibs;
e2840221 1120 void *owner;
3aecd24c 1121 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1122 bool vm_needs_flush;
d88bf583
CK		 1123 unsigned vm_id;
1124 uint64_t vm_pd_addr;
1125 uint32_t gds_base, gds_size;
1126 uint32_t gws_base, gws_size;
1127 uint32_t oa_base, oa_size;
758ac17f
CK		 1128
1129 /* user fence handling */
b5f5acbc 1130 uint64_t uf_addr;
758ac17f
CK		 1131 uint64_t uf_sequence;
1132
bb977d37 1133};
a6db8a33
JZ		 1134#define to_amdgpu_job(sched_job) \
1135 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1136
7270f839
CK		 1137static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1138 uint32_t ib_idx, int idx)
97b2e202 1139{
50838c8c 1140 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1141}
1142
7270f839
CK		 1143static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1144 uint32_t ib_idx, int idx,
1145 uint32_t value)
1146{
50838c8c 1147 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1148}
1149
97b2e202
AD		 1150/*
1151 * Writeback
1152 */
1153#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1154
1155struct amdgpu_wb {
1156 struct amdgpu_bo *wb_obj;
1157 volatile uint32_t *wb;
1158 uint64_t gpu_addr;
1159 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1160 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1161};
1162
1163int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1164void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1165
d0dd7f0c
AD		 1166void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1167
97b2e202
AD		 1168/*
1169 * SDMA
1170 */
c113ea1c 1171struct amdgpu_sdma_instance {
97b2e202
AD		 1172 /* SDMA firmware */
1173 const struct firmware *fw;
1174 uint32_t fw_version;
cfa2104f 1175 uint32_t feature_version;
97b2e202
AD		 1176
1177 struct amdgpu_ring ring;
18111de0 1178 bool burst_nop;
97b2e202
AD		 1179};
1180
c113ea1c
AD		 1181struct amdgpu_sdma {
1182 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1183#ifdef CONFIG_DRM_AMDGPU_SI
1184 //SI DMA has a difference trap irq number for the second engine
1185 struct amdgpu_irq_src trap_irq_1;
1186#endif
c113ea1c
AD		 1187 struct amdgpu_irq_src trap_irq;
1188 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1189 int num_instances;
e702a680 1190 uint32_t srbm_soft_reset;
c113ea1c
AD		 1191};
1192
97b2e202
AD		 1193/*
1194 * Firmware
1195 */
e635ee07
HR		 1196enum amdgpu_firmware_load_type {
1197 AMDGPU_FW_LOAD_DIRECT = 0,
1198 AMDGPU_FW_LOAD_SMU,
1199 AMDGPU_FW_LOAD_PSP,
1200};
1201
97b2e202
AD		 1202struct amdgpu_firmware {
1203 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1204 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1205 struct amdgpu_bo *fw_buf;
1206 unsigned int fw_size;
2445b227 1207 unsigned int max_ucodes;
0e5ca0d1
HR		 1208 /* firmwares are loaded by psp instead of smu from vega10 */
1209 const struct amdgpu_psp_funcs *funcs;
1210 struct amdgpu_bo *rbuf;
1211 struct mutex mutex;
ab4fe3e1
HR		 1212
1213 /* gpu info firmware data pointer */
1214 const struct firmware *gpu_info_fw;
d59c026b
ML		 1215
1216 void *fw_buf_ptr;
1217 uint64_t fw_buf_mc;
97b2e202
AD		 1218};
1219
1220/*
1221 * Benchmarking
1222 */
1223void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1224
1225
1226/*
1227 * Testing
1228 */
1229void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1230
97b2e202
AD		 1231/*
1232 * Debugfs
1233 */
1234struct amdgpu_debugfs {
06ab6832 1235 const struct drm_info_list *files;
97b2e202
AD		 1236 unsigned num_files;
1237};
1238
1239int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1240 const struct drm_info_list *files,
97b2e202
AD		 1241 unsigned nfiles);
1242int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1243
1244#if defined(CONFIG_DEBUG_FS)
1245int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1246#endif
1247
50ab2533
HR		 1248int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1249
97b2e202
AD		 1250/*
1251 * amdgpu smumgr functions
1252 */
1253struct amdgpu_smumgr_funcs {
1254 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1255 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1256 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1257};
1258
1259/*
1260 * amdgpu smumgr
1261 */
1262struct amdgpu_smumgr {
1263 struct amdgpu_bo *toc_buf;
1264 struct amdgpu_bo *smu_buf;
1265 /* asic priv smu data */
1266 void *priv;
1267 spinlock_t smu_lock;
1268 /* smumgr functions */
1269 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1270 /* ucode loading complete flag */
1271 uint32_t fw_flags;
1272};
1273
1274/*
1275 * ASIC specific register table accessible by UMD
1276 */
1277struct amdgpu_allowed_register_entry {
1278 uint32_t reg_offset;
97b2e202
AD		 1279 bool grbm_indexed;
1280};
1281
97b2e202
AD		 1282/*
1283 * ASIC specific functions.
1284 */
1285struct amdgpu_asic_funcs {
1286 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1287 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1288 u8 *bios, u32 length_bytes);
97b2e202
AD		 1289 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1290 u32 sh_num, u32 reg_offset, u32 *value);
1291 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1292 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1293 /* get the reference clock */
1294 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1295 /* MM block clocks */
1296 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1297 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1298 /* static power management */
1299 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1300 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1301 /* get config memsize register */
1302 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1303};
1304
1305/*
1306 * IOCTL.
1307 */
1308int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1309 struct drm_file *filp);
1310int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1311 struct drm_file *filp);
1312
1313int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1314 struct drm_file *filp);
1315int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *filp);
1317int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1318 struct drm_file *filp);
1319int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *filp);
1321int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
1323int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *filp);
1325int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1326int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *filp);
97b2e202 1328int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1329int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1330 struct drm_file *filp);
97b2e202
AD		 1331
1332int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1333 struct drm_file *filp);
1334
1335/* VRAM scratch page for HDP bug, default vram page */
1336struct amdgpu_vram_scratch {
1337 struct amdgpu_bo *robj;
1338 volatile uint32_t *ptr;
1339 u64 gpu_addr;
1340};
1341
1342/*
1343 * ACPI
1344 */
1345struct amdgpu_atif_notification_cfg {
1346 bool enabled;
1347 int command_code;
1348};
1349
1350struct amdgpu_atif_notifications {
1351 bool display_switch;
1352 bool expansion_mode_change;
1353 bool thermal_state;
1354 bool forced_power_state;
1355 bool system_power_state;
1356 bool display_conf_change;
1357 bool px_gfx_switch;
1358 bool brightness_change;
1359 bool dgpu_display_event;
1360};
1361
1362struct amdgpu_atif_functions {
1363 bool system_params;
1364 bool sbios_requests;
1365 bool select_active_disp;
1366 bool lid_state;
1367 bool get_tv_standard;
1368 bool set_tv_standard;
1369 bool get_panel_expansion_mode;
1370 bool set_panel_expansion_mode;
1371 bool temperature_change;
1372 bool graphics_device_types;
1373};
1374
1375struct amdgpu_atif {
1376 struct amdgpu_atif_notifications notifications;
1377 struct amdgpu_atif_functions functions;
1378 struct amdgpu_atif_notification_cfg notification_cfg;
1379 struct amdgpu_encoder *encoder_for_bl;
1380};
1381
1382struct amdgpu_atcs_functions {
1383 bool get_ext_state;
1384 bool pcie_perf_req;
1385 bool pcie_dev_rdy;
1386 bool pcie_bus_width;
1387};
1388
1389struct amdgpu_atcs {
1390 struct amdgpu_atcs_functions functions;
1391};
1392
a05502e5
HC		 1393/*
1394 * Firmware VRAM reservation
1395 */
1396struct amdgpu_fw_vram_usage {
1397 u64 start_offset;
1398 u64 size;
1399 struct amdgpu_bo *reserved_bo;
1400 void *va;
1401};
1402
1403int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
1404
d03846af
CZ		 1405/*
1406 * CGS
1407 */
110e6f26
DA		 1408struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1409void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1410
97b2e202
AD		 1411/*
1412 * Core structure, functions and helpers.
1413 */
1414typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1415typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1416
1417typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1418typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1419
0c49e0b8 1420#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1421struct amdgpu_device {
1422 struct device *dev;
1423 struct drm_device *ddev;
1424 struct pci_dev *pdev;
97b2e202 1425
a8fe58ce
MB		 1426#ifdef CONFIG_DRM_AMD_ACP
1427 struct amdgpu_acp acp;
1428#endif
1429
97b2e202 1430 /* ASIC */
2f7d10b3 1431 enum amd_asic_type asic_type;
97b2e202
AD		 1432 uint32_t family;
1433 uint32_t rev_id;
1434 uint32_t external_rev_id;
1435 unsigned long flags;
1436 int usec_timeout;
1437 const struct amdgpu_asic_funcs *asic_funcs;
1438 bool shutdown;
97b2e202
AD		 1439 bool need_dma32;
1440 bool accel_working;
edf600da 1441 struct work_struct reset_work;
97b2e202
AD		 1442 struct notifier_block acpi_nb;
1443 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1444 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1445 unsigned debugfs_count;
97b2e202 1446#if defined(CONFIG_DEBUG_FS)
adcec288 1447 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1448#endif
1449 struct amdgpu_atif atif;
1450 struct amdgpu_atcs atcs;
1451 struct mutex srbm_mutex;
1452 /* GRBM index mutex. Protects concurrent access to GRBM index */
1453 struct mutex grbm_idx_mutex;
1454 struct dev_pm_domain vga_pm_domain;
1455 bool have_disp_power_ref;
1456
1457 /* BIOS */
0cdd5005 1458 bool is_atom_fw;
97b2e202 1459 uint8_t *bios;
a9f5db9c 1460 uint32_t bios_size;
5af2c10d 1461 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1462 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1463 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1464
1465 /* Register/doorbell mmio */
1466 resource_size_t rmmio_base;
1467 resource_size_t rmmio_size;
1468 void __iomem *rmmio;
1469 /* protects concurrent MM_INDEX/DATA based register access */
1470 spinlock_t mmio_idx_lock;
1471 /* protects concurrent SMC based register access */
1472 spinlock_t smc_idx_lock;
1473 amdgpu_rreg_t smc_rreg;
1474 amdgpu_wreg_t smc_wreg;
1475 /* protects concurrent PCIE register access */
1476 spinlock_t pcie_idx_lock;
1477 amdgpu_rreg_t pcie_rreg;
1478 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1479 amdgpu_rreg_t pciep_rreg;
1480 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1481 /* protects concurrent UVD register access */
1482 spinlock_t uvd_ctx_idx_lock;
1483 amdgpu_rreg_t uvd_ctx_rreg;
1484 amdgpu_wreg_t uvd_ctx_wreg;
1485 /* protects concurrent DIDT register access */
1486 spinlock_t didt_idx_lock;
1487 amdgpu_rreg_t didt_rreg;
1488 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1489 /* protects concurrent gc_cac register access */
1490 spinlock_t gc_cac_idx_lock;
1491 amdgpu_rreg_t gc_cac_rreg;
1492 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1493 /* protects concurrent se_cac register access */
1494 spinlock_t se_cac_idx_lock;
1495 amdgpu_rreg_t se_cac_rreg;
1496 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1497 /* protects concurrent ENDPOINT (audio) register access */
1498 spinlock_t audio_endpt_idx_lock;
1499 amdgpu_block_rreg_t audio_endpt_rreg;
1500 amdgpu_block_wreg_t audio_endpt_wreg;
1501 void __iomem *rio_mem;
1502 resource_size_t rio_mem_size;
1503 struct amdgpu_doorbell doorbell;
1504
1505 /* clock/pll info */
1506 struct amdgpu_clock clock;
1507
1508 /* MC */
1509 struct amdgpu_mc mc;
1510 struct amdgpu_gart gart;
1511 struct amdgpu_dummy_page dummy_page;
1512 struct amdgpu_vm_manager vm_manager;
e60f8db5 1513 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1514
1515 /* memory management */
1516 struct amdgpu_mman mman;
97b2e202
AD		 1517 struct amdgpu_vram_scratch vram_scratch;
1518 struct amdgpu_wb wb;
97b2e202 1519 atomic64_t num_bytes_moved;
dbd5ed60 1520 atomic64_t num_evictions;
68e2c5ff 1521 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1522 atomic_t gpu_reset_counter;
f1892138 1523 atomic_t vram_lost_counter;
97b2e202 1524
95844d20
MO		 1525 /* data for buffer migration throttling */
1526 struct {
1527 spinlock_t lock;
1528 s64 last_update_us;
1529 s64 accum_us; /* accumulated microseconds */
00f06b24 1530 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1531 u32 log2_max_MBps;
1532 } mm_stats;
1533
97b2e202 1534 /* display */
9accf2fd 1535 bool enable_virtual_display;
97b2e202
AD		 1536 struct amdgpu_mode_info mode_info;
1537 struct work_struct hotplug_work;
1538 struct amdgpu_irq_src crtc_irq;
1539 struct amdgpu_irq_src pageflip_irq;
1540 struct amdgpu_irq_src hpd_irq;
1541
1542 /* rings */
76bf0db5 1543 u64 fence_context;
97b2e202
AD		 1544 unsigned num_rings;
1545 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1546 bool ib_pool_ready;
1547 struct amdgpu_sa_manager ring_tmp_bo;
1548
1549 /* interrupts */
1550 struct amdgpu_irq irq;
1551
1f7371b2
AD		 1552 /* powerplay */
1553 struct amd_powerplay powerplay;
f3898ea1 1554 bool pp_force_state_enabled;
1f7371b2 1555
97b2e202
AD		 1556 /* dpm */
1557 struct amdgpu_pm pm;
1558 u32 cg_flags;
1559 u32 pg_flags;
1560
1561 /* amdgpu smumgr */
1562 struct amdgpu_smumgr smu;
1563
1564 /* gfx */
1565 struct amdgpu_gfx gfx;
1566
1567 /* sdma */
c113ea1c 1568 struct amdgpu_sdma sdma;
97b2e202 1569
95d0906f
LL		 1570 union {
1571 struct {
1572 /* uvd */
1573 struct amdgpu_uvd uvd;
1574
1575 /* vce */
1576 struct amdgpu_vce vce;
1577 };
97b2e202 1578
95d0906f
LL		 1579 /* vcn */
1580 struct amdgpu_vcn vcn;
1581 };
97b2e202
AD		 1582
1583 /* firmwares */
1584 struct amdgpu_firmware firmware;
1585
0e5ca0d1
HR		 1586 /* PSP */
1587 struct psp_context psp;
1588
97b2e202
AD		 1589 /* GDS */
1590 struct amdgpu_gds gds;
1591
a1255107 1592 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1593 int num_ip_blocks;
97b2e202
AD		 1594 struct mutex mn_lock;
1595 DECLARE_HASHTABLE(mn_hash, 7);
1596
1597 /* tracking pinned memory */
1598 u64 vram_pin_size;
e131b914 1599 u64 invisible_pin_size;
97b2e202 1600 u64 gart_pin_size;
130e0371
OG		 1601
1602 /* amdkfd interface */
1603 struct kfd_dev *kfd;
23ca0e4e 1604
2dc80b00
S		 1605 /* delayed work_func for deferring clockgating during resume */
1606 struct delayed_work late_init_work;
1607
5a5099cb 1608 struct amdgpu_virt virt;
a05502e5
HC		 1609 /* firmware VRAM reservation */
1610 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1611
1612 /* link all shadow bo */
1613 struct list_head shadow_list;
1614 struct mutex shadow_list_lock;
5c1354bd
CZ		 1615 /* link all gtt */
1616 spinlock_t gtt_list_lock;
1617 struct list_head gtt_list;
795f2813
AR		 1618 /* keep an lru list of rings by HW IP */
1619 struct list_head ring_lru_list;
1620 spinlock_t ring_lru_list_lock;
5c1354bd 1621
c836fec5
JQ		 1622 /* record hw reset is performed */
1623 bool has_hw_reset;
0c49e0b8 1624 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1625
47ed4e1c
KW		 1626 /* record last mm index being written through WREG32*/
1627 unsigned long last_mm_index;
3224a12b 1628 bool in_sriov_reset;
97b2e202
AD		 1629};
1630
a7d64de6
CK		 1631static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1632{
1633 return container_of(bdev, struct amdgpu_device, mman.bdev);
1634}
1635
97b2e202
AD		 1636int amdgpu_device_init(struct amdgpu_device *adev,
1637 struct drm_device *ddev,
1638 struct pci_dev *pdev,
1639 uint32_t flags);
1640void amdgpu_device_fini(struct amdgpu_device *adev);
1641int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1642
1643uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1644 uint32_t acc_flags);
97b2e202 1645void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1646 uint32_t acc_flags);
97b2e202
AD		 1647u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1648void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1649
1650u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1651void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1652u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1653void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1654
97b2e202
AD		 1655/*
1656 * Registers read & write functions.
1657 */
15d72fd7
ML		 1658
1659#define AMDGPU_REGS_IDX (1<<0)
1660#define AMDGPU_REGS_NO_KIQ (1<<1)
1661
1662#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1663#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1664
1665#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1666#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1667#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1668#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1669#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1670#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1671#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1672#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1673#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1674#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1675#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1676#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1677#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1678#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1679#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1680#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1681#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1682#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1683#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1684#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1685#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1686#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1687#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1688#define WREG32_P(reg, val, mask) \
1689 do { \
1690 uint32_t tmp_ = RREG32(reg); \
1691 tmp_ &= (mask); \
1692 tmp_ |= ((val) & ~(mask)); \
1693 WREG32(reg, tmp_); \
1694 } while (0)
1695#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1696#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1697#define WREG32_PLL_P(reg, val, mask) \
1698 do { \
1699 uint32_t tmp_ = RREG32_PLL(reg); \
1700 tmp_ &= (mask); \
1701 tmp_ |= ((val) & ~(mask)); \
1702 WREG32_PLL(reg, tmp_); \
1703 } while (0)
1704#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1705#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1706#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1707
1708#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1709#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1710#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1711#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1712
1713#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1714#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1715
1716#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1717 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1718 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1719
1720#define REG_GET_FIELD(value, reg, field) \
1721 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1722
1723#define WREG32_FIELD(reg, field, val) \
1724 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1725
ccaf3574
TSD		 1726#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1727 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1728
97b2e202
AD		 1729/*
1730 * BIOS helpers.
1731 */
1732#define RBIOS8(i) (adev->bios[i])
1733#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1734#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1735
c113ea1c
AD		 1736static inline struct amdgpu_sdma_instance *
1737amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1738{
1739 struct amdgpu_device *adev = ring->adev;
1740 int i;
1741
c113ea1c
AD		 1742 for (i = 0; i < adev->sdma.num_instances; i++)
1743 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1744 break;
1745
1746 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1747 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1748 else
1749 return NULL;
1750}
1751
97b2e202
AD		 1752/*
1753 * ASICs macro.
1754 */
1755#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1756#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1757#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1758#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1759#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1760#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1761#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1762#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1763#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1764#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1765#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1766#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1767#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1768#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1769#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1770#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1771#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1772#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1773#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1774#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1775#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1776#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1777#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1778#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1779#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1780#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1781#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1782#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1783#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1784#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1785#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1786#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1787#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1788#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1789#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1790#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1791#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1792#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1793#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1794#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1795#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1796#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1797#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1798#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1799#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1800#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1801#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1802#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1803#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1804#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1805#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1806#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1807#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1808#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1809#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1810#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1811#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1812#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1813#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1814#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1815#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1816#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1817
1818/* Common functions */
1819int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 1820bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1821void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1822bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1823void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1824
00f06b24
JB		 1825void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1826 u64 num_vis_bytes);
765e7fbf 1827void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1828bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1829void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1830void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
97b2e202 1831void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1832int amdgpu_ttm_init(struct amdgpu_device *adev);
1833void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1834void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1835 const u32 *registers,
1836 const u32 array_size);
1837
1838bool amdgpu_device_is_px(struct drm_device *dev);
1839/* atpx handler */
1840#if defined(CONFIG_VGA_SWITCHEROO)
1841void amdgpu_register_atpx_handler(void);
1842void amdgpu_unregister_atpx_handler(void);
a78fe133 1843bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1844bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1845bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1846bool amdgpu_has_atpx(void);
97b2e202
AD		 1847#else
1848static inline void amdgpu_register_atpx_handler(void) {}
1849static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1850static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1851static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1852static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1853static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1854#endif
1855
1856/*
1857 * KMS
1858 */
1859extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1860extern const int amdgpu_max_kms_ioctl;
97b2e202 1861
f1892138
CZ		 1862bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1863 struct amdgpu_fpriv *fpriv);
97b2e202 1864int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1865void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1866void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1867int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1868void amdgpu_driver_postclose_kms(struct drm_device *dev,
1869 struct drm_file *file_priv);
faefba95 1870int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1871int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1872int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1873u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1874int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1875void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1876long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1877 unsigned long arg);
1878
97b2e202
AD		 1879/*
1880 * functions used by amdgpu_encoder.c
1881 */
1882struct amdgpu_afmt_acr {
1883 u32 clock;
1884
1885 int n_32khz;
1886 int cts_32khz;
1887
1888 int n_44_1khz;
1889 int cts_44_1khz;
1890
1891 int n_48khz;
1892 int cts_48khz;
1893
1894};
1895
1896struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1897
1898/* amdgpu_acpi.c */
1899#if defined(CONFIG_ACPI)
1900int amdgpu_acpi_init(struct amdgpu_device *adev);
1901void amdgpu_acpi_fini(struct amdgpu_device *adev);
1902bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1903int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1904 u8 perf_req, bool advertise);
1905int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1906#else
1907static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1908static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1909#endif
1910
9cca0b8e
CK		 1911int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1912 uint64_t addr, struct amdgpu_bo **bo,
1913 struct amdgpu_bo_va_mapping **mapping);
97b2e202
AD		 1914
1915#include "amdgpu_object.h"
97b2e202 1916#endif
Linux 6.x block layer and io_uring tree(s)