projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/powerplay: enable gpu_busy_percent sys interface for renoir (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
8290268f
CK		 31#include "amdgpu_ctx.h"
32
97b2e202
AD		 33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
a9f87f64 37#include <linux/rbtree.h>
97b2e202 38#include <linux/hashtable.h>
f54d1867 39#include <linux/dma-fence.h>
97b2e202 40
248a1d6f
MY		 41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 46
7e5a547f 47#include <drm/amdgpu_drm.h>
f867723b
SR		 48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
1b1f42d8 50#include <drm/gpu_scheduler.h>
97b2e202 51
78c16834 52#include <kgd_kfd_interface.h>
c79563a3
RZ		 53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
78c16834 55
5fc3aeeb 56#include "amd_shared.h"
97b2e202
AD		 57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
c632d799 61#include "amdgpu_ttm.h"
0e5ca0d1 62#include "amdgpu_psp.h"
97b2e202 63#include "amdgpu_gds.h"
56113504 64#include "amdgpu_sync.h"
78023016 65#include "amdgpu_ring.h"
073440d2 66#include "amdgpu_vm.h"
cf097881 67#include "amdgpu_dpm.h"
a8fe58ce 68#include "amdgpu_acp.h"
4df654d2 69#include "amdgpu_uvd.h"
5e568178 70#include "amdgpu_vce.h"
95aa13f6 71#include "amdgpu_vcn.h"
88a1c40a 72#include "amdgpu_jpeg.h"
9a189996 73#include "amdgpu_mn.h"
770d13b1 74#include "amdgpu_gmc.h"
448fe192 75#include "amdgpu_gfx.h"
bb7743bc 76#include "amdgpu_sdma.h"
bebc0762 77#include "amdgpu_nbio.h"
4562236b 78#include "amdgpu_dm.h"
ceeb50ed 79#include "amdgpu_virt.h"
7946340f 80#include "amdgpu_csa.h"
3490bdb5 81#include "amdgpu_gart.h"
75758255 82#include "amdgpu_debugfs.h"
050d9d43 83#include "amdgpu_job.h"
4a8c21a1 84#include "amdgpu_bo_list.h"
2cddc50e 85#include "amdgpu_gem.h"
cde577bd 86#include "amdgpu_doorbell.h"
611736d8 87#include "amdgpu_amdkfd.h"
137d63ab 88#include "amdgpu_smu.h"
f39f5bb1 89#include "amdgpu_discovery.h"
a538bbe7 90#include "amdgpu_mes.h"
9e585a52 91#include "amdgpu_umc.h"
3d093da0 92#include "amdgpu_mmhub.h"
c79563a3 93
62d73fbc
EQ		 94#define MAX_GPU_INSTANCE 16
95
96struct amdgpu_gpu_instance
97{
98 struct amdgpu_device *adev;
99 int mgpu_fan_enabled;
100};
101
102struct amdgpu_mgpu_info
103{
104 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
105 struct mutex mutex;
106 uint32_t num_gpu;
107 uint32_t num_dgpu;
108 uint32_t num_apu;
109};
110
f440ff44 111#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
71f98027 112
97b2e202
AD		 113/*
114 * Modules parameters.
115 */
116extern int amdgpu_modeset;
117extern int amdgpu_vram_limit;
218b5dcd 118extern int amdgpu_vis_vram_limit;
83e74db6 119extern int amdgpu_gart_size;
36d38372 120extern int amdgpu_gtt_size;
95844d20 121extern int amdgpu_moverate;
97b2e202
AD		 122extern int amdgpu_benchmarking;
123extern int amdgpu_testing;
124extern int amdgpu_audio;
125extern int amdgpu_disp_priority;
126extern int amdgpu_hw_i2c;
127extern int amdgpu_pcie_gen2;
128extern int amdgpu_msi;
f440ff44 129extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
97b2e202 130extern int amdgpu_dpm;
e635ee07 131extern int amdgpu_fw_load_type;
97b2e202
AD		 132extern int amdgpu_aspm;
133extern int amdgpu_runtime_pm;
0b693f0b 134extern uint amdgpu_ip_block_mask;
97b2e202
AD		 135extern int amdgpu_bapm;
136extern int amdgpu_deep_color;
137extern int amdgpu_vm_size;
138extern int amdgpu_vm_block_size;
d07f14be 139extern int amdgpu_vm_fragment_size;
d9c13156 140extern int amdgpu_vm_fault_stop;
b495bd3a 141extern int amdgpu_vm_debug;
9a4b7d4c 142extern int amdgpu_vm_update_mode;
7e0ff20c 143extern int amdgpu_exp_hw_support;
4562236b 144extern int amdgpu_dc;
1333f723 145extern int amdgpu_sched_jobs;
4afcb303 146extern int amdgpu_sched_hw_submission;
0b693f0b
RZ		 147extern uint amdgpu_pcie_gen_cap;
148extern uint amdgpu_pcie_lane_cap;
149extern uint amdgpu_cg_mask;
150extern uint amdgpu_pg_mask;
151extern uint amdgpu_sdma_phase_quantum;
6f8941a2 152extern char *amdgpu_disable_cu;
9accf2fd 153extern char *amdgpu_virtual_display;
0b693f0b 154extern uint amdgpu_pp_feature_mask;
367039bf 155extern uint amdgpu_force_long_training;
65781c78 156extern int amdgpu_job_hang_limit;
e8835e0e 157extern int amdgpu_lbpw;
4a75aefe 158extern int amdgpu_compute_multipipe;
dcebf026 159extern int amdgpu_gpu_recovery;
bfca0289 160extern int amdgpu_emu_mode;
7951e376 161extern uint amdgpu_smu_memory_pool_size;
7875a226 162extern uint amdgpu_dc_feature_mask;
ad4de27f 163extern uint amdgpu_dm_abm_level;
62d73fbc 164extern struct amdgpu_mgpu_info mgpu_info;
1218252f 165extern int amdgpu_ras_enable;
166extern uint amdgpu_ras_mask;
51bcce46 167extern int amdgpu_async_gfx_ring;
b239c017 168extern int amdgpu_mcbp;
a190d1c7 169extern int amdgpu_discovery;
38487284 170extern int amdgpu_mes;
75ee6487 171extern int amdgpu_noretry;
4e66d7d2 172extern int amdgpu_force_asic_type;
8c9f69bc 173#ifdef CONFIG_HSA_AMD
aa978594 174extern int sched_policy;
a35ad98b
S		 175#else
176static const int sched_policy = KFD_SCHED_POLICY_HWS;
8c9f69bc 177#endif
97b2e202 178
6dd13096
FK		 179#ifdef CONFIG_DRM_AMDGPU_SI
180extern int amdgpu_si_support;
181#endif
7df28986
FK		 182#ifdef CONFIG_DRM_AMDGPU_CIK
183extern int amdgpu_cik_support;
184#endif
97b2e202 185
08d1bdd4 186#define AMDGPU_VM_MAX_NUM_CTX 4096
6c8d74ca 187#define AMDGPU_SG_THRESHOLD (256*1024*1024)
55ed8caf 188#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 189#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202 190#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
8c5e13ec 191#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
97b2e202
AD		 192/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
193#define AMDGPU_IB_POOL_SIZE 16
194#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
195#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 196#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 197
97b2e202
AD		 198/* hard reset data */
199#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
200
201/* reset flags */
202#define AMDGPU_RESET_GFX (1 << 0)
203#define AMDGPU_RESET_COMPUTE (1 << 1)
204#define AMDGPU_RESET_DMA (1 << 2)
205#define AMDGPU_RESET_CP (1 << 3)
206#define AMDGPU_RESET_GRBM (1 << 4)
207#define AMDGPU_RESET_DMA1 (1 << 5)
208#define AMDGPU_RESET_RLC (1 << 6)
209#define AMDGPU_RESET_SEM (1 << 7)
210#define AMDGPU_RESET_IH (1 << 8)
211#define AMDGPU_RESET_VMC (1 << 9)
212#define AMDGPU_RESET_MC (1 << 10)
213#define AMDGPU_RESET_DISPLAY (1 << 11)
214#define AMDGPU_RESET_UVD (1 << 12)
215#define AMDGPU_RESET_VCE (1 << 13)
216#define AMDGPU_RESET_VCE1 (1 << 14)
217
97b2e202
AD		 218/* max cursor sizes (in pixels) */
219#define CIK_CURSOR_WIDTH 128
220#define CIK_CURSOR_HEIGHT 128
221
222struct amdgpu_device;
97b2e202 223struct amdgpu_ib;
97b2e202 224struct amdgpu_cs_parser;
bb977d37 225struct amdgpu_job;
97b2e202 226struct amdgpu_irq_src;
0b492a4c 227struct amdgpu_fpriv;
9cca0b8e 228struct amdgpu_bo_va_mapping;
102c16a0 229struct amdgpu_atif;
992af942 230struct kfd_vm_fault_info;
97b2e202
AD		 231
232enum amdgpu_cp_irq {
53b2fe41
HZ		 233 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
234 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
97b2e202
AD		 235 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
236 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
237 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
238 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
239 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
240 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
241 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
242 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
243
244 AMDGPU_CP_IRQ_LAST
245};
246
97b2e202
AD		 247enum amdgpu_thermal_irq {
248 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
249 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
250
251 AMDGPU_THERMAL_IRQ_LAST
252};
253
4e638ae9
XY		 254enum amdgpu_kiq_irq {
255 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
256 AMDGPU_CP_KIQ_IRQ_LAST
257};
258
3890d111
ED		 259#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
260#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
4944af67 261#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
3890d111 262
43fa561f 263int amdgpu_device_ip_set_clockgating_state(void *dev,
2990a1fc
AD		 264 enum amd_ip_block_type block_type,
265 enum amd_clockgating_state state);
43fa561f 266int amdgpu_device_ip_set_powergating_state(void *dev,
2990a1fc
AD		 267 enum amd_ip_block_type block_type,
268 enum amd_powergating_state state);
269void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
270 u32 *flags);
271int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
272 enum amd_ip_block_type block_type);
273bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
274 enum amd_ip_block_type block_type);
97b2e202 275
a1255107
AD		 276#define AMDGPU_MAX_IP_NUM 16
277
278struct amdgpu_ip_block_status {
279 bool valid;
280 bool sw;
281 bool hw;
282 bool late_initialized;
283 bool hang;
284};
285
97b2e202 286struct amdgpu_ip_block_version {
a1255107
AD		 287 const enum amd_ip_block_type type;
288 const u32 major;
289 const u32 minor;
290 const u32 rev;
5fc3aeeb 291 const struct amd_ip_funcs *funcs;
97b2e202
AD		 292};
293
efe4f000
TY		 294#define HW_REV(_Major, _Minor, _Rev) \
295 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
296
a1255107
AD		 297struct amdgpu_ip_block {
298 struct amdgpu_ip_block_status status;
299 const struct amdgpu_ip_block_version *version;
300};
301
2990a1fc
AD		 302int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
303 enum amd_ip_block_type type,
304 u32 major, u32 minor);
97b2e202 305
2990a1fc
AD		 306struct amdgpu_ip_block *
307amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
308 enum amd_ip_block_type type);
a1255107 309
2990a1fc
AD		 310int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
311 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202 312
97b2e202
AD		 313/*
314 * BIOS.
315 */
316bool amdgpu_get_bios(struct amdgpu_device *adev);
317bool amdgpu_read_bios(struct amdgpu_device *adev);
318
97b2e202
AD		 319/*
320 * Clocks
321 */
322
323#define AMDGPU_MAX_PPLL 3
324
325struct amdgpu_clock {
326 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
327 struct amdgpu_pll spll;
328 struct amdgpu_pll mpll;
329 /* 10 Khz units */
330 uint32_t default_mclk;
331 uint32_t default_sclk;
332 uint32_t default_dispclk;
333 uint32_t current_dispclk;
334 uint32_t dp_extclk;
335 uint32_t max_pixel_clock;
336};
337
97b2e202
AD		 338/* sub-allocation manager, it has to be protected by another lock.
339 * By conception this is an helper for other part of the driver
340 * like the indirect buffer or semaphore, which both have their
341 * locking.
342 *
343 * Principe is simple, we keep a list of sub allocation in offset
344 * order (first entry has offset == 0, last entry has the highest
345 * offset).
346 *
347 * When allocating new object we first check if there is room at
348 * the end total_size - (last_object_offset + last_object_size) >=
349 * alloc_size. If so we allocate new object there.
350 *
351 * When there is not enough room at the end, we start waiting for
352 * each sub object until we reach object_offset+object_size >=
353 * alloc_size, this object then become the sub object we return.
354 *
355 * Alignment can't be bigger than page size.
356 *
357 * Hole are not considered for allocation to keep things simple.
358 * Assumption is that there won't be hole (all object on same
359 * alignment).
360 */
6ba60b89
CK		 361
362#define AMDGPU_SA_NUM_FENCE_LISTS 32
363
97b2e202
AD		 364struct amdgpu_sa_manager {
365 wait_queue_head_t wq;
366 struct amdgpu_bo *bo;
367 struct list_head *hole;
6ba60b89 368 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 369 struct list_head olist;
370 unsigned size;
371 uint64_t gpu_addr;
372 void *cpu_ptr;
373 uint32_t domain;
374 uint32_t align;
375};
376
97b2e202
AD		 377/* sub-allocation buffer */
378struct amdgpu_sa_bo {
379 struct list_head olist;
380 struct list_head flist;
381 struct amdgpu_sa_manager *manager;
382 unsigned soffset;
383 unsigned eoffset;
f54d1867 384 struct dma_fence *fence;
97b2e202
AD		 385};
386
d573de2d
RZ		 387int amdgpu_fence_slab_init(void);
388void amdgpu_fence_slab_fini(void);
97b2e202 389
97b2e202
AD		 390/*
391 * IRQS.
392 */
393
394struct amdgpu_flip_work {
325cbba1 395 struct delayed_work flip_work;
97b2e202
AD		 396 struct work_struct unpin_work;
397 struct amdgpu_device *adev;
398 int crtc_id;
325cbba1 399 u32 target_vblank;
97b2e202
AD		 400 uint64_t base;
401 struct drm_pending_vblank_event *event;
765e7fbf 402 struct amdgpu_bo *old_abo;
f54d1867 403 struct dma_fence *excl;
1ffd2652 404 unsigned shared_count;
f54d1867
CW		 405 struct dma_fence **shared;
406 struct dma_fence_cb cb;
cb9e59d7 407 bool async;
97b2e202
AD		 408};
409
410
411/*
412 * CP & rings.
413 */
414
415struct amdgpu_ib {
416 struct amdgpu_sa_bo *sa_bo;
417 uint32_t length_dw;
418 uint64_t gpu_addr;
419 uint32_t *ptr;
de807f81 420 uint32_t flags;
97b2e202
AD		 421};
422
1b1f42d8 423extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 424
97b2e202
AD		 425/*
426 * file private structure
427 */
428
429struct amdgpu_fpriv {
430 struct amdgpu_vm vm;
b85891bd 431 struct amdgpu_bo_va *prt_va;
0f4b3c68 432 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 433 struct mutex bo_list_lock;
434 struct idr bo_list_handles;
0b492a4c 435 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 436};
437
021830d2
BN		 438int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
439
b07c60c0 440int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 441 unsigned size, struct amdgpu_ib *ib);
4d9c514d 442void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 443 struct dma_fence *f);
b07c60c0 444int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 445 struct amdgpu_ib *ibs, struct amdgpu_job *job,
446 struct dma_fence **f);
97b2e202
AD		 447int amdgpu_ib_pool_init(struct amdgpu_device *adev);
448void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
449int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 450
451/*
452 * CS.
453 */
454struct amdgpu_cs_chunk {
455 uint32_t chunk_id;
456 uint32_t length_dw;
758ac17f 457 void *kdata;
97b2e202
AD		 458};
459
2624dd15
CZ		 460struct amdgpu_cs_post_dep {
461 struct drm_syncobj *syncobj;
462 struct dma_fence_chain *chain;
463 u64 point;
464};
465
97b2e202
AD		 466struct amdgpu_cs_parser {
467 struct amdgpu_device *adev;
468 struct drm_file *filp;
3cb485f3 469 struct amdgpu_ctx *ctx;
c3cca41e 470
97b2e202
AD		 471 /* chunks */
472 unsigned nchunks;
473 struct amdgpu_cs_chunk *chunks;
97b2e202 474
50838c8c
CK		 475 /* scheduler job object */
476 struct amdgpu_job *job;
0d346a14 477 struct drm_sched_entity *entity;
97b2e202 478
c3cca41e
CK		 479 /* buffer objects */
480 struct ww_acquire_ctx ticket;
481 struct amdgpu_bo_list *bo_list;
3fe89771 482 struct amdgpu_mn *mn;
c3cca41e
CK		 483 struct amdgpu_bo_list_entry vm_pd;
484 struct list_head validated;
f54d1867 485 struct dma_fence *fence;
c3cca41e 486 uint64_t bytes_moved_threshold;
00f06b24 487 uint64_t bytes_moved_vis_threshold;
c3cca41e 488 uint64_t bytes_moved;
00f06b24 489 uint64_t bytes_moved_vis;
97b2e202
AD		 490
491 /* user fence */
91acbeb6 492 struct amdgpu_bo_list_entry uf_entry;
660e8558 493
2624dd15
CZ		 494 unsigned num_post_deps;
495 struct amdgpu_cs_post_dep *post_deps;
97b2e202
AD		 496};
497
7270f839
CK		 498static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
499 uint32_t ib_idx, int idx)
97b2e202 500{
50838c8c 501 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 502}
503
7270f839
CK		 504static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
505 uint32_t ib_idx, int idx,
506 uint32_t value)
507{
50838c8c 508 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 509}
510
97b2e202
AD		 511/*
512 * Writeback
513 */
73469585 514#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
97b2e202
AD		 515
516struct amdgpu_wb {
517 struct amdgpu_bo *wb_obj;
518 volatile uint32_t *wb;
519 uint64_t gpu_addr;
520 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
521 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
522};
523
131b4b36
AD		 524int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
525void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
97b2e202 526
97b2e202
AD		 527/*
528 * Benchmarking
529 */
530void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
531
532
533/*
534 * Testing
535 */
536void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 537
97b2e202
AD		 538/*
539 * ASIC specific register table accessible by UMD
540 */
541struct amdgpu_allowed_register_entry {
542 uint32_t reg_offset;
97b2e202
AD		 543 bool grbm_indexed;
544};
545
0cf3c64f
AD		 546enum amd_reset_method {
547 AMD_RESET_METHOD_LEGACY = 0,
548 AMD_RESET_METHOD_MODE0,
549 AMD_RESET_METHOD_MODE1,
550 AMD_RESET_METHOD_MODE2,
551 AMD_RESET_METHOD_BACO
552};
553
97b2e202
AD		 554/*
555 * ASIC specific functions.
556 */
557struct amdgpu_asic_funcs {
558 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 559 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
560 u8 *bios, u32 length_bytes);
97b2e202
AD		 561 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
562 u32 sh_num, u32 reg_offset, u32 *value);
563 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
564 int (*reset)(struct amdgpu_device *adev);
0cf3c64f 565 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
97b2e202
AD		 566 /* get the reference clock */
567 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 568 /* MM block clocks */
569 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
570 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 571 /* static power management */
572 int (*get_pcie_lanes)(struct amdgpu_device *adev);
573 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 574 /* get config memsize register */
575 u32 (*get_config_memsize)(struct amdgpu_device *adev);
2df1b8b6 576 /* flush hdp write queue */
69882565 577 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
2df1b8b6 578 /* invalidate hdp read cache */
69882565
CK		 579 void (*invalidate_hdp)(struct amdgpu_device *adev,
580 struct amdgpu_ring *ring);
69070690
AD		 581 /* check if the asic needs a full reset of if soft reset will work */
582 bool (*need_full_reset)(struct amdgpu_device *adev);
5253163a
OZ		 583 /* initialize doorbell layout for specific asic*/
584 void (*init_doorbell_index)(struct amdgpu_device *adev);
b45e18ac
KR		 585 /* PCIe bandwidth usage */
586 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
587 uint64_t *count1);
44401889
AD		 588 /* do we need to reset the asic at init time (e.g., kexec) */
589 bool (*need_reset_on_init)(struct amdgpu_device *adev);
dcea6e65
KR		 590 /* PCIe replay counter */
591 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
97b2e202
AD		 592};
593
594/*
595 * IOCTL.
596 */
97b2e202
AD		 597int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
598 struct drm_file *filp);
599
97b2e202 600int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 601int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
602 struct drm_file *filp);
97b2e202 603int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 604int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *filp);
97b2e202 606
97b2e202
AD		 607/* VRAM scratch page for HDP bug, default vram page */
608struct amdgpu_vram_scratch {
609 struct amdgpu_bo *robj;
610 volatile uint32_t *ptr;
611 u64 gpu_addr;
612};
613
614/*
615 * ACPI
616 */
97b2e202
AD		 617struct amdgpu_atcs_functions {
618 bool get_ext_state;
619 bool pcie_perf_req;
620 bool pcie_dev_rdy;
621 bool pcie_bus_width;
622};
623
624struct amdgpu_atcs {
625 struct amdgpu_atcs_functions functions;
626};
627
a05502e5
HC		 628/*
629 * Firmware VRAM reservation
630 */
631struct amdgpu_fw_vram_usage {
632 u64 start_offset;
633 u64 size;
634 struct amdgpu_bo *reserved_bo;
635 void *va;
efe4f000
TY		 636
637 /* Offset on the top of VRAM, used as c2p write buffer.
638 */
639 u64 mem_train_fb_loc;
640 bool mem_train_support;
a05502e5
HC		 641};
642
d03846af
CZ		 643/*
644 * CGS
645 */
110e6f26
DA		 646struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
647void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 648
97b2e202
AD		 649/*
650 * Core structure, functions and helpers.
651 */
652typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
653typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
654
4fa1c6a6
TZ		 655typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
656typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
657
97b2e202
AD		 658typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
659typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
660
88807dc8
OZ		 661struct amdgpu_mmio_remap {
662 u32 reg_offset;
663 resource_size_t bus_addr;
664};
665
634c96e3 666struct amdgpu_df_funcs {
e4cf4bf5 667 void (*sw_init)(struct amdgpu_device *adev);
f1d59e00 668 void (*sw_fini)(struct amdgpu_device *adev);
634c96e3
HZ		 669 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
670 bool enable);
671 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
672 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
673 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
674 bool enable);
675 void (*get_clockgating_state)(struct amdgpu_device *adev,
676 u32 *flags);
8f9b2e50
AD		 677 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
678 bool enable);
992af942
JK		 679 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
680 int is_enable);
681 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
682 int is_disable);
683 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
684 uint64_t *count);
64671c0f
JK		 685 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
686 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
687 uint32_t ficadl_val, uint32_t ficadh_val);
634c96e3 688};
4522824c
SL		 689/* Define the HW IP blocks will be used in driver , add more if necessary */
690enum amd_hw_ip_block_type {
691 GC_HWIP = 1,
692 HDP_HWIP,
693 SDMA0_HWIP,
694 SDMA1_HWIP,
fa5d2e6f
LM		 695 SDMA2_HWIP,
696 SDMA3_HWIP,
697 SDMA4_HWIP,
698 SDMA5_HWIP,
699 SDMA6_HWIP,
700 SDMA7_HWIP,
4522824c
SL		 701 MMHUB_HWIP,
702 ATHUB_HWIP,
703 NBIO_HWIP,
704 MP0_HWIP,
e6636ae1 705 MP1_HWIP,
4522824c
SL		 706 UVD_HWIP,
707 VCN_HWIP = UVD_HWIP,
88a1c40a 708 JPEG_HWIP = VCN_HWIP,
4522824c
SL		 709 VCE_HWIP,
710 DF_HWIP,
711 DCE_HWIP,
712 OSSSYS_HWIP,
713 SMUIO_HWIP,
714 PWR_HWIP,
715 NBIF_HWIP,
e6636ae1 716 THM_HWIP,
73b19174 717 CLK_HWIP,
6501a771
HZ		 718 UMC_HWIP,
719 RSMU_HWIP,
4522824c
SL		 720 MAX_HWIP
721};
722
113b47e7 723#define HWIP_MAX_INSTANCE 8
4522824c 724
11dc9364 725struct amd_powerplay {
11dc9364 726 void *pp_handle;
11dc9364
RZ		 727 const struct amd_pm_funcs *pp_funcs;
728};
729
0c49e0b8 730#define AMDGPU_RESET_MAGIC_NUM 64
e4cf4bf5 731#define AMDGPU_MAX_DF_PERFMONS 4
97b2e202
AD		 732struct amdgpu_device {
733 struct device *dev;
734 struct drm_device *ddev;
735 struct pci_dev *pdev;
97b2e202 736
a8fe58ce
MB		 737#ifdef CONFIG_DRM_AMD_ACP
738 struct amdgpu_acp acp;
739#endif
740
97b2e202 741 /* ASIC */
2f7d10b3 742 enum amd_asic_type asic_type;
97b2e202
AD		 743 uint32_t family;
744 uint32_t rev_id;
745 uint32_t external_rev_id;
746 unsigned long flags;
747 int usec_timeout;
748 const struct amdgpu_asic_funcs *asic_funcs;
749 bool shutdown;
fd5fd480 750 bool need_swiotlb;
97b2e202 751 bool accel_working;
97b2e202
AD		 752 struct notifier_block acpi_nb;
753 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
754 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 755 unsigned debugfs_count;
97b2e202 756#if defined(CONFIG_DEBUG_FS)
6698a3d0 757 struct dentry *debugfs_preempt;
adcec288 758 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202 759#endif
102c16a0 760 struct amdgpu_atif *atif;
97b2e202
AD		 761 struct amdgpu_atcs atcs;
762 struct mutex srbm_mutex;
763 /* GRBM index mutex. Protects concurrent access to GRBM index */
764 struct mutex grbm_idx_mutex;
765 struct dev_pm_domain vga_pm_domain;
766 bool have_disp_power_ref;
bae17d2a 767 bool have_atomics_support;
97b2e202
AD		 768
769 /* BIOS */
0cdd5005 770 bool is_atom_fw;
97b2e202 771 uint8_t *bios;
a9f5db9c 772 uint32_t bios_size;
5af2c10d 773 struct amdgpu_bo *stolen_vga_memory;
5f6a556f 774 struct amdgpu_bo *discovery_memory;
a5bde2f9 775 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 776 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
777
778 /* Register/doorbell mmio */
779 resource_size_t rmmio_base;
780 resource_size_t rmmio_size;
781 void __iomem *rmmio;
782 /* protects concurrent MM_INDEX/DATA based register access */
783 spinlock_t mmio_idx_lock;
88807dc8 784 struct amdgpu_mmio_remap rmmio_remap;
97b2e202
AD		 785 /* protects concurrent SMC based register access */
786 spinlock_t smc_idx_lock;
787 amdgpu_rreg_t smc_rreg;
788 amdgpu_wreg_t smc_wreg;
789 /* protects concurrent PCIE register access */
790 spinlock_t pcie_idx_lock;
791 amdgpu_rreg_t pcie_rreg;
792 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 793 amdgpu_rreg_t pciep_rreg;
794 amdgpu_wreg_t pciep_wreg;
4fa1c6a6
TZ		 795 amdgpu_rreg64_t pcie_rreg64;
796 amdgpu_wreg64_t pcie_wreg64;
97b2e202
AD		 797 /* protects concurrent UVD register access */
798 spinlock_t uvd_ctx_idx_lock;
799 amdgpu_rreg_t uvd_ctx_rreg;
800 amdgpu_wreg_t uvd_ctx_wreg;
801 /* protects concurrent DIDT register access */
802 spinlock_t didt_idx_lock;
803 amdgpu_rreg_t didt_rreg;
804 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 805 /* protects concurrent gc_cac register access */
806 spinlock_t gc_cac_idx_lock;
807 amdgpu_rreg_t gc_cac_rreg;
808 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 809 /* protects concurrent se_cac register access */
810 spinlock_t se_cac_idx_lock;
811 amdgpu_rreg_t se_cac_rreg;
812 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 813 /* protects concurrent ENDPOINT (audio) register access */
814 spinlock_t audio_endpt_idx_lock;
815 amdgpu_block_rreg_t audio_endpt_rreg;
816 amdgpu_block_wreg_t audio_endpt_wreg;
817 void __iomem *rio_mem;
818 resource_size_t rio_mem_size;
819 struct amdgpu_doorbell doorbell;
820
821 /* clock/pll info */
822 struct amdgpu_clock clock;
823
824 /* MC */
770d13b1 825 struct amdgpu_gmc gmc;
97b2e202 826 struct amdgpu_gart gart;
92e71b06 827 dma_addr_t dummy_page_addr;
97b2e202 828 struct amdgpu_vm_manager vm_manager;
e60f8db5 829 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1daa2bfa 830 unsigned num_vmhubs;
97b2e202
AD		 831
832 /* memory management */
833 struct amdgpu_mman mman;
97b2e202
AD		 834 struct amdgpu_vram_scratch vram_scratch;
835 struct amdgpu_wb wb;
97b2e202 836 atomic64_t num_bytes_moved;
dbd5ed60 837 atomic64_t num_evictions;
68e2c5ff 838 atomic64_t num_vram_cpu_page_faults;
d94aed5a 839 atomic_t gpu_reset_counter;
f1892138 840 atomic_t vram_lost_counter;
97b2e202 841
95844d20
MO		 842 /* data for buffer migration throttling */
843 struct {
844 spinlock_t lock;
845 s64 last_update_us;
846 s64 accum_us; /* accumulated microseconds */
00f06b24 847 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 848 u32 log2_max_MBps;
849 } mm_stats;
850
97b2e202 851 /* display */
9accf2fd 852 bool enable_virtual_display;
97b2e202 853 struct amdgpu_mode_info mode_info;
4562236b 854 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 855 struct work_struct hotplug_work;
856 struct amdgpu_irq_src crtc_irq;
d2574c33 857 struct amdgpu_irq_src vupdate_irq;
97b2e202
AD		 858 struct amdgpu_irq_src pageflip_irq;
859 struct amdgpu_irq_src hpd_irq;
860
861 /* rings */
76bf0db5 862 u64 fence_context;
97b2e202
AD		 863 unsigned num_rings;
864 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
865 bool ib_pool_ready;
866 struct amdgpu_sa_manager ring_tmp_bo;
867
868 /* interrupts */
869 struct amdgpu_irq irq;
870
1f7371b2
AD		 871 /* powerplay */
872 struct amd_powerplay powerplay;
f3898ea1 873 bool pp_force_state_enabled;
1f7371b2 874
137d63ab
HR		 875 /* smu */
876 struct smu_context smu;
877
97b2e202
AD		 878 /* dpm */
879 struct amdgpu_pm pm;
880 u32 cg_flags;
881 u32 pg_flags;
882
bebc0762
HZ		 883 /* nbio */
884 struct amdgpu_nbio nbio;
885
d3a5a121
TZ		 886 /* mmhub */
887 struct amdgpu_mmhub mmhub;
888
97b2e202
AD		 889 /* gfx */
890 struct amdgpu_gfx gfx;
891
892 /* sdma */
c113ea1c 893 struct amdgpu_sdma sdma;
97b2e202 894
b43aaee6
LL		 895 /* uvd */
896 struct amdgpu_uvd uvd;
897
898 /* vce */
899 struct amdgpu_vce vce;
900
901 /* vcn */
902 struct amdgpu_vcn vcn;
97b2e202 903
88a1c40a
LL		 904 /* jpeg */
905 struct amdgpu_jpeg jpeg;
906
97b2e202
AD		 907 /* firmwares */
908 struct amdgpu_firmware firmware;
909
0e5ca0d1
HR		 910 /* PSP */
911 struct psp_context psp;
912
97b2e202
AD		 913 /* GDS */
914 struct amdgpu_gds gds;
915
611736d8
FK		 916 /* KFD */
917 struct amdgpu_kfd_dev kfd;
918
045c0216
TZ		 919 /* UMC */
920 struct amdgpu_umc umc;
921
4562236b
HW		 922 /* display related functionality */
923 struct amdgpu_display_manager dm;
924
f39f5bb1
XY		 925 /* discovery */
926 uint8_t *discovery;
927
a538bbe7
JX		 928 /* mes */
929 bool enable_mes;
930 struct amdgpu_mes mes;
931
a1255107 932 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 933 int num_ip_blocks;
97b2e202
AD		 934 struct mutex mn_lock;
935 DECLARE_HASHTABLE(mn_hash, 7);
936
937 /* tracking pinned memory */
a5ccfe5c
MD		 938 atomic64_t vram_pin_size;
939 atomic64_t visible_pin_size;
940 atomic64_t gart_pin_size;
130e0371 941
4522824c
SL		 942 /* soc15 register offset based on ip, instance and segment */
943 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
944
634c96e3 945 const struct amdgpu_df_funcs *df_funcs;
946a4d5b 946
2dc80b00 947 /* delayed work_func for deferring clockgating during resume */
beff74bc 948 struct delayed_work delayed_init_work;
2dc80b00 949
5a5099cb 950 struct amdgpu_virt virt;
a05502e5
HC		 951 /* firmware VRAM reservation */
952 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 953
954 /* link all shadow bo */
955 struct list_head shadow_list;
956 struct mutex shadow_list_lock;
795f2813
AR		 957 /* keep an lru list of rings by HW IP */
958 struct list_head ring_lru_list;
959 spinlock_t ring_lru_list_lock;
5c1354bd 960
c836fec5
JQ		 961 /* record hw reset is performed */
962 bool has_hw_reset;
0c49e0b8 963 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 964
44779b43
RZ		 965 /* s3/s4 mask */
966 bool in_suspend;
967
47ed4e1c
KW		 968 /* record last mm index being written through WREG32*/
969 unsigned long last_mm_index;
13a752e3 970 bool in_gpu_reset;
a3a09142 971 enum pp_mp1_state mp1_state;
13a752e3 972 struct mutex lock_reset;
409c5191 973 struct amdgpu_doorbell_index doorbell_index;
d4535e2c 974
26bc5340 975 int asic_reset_res;
d4535e2c 976 struct work_struct xgmi_reset_work;
9b638f97 977
912dfc84
EQ		 978 long gfx_timeout;
979 long sdma_timeout;
980 long video_timeout;
981 long compute_timeout;
fb2dbfd2
KR		 982
983 uint64_t unique_id;
e4cf4bf5 984 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
5c5b2ba0
EQ		 985
986 /* device pstate */
987 int pstate;
97b2e202
AD		 988};
989
a7d64de6
CK		 990static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
991{
992 return container_of(bdev, struct amdgpu_device, mman.bdev);
993}
994
97b2e202
AD		 995int amdgpu_device_init(struct amdgpu_device *adev,
996 struct drm_device *ddev,
997 struct pci_dev *pdev,
998 uint32_t flags);
999void amdgpu_device_fini(struct amdgpu_device *adev);
1000int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1001
e35e2b11
TY		 1002void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1003 uint32_t *buf, size_t size, bool write);
97b2e202 1004uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1005 uint32_t acc_flags);
97b2e202 1006void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1007 uint32_t acc_flags);
421a2a30
ML		 1008void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1009uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1010
97b2e202
AD		 1011u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1012void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1013
4562236b
HW		 1014bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1015bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1016
9475a943
SL		 1017int emu_soc_asic_init(struct amdgpu_device *adev);
1018
97b2e202
AD		 1019/*
1020 * Registers read & write functions.
1021 */
15d72fd7
ML		 1022
1023#define AMDGPU_REGS_IDX (1<<0)
1024#define AMDGPU_REGS_NO_KIQ (1<<1)
1025
1026#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1027#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1028
421a2a30
ML		 1029#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1030#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1031
15d72fd7
ML		 1032#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1033#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1034#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1035#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1036#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1037#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1038#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1039#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1040#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1041#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1042#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
4fa1c6a6
TZ		 1043#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1044#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
97b2e202
AD		 1045#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1046#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1047#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1048#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1049#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1050#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1051#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1052#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1053#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1054#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1055#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1056#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1057#define WREG32_P(reg, val, mask) \
1058 do { \
1059 uint32_t tmp_ = RREG32(reg); \
1060 tmp_ &= (mask); \
1061 tmp_ |= ((val) & ~(mask)); \
1062 WREG32(reg, tmp_); \
1063 } while (0)
1064#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1065#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1066#define WREG32_PLL_P(reg, val, mask) \
1067 do { \
1068 uint32_t tmp_ = RREG32_PLL(reg); \
1069 tmp_ &= (mask); \
1070 tmp_ |= ((val) & ~(mask)); \
1071 WREG32_PLL(reg, tmp_); \
1072 } while (0)
1073#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1074#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1075#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1076
97b2e202
AD		 1077#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1078#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1079
1080#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1081 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1082 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1083
1084#define REG_GET_FIELD(value, reg, field) \
1085 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1086
1087#define WREG32_FIELD(reg, field, val) \
1088 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1089
ccaf3574
TSD		 1090#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1091 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1092
97b2e202
AD		 1093/*
1094 * BIOS helpers.
1095 */
1096#define RBIOS8(i) (adev->bios[i])
1097#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1098#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1099
97b2e202
AD		 1100/*
1101 * ASICs macro.
1102 */
1103#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1104#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
0cf3c64f 1105#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
97b2e202
AD		 1106#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1107#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1108#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1109#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1110#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1111#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1112#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1113#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1114#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1115#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
69882565
CK		 1116#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1117#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
69070690 1118#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
5253163a 1119#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
b45e18ac 1120#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
44401889 1121#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
dcea6e65 1122#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
e3526257 1123#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
97b2e202
AD		 1124
1125/* Common functions */
12938fad 1126bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
5f152b5e 1127int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12938fad 1128 struct amdgpu_job* job);
8111c387 1129void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
39c640c0 1130bool amdgpu_device_need_post(struct amdgpu_device *adev);
d5fc5e82 1131
00f06b24
JB		 1132void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1133 u64 num_vis_bytes);
d6895ad3 1134int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
9c3f2b54 1135void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
97b2e202
AD		 1136 const u32 *registers,
1137 const u32 array_size);
1138
1139bool amdgpu_device_is_px(struct drm_device *dev);
992af942
JK		 1140bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1141 struct amdgpu_device *peer_adev);
1142
97b2e202
AD		 1143/* atpx handler */
1144#if defined(CONFIG_VGA_SWITCHEROO)
1145void amdgpu_register_atpx_handler(void);
1146void amdgpu_unregister_atpx_handler(void);
a78fe133 1147bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1148bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1149bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1150bool amdgpu_has_atpx(void);
97b2e202
AD		 1151#else
1152static inline void amdgpu_register_atpx_handler(void) {}
1153static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1154static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1155static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1156static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1157static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1158#endif
1159
24aeefcd
LP		 1160#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1161void *amdgpu_atpx_get_dhandle(void);
1162#else
1163static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1164#endif
1165
97b2e202
AD		 1166/*
1167 * KMS
1168 */
1169extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1170extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1171
1172int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1173void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1174void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1175int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1176void amdgpu_driver_postclose_kms(struct drm_device *dev,
1177 struct drm_file *file_priv);
cdd61df6 1178int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1179int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1180int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1181u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1182int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1183void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1184long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1185 unsigned long arg);
1186
97b2e202
AD		 1187/*
1188 * functions used by amdgpu_encoder.c
1189 */
1190struct amdgpu_afmt_acr {
1191 u32 clock;
1192
1193 int n_32khz;
1194 int cts_32khz;
1195
1196 int n_44_1khz;
1197 int cts_44_1khz;
1198
1199 int n_48khz;
1200 int cts_48khz;
1201
1202};
1203
1204struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1205
1206/* amdgpu_acpi.c */
1207#if defined(CONFIG_ACPI)
1208int amdgpu_acpi_init(struct amdgpu_device *adev);
1209void amdgpu_acpi_fini(struct amdgpu_device *adev);
1210bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1211int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1212 u8 perf_req, bool advertise);
1213int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
206bbafe
DF		 1214
1215void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1216 struct amdgpu_dm_backlight_caps *caps);
97b2e202
AD		 1217#else
1218static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1219static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1220#endif
1221
9cca0b8e
CK		 1222int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1223 uint64_t addr, struct amdgpu_bo **bo,
1224 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1225
4562236b
HW		 1226#if defined(CONFIG_DRM_AMD_DC)
1227int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1228#else
1229static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1230#endif
1231
fdafb359
EQ		 1232
1233void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1234void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1235
97b2e202 1236#include "amdgpu_object.h"
e4cf4bf5
JK		 1237
1238/* used by df_v3_6.c and amdgpu_pmu.c */
1239#define AMDGPU_PMU_ATTR(_name, _object) \
1240static ssize_t \
1241_name##_show(struct device *dev, \
1242 struct device_attribute *attr, \
1243 char *page) \
1244{ \
1245 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1246 return sprintf(page, _object "\n"); \
1247} \
1248 \
1249static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1250
97b2e202 1251#endif
e4cf4bf5 1252
Linux 6.x block layer and io_uring tree(s)