Commit | Line | Data |
---|---|---|
97b2e202 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_H__ | |
29 | #define __AMDGPU_H__ | |
30 | ||
8290268f CK |
31 | #include "amdgpu_ctx.h" |
32 | ||
97b2e202 AD |
33 | #include <linux/atomic.h> |
34 | #include <linux/wait.h> | |
35 | #include <linux/list.h> | |
36 | #include <linux/kref.h> | |
a9f87f64 | 37 | #include <linux/rbtree.h> |
97b2e202 | 38 | #include <linux/hashtable.h> |
f54d1867 | 39 | #include <linux/dma-fence.h> |
97b2e202 | 40 | |
248a1d6f MY |
41 | #include <drm/ttm/ttm_bo_api.h> |
42 | #include <drm/ttm/ttm_bo_driver.h> | |
43 | #include <drm/ttm/ttm_placement.h> | |
44 | #include <drm/ttm/ttm_module.h> | |
45 | #include <drm/ttm/ttm_execbuf_util.h> | |
97b2e202 | 46 | |
7e5a547f | 47 | #include <drm/amdgpu_drm.h> |
f867723b SR |
48 | #include <drm/drm_gem.h> |
49 | #include <drm/drm_ioctl.h> | |
1b1f42d8 | 50 | #include <drm/gpu_scheduler.h> |
97b2e202 | 51 | |
78c16834 | 52 | #include <kgd_kfd_interface.h> |
c79563a3 RZ |
53 | #include "dm_pp_interface.h" |
54 | #include "kgd_pp_interface.h" | |
78c16834 | 55 | |
5fc3aeeb | 56 | #include "amd_shared.h" |
97b2e202 AD |
57 | #include "amdgpu_mode.h" |
58 | #include "amdgpu_ih.h" | |
59 | #include "amdgpu_irq.h" | |
60 | #include "amdgpu_ucode.h" | |
c632d799 | 61 | #include "amdgpu_ttm.h" |
0e5ca0d1 | 62 | #include "amdgpu_psp.h" |
97b2e202 | 63 | #include "amdgpu_gds.h" |
56113504 | 64 | #include "amdgpu_sync.h" |
78023016 | 65 | #include "amdgpu_ring.h" |
073440d2 | 66 | #include "amdgpu_vm.h" |
cf097881 | 67 | #include "amdgpu_dpm.h" |
a8fe58ce | 68 | #include "amdgpu_acp.h" |
4df654d2 | 69 | #include "amdgpu_uvd.h" |
5e568178 | 70 | #include "amdgpu_vce.h" |
95aa13f6 | 71 | #include "amdgpu_vcn.h" |
88a1c40a | 72 | #include "amdgpu_jpeg.h" |
9a189996 | 73 | #include "amdgpu_mn.h" |
770d13b1 | 74 | #include "amdgpu_gmc.h" |
448fe192 | 75 | #include "amdgpu_gfx.h" |
bb7743bc | 76 | #include "amdgpu_sdma.h" |
bebc0762 | 77 | #include "amdgpu_nbio.h" |
4562236b | 78 | #include "amdgpu_dm.h" |
ceeb50ed | 79 | #include "amdgpu_virt.h" |
7946340f | 80 | #include "amdgpu_csa.h" |
3490bdb5 | 81 | #include "amdgpu_gart.h" |
75758255 | 82 | #include "amdgpu_debugfs.h" |
050d9d43 | 83 | #include "amdgpu_job.h" |
4a8c21a1 | 84 | #include "amdgpu_bo_list.h" |
2cddc50e | 85 | #include "amdgpu_gem.h" |
cde577bd | 86 | #include "amdgpu_doorbell.h" |
611736d8 | 87 | #include "amdgpu_amdkfd.h" |
137d63ab | 88 | #include "amdgpu_smu.h" |
f39f5bb1 | 89 | #include "amdgpu_discovery.h" |
a538bbe7 | 90 | #include "amdgpu_mes.h" |
9e585a52 | 91 | #include "amdgpu_umc.h" |
3d093da0 | 92 | #include "amdgpu_mmhub.h" |
bdf84a80 | 93 | #include "amdgpu_df.h" |
c79563a3 | 94 | |
62d73fbc EQ |
95 | #define MAX_GPU_INSTANCE 16 |
96 | ||
97 | struct amdgpu_gpu_instance | |
98 | { | |
99 | struct amdgpu_device *adev; | |
100 | int mgpu_fan_enabled; | |
101 | }; | |
102 | ||
103 | struct amdgpu_mgpu_info | |
104 | { | |
105 | struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; | |
106 | struct mutex mutex; | |
107 | uint32_t num_gpu; | |
108 | uint32_t num_dgpu; | |
109 | uint32_t num_apu; | |
110 | }; | |
111 | ||
f440ff44 | 112 | #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 |
71f98027 | 113 | |
97b2e202 AD |
114 | /* |
115 | * Modules parameters. | |
116 | */ | |
117 | extern int amdgpu_modeset; | |
118 | extern int amdgpu_vram_limit; | |
218b5dcd | 119 | extern int amdgpu_vis_vram_limit; |
83e74db6 | 120 | extern int amdgpu_gart_size; |
36d38372 | 121 | extern int amdgpu_gtt_size; |
95844d20 | 122 | extern int amdgpu_moverate; |
97b2e202 AD |
123 | extern int amdgpu_benchmarking; |
124 | extern int amdgpu_testing; | |
125 | extern int amdgpu_audio; | |
126 | extern int amdgpu_disp_priority; | |
127 | extern int amdgpu_hw_i2c; | |
128 | extern int amdgpu_pcie_gen2; | |
129 | extern int amdgpu_msi; | |
f440ff44 | 130 | extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; |
97b2e202 | 131 | extern int amdgpu_dpm; |
e635ee07 | 132 | extern int amdgpu_fw_load_type; |
97b2e202 AD |
133 | extern int amdgpu_aspm; |
134 | extern int amdgpu_runtime_pm; | |
0b693f0b | 135 | extern uint amdgpu_ip_block_mask; |
97b2e202 AD |
136 | extern int amdgpu_bapm; |
137 | extern int amdgpu_deep_color; | |
138 | extern int amdgpu_vm_size; | |
139 | extern int amdgpu_vm_block_size; | |
d07f14be | 140 | extern int amdgpu_vm_fragment_size; |
d9c13156 | 141 | extern int amdgpu_vm_fault_stop; |
b495bd3a | 142 | extern int amdgpu_vm_debug; |
9a4b7d4c | 143 | extern int amdgpu_vm_update_mode; |
7e0ff20c | 144 | extern int amdgpu_exp_hw_support; |
4562236b | 145 | extern int amdgpu_dc; |
1333f723 | 146 | extern int amdgpu_sched_jobs; |
4afcb303 | 147 | extern int amdgpu_sched_hw_submission; |
0b693f0b RZ |
148 | extern uint amdgpu_pcie_gen_cap; |
149 | extern uint amdgpu_pcie_lane_cap; | |
150 | extern uint amdgpu_cg_mask; | |
151 | extern uint amdgpu_pg_mask; | |
152 | extern uint amdgpu_sdma_phase_quantum; | |
6f8941a2 | 153 | extern char *amdgpu_disable_cu; |
9accf2fd | 154 | extern char *amdgpu_virtual_display; |
0b693f0b | 155 | extern uint amdgpu_pp_feature_mask; |
367039bf | 156 | extern uint amdgpu_force_long_training; |
65781c78 | 157 | extern int amdgpu_job_hang_limit; |
e8835e0e | 158 | extern int amdgpu_lbpw; |
4a75aefe | 159 | extern int amdgpu_compute_multipipe; |
dcebf026 | 160 | extern int amdgpu_gpu_recovery; |
bfca0289 | 161 | extern int amdgpu_emu_mode; |
7951e376 | 162 | extern uint amdgpu_smu_memory_pool_size; |
7875a226 | 163 | extern uint amdgpu_dc_feature_mask; |
ad4de27f | 164 | extern uint amdgpu_dm_abm_level; |
62d73fbc | 165 | extern struct amdgpu_mgpu_info mgpu_info; |
1218252f | 166 | extern int amdgpu_ras_enable; |
167 | extern uint amdgpu_ras_mask; | |
51bcce46 | 168 | extern int amdgpu_async_gfx_ring; |
b239c017 | 169 | extern int amdgpu_mcbp; |
a190d1c7 | 170 | extern int amdgpu_discovery; |
38487284 | 171 | extern int amdgpu_mes; |
75ee6487 | 172 | extern int amdgpu_noretry; |
4e66d7d2 | 173 | extern int amdgpu_force_asic_type; |
8c9f69bc | 174 | #ifdef CONFIG_HSA_AMD |
aa978594 | 175 | extern int sched_policy; |
a35ad98b S |
176 | #else |
177 | static const int sched_policy = KFD_SCHED_POLICY_HWS; | |
8c9f69bc | 178 | #endif |
97b2e202 | 179 | |
6dd13096 FK |
180 | #ifdef CONFIG_DRM_AMDGPU_SI |
181 | extern int amdgpu_si_support; | |
182 | #endif | |
7df28986 FK |
183 | #ifdef CONFIG_DRM_AMDGPU_CIK |
184 | extern int amdgpu_cik_support; | |
185 | #endif | |
97b2e202 | 186 | |
08d1bdd4 | 187 | #define AMDGPU_VM_MAX_NUM_CTX 4096 |
6c8d74ca | 188 | #define AMDGPU_SG_THRESHOLD (256*1024*1024) |
55ed8caf | 189 | #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ |
4b559c90 | 190 | #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 |
97b2e202 | 191 | #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
8c5e13ec | 192 | #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
97b2e202 AD |
193 | /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ |
194 | #define AMDGPU_IB_POOL_SIZE 16 | |
195 | #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 | |
196 | #define AMDGPUFB_CONN_LIMIT 4 | |
a5bde2f9 | 197 | #define AMDGPU_BIOS_NUM_SCRATCH 16 |
97b2e202 | 198 | |
97b2e202 AD |
199 | /* hard reset data */ |
200 | #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b | |
201 | ||
202 | /* reset flags */ | |
203 | #define AMDGPU_RESET_GFX (1 << 0) | |
204 | #define AMDGPU_RESET_COMPUTE (1 << 1) | |
205 | #define AMDGPU_RESET_DMA (1 << 2) | |
206 | #define AMDGPU_RESET_CP (1 << 3) | |
207 | #define AMDGPU_RESET_GRBM (1 << 4) | |
208 | #define AMDGPU_RESET_DMA1 (1 << 5) | |
209 | #define AMDGPU_RESET_RLC (1 << 6) | |
210 | #define AMDGPU_RESET_SEM (1 << 7) | |
211 | #define AMDGPU_RESET_IH (1 << 8) | |
212 | #define AMDGPU_RESET_VMC (1 << 9) | |
213 | #define AMDGPU_RESET_MC (1 << 10) | |
214 | #define AMDGPU_RESET_DISPLAY (1 << 11) | |
215 | #define AMDGPU_RESET_UVD (1 << 12) | |
216 | #define AMDGPU_RESET_VCE (1 << 13) | |
217 | #define AMDGPU_RESET_VCE1 (1 << 14) | |
218 | ||
97b2e202 AD |
219 | /* max cursor sizes (in pixels) */ |
220 | #define CIK_CURSOR_WIDTH 128 | |
221 | #define CIK_CURSOR_HEIGHT 128 | |
222 | ||
223 | struct amdgpu_device; | |
97b2e202 | 224 | struct amdgpu_ib; |
97b2e202 | 225 | struct amdgpu_cs_parser; |
bb977d37 | 226 | struct amdgpu_job; |
97b2e202 | 227 | struct amdgpu_irq_src; |
0b492a4c | 228 | struct amdgpu_fpriv; |
9cca0b8e | 229 | struct amdgpu_bo_va_mapping; |
102c16a0 | 230 | struct amdgpu_atif; |
992af942 | 231 | struct kfd_vm_fault_info; |
97b2e202 AD |
232 | |
233 | enum amdgpu_cp_irq { | |
53b2fe41 HZ |
234 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, |
235 | AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, | |
97b2e202 AD |
236 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, |
237 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, | |
238 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, | |
239 | AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, | |
240 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, | |
241 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, | |
242 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, | |
243 | AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, | |
244 | ||
245 | AMDGPU_CP_IRQ_LAST | |
246 | }; | |
247 | ||
97b2e202 AD |
248 | enum amdgpu_thermal_irq { |
249 | AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, | |
250 | AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, | |
251 | ||
252 | AMDGPU_THERMAL_IRQ_LAST | |
253 | }; | |
254 | ||
4e638ae9 XY |
255 | enum amdgpu_kiq_irq { |
256 | AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, | |
257 | AMDGPU_CP_KIQ_IRQ_LAST | |
258 | }; | |
259 | ||
3890d111 ED |
260 | #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ |
261 | #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ | |
4944af67 | 262 | #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ |
3890d111 | 263 | |
43fa561f | 264 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
265 | enum amd_ip_block_type block_type, |
266 | enum amd_clockgating_state state); | |
43fa561f | 267 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
268 | enum amd_ip_block_type block_type, |
269 | enum amd_powergating_state state); | |
270 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, | |
271 | u32 *flags); | |
272 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, | |
273 | enum amd_ip_block_type block_type); | |
274 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, | |
275 | enum amd_ip_block_type block_type); | |
97b2e202 | 276 | |
a1255107 AD |
277 | #define AMDGPU_MAX_IP_NUM 16 |
278 | ||
279 | struct amdgpu_ip_block_status { | |
280 | bool valid; | |
281 | bool sw; | |
282 | bool hw; | |
283 | bool late_initialized; | |
284 | bool hang; | |
285 | }; | |
286 | ||
97b2e202 | 287 | struct amdgpu_ip_block_version { |
a1255107 AD |
288 | const enum amd_ip_block_type type; |
289 | const u32 major; | |
290 | const u32 minor; | |
291 | const u32 rev; | |
5fc3aeeb | 292 | const struct amd_ip_funcs *funcs; |
97b2e202 AD |
293 | }; |
294 | ||
efe4f000 TY |
295 | #define HW_REV(_Major, _Minor, _Rev) \ |
296 | ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) | |
297 | ||
a1255107 AD |
298 | struct amdgpu_ip_block { |
299 | struct amdgpu_ip_block_status status; | |
300 | const struct amdgpu_ip_block_version *version; | |
301 | }; | |
302 | ||
2990a1fc AD |
303 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
304 | enum amd_ip_block_type type, | |
305 | u32 major, u32 minor); | |
97b2e202 | 306 | |
2990a1fc AD |
307 | struct amdgpu_ip_block * |
308 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
309 | enum amd_ip_block_type type); | |
a1255107 | 310 | |
2990a1fc AD |
311 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
312 | const struct amdgpu_ip_block_version *ip_block_version); | |
97b2e202 | 313 | |
97b2e202 AD |
314 | /* |
315 | * BIOS. | |
316 | */ | |
317 | bool amdgpu_get_bios(struct amdgpu_device *adev); | |
318 | bool amdgpu_read_bios(struct amdgpu_device *adev); | |
319 | ||
97b2e202 AD |
320 | /* |
321 | * Clocks | |
322 | */ | |
323 | ||
324 | #define AMDGPU_MAX_PPLL 3 | |
325 | ||
326 | struct amdgpu_clock { | |
327 | struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; | |
328 | struct amdgpu_pll spll; | |
329 | struct amdgpu_pll mpll; | |
330 | /* 10 Khz units */ | |
331 | uint32_t default_mclk; | |
332 | uint32_t default_sclk; | |
333 | uint32_t default_dispclk; | |
334 | uint32_t current_dispclk; | |
335 | uint32_t dp_extclk; | |
336 | uint32_t max_pixel_clock; | |
337 | }; | |
338 | ||
97b2e202 AD |
339 | /* sub-allocation manager, it has to be protected by another lock. |
340 | * By conception this is an helper for other part of the driver | |
341 | * like the indirect buffer or semaphore, which both have their | |
342 | * locking. | |
343 | * | |
344 | * Principe is simple, we keep a list of sub allocation in offset | |
345 | * order (first entry has offset == 0, last entry has the highest | |
346 | * offset). | |
347 | * | |
348 | * When allocating new object we first check if there is room at | |
349 | * the end total_size - (last_object_offset + last_object_size) >= | |
350 | * alloc_size. If so we allocate new object there. | |
351 | * | |
352 | * When there is not enough room at the end, we start waiting for | |
353 | * each sub object until we reach object_offset+object_size >= | |
354 | * alloc_size, this object then become the sub object we return. | |
355 | * | |
356 | * Alignment can't be bigger than page size. | |
357 | * | |
358 | * Hole are not considered for allocation to keep things simple. | |
359 | * Assumption is that there won't be hole (all object on same | |
360 | * alignment). | |
361 | */ | |
6ba60b89 CK |
362 | |
363 | #define AMDGPU_SA_NUM_FENCE_LISTS 32 | |
364 | ||
97b2e202 AD |
365 | struct amdgpu_sa_manager { |
366 | wait_queue_head_t wq; | |
367 | struct amdgpu_bo *bo; | |
368 | struct list_head *hole; | |
6ba60b89 | 369 | struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; |
97b2e202 AD |
370 | struct list_head olist; |
371 | unsigned size; | |
372 | uint64_t gpu_addr; | |
373 | void *cpu_ptr; | |
374 | uint32_t domain; | |
375 | uint32_t align; | |
376 | }; | |
377 | ||
97b2e202 AD |
378 | /* sub-allocation buffer */ |
379 | struct amdgpu_sa_bo { | |
380 | struct list_head olist; | |
381 | struct list_head flist; | |
382 | struct amdgpu_sa_manager *manager; | |
383 | unsigned soffset; | |
384 | unsigned eoffset; | |
f54d1867 | 385 | struct dma_fence *fence; |
97b2e202 AD |
386 | }; |
387 | ||
d573de2d RZ |
388 | int amdgpu_fence_slab_init(void); |
389 | void amdgpu_fence_slab_fini(void); | |
97b2e202 | 390 | |
c8e42d57 | 391 | enum amdgpu_ib_pool_type { |
392 | AMDGPU_IB_POOL_NORMAL = 0, | |
393 | AMDGPU_IB_POOL_VM, | |
394 | AMDGPU_IB_POOL_DIRECT, | |
395 | ||
396 | AMDGPU_IB_POOL_MAX | |
397 | }; | |
97b2e202 AD |
398 | /* |
399 | * IRQS. | |
400 | */ | |
401 | ||
402 | struct amdgpu_flip_work { | |
325cbba1 | 403 | struct delayed_work flip_work; |
97b2e202 AD |
404 | struct work_struct unpin_work; |
405 | struct amdgpu_device *adev; | |
406 | int crtc_id; | |
325cbba1 | 407 | u32 target_vblank; |
97b2e202 AD |
408 | uint64_t base; |
409 | struct drm_pending_vblank_event *event; | |
765e7fbf | 410 | struct amdgpu_bo *old_abo; |
f54d1867 | 411 | struct dma_fence *excl; |
1ffd2652 | 412 | unsigned shared_count; |
f54d1867 CW |
413 | struct dma_fence **shared; |
414 | struct dma_fence_cb cb; | |
cb9e59d7 | 415 | bool async; |
97b2e202 AD |
416 | }; |
417 | ||
418 | ||
419 | /* | |
420 | * CP & rings. | |
421 | */ | |
422 | ||
423 | struct amdgpu_ib { | |
424 | struct amdgpu_sa_bo *sa_bo; | |
425 | uint32_t length_dw; | |
426 | uint64_t gpu_addr; | |
427 | uint32_t *ptr; | |
de807f81 | 428 | uint32_t flags; |
97b2e202 AD |
429 | }; |
430 | ||
1b1f42d8 | 431 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
c1b69ed0 | 432 | |
97b2e202 AD |
433 | /* |
434 | * file private structure | |
435 | */ | |
436 | ||
437 | struct amdgpu_fpriv { | |
438 | struct amdgpu_vm vm; | |
b85891bd | 439 | struct amdgpu_bo_va *prt_va; |
0f4b3c68 | 440 | struct amdgpu_bo_va *csa_va; |
97b2e202 AD |
441 | struct mutex bo_list_lock; |
442 | struct idr bo_list_handles; | |
0b492a4c | 443 | struct amdgpu_ctx_mgr ctx_mgr; |
97b2e202 AD |
444 | }; |
445 | ||
021830d2 BN |
446 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); |
447 | ||
b07c60c0 | 448 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
c8e42d57 | 449 | unsigned size, |
450 | enum amdgpu_ib_pool_type pool, | |
451 | struct amdgpu_ib *ib); | |
4d9c514d | 452 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, |
f54d1867 | 453 | struct dma_fence *f); |
b07c60c0 | 454 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, |
50ddc75e JZ |
455 | struct amdgpu_ib *ibs, struct amdgpu_job *job, |
456 | struct dma_fence **f); | |
97b2e202 AD |
457 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); |
458 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
459 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
97b2e202 AD |
460 | |
461 | /* | |
462 | * CS. | |
463 | */ | |
464 | struct amdgpu_cs_chunk { | |
465 | uint32_t chunk_id; | |
466 | uint32_t length_dw; | |
758ac17f | 467 | void *kdata; |
97b2e202 AD |
468 | }; |
469 | ||
2624dd15 CZ |
470 | struct amdgpu_cs_post_dep { |
471 | struct drm_syncobj *syncobj; | |
472 | struct dma_fence_chain *chain; | |
473 | u64 point; | |
474 | }; | |
475 | ||
97b2e202 AD |
476 | struct amdgpu_cs_parser { |
477 | struct amdgpu_device *adev; | |
478 | struct drm_file *filp; | |
3cb485f3 | 479 | struct amdgpu_ctx *ctx; |
c3cca41e | 480 | |
97b2e202 AD |
481 | /* chunks */ |
482 | unsigned nchunks; | |
483 | struct amdgpu_cs_chunk *chunks; | |
97b2e202 | 484 | |
50838c8c CK |
485 | /* scheduler job object */ |
486 | struct amdgpu_job *job; | |
0d346a14 | 487 | struct drm_sched_entity *entity; |
97b2e202 | 488 | |
c3cca41e CK |
489 | /* buffer objects */ |
490 | struct ww_acquire_ctx ticket; | |
491 | struct amdgpu_bo_list *bo_list; | |
3fe89771 | 492 | struct amdgpu_mn *mn; |
c3cca41e CK |
493 | struct amdgpu_bo_list_entry vm_pd; |
494 | struct list_head validated; | |
f54d1867 | 495 | struct dma_fence *fence; |
c3cca41e | 496 | uint64_t bytes_moved_threshold; |
00f06b24 | 497 | uint64_t bytes_moved_vis_threshold; |
c3cca41e | 498 | uint64_t bytes_moved; |
00f06b24 | 499 | uint64_t bytes_moved_vis; |
97b2e202 AD |
500 | |
501 | /* user fence */ | |
91acbeb6 | 502 | struct amdgpu_bo_list_entry uf_entry; |
660e8558 | 503 | |
2624dd15 CZ |
504 | unsigned num_post_deps; |
505 | struct amdgpu_cs_post_dep *post_deps; | |
97b2e202 AD |
506 | }; |
507 | ||
7270f839 CK |
508 | static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, |
509 | uint32_t ib_idx, int idx) | |
97b2e202 | 510 | { |
50838c8c | 511 | return p->job->ibs[ib_idx].ptr[idx]; |
97b2e202 AD |
512 | } |
513 | ||
7270f839 CK |
514 | static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, |
515 | uint32_t ib_idx, int idx, | |
516 | uint32_t value) | |
517 | { | |
50838c8c | 518 | p->job->ibs[ib_idx].ptr[idx] = value; |
7270f839 CK |
519 | } |
520 | ||
97b2e202 AD |
521 | /* |
522 | * Writeback | |
523 | */ | |
73469585 | 524 | #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ |
97b2e202 AD |
525 | |
526 | struct amdgpu_wb { | |
527 | struct amdgpu_bo *wb_obj; | |
528 | volatile uint32_t *wb; | |
529 | uint64_t gpu_addr; | |
530 | u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ | |
531 | unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; | |
532 | }; | |
533 | ||
131b4b36 AD |
534 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); |
535 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); | |
97b2e202 | 536 | |
97b2e202 AD |
537 | /* |
538 | * Benchmarking | |
539 | */ | |
540 | void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); | |
541 | ||
542 | ||
543 | /* | |
544 | * Testing | |
545 | */ | |
546 | void amdgpu_test_moves(struct amdgpu_device *adev); | |
97b2e202 | 547 | |
97b2e202 AD |
548 | /* |
549 | * ASIC specific register table accessible by UMD | |
550 | */ | |
551 | struct amdgpu_allowed_register_entry { | |
552 | uint32_t reg_offset; | |
97b2e202 AD |
553 | bool grbm_indexed; |
554 | }; | |
555 | ||
0cf3c64f AD |
556 | enum amd_reset_method { |
557 | AMD_RESET_METHOD_LEGACY = 0, | |
558 | AMD_RESET_METHOD_MODE0, | |
559 | AMD_RESET_METHOD_MODE1, | |
560 | AMD_RESET_METHOD_MODE2, | |
561 | AMD_RESET_METHOD_BACO | |
562 | }; | |
563 | ||
97b2e202 AD |
564 | /* |
565 | * ASIC specific functions. | |
566 | */ | |
567 | struct amdgpu_asic_funcs { | |
568 | bool (*read_disabled_bios)(struct amdgpu_device *adev); | |
7946b878 AD |
569 | bool (*read_bios_from_rom)(struct amdgpu_device *adev, |
570 | u8 *bios, u32 length_bytes); | |
97b2e202 AD |
571 | int (*read_register)(struct amdgpu_device *adev, u32 se_num, |
572 | u32 sh_num, u32 reg_offset, u32 *value); | |
573 | void (*set_vga_state)(struct amdgpu_device *adev, bool state); | |
574 | int (*reset)(struct amdgpu_device *adev); | |
0cf3c64f | 575 | enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); |
97b2e202 AD |
576 | /* get the reference clock */ |
577 | u32 (*get_xclk)(struct amdgpu_device *adev); | |
97b2e202 AD |
578 | /* MM block clocks */ |
579 | int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); | |
580 | int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); | |
841686df MB |
581 | /* static power management */ |
582 | int (*get_pcie_lanes)(struct amdgpu_device *adev); | |
583 | void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); | |
bbf282d8 AD |
584 | /* get config memsize register */ |
585 | u32 (*get_config_memsize)(struct amdgpu_device *adev); | |
2df1b8b6 | 586 | /* flush hdp write queue */ |
69882565 | 587 | void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
2df1b8b6 | 588 | /* invalidate hdp read cache */ |
69882565 CK |
589 | void (*invalidate_hdp)(struct amdgpu_device *adev, |
590 | struct amdgpu_ring *ring); | |
4a89ad9b | 591 | void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); |
69070690 AD |
592 | /* check if the asic needs a full reset of if soft reset will work */ |
593 | bool (*need_full_reset)(struct amdgpu_device *adev); | |
5253163a OZ |
594 | /* initialize doorbell layout for specific asic*/ |
595 | void (*init_doorbell_index)(struct amdgpu_device *adev); | |
b45e18ac KR |
596 | /* PCIe bandwidth usage */ |
597 | void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, | |
598 | uint64_t *count1); | |
44401889 AD |
599 | /* do we need to reset the asic at init time (e.g., kexec) */ |
600 | bool (*need_reset_on_init)(struct amdgpu_device *adev); | |
dcea6e65 KR |
601 | /* PCIe replay counter */ |
602 | uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); | |
69d5436d AD |
603 | /* device supports BACO */ |
604 | bool (*supports_baco)(struct amdgpu_device *adev); | |
97b2e202 AD |
605 | }; |
606 | ||
607 | /* | |
608 | * IOCTL. | |
609 | */ | |
97b2e202 AD |
610 | int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, |
611 | struct drm_file *filp); | |
612 | ||
97b2e202 | 613 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
7ca24cf2 MO |
614 | int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, |
615 | struct drm_file *filp); | |
97b2e202 | 616 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
eef18a82 JZ |
617 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, |
618 | struct drm_file *filp); | |
97b2e202 | 619 | |
97b2e202 AD |
620 | /* VRAM scratch page for HDP bug, default vram page */ |
621 | struct amdgpu_vram_scratch { | |
622 | struct amdgpu_bo *robj; | |
623 | volatile uint32_t *ptr; | |
624 | u64 gpu_addr; | |
625 | }; | |
626 | ||
627 | /* | |
628 | * ACPI | |
629 | */ | |
97b2e202 AD |
630 | struct amdgpu_atcs_functions { |
631 | bool get_ext_state; | |
632 | bool pcie_perf_req; | |
633 | bool pcie_dev_rdy; | |
634 | bool pcie_bus_width; | |
635 | }; | |
636 | ||
637 | struct amdgpu_atcs { | |
638 | struct amdgpu_atcs_functions functions; | |
639 | }; | |
640 | ||
a05502e5 HC |
641 | /* |
642 | * Firmware VRAM reservation | |
643 | */ | |
644 | struct amdgpu_fw_vram_usage { | |
645 | u64 start_offset; | |
646 | u64 size; | |
647 | struct amdgpu_bo *reserved_bo; | |
648 | void *va; | |
efe4f000 | 649 | |
8d40002f | 650 | /* GDDR6 training support flag. |
efe4f000 | 651 | */ |
efe4f000 | 652 | bool mem_train_support; |
a05502e5 HC |
653 | }; |
654 | ||
d03846af CZ |
655 | /* |
656 | * CGS | |
657 | */ | |
110e6f26 DA |
658 | struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); |
659 | void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); | |
a8fe58ce | 660 | |
97b2e202 AD |
661 | /* |
662 | * Core structure, functions and helpers. | |
663 | */ | |
664 | typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); | |
665 | typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); | |
666 | ||
4fa1c6a6 TZ |
667 | typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); |
668 | typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); | |
669 | ||
97b2e202 AD |
670 | typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); |
671 | typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); | |
672 | ||
88807dc8 OZ |
673 | struct amdgpu_mmio_remap { |
674 | u32 reg_offset; | |
675 | resource_size_t bus_addr; | |
676 | }; | |
677 | ||
4522824c SL |
678 | /* Define the HW IP blocks will be used in driver , add more if necessary */ |
679 | enum amd_hw_ip_block_type { | |
680 | GC_HWIP = 1, | |
681 | HDP_HWIP, | |
682 | SDMA0_HWIP, | |
683 | SDMA1_HWIP, | |
fa5d2e6f LM |
684 | SDMA2_HWIP, |
685 | SDMA3_HWIP, | |
686 | SDMA4_HWIP, | |
687 | SDMA5_HWIP, | |
688 | SDMA6_HWIP, | |
689 | SDMA7_HWIP, | |
4522824c SL |
690 | MMHUB_HWIP, |
691 | ATHUB_HWIP, | |
692 | NBIO_HWIP, | |
693 | MP0_HWIP, | |
e6636ae1 | 694 | MP1_HWIP, |
4522824c SL |
695 | UVD_HWIP, |
696 | VCN_HWIP = UVD_HWIP, | |
88a1c40a | 697 | JPEG_HWIP = VCN_HWIP, |
4522824c SL |
698 | VCE_HWIP, |
699 | DF_HWIP, | |
700 | DCE_HWIP, | |
701 | OSSSYS_HWIP, | |
702 | SMUIO_HWIP, | |
703 | PWR_HWIP, | |
704 | NBIF_HWIP, | |
e6636ae1 | 705 | THM_HWIP, |
73b19174 | 706 | CLK_HWIP, |
6501a771 HZ |
707 | UMC_HWIP, |
708 | RSMU_HWIP, | |
4522824c SL |
709 | MAX_HWIP |
710 | }; | |
711 | ||
113b47e7 | 712 | #define HWIP_MAX_INSTANCE 8 |
4522824c | 713 | |
11dc9364 | 714 | struct amd_powerplay { |
11dc9364 | 715 | void *pp_handle; |
11dc9364 RZ |
716 | const struct amd_pm_funcs *pp_funcs; |
717 | }; | |
718 | ||
0c49e0b8 | 719 | #define AMDGPU_RESET_MAGIC_NUM 64 |
e4cf4bf5 | 720 | #define AMDGPU_MAX_DF_PERFMONS 4 |
97b2e202 AD |
721 | struct amdgpu_device { |
722 | struct device *dev; | |
723 | struct drm_device *ddev; | |
724 | struct pci_dev *pdev; | |
97b2e202 | 725 | |
a8fe58ce MB |
726 | #ifdef CONFIG_DRM_AMD_ACP |
727 | struct amdgpu_acp acp; | |
728 | #endif | |
729 | ||
97b2e202 | 730 | /* ASIC */ |
2f7d10b3 | 731 | enum amd_asic_type asic_type; |
97b2e202 AD |
732 | uint32_t family; |
733 | uint32_t rev_id; | |
734 | uint32_t external_rev_id; | |
735 | unsigned long flags; | |
736 | int usec_timeout; | |
737 | const struct amdgpu_asic_funcs *asic_funcs; | |
738 | bool shutdown; | |
fd5fd480 | 739 | bool need_swiotlb; |
97b2e202 | 740 | bool accel_working; |
97b2e202 AD |
741 | struct notifier_block acpi_nb; |
742 | struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; | |
743 | struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; | |
edf600da | 744 | unsigned debugfs_count; |
97b2e202 | 745 | #if defined(CONFIG_DEBUG_FS) |
6698a3d0 | 746 | struct dentry *debugfs_preempt; |
adcec288 | 747 | struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; |
97b2e202 | 748 | #endif |
102c16a0 | 749 | struct amdgpu_atif *atif; |
97b2e202 AD |
750 | struct amdgpu_atcs atcs; |
751 | struct mutex srbm_mutex; | |
752 | /* GRBM index mutex. Protects concurrent access to GRBM index */ | |
753 | struct mutex grbm_idx_mutex; | |
754 | struct dev_pm_domain vga_pm_domain; | |
755 | bool have_disp_power_ref; | |
bae17d2a | 756 | bool have_atomics_support; |
97b2e202 AD |
757 | |
758 | /* BIOS */ | |
0cdd5005 | 759 | bool is_atom_fw; |
97b2e202 | 760 | uint8_t *bios; |
a9f5db9c | 761 | uint32_t bios_size; |
5af2c10d | 762 | struct amdgpu_bo *stolen_vga_memory; |
5f6a556f | 763 | struct amdgpu_bo *discovery_memory; |
a5bde2f9 | 764 | uint32_t bios_scratch_reg_offset; |
97b2e202 AD |
765 | uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; |
766 | ||
767 | /* Register/doorbell mmio */ | |
768 | resource_size_t rmmio_base; | |
769 | resource_size_t rmmio_size; | |
770 | void __iomem *rmmio; | |
771 | /* protects concurrent MM_INDEX/DATA based register access */ | |
772 | spinlock_t mmio_idx_lock; | |
88807dc8 | 773 | struct amdgpu_mmio_remap rmmio_remap; |
97b2e202 AD |
774 | /* protects concurrent SMC based register access */ |
775 | spinlock_t smc_idx_lock; | |
776 | amdgpu_rreg_t smc_rreg; | |
777 | amdgpu_wreg_t smc_wreg; | |
778 | /* protects concurrent PCIE register access */ | |
779 | spinlock_t pcie_idx_lock; | |
780 | amdgpu_rreg_t pcie_rreg; | |
781 | amdgpu_wreg_t pcie_wreg; | |
36b9a952 HR |
782 | amdgpu_rreg_t pciep_rreg; |
783 | amdgpu_wreg_t pciep_wreg; | |
4fa1c6a6 TZ |
784 | amdgpu_rreg64_t pcie_rreg64; |
785 | amdgpu_wreg64_t pcie_wreg64; | |
97b2e202 AD |
786 | /* protects concurrent UVD register access */ |
787 | spinlock_t uvd_ctx_idx_lock; | |
788 | amdgpu_rreg_t uvd_ctx_rreg; | |
789 | amdgpu_wreg_t uvd_ctx_wreg; | |
790 | /* protects concurrent DIDT register access */ | |
791 | spinlock_t didt_idx_lock; | |
792 | amdgpu_rreg_t didt_rreg; | |
793 | amdgpu_wreg_t didt_wreg; | |
ccdbb20a RZ |
794 | /* protects concurrent gc_cac register access */ |
795 | spinlock_t gc_cac_idx_lock; | |
796 | amdgpu_rreg_t gc_cac_rreg; | |
797 | amdgpu_wreg_t gc_cac_wreg; | |
16abb5d2 EQ |
798 | /* protects concurrent se_cac register access */ |
799 | spinlock_t se_cac_idx_lock; | |
800 | amdgpu_rreg_t se_cac_rreg; | |
801 | amdgpu_wreg_t se_cac_wreg; | |
97b2e202 AD |
802 | /* protects concurrent ENDPOINT (audio) register access */ |
803 | spinlock_t audio_endpt_idx_lock; | |
804 | amdgpu_block_rreg_t audio_endpt_rreg; | |
805 | amdgpu_block_wreg_t audio_endpt_wreg; | |
806 | void __iomem *rio_mem; | |
807 | resource_size_t rio_mem_size; | |
808 | struct amdgpu_doorbell doorbell; | |
809 | ||
810 | /* clock/pll info */ | |
811 | struct amdgpu_clock clock; | |
812 | ||
813 | /* MC */ | |
770d13b1 | 814 | struct amdgpu_gmc gmc; |
97b2e202 | 815 | struct amdgpu_gart gart; |
92e71b06 | 816 | dma_addr_t dummy_page_addr; |
97b2e202 | 817 | struct amdgpu_vm_manager vm_manager; |
e60f8db5 | 818 | struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; |
1daa2bfa | 819 | unsigned num_vmhubs; |
97b2e202 AD |
820 | |
821 | /* memory management */ | |
822 | struct amdgpu_mman mman; | |
97b2e202 AD |
823 | struct amdgpu_vram_scratch vram_scratch; |
824 | struct amdgpu_wb wb; | |
97b2e202 | 825 | atomic64_t num_bytes_moved; |
dbd5ed60 | 826 | atomic64_t num_evictions; |
68e2c5ff | 827 | atomic64_t num_vram_cpu_page_faults; |
d94aed5a | 828 | atomic_t gpu_reset_counter; |
f1892138 | 829 | atomic_t vram_lost_counter; |
97b2e202 | 830 | |
95844d20 MO |
831 | /* data for buffer migration throttling */ |
832 | struct { | |
833 | spinlock_t lock; | |
834 | s64 last_update_us; | |
835 | s64 accum_us; /* accumulated microseconds */ | |
00f06b24 | 836 | s64 accum_us_vis; /* for visible VRAM */ |
95844d20 MO |
837 | u32 log2_max_MBps; |
838 | } mm_stats; | |
839 | ||
97b2e202 | 840 | /* display */ |
9accf2fd | 841 | bool enable_virtual_display; |
97b2e202 | 842 | struct amdgpu_mode_info mode_info; |
4562236b | 843 | /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ |
97b2e202 AD |
844 | struct work_struct hotplug_work; |
845 | struct amdgpu_irq_src crtc_irq; | |
d2574c33 | 846 | struct amdgpu_irq_src vupdate_irq; |
97b2e202 AD |
847 | struct amdgpu_irq_src pageflip_irq; |
848 | struct amdgpu_irq_src hpd_irq; | |
849 | ||
850 | /* rings */ | |
76bf0db5 | 851 | u64 fence_context; |
97b2e202 AD |
852 | unsigned num_rings; |
853 | struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; | |
854 | bool ib_pool_ready; | |
c8e42d57 | 855 | struct amdgpu_sa_manager ring_tmp_bo[AMDGPU_IB_POOL_MAX]; |
1c6d567b | 856 | struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; |
97b2e202 AD |
857 | |
858 | /* interrupts */ | |
859 | struct amdgpu_irq irq; | |
860 | ||
1f7371b2 AD |
861 | /* powerplay */ |
862 | struct amd_powerplay powerplay; | |
f3898ea1 | 863 | bool pp_force_state_enabled; |
1f7371b2 | 864 | |
137d63ab HR |
865 | /* smu */ |
866 | struct smu_context smu; | |
867 | ||
97b2e202 AD |
868 | /* dpm */ |
869 | struct amdgpu_pm pm; | |
870 | u32 cg_flags; | |
871 | u32 pg_flags; | |
872 | ||
bebc0762 HZ |
873 | /* nbio */ |
874 | struct amdgpu_nbio nbio; | |
875 | ||
d3a5a121 TZ |
876 | /* mmhub */ |
877 | struct amdgpu_mmhub mmhub; | |
878 | ||
97b2e202 AD |
879 | /* gfx */ |
880 | struct amdgpu_gfx gfx; | |
881 | ||
882 | /* sdma */ | |
c113ea1c | 883 | struct amdgpu_sdma sdma; |
97b2e202 | 884 | |
b43aaee6 LL |
885 | /* uvd */ |
886 | struct amdgpu_uvd uvd; | |
887 | ||
888 | /* vce */ | |
889 | struct amdgpu_vce vce; | |
890 | ||
891 | /* vcn */ | |
892 | struct amdgpu_vcn vcn; | |
97b2e202 | 893 | |
88a1c40a LL |
894 | /* jpeg */ |
895 | struct amdgpu_jpeg jpeg; | |
896 | ||
97b2e202 AD |
897 | /* firmwares */ |
898 | struct amdgpu_firmware firmware; | |
899 | ||
0e5ca0d1 HR |
900 | /* PSP */ |
901 | struct psp_context psp; | |
902 | ||
97b2e202 AD |
903 | /* GDS */ |
904 | struct amdgpu_gds gds; | |
905 | ||
611736d8 FK |
906 | /* KFD */ |
907 | struct amdgpu_kfd_dev kfd; | |
908 | ||
045c0216 TZ |
909 | /* UMC */ |
910 | struct amdgpu_umc umc; | |
911 | ||
4562236b HW |
912 | /* display related functionality */ |
913 | struct amdgpu_display_manager dm; | |
914 | ||
f39f5bb1 XY |
915 | /* discovery */ |
916 | uint8_t *discovery; | |
917 | ||
a538bbe7 JX |
918 | /* mes */ |
919 | bool enable_mes; | |
920 | struct amdgpu_mes mes; | |
921 | ||
bdf84a80 JG |
922 | /* df */ |
923 | struct amdgpu_df df; | |
924 | ||
a1255107 | 925 | struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; |
97b2e202 | 926 | int num_ip_blocks; |
97b2e202 AD |
927 | struct mutex mn_lock; |
928 | DECLARE_HASHTABLE(mn_hash, 7); | |
929 | ||
930 | /* tracking pinned memory */ | |
a5ccfe5c MD |
931 | atomic64_t vram_pin_size; |
932 | atomic64_t visible_pin_size; | |
933 | atomic64_t gart_pin_size; | |
130e0371 | 934 | |
4522824c SL |
935 | /* soc15 register offset based on ip, instance and segment */ |
936 | uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; | |
937 | ||
2dc80b00 | 938 | /* delayed work_func for deferring clockgating during resume */ |
beff74bc | 939 | struct delayed_work delayed_init_work; |
2dc80b00 | 940 | |
5a5099cb | 941 | struct amdgpu_virt virt; |
a05502e5 HC |
942 | /* firmware VRAM reservation */ |
943 | struct amdgpu_fw_vram_usage fw_vram_usage; | |
0c4e7fa5 CZ |
944 | |
945 | /* link all shadow bo */ | |
946 | struct list_head shadow_list; | |
947 | struct mutex shadow_list_lock; | |
795f2813 AR |
948 | /* keep an lru list of rings by HW IP */ |
949 | struct list_head ring_lru_list; | |
950 | spinlock_t ring_lru_list_lock; | |
5c1354bd | 951 | |
c836fec5 JQ |
952 | /* record hw reset is performed */ |
953 | bool has_hw_reset; | |
0c49e0b8 | 954 | u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; |
c836fec5 | 955 | |
44779b43 RZ |
956 | /* s3/s4 mask */ |
957 | bool in_suspend; | |
958 | ||
13a752e3 | 959 | bool in_gpu_reset; |
a3a09142 | 960 | enum pp_mp1_state mp1_state; |
13a752e3 | 961 | struct mutex lock_reset; |
409c5191 | 962 | struct amdgpu_doorbell_index doorbell_index; |
d4535e2c | 963 | |
62914a99 JG |
964 | struct mutex notifier_lock; |
965 | ||
26bc5340 | 966 | int asic_reset_res; |
d4535e2c | 967 | struct work_struct xgmi_reset_work; |
9b638f97 | 968 | |
912dfc84 EQ |
969 | long gfx_timeout; |
970 | long sdma_timeout; | |
971 | long video_timeout; | |
972 | long compute_timeout; | |
fb2dbfd2 KR |
973 | |
974 | uint64_t unique_id; | |
e4cf4bf5 | 975 | uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; |
5c5b2ba0 EQ |
976 | |
977 | /* device pstate */ | |
978 | int pstate; | |
6ae6c7d4 AD |
979 | /* enable runtime pm on the device */ |
980 | bool runpm; | |
f0f7ddfc | 981 | bool in_runpm; |
7c868b59 YT |
982 | |
983 | bool pm_sysfs_en; | |
984 | bool ucode_sysfs_en; | |
bd607166 KR |
985 | |
986 | /* Chip product information */ | |
987 | char product_number[16]; | |
988 | char product_name[32]; | |
989 | char serial[16]; | |
97b2e202 AD |
990 | }; |
991 | ||
a7d64de6 CK |
992 | static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) |
993 | { | |
994 | return container_of(bdev, struct amdgpu_device, mman.bdev); | |
995 | } | |
996 | ||
97b2e202 AD |
997 | int amdgpu_device_init(struct amdgpu_device *adev, |
998 | struct drm_device *ddev, | |
999 | struct pci_dev *pdev, | |
1000 | uint32_t flags); | |
1001 | void amdgpu_device_fini(struct amdgpu_device *adev); | |
1002 | int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); | |
1003 | ||
e35e2b11 TY |
1004 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, |
1005 | uint32_t *buf, size_t size, bool write); | |
2eee0229 HZ |
1006 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, |
1007 | uint32_t acc_flags); | |
1008 | void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
15d72fd7 | 1009 | uint32_t acc_flags); |
2e0cc4d4 ML |
1010 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
1011 | uint32_t acc_flags); | |
421a2a30 ML |
1012 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); |
1013 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); | |
1014 | ||
97b2e202 AD |
1015 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); |
1016 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); | |
1017 | ||
4562236b HW |
1018 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); |
1019 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); | |
1020 | ||
9475a943 SL |
1021 | int emu_soc_asic_init(struct amdgpu_device *adev); |
1022 | ||
97b2e202 AD |
1023 | /* |
1024 | * Registers read & write functions. | |
1025 | */ | |
15d72fd7 ML |
1026 | #define AMDGPU_REGS_NO_KIQ (1<<1) |
1027 | ||
2eee0229 HZ |
1028 | #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) |
1029 | #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) | |
15d72fd7 | 1030 | |
f384ff95 HZ |
1031 | #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) |
1032 | #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) | |
c68dbcd8 | 1033 | |
421a2a30 ML |
1034 | #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) |
1035 | #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) | |
1036 | ||
2eee0229 HZ |
1037 | #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) |
1038 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) | |
1039 | #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) | |
97b2e202 AD |
1040 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1041 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1042 | #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) | |
1043 | #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) | |
36b9a952 HR |
1044 | #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) |
1045 | #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) | |
4fa1c6a6 TZ |
1046 | #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) |
1047 | #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) | |
97b2e202 AD |
1048 | #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) |
1049 | #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) | |
1050 | #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) | |
1051 | #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) | |
1052 | #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) | |
1053 | #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) | |
ccdbb20a RZ |
1054 | #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) |
1055 | #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) | |
16abb5d2 EQ |
1056 | #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) |
1057 | #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) | |
97b2e202 AD |
1058 | #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) |
1059 | #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) | |
1060 | #define WREG32_P(reg, val, mask) \ | |
1061 | do { \ | |
1062 | uint32_t tmp_ = RREG32(reg); \ | |
1063 | tmp_ &= (mask); \ | |
1064 | tmp_ |= ((val) & ~(mask)); \ | |
1065 | WREG32(reg, tmp_); \ | |
1066 | } while (0) | |
1067 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | |
1068 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) | |
1069 | #define WREG32_PLL_P(reg, val, mask) \ | |
1070 | do { \ | |
1071 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1072 | tmp_ &= (mask); \ | |
1073 | tmp_ |= ((val) & ~(mask)); \ | |
1074 | WREG32_PLL(reg, tmp_); \ | |
1075 | } while (0) | |
2eee0229 | 1076 | #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) |
97b2e202 AD |
1077 | #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) |
1078 | #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) | |
1079 | ||
97b2e202 AD |
1080 | #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
1081 | #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK | |
1082 | ||
1083 | #define REG_SET_FIELD(orig_val, reg, field, field_val) \ | |
1084 | (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ | |
1085 | (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) | |
1086 | ||
1087 | #define REG_GET_FIELD(value, reg, field) \ | |
1088 | (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) | |
61cb8cef TSD |
1089 | |
1090 | #define WREG32_FIELD(reg, field, val) \ | |
1091 | WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
97b2e202 | 1092 | |
ccaf3574 TSD |
1093 | #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ |
1094 | WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) | |
1095 | ||
97b2e202 AD |
1096 | /* |
1097 | * BIOS helpers. | |
1098 | */ | |
1099 | #define RBIOS8(i) (adev->bios[i]) | |
1100 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1101 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1102 | ||
97b2e202 AD |
1103 | /* |
1104 | * ASICs macro. | |
1105 | */ | |
1106 | #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) | |
1107 | #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) | |
0cf3c64f | 1108 | #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) |
97b2e202 AD |
1109 | #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) |
1110 | #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) | |
1111 | #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) | |
841686df MB |
1112 | #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) |
1113 | #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) | |
1114 | #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) | |
97b2e202 | 1115 | #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) |
7946b878 | 1116 | #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) |
97b2e202 | 1117 | #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) |
bbf282d8 | 1118 | #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) |
69882565 CK |
1119 | #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) |
1120 | #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) | |
69070690 | 1121 | #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) |
5253163a | 1122 | #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) |
b45e18ac | 1123 | #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) |
44401889 | 1124 | #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) |
dcea6e65 | 1125 | #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) |
69d5436d AD |
1126 | #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) |
1127 | ||
e3526257 | 1128 | #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); |
97b2e202 AD |
1129 | |
1130 | /* Common functions */ | |
12938fad | 1131 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); |
5f152b5e | 1132 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, |
12938fad | 1133 | struct amdgpu_job* job); |
8111c387 | 1134 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); |
39c640c0 | 1135 | bool amdgpu_device_need_post(struct amdgpu_device *adev); |
d5fc5e82 | 1136 | |
00f06b24 JB |
1137 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
1138 | u64 num_vis_bytes); | |
d6895ad3 | 1139 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); |
9c3f2b54 | 1140 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
97b2e202 AD |
1141 | const u32 *registers, |
1142 | const u32 array_size); | |
1143 | ||
31af062a | 1144 | bool amdgpu_device_supports_boco(struct drm_device *dev); |
a69cba42 | 1145 | bool amdgpu_device_supports_baco(struct drm_device *dev); |
992af942 JK |
1146 | bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, |
1147 | struct amdgpu_device *peer_adev); | |
361dbd01 AD |
1148 | int amdgpu_device_baco_enter(struct drm_device *dev); |
1149 | int amdgpu_device_baco_exit(struct drm_device *dev); | |
992af942 | 1150 | |
97b2e202 AD |
1151 | /* atpx handler */ |
1152 | #if defined(CONFIG_VGA_SWITCHEROO) | |
1153 | void amdgpu_register_atpx_handler(void); | |
1154 | void amdgpu_unregister_atpx_handler(void); | |
a78fe133 | 1155 | bool amdgpu_has_atpx_dgpu_power_cntl(void); |
2f5af82e | 1156 | bool amdgpu_is_atpx_hybrid(void); |
efc83cf4 | 1157 | bool amdgpu_atpx_dgpu_req_power_for_displays(void); |
714f88e0 | 1158 | bool amdgpu_has_atpx(void); |
97b2e202 AD |
1159 | #else |
1160 | static inline void amdgpu_register_atpx_handler(void) {} | |
1161 | static inline void amdgpu_unregister_atpx_handler(void) {} | |
a78fe133 | 1162 | static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } |
2f5af82e | 1163 | static inline bool amdgpu_is_atpx_hybrid(void) { return false; } |
efc83cf4 | 1164 | static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } |
714f88e0 | 1165 | static inline bool amdgpu_has_atpx(void) { return false; } |
97b2e202 AD |
1166 | #endif |
1167 | ||
24aeefcd LP |
1168 | #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) |
1169 | void *amdgpu_atpx_get_dhandle(void); | |
1170 | #else | |
1171 | static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } | |
1172 | #endif | |
1173 | ||
97b2e202 AD |
1174 | /* |
1175 | * KMS | |
1176 | */ | |
1177 | extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; | |
f498d9ed | 1178 | extern const int amdgpu_max_kms_ioctl; |
97b2e202 AD |
1179 | |
1180 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); | |
11b3c20b | 1181 | void amdgpu_driver_unload_kms(struct drm_device *dev); |
97b2e202 AD |
1182 | void amdgpu_driver_lastclose_kms(struct drm_device *dev); |
1183 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); | |
1184 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
1185 | struct drm_file *file_priv); | |
cdd61df6 | 1186 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev); |
de185019 AD |
1187 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); |
1188 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon); | |
e3eff4b5 TZ |
1189 | u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); |
1190 | int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); | |
1191 | void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); | |
97b2e202 AD |
1192 | long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, |
1193 | unsigned long arg); | |
1194 | ||
97b2e202 AD |
1195 | /* |
1196 | * functions used by amdgpu_encoder.c | |
1197 | */ | |
1198 | struct amdgpu_afmt_acr { | |
1199 | u32 clock; | |
1200 | ||
1201 | int n_32khz; | |
1202 | int cts_32khz; | |
1203 | ||
1204 | int n_44_1khz; | |
1205 | int cts_44_1khz; | |
1206 | ||
1207 | int n_48khz; | |
1208 | int cts_48khz; | |
1209 | ||
1210 | }; | |
1211 | ||
1212 | struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); | |
1213 | ||
1214 | /* amdgpu_acpi.c */ | |
1215 | #if defined(CONFIG_ACPI) | |
1216 | int amdgpu_acpi_init(struct amdgpu_device *adev); | |
1217 | void amdgpu_acpi_fini(struct amdgpu_device *adev); | |
1218 | bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); | |
1219 | int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, | |
1220 | u8 perf_req, bool advertise); | |
1221 | int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); | |
206bbafe DF |
1222 | |
1223 | void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, | |
1224 | struct amdgpu_dm_backlight_caps *caps); | |
97b2e202 AD |
1225 | #else |
1226 | static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } | |
1227 | static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } | |
1228 | #endif | |
1229 | ||
9cca0b8e CK |
1230 | int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, |
1231 | uint64_t addr, struct amdgpu_bo **bo, | |
1232 | struct amdgpu_bo_va_mapping **mapping); | |
97b2e202 | 1233 | |
4562236b HW |
1234 | #if defined(CONFIG_DRM_AMD_DC) |
1235 | int amdgpu_dm_display_resume(struct amdgpu_device *adev ); | |
1236 | #else | |
1237 | static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } | |
1238 | #endif | |
1239 | ||
fdafb359 EQ |
1240 | |
1241 | void amdgpu_register_gpu_instance(struct amdgpu_device *adev); | |
1242 | void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); | |
1243 | ||
97b2e202 | 1244 | #include "amdgpu_object.h" |
e4cf4bf5 JK |
1245 | |
1246 | /* used by df_v3_6.c and amdgpu_pmu.c */ | |
1247 | #define AMDGPU_PMU_ATTR(_name, _object) \ | |
1248 | static ssize_t \ | |
1249 | _name##_show(struct device *dev, \ | |
1250 | struct device_attribute *attr, \ | |
1251 | char *page) \ | |
1252 | { \ | |
1253 | BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ | |
1254 | return sprintf(page, _object "\n"); \ | |
1255 | } \ | |
1256 | \ | |
1257 | static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) | |
1258 | ||
97b2e202 | 1259 | #endif |
e4cf4bf5 | 1260 |