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drm/amdgpu:cleanup in_sriov_reset and lock_reset
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
78c16834 49#include <kgd_kfd_interface.h>
c79563a3
RZ		 50#include "dm_pp_interface.h"
51#include "kgd_pp_interface.h"
78c16834 52
5fc3aeeb 53#include "amd_shared.h"
97b2e202
AD		 54#include "amdgpu_mode.h"
55#include "amdgpu_ih.h"
56#include "amdgpu_irq.h"
57#include "amdgpu_ucode.h"
c632d799 58#include "amdgpu_ttm.h"
0e5ca0d1 59#include "amdgpu_psp.h"
97b2e202 60#include "amdgpu_gds.h"
56113504 61#include "amdgpu_sync.h"
78023016 62#include "amdgpu_ring.h"
073440d2 63#include "amdgpu_vm.h"
cf097881 64#include "amdgpu_dpm.h"
a8fe58ce 65#include "amdgpu_acp.h"
4df654d2 66#include "amdgpu_uvd.h"
5e568178 67#include "amdgpu_vce.h"
95aa13f6 68#include "amdgpu_vcn.h"
9a189996 69#include "amdgpu_mn.h"
4562236b 70#include "amdgpu_dm.h"
b80d8475 71#include "gpu_scheduler.h"
ceeb50ed 72#include "amdgpu_virt.h"
3490bdb5 73#include "amdgpu_gart.h"
b80d8475 74
c79563a3 75
97b2e202
AD		 76/*
77 * Modules parameters.
78 */
79extern int amdgpu_modeset;
80extern int amdgpu_vram_limit;
218b5dcd 81extern int amdgpu_vis_vram_limit;
83e74db6 82extern int amdgpu_gart_size;
36d38372 83extern int amdgpu_gtt_size;
95844d20 84extern int amdgpu_moverate;
97b2e202
AD		 85extern int amdgpu_benchmarking;
86extern int amdgpu_testing;
87extern int amdgpu_audio;
88extern int amdgpu_disp_priority;
89extern int amdgpu_hw_i2c;
90extern int amdgpu_pcie_gen2;
91extern int amdgpu_msi;
92extern int amdgpu_lockup_timeout;
93extern int amdgpu_dpm;
e635ee07 94extern int amdgpu_fw_load_type;
97b2e202
AD		 95extern int amdgpu_aspm;
96extern int amdgpu_runtime_pm;
0b693f0b 97extern uint amdgpu_ip_block_mask;
97b2e202
AD		 98extern int amdgpu_bapm;
99extern int amdgpu_deep_color;
100extern int amdgpu_vm_size;
101extern int amdgpu_vm_block_size;
d07f14be 102extern int amdgpu_vm_fragment_size;
d9c13156 103extern int amdgpu_vm_fault_stop;
b495bd3a 104extern int amdgpu_vm_debug;
9a4b7d4c 105extern int amdgpu_vm_update_mode;
4562236b 106extern int amdgpu_dc;
02e749dc 107extern int amdgpu_dc_log;
1333f723 108extern int amdgpu_sched_jobs;
4afcb303 109extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 110extern int amdgpu_no_evict;
111extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 112extern uint amdgpu_pcie_gen_cap;
113extern uint amdgpu_pcie_lane_cap;
114extern uint amdgpu_cg_mask;
115extern uint amdgpu_pg_mask;
116extern uint amdgpu_sdma_phase_quantum;
6f8941a2 117extern char *amdgpu_disable_cu;
9accf2fd 118extern char *amdgpu_virtual_display;
0b693f0b 119extern uint amdgpu_pp_feature_mask;
6a7f76e7 120extern int amdgpu_vram_page_split;
bce23e00
AD		 121extern int amdgpu_ngg;
122extern int amdgpu_prim_buf_per_se;
123extern int amdgpu_pos_buf_per_se;
124extern int amdgpu_cntl_sb_buf_per_se;
125extern int amdgpu_param_buf_per_se;
65781c78 126extern int amdgpu_job_hang_limit;
e8835e0e 127extern int amdgpu_lbpw;
4a75aefe 128extern int amdgpu_compute_multipipe;
97b2e202 129
6dd13096
FK		 130#ifdef CONFIG_DRM_AMDGPU_SI
131extern int amdgpu_si_support;
132#endif
7df28986
FK		 133#ifdef CONFIG_DRM_AMDGPU_CIK
134extern int amdgpu_cik_support;
135#endif
97b2e202 136
55ed8caf 137#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 138#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 139#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
140#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
141/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
142#define AMDGPU_IB_POOL_SIZE 16
143#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
144#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 145#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 146
36f523a7
JZ		 147/* max number of IP instances */
148#define AMDGPU_MAX_SDMA_INSTANCES 2
149
97b2e202
AD		 150/* hard reset data */
151#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
152
153/* reset flags */
154#define AMDGPU_RESET_GFX (1 << 0)
155#define AMDGPU_RESET_COMPUTE (1 << 1)
156#define AMDGPU_RESET_DMA (1 << 2)
157#define AMDGPU_RESET_CP (1 << 3)
158#define AMDGPU_RESET_GRBM (1 << 4)
159#define AMDGPU_RESET_DMA1 (1 << 5)
160#define AMDGPU_RESET_RLC (1 << 6)
161#define AMDGPU_RESET_SEM (1 << 7)
162#define AMDGPU_RESET_IH (1 << 8)
163#define AMDGPU_RESET_VMC (1 << 9)
164#define AMDGPU_RESET_MC (1 << 10)
165#define AMDGPU_RESET_DISPLAY (1 << 11)
166#define AMDGPU_RESET_UVD (1 << 12)
167#define AMDGPU_RESET_VCE (1 << 13)
168#define AMDGPU_RESET_VCE1 (1 << 14)
169
97b2e202
AD		 170/* GFX current status */
171#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
172#define AMDGPU_GFX_SAFE_MODE 0x00000001L
173#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
174#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
175#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
176
177/* max cursor sizes (in pixels) */
178#define CIK_CURSOR_WIDTH 128
179#define CIK_CURSOR_HEIGHT 128
180
5740682e
ML		 181/* GPU RESET flags */
182#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0)
183#define AMDGPU_RESET_INFO_FULLRESET (1 << 1)
184
97b2e202 185struct amdgpu_device;
97b2e202 186struct amdgpu_ib;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
9cca0b8e 191struct amdgpu_bo_va_mapping;
97b2e202
AD		 192
193enum amdgpu_cp_irq {
194 AMDGPU_CP_IRQ_GFX_EOP = 0,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
203
204 AMDGPU_CP_IRQ_LAST
205};
206
207enum amdgpu_sdma_irq {
208 AMDGPU_SDMA_IRQ_TRAP0 = 0,
209 AMDGPU_SDMA_IRQ_TRAP1,
210
211 AMDGPU_SDMA_IRQ_LAST
212};
213
214enum amdgpu_thermal_irq {
215 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
216 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
217
218 AMDGPU_THERMAL_IRQ_LAST
219};
220
4e638ae9
XY		 221enum amdgpu_kiq_irq {
222 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
223 AMDGPU_CP_KIQ_IRQ_LAST
224};
225
97b2e202 226int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
97b2e202 229int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
6cb2d4e4 232void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 233int amdgpu_wait_for_idle(struct amdgpu_device *adev,
234 enum amd_ip_block_type block_type);
235bool amdgpu_is_idle(struct amdgpu_device *adev,
236 enum amd_ip_block_type block_type);
97b2e202 237
a1255107
AD		 238#define AMDGPU_MAX_IP_NUM 16
239
240struct amdgpu_ip_block_status {
241 bool valid;
242 bool sw;
243 bool hw;
244 bool late_initialized;
245 bool hang;
246};
247
97b2e202 248struct amdgpu_ip_block_version {
a1255107
AD		 249 const enum amd_ip_block_type type;
250 const u32 major;
251 const u32 minor;
252 const u32 rev;
5fc3aeeb 253 const struct amd_ip_funcs *funcs;
97b2e202
AD		 254};
255
a1255107
AD		 256struct amdgpu_ip_block {
257 struct amdgpu_ip_block_status status;
258 const struct amdgpu_ip_block_version *version;
259};
260
97b2e202 261int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 262 enum amd_ip_block_type type,
97b2e202
AD		 263 u32 major, u32 minor);
264
a1255107
AD		 265struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
266 enum amd_ip_block_type type);
267
268int amdgpu_ip_block_add(struct amdgpu_device *adev,
269 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 270
271/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
272struct amdgpu_buffer_funcs {
273 /* maximum bytes in a single operation */
274 uint32_t copy_max_bytes;
275
276 /* number of dw to reserve per operation */
277 unsigned copy_num_dw;
278
279 /* used for buffer migration */
c7ae72c0 280 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 281 /* src addr in bytes */
282 uint64_t src_offset,
283 /* dst addr in bytes */
284 uint64_t dst_offset,
285 /* number of byte to transfer */
286 uint32_t byte_count);
287
288 /* maximum bytes in a single operation */
289 uint32_t fill_max_bytes;
290
291 /* number of dw to reserve per operation */
292 unsigned fill_num_dw;
293
294 /* used for buffer clearing */
6e7a3840 295 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 296 /* value to write to memory */
297 uint32_t src_data,
298 /* dst addr in bytes */
299 uint64_t dst_offset,
300 /* number of byte to fill */
301 uint32_t byte_count);
302};
303
304/* provided by hw blocks that can write ptes, e.g., sdma */
305struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 306 /* number of dw to reserve per operation */
307 unsigned copy_pte_num_dw;
308
97b2e202
AD		 309 /* copy pte entries from GART */
310 void (*copy_pte)(struct amdgpu_ib *ib,
311 uint64_t pe, uint64_t src,
312 unsigned count);
e6d92197 313
97b2e202 314 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 315 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
316 uint64_t value, unsigned count,
317 uint32_t incr);
7bdc53f9
YZ		 318
319 /* maximum nums of PTEs/PDEs in a single operation */
320 uint32_t set_max_nums_pte_pde;
321
322 /* number of dw to reserve per operation */
323 unsigned set_pte_pde_num_dw;
324
97b2e202
AD		 325 /* for linear pte/pde updates without addr mapping */
326 void (*set_pte_pde)(struct amdgpu_ib *ib,
327 uint64_t pe,
328 uint64_t addr, unsigned count,
6b777607 329 uint32_t incr, uint64_t flags);
97b2e202
AD		 330};
331
332/* provided by the gmc block */
333struct amdgpu_gart_funcs {
334 /* flush the vm tlb via mmio */
335 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
336 uint32_t vmid);
337 /* write pte/pde updates using the cpu */
338 int (*set_pte_pde)(struct amdgpu_device *adev,
339 void *cpu_pt_addr, /* cpu addr of page table */
340 uint32_t gpu_page_idx, /* pte/pde to update */
341 uint64_t addr, /* addr to write into pte/pde */
6b777607 342 uint64_t flags); /* access flags */
284710fa
CK		 343 /* enable/disable PRT support */
344 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 345 /* set pte flags based per asic */
346 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
347 uint32_t flags);
b1166325
CK		 348 /* get the pde for a given mc addr */
349 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
03f89feb 350 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 351};
352
97b2e202
AD		 353/* provided by the ih block */
354struct amdgpu_ih_funcs {
355 /* ring read/write ptr handling, called from interrupt context */
356 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 357 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 358 void (*decode_iv)(struct amdgpu_device *adev,
359 struct amdgpu_iv_entry *entry);
360 void (*set_rptr)(struct amdgpu_device *adev);
361};
362
97b2e202
AD		 363/*
364 * BIOS.
365 */
366bool amdgpu_get_bios(struct amdgpu_device *adev);
367bool amdgpu_read_bios(struct amdgpu_device *adev);
368
369/*
370 * Dummy page
371 */
372struct amdgpu_dummy_page {
373 struct page *page;
374 dma_addr_t addr;
375};
376int amdgpu_dummy_page_init(struct amdgpu_device *adev);
377void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
378
379
380/*
381 * Clocks
382 */
383
384#define AMDGPU_MAX_PPLL 3
385
386struct amdgpu_clock {
387 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
388 struct amdgpu_pll spll;
389 struct amdgpu_pll mpll;
390 /* 10 Khz units */
391 uint32_t default_mclk;
392 uint32_t default_sclk;
393 uint32_t default_dispclk;
394 uint32_t current_dispclk;
395 uint32_t dp_extclk;
396 uint32_t max_pixel_clock;
397};
398
97b2e202 399/*
9124a398 400 * GEM.
97b2e202 401 */
97b2e202 402
7e5a547f 403#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 404#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
405
406void amdgpu_gem_object_free(struct drm_gem_object *obj);
407int amdgpu_gem_object_open(struct drm_gem_object *obj,
408 struct drm_file *file_priv);
409void amdgpu_gem_object_close(struct drm_gem_object *obj,
410 struct drm_file *file_priv);
411unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
412struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 413struct drm_gem_object *
414amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
415 struct dma_buf_attachment *attach,
416 struct sg_table *sg);
97b2e202
AD		 417struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
418 struct drm_gem_object *gobj,
419 int flags);
420int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
421void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
422struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
423void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
424void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 425int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 426int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
427
428/* sub-allocation manager, it has to be protected by another lock.
429 * By conception this is an helper for other part of the driver
430 * like the indirect buffer or semaphore, which both have their
431 * locking.
432 *
433 * Principe is simple, we keep a list of sub allocation in offset
434 * order (first entry has offset == 0, last entry has the highest
435 * offset).
436 *
437 * When allocating new object we first check if there is room at
438 * the end total_size - (last_object_offset + last_object_size) >=
439 * alloc_size. If so we allocate new object there.
440 *
441 * When there is not enough room at the end, we start waiting for
442 * each sub object until we reach object_offset+object_size >=
443 * alloc_size, this object then become the sub object we return.
444 *
445 * Alignment can't be bigger than page size.
446 *
447 * Hole are not considered for allocation to keep things simple.
448 * Assumption is that there won't be hole (all object on same
449 * alignment).
450 */
6ba60b89
CK		 451
452#define AMDGPU_SA_NUM_FENCE_LISTS 32
453
97b2e202
AD		 454struct amdgpu_sa_manager {
455 wait_queue_head_t wq;
456 struct amdgpu_bo *bo;
457 struct list_head *hole;
6ba60b89 458 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 459 struct list_head olist;
460 unsigned size;
461 uint64_t gpu_addr;
462 void *cpu_ptr;
463 uint32_t domain;
464 uint32_t align;
465};
466
97b2e202
AD		 467/* sub-allocation buffer */
468struct amdgpu_sa_bo {
469 struct list_head olist;
470 struct list_head flist;
471 struct amdgpu_sa_manager *manager;
472 unsigned soffset;
473 unsigned eoffset;
f54d1867 474 struct dma_fence *fence;
97b2e202
AD		 475};
476
477/*
478 * GEM objects.
479 */
418aa0c2 480void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 481int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 482 int alignment, u32 initial_domain,
483 u64 flags, bool kernel,
484 struct reservation_object *resv,
485 struct drm_gem_object **obj);
97b2e202
AD		 486
487int amdgpu_mode_dumb_create(struct drm_file *file_priv,
488 struct drm_device *dev,
489 struct drm_mode_create_dumb *args);
490int amdgpu_mode_dumb_mmap(struct drm_file *filp,
491 struct drm_device *dev,
492 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 493int amdgpu_fence_slab_init(void);
494void amdgpu_fence_slab_fini(void);
97b2e202 495
e60f8db5
AX		 496/*
497 * VMHUB structures, functions & helpers
498 */
499struct amdgpu_vmhub {
500 uint32_t ctx0_ptb_addr_lo32;
501 uint32_t ctx0_ptb_addr_hi32;
502 uint32_t vm_inv_eng0_req;
503 uint32_t vm_inv_eng0_ack;
504 uint32_t vm_context0_cntl;
505 uint32_t vm_l2_pro_fault_status;
506 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 507};
508
97b2e202
AD		 509/*
510 * GPU MC structures, functions & helpers
511 */
512struct amdgpu_mc {
513 resource_size_t aper_size;
514 resource_size_t aper_base;
515 resource_size_t agp_base;
516 /* for some chips with <= 32MB we need to lie
517 * about vram size near mc fb location */
518 u64 mc_vram_size;
519 u64 visible_vram_size;
6f02a696
CK		 520 u64 gart_size;
521 u64 gart_start;
522 u64 gart_end;
97b2e202
AD		 523 u64 vram_start;
524 u64 vram_end;
525 unsigned vram_width;
526 u64 real_vram_size;
527 int vram_mtrr;
97b2e202
AD		 528 u64 mc_mask;
529 const struct firmware *fw; /* MC firmware */
530 uint32_t fw_version;
531 struct amdgpu_irq_src vm_fault;
81c59f54 532 uint32_t vram_type;
50b0197a 533 uint32_t srbm_soft_reset;
f7c35abe 534 bool prt_warning;
916910ad 535 uint64_t stolen_size;
8fe73328
JZ		 536 /* apertures */
537 u64 shared_aperture_start;
538 u64 shared_aperture_end;
539 u64 private_aperture_start;
540 u64 private_aperture_end;
e60f8db5
AX		 541 /* protects concurrent invalidation */
542 spinlock_t invalidate_lock;
97b2e202
AD		 543};
544
545/*
546 * GPU doorbell structures, functions & helpers
547 */
548typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
549{
550 AMDGPU_DOORBELL_KIQ = 0x000,
551 AMDGPU_DOORBELL_HIQ = 0x001,
552 AMDGPU_DOORBELL_DIQ = 0x002,
553 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
554 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
555 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
556 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
557 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
558 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
559 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
560 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
561 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
562 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
563 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
564 AMDGPU_DOORBELL_IH = 0x1E8,
565 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
566 AMDGPU_DOORBELL_INVALID = 0xFFFF
567} AMDGPU_DOORBELL_ASSIGNMENT;
568
569struct amdgpu_doorbell {
570 /* doorbell mmio */
571 resource_size_t base;
572 resource_size_t size;
573 u32 __iomem *ptr;
574 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
575};
576
39807b93
KW		 577/*
578 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
579 */
580typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
581{
582 /*
583 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
584 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
585 * Compute related doorbells are allocated from 0x00 to 0x8a
586 */
587
588
589 /* kernel scheduling */
590 AMDGPU_DOORBELL64_KIQ = 0x00,
591
592 /* HSA interface queue and debug queue */
593 AMDGPU_DOORBELL64_HIQ = 0x01,
594 AMDGPU_DOORBELL64_DIQ = 0x02,
595
596 /* Compute engines */
597 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
598 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
599 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
600 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
601 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
602 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
603 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
604 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
605
606 /* User queue doorbell range (128 doorbells) */
607 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
608 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
609
610 /* Graphics engine */
611 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
612
613 /*
614 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
615 * Graphics voltage island aperture 1
616 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
617 */
618
619 /* sDMA engines */
620 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
621 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
622 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
623 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
624
625 /* Interrupt handler */
626 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
627 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
628 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
629
e6b3ecb4
ML		 630 /* VCN engine use 32 bits doorbell */
631 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
632 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
633 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
634 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
635
636 /* overlap the doorbell assignment with VCN as they are mutually exclusive
637 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
638 */
4ed11d79
FM		 639 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
640 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
641 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
642 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
643
644 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
645 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
646 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
647 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 648
649 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
650 AMDGPU_DOORBELL64_INVALID = 0xFFFF
651} AMDGPU_DOORBELL64_ASSIGNMENT;
652
653
97b2e202
AD		 654void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
655 phys_addr_t *aperture_base,
656 size_t *aperture_size,
657 size_t *start_offset);
658
659/*
660 * IRQS.
661 */
662
663struct amdgpu_flip_work {
325cbba1 664 struct delayed_work flip_work;
97b2e202
AD		 665 struct work_struct unpin_work;
666 struct amdgpu_device *adev;
667 int crtc_id;
325cbba1 668 u32 target_vblank;
97b2e202
AD		 669 uint64_t base;
670 struct drm_pending_vblank_event *event;
765e7fbf 671 struct amdgpu_bo *old_abo;
f54d1867 672 struct dma_fence *excl;
1ffd2652 673 unsigned shared_count;
f54d1867
CW		 674 struct dma_fence **shared;
675 struct dma_fence_cb cb;
cb9e59d7 676 bool async;
97b2e202
AD		 677};
678
679
680/*
681 * CP & rings.
682 */
683
684struct amdgpu_ib {
685 struct amdgpu_sa_bo *sa_bo;
686 uint32_t length_dw;
687 uint64_t gpu_addr;
688 uint32_t *ptr;
de807f81 689 uint32_t flags;
97b2e202
AD		 690};
691
62250a91 692extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 693
50838c8c 694int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 695 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 696int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
697 struct amdgpu_job **job);
b6723c8d 698
a5fb4ec2 699void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 700void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 701int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa 702 struct amd_sched_entity *entity, void *owner,
f54d1867 703 struct dma_fence **f);
8b4fb00b 704
effd924d
AR		 705/*
706 * Queue manager
707 */
708struct amdgpu_queue_mapper {
709 int hw_ip;
710 struct mutex lock;
711 /* protected by lock */
712 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
713};
714
715struct amdgpu_queue_mgr {
716 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
717};
718
719int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
720 struct amdgpu_queue_mgr *mgr);
721int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
722 struct amdgpu_queue_mgr *mgr);
723int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
724 struct amdgpu_queue_mgr *mgr,
fa7c7939 725 u32 hw_ip, u32 instance, u32 ring,
effd924d
AR		 726 struct amdgpu_ring **out_ring);
727
97b2e202
AD		 728/*
729 * context related structures
730 */
731
21c16bf6 732struct amdgpu_ctx_ring {
91404fb2 733 uint64_t sequence;
f54d1867 734 struct dma_fence **fences;
91404fb2 735 struct amd_sched_entity entity;
21c16bf6
CK		 736};
737
97b2e202 738struct amdgpu_ctx {
0b492a4c 739 struct kref refcount;
9cb7e5a9 740 struct amdgpu_device *adev;
effd924d 741 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 742 unsigned reset_counter;
668ca1b4 743 unsigned reset_counter_query;
e55f2b64 744 uint32_t vram_lost_counter;
21c16bf6 745 spinlock_t ring_lock;
f54d1867 746 struct dma_fence **fences;
21c16bf6 747 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
e55f2b64 748 bool preamble_presented;
c23be4ae
AR		 749 enum amd_sched_priority init_priority;
750 enum amd_sched_priority override_priority;
0ae94444 751 struct mutex lock;
1102900d 752 atomic_t guilty;
97b2e202
AD		 753};
754
755struct amdgpu_ctx_mgr {
0b492a4c
AD		 756 struct amdgpu_device *adev;
757 struct mutex lock;
758 /* protected by lock */
759 struct idr ctx_handles;
97b2e202
AD		 760};
761
0b492a4c
AD		 762struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
763int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
764
eb01abc7
ML		 765int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
766 struct dma_fence *fence, uint64_t *seq);
f54d1867 767struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 768 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae
AR		 769void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
770 enum amd_sched_priority priority);
21c16bf6 771
0b492a4c
AD		 772int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
773 struct drm_file *filp);
774
0ae94444
AG		 775int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
776
efd4ccb5
CK		 777void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
778void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 779
0ae94444 780
97b2e202
AD		 781/*
782 * file private structure
783 */
784
785struct amdgpu_fpriv {
786 struct amdgpu_vm vm;
b85891bd 787 struct amdgpu_bo_va *prt_va;
0f4b3c68 788 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 789 struct mutex bo_list_lock;
790 struct idr bo_list_handles;
0b492a4c 791 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 792};
793
794/*
795 * residency list
796 */
9124a398
CK		 797struct amdgpu_bo_list_entry {
798 struct amdgpu_bo *robj;
799 struct ttm_validate_buffer tv;
800 struct amdgpu_bo_va *bo_va;
801 uint32_t priority;
802 struct page **user_pages;
803 int user_invalidated;
804};
97b2e202
AD		 805
806struct amdgpu_bo_list {
807 struct mutex lock;
5ac55629
AX		 808 struct rcu_head rhead;
809 struct kref refcount;
97b2e202
AD		 810 struct amdgpu_bo *gds_obj;
811 struct amdgpu_bo *gws_obj;
812 struct amdgpu_bo *oa_obj;
211dff55 813 unsigned first_userptr;
97b2e202
AD		 814 unsigned num_entries;
815 struct amdgpu_bo_list_entry *array;
816};
817
818struct amdgpu_bo_list *
819amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 820void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
821 struct list_head *validated);
97b2e202
AD		 822void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
823void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
824
825/*
826 * GFX stuff
827 */
828#include "clearstate_defs.h"
829
79e5412c
AD		 830struct amdgpu_rlc_funcs {
831 void (*enter_safe_mode)(struct amdgpu_device *adev);
832 void (*exit_safe_mode)(struct amdgpu_device *adev);
833};
834
97b2e202
AD		 835struct amdgpu_rlc {
836 /* for power gating */
837 struct amdgpu_bo *save_restore_obj;
838 uint64_t save_restore_gpu_addr;
839 volatile uint32_t *sr_ptr;
840 const u32 *reg_list;
841 u32 reg_list_size;
842 /* for clear state */
843 struct amdgpu_bo *clear_state_obj;
844 uint64_t clear_state_gpu_addr;
845 volatile uint32_t *cs_ptr;
846 const struct cs_section_def *cs_data;
847 u32 clear_state_size;
848 /* for cp tables */
849 struct amdgpu_bo *cp_table_obj;
850 uint64_t cp_table_gpu_addr;
851 volatile uint32_t *cp_table_ptr;
852 u32 cp_table_size;
79e5412c
AD		 853
854 /* safe mode for updating CG/PG state */
855 bool in_safe_mode;
856 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 857
858 /* for firmware data */
859 u32 save_and_restore_offset;
860 u32 clear_state_descriptor_offset;
861 u32 avail_scratch_ram_locations;
862 u32 reg_restore_list_size;
863 u32 reg_list_format_start;
864 u32 reg_list_format_separate_start;
865 u32 starting_offsets_start;
866 u32 reg_list_format_size_bytes;
867 u32 reg_list_size_bytes;
868
869 u32 *register_list_format;
870 u32 *register_restore;
97b2e202
AD		 871};
872
78c16834
AR		 873#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
874
97b2e202
AD		 875struct amdgpu_mec {
876 struct amdgpu_bo *hpd_eop_obj;
877 u64 hpd_eop_gpu_addr;
b1023571
KW		 878 struct amdgpu_bo *mec_fw_obj;
879 u64 mec_fw_gpu_addr;
97b2e202 880 u32 num_mec;
42794b27
AR		 881 u32 num_pipe_per_mec;
882 u32 num_queue_per_pipe;
59a82d7d 883 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 884
885 /* These are the resources for which amdgpu takes ownership */
886 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 887};
888
4e638ae9
XY		 889struct amdgpu_kiq {
890 u64 eop_gpu_addr;
891 struct amdgpu_bo *eop_obj;
43ca8efa 892 spinlock_t ring_lock;
4e638ae9
XY		 893 struct amdgpu_ring ring;
894 struct amdgpu_irq_src irq;
895};
896
97b2e202
AD		 897/*
898 * GPU scratch registers structures, functions & helpers
899 */
900struct amdgpu_scratch {
901 unsigned num_reg;
902 uint32_t reg_base;
50261151 903 uint32_t free_mask;
97b2e202
AD		 904};
905
906/*
907 * GFX configurations
908 */
e3fa7630
AD		 909#define AMDGPU_GFX_MAX_SE 4
910#define AMDGPU_GFX_MAX_SH_PER_SE 2
911
912struct amdgpu_rb_config {
913 uint32_t rb_backend_disable;
914 uint32_t user_rb_backend_disable;
915 uint32_t raster_config;
916 uint32_t raster_config_1;
917};
918
d0e95758
AG		 919struct gb_addr_config {
920 uint16_t pipe_interleave_size;
921 uint8_t num_pipes;
922 uint8_t max_compress_frags;
923 uint8_t num_banks;
924 uint8_t num_se;
925 uint8_t num_rb_per_se;
926};
927
ea323f88 928struct amdgpu_gfx_config {
97b2e202
AD		 929 unsigned max_shader_engines;
930 unsigned max_tile_pipes;
931 unsigned max_cu_per_sh;
932 unsigned max_sh_per_se;
933 unsigned max_backends_per_se;
934 unsigned max_texture_channel_caches;
935 unsigned max_gprs;
936 unsigned max_gs_threads;
937 unsigned max_hw_contexts;
938 unsigned sc_prim_fifo_size_frontend;
939 unsigned sc_prim_fifo_size_backend;
940 unsigned sc_hiz_tile_fifo_size;
941 unsigned sc_earlyz_tile_fifo_size;
942
943 unsigned num_tile_pipes;
944 unsigned backend_enable_mask;
945 unsigned mem_max_burst_length_bytes;
946 unsigned mem_row_size_in_kb;
947 unsigned shader_engine_tile_size;
948 unsigned num_gpus;
949 unsigned multi_gpu_tile_size;
950 unsigned mc_arb_ramcfg;
951 unsigned gb_addr_config;
8f8e00c1 952 unsigned num_rbs;
408bfe7c
JZ		 953 unsigned gs_vgt_table_depth;
954 unsigned gs_prim_buffer_depth;
97b2e202
AD		 955
956 uint32_t tile_mode_array[32];
957 uint32_t macrotile_mode_array[16];
e3fa7630 958
d0e95758 959 struct gb_addr_config gb_addr_config_fields;
e3fa7630 960 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 961
962 /* gfx configure feature */
963 uint32_t double_offchip_lds_buf;
97b2e202
AD		 964};
965
7dae69a2 966struct amdgpu_cu_info {
51fd0370 967 uint32_t max_waves_per_simd;
408bfe7c 968 uint32_t wave_front_size;
51fd0370
HZ		 969 uint32_t max_scratch_slots_per_cu;
970 uint32_t lds_size;
dbfe85ea
FC		 971
972 /* total active CU number */
973 uint32_t number;
974 uint32_t ao_cu_mask;
975 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 976 uint32_t bitmap[4][4];
977};
978
b95e31fd
AD		 979struct amdgpu_gfx_funcs {
980 /* get the gpu clock counter */
981 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 982 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 983 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 984 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
985 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 986};
987
bce23e00
AD		 988struct amdgpu_ngg_buf {
989 struct amdgpu_bo *bo;
990 uint64_t gpu_addr;
991 uint32_t size;
992 uint32_t bo_size;
993};
994
995enum {
af8baf15
GR		 996 NGG_PRIM = 0,
997 NGG_POS,
998 NGG_CNTL,
999 NGG_PARAM,
bce23e00
AD		 1000 NGG_BUF_MAX
1001};
1002
1003struct amdgpu_ngg {
1004 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1005 uint32_t gds_reserve_addr;
1006 uint32_t gds_reserve_size;
1007 bool init;
1008};
1009
97b2e202
AD		 1010struct amdgpu_gfx {
1011 struct mutex gpu_clock_mutex;
ea323f88 1012 struct amdgpu_gfx_config config;
97b2e202
AD		 1013 struct amdgpu_rlc rlc;
1014 struct amdgpu_mec mec;
4e638ae9 1015 struct amdgpu_kiq kiq;
97b2e202
AD		 1016 struct amdgpu_scratch scratch;
1017 const struct firmware *me_fw; /* ME firmware */
1018 uint32_t me_fw_version;
1019 const struct firmware *pfp_fw; /* PFP firmware */
1020 uint32_t pfp_fw_version;
1021 const struct firmware *ce_fw; /* CE firmware */
1022 uint32_t ce_fw_version;
1023 const struct firmware *rlc_fw; /* RLC firmware */
1024 uint32_t rlc_fw_version;
1025 const struct firmware *mec_fw; /* MEC firmware */
1026 uint32_t mec_fw_version;
1027 const struct firmware *mec2_fw; /* MEC2 firmware */
1028 uint32_t mec2_fw_version;
02558a00
KW		 1029 uint32_t me_feature_version;
1030 uint32_t ce_feature_version;
1031 uint32_t pfp_feature_version;
351643d7
JZ		 1032 uint32_t rlc_feature_version;
1033 uint32_t mec_feature_version;
1034 uint32_t mec2_feature_version;
97b2e202
AD		 1035 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1036 unsigned num_gfx_rings;
1037 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1038 unsigned num_compute_rings;
1039 struct amdgpu_irq_src eop_irq;
1040 struct amdgpu_irq_src priv_reg_irq;
1041 struct amdgpu_irq_src priv_inst_irq;
1042 /* gfx status */
7dae69a2 1043 uint32_t gfx_current_status;
a101a899 1044 /* ce ram size*/
7dae69a2
AD		 1045 unsigned ce_ram_size;
1046 struct amdgpu_cu_info cu_info;
b95e31fd 1047 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1048
1049 /* reset mask */
1050 uint32_t grbm_soft_reset;
1051 uint32_t srbm_soft_reset;
b4e40676
DP		 1052 /* s3/s4 mask */
1053 bool in_suspend;
bce23e00
AD		 1054 /* NGG */
1055 struct amdgpu_ngg ngg;
b8866c26
AR		 1056
1057 /* pipe reservation */
1058 struct mutex pipe_reserve_mutex;
1059 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 1060};
1061
b07c60c0 1062int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1063 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1064void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1065 struct dma_fence *f);
b07c60c0 1066int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1067 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1068 struct dma_fence **f);
97b2e202
AD		 1069int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1070void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1071int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1072
1073/*
1074 * CS.
1075 */
1076struct amdgpu_cs_chunk {
1077 uint32_t chunk_id;
1078 uint32_t length_dw;
758ac17f 1079 void *kdata;
97b2e202
AD		 1080};
1081
1082struct amdgpu_cs_parser {
1083 struct amdgpu_device *adev;
1084 struct drm_file *filp;
3cb485f3 1085 struct amdgpu_ctx *ctx;
c3cca41e 1086
97b2e202
AD		 1087 /* chunks */
1088 unsigned nchunks;
1089 struct amdgpu_cs_chunk *chunks;
97b2e202 1090
50838c8c
CK		 1091 /* scheduler job object */
1092 struct amdgpu_job *job;
97b2e202 1093
c3cca41e
CK		 1094 /* buffer objects */
1095 struct ww_acquire_ctx ticket;
1096 struct amdgpu_bo_list *bo_list;
3fe89771 1097 struct amdgpu_mn *mn;
c3cca41e
CK		 1098 struct amdgpu_bo_list_entry vm_pd;
1099 struct list_head validated;
f54d1867 1100 struct dma_fence *fence;
c3cca41e 1101 uint64_t bytes_moved_threshold;
00f06b24 1102 uint64_t bytes_moved_vis_threshold;
c3cca41e 1103 uint64_t bytes_moved;
00f06b24 1104 uint64_t bytes_moved_vis;
662bfa61 1105 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1106
1107 /* user fence */
91acbeb6 1108 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1109
1110 unsigned num_post_dep_syncobjs;
1111 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1112};
1113
753ad49c
ML		 1114#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1115#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1116#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1117
bb977d37
CZ		 1118struct amdgpu_job {
1119 struct amd_sched_job base;
1120 struct amdgpu_device *adev;
edf600da 1121 struct amdgpu_vm *vm;
b07c60c0 1122 struct amdgpu_ring *ring;
e86f9cee 1123 struct amdgpu_sync sync;
a340c7bc 1124 struct amdgpu_sync dep_sync;
df83d1eb 1125 struct amdgpu_sync sched_sync;
bb977d37 1126 struct amdgpu_ib *ibs;
f54d1867 1127 struct dma_fence *fence; /* the hw fence */
753ad49c 1128 uint32_t preamble_status;
bb977d37 1129 uint32_t num_ibs;
e2840221 1130 void *owner;
3aecd24c 1131 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1132 bool vm_needs_flush;
d88bf583
CK		 1133 unsigned vm_id;
1134 uint64_t vm_pd_addr;
1135 uint32_t gds_base, gds_size;
1136 uint32_t gws_base, gws_size;
1137 uint32_t oa_base, oa_size;
14e47f93 1138 uint32_t vram_lost_counter;
758ac17f
CK		 1139
1140 /* user fence handling */
b5f5acbc 1141 uint64_t uf_addr;
758ac17f
CK		 1142 uint64_t uf_sequence;
1143
bb977d37 1144};
a6db8a33
JZ		 1145#define to_amdgpu_job(sched_job) \
1146 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1147
7270f839
CK		 1148static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1149 uint32_t ib_idx, int idx)
97b2e202 1150{
50838c8c 1151 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1152}
1153
7270f839
CK		 1154static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1155 uint32_t ib_idx, int idx,
1156 uint32_t value)
1157{
50838c8c 1158 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1159}
1160
97b2e202
AD		 1161/*
1162 * Writeback
1163 */
896a664c 1164#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
97b2e202
AD		 1165
1166struct amdgpu_wb {
1167 struct amdgpu_bo *wb_obj;
1168 volatile uint32_t *wb;
1169 uint64_t gpu_addr;
1170 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1171 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1172};
1173
1174int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1175void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1176
d0dd7f0c
AD		 1177void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1178
97b2e202
AD		 1179/*
1180 * SDMA
1181 */
c113ea1c 1182struct amdgpu_sdma_instance {
97b2e202
AD		 1183 /* SDMA firmware */
1184 const struct firmware *fw;
1185 uint32_t fw_version;
cfa2104f 1186 uint32_t feature_version;
97b2e202
AD		 1187
1188 struct amdgpu_ring ring;
18111de0 1189 bool burst_nop;
97b2e202
AD		 1190};
1191
c113ea1c
AD		 1192struct amdgpu_sdma {
1193 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1194#ifdef CONFIG_DRM_AMDGPU_SI
1195 //SI DMA has a difference trap irq number for the second engine
1196 struct amdgpu_irq_src trap_irq_1;
1197#endif
c113ea1c
AD		 1198 struct amdgpu_irq_src trap_irq;
1199 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1200 int num_instances;
e702a680 1201 uint32_t srbm_soft_reset;
c113ea1c
AD		 1202};
1203
97b2e202
AD		 1204/*
1205 * Firmware
1206 */
e635ee07
HR		 1207enum amdgpu_firmware_load_type {
1208 AMDGPU_FW_LOAD_DIRECT = 0,
1209 AMDGPU_FW_LOAD_SMU,
1210 AMDGPU_FW_LOAD_PSP,
1211};
1212
97b2e202
AD		 1213struct amdgpu_firmware {
1214 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1215 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1216 struct amdgpu_bo *fw_buf;
1217 unsigned int fw_size;
2445b227 1218 unsigned int max_ucodes;
0e5ca0d1
HR		 1219 /* firmwares are loaded by psp instead of smu from vega10 */
1220 const struct amdgpu_psp_funcs *funcs;
1221 struct amdgpu_bo *rbuf;
1222 struct mutex mutex;
ab4fe3e1
HR		 1223
1224 /* gpu info firmware data pointer */
1225 const struct firmware *gpu_info_fw;
d59c026b
ML		 1226
1227 void *fw_buf_ptr;
1228 uint64_t fw_buf_mc;
97b2e202
AD		 1229};
1230
1231/*
1232 * Benchmarking
1233 */
1234void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1235
1236
1237/*
1238 * Testing
1239 */
1240void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1241
97b2e202
AD		 1242/*
1243 * Debugfs
1244 */
1245struct amdgpu_debugfs {
06ab6832 1246 const struct drm_info_list *files;
97b2e202
AD		 1247 unsigned num_files;
1248};
1249
1250int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1251 const struct drm_info_list *files,
97b2e202
AD		 1252 unsigned nfiles);
1253int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1254
1255#if defined(CONFIG_DEBUG_FS)
1256int amdgpu_debugfs_init(struct drm_minor *minor);
97b2e202
AD		 1257#endif
1258
50ab2533
HR		 1259int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1260
97b2e202
AD		 1261/*
1262 * amdgpu smumgr functions
1263 */
1264struct amdgpu_smumgr_funcs {
1265 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1266 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1267 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1268};
1269
1270/*
1271 * amdgpu smumgr
1272 */
1273struct amdgpu_smumgr {
1274 struct amdgpu_bo *toc_buf;
1275 struct amdgpu_bo *smu_buf;
1276 /* asic priv smu data */
1277 void *priv;
1278 spinlock_t smu_lock;
1279 /* smumgr functions */
1280 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1281 /* ucode loading complete flag */
1282 uint32_t fw_flags;
1283};
1284
1285/*
1286 * ASIC specific register table accessible by UMD
1287 */
1288struct amdgpu_allowed_register_entry {
1289 uint32_t reg_offset;
97b2e202
AD		 1290 bool grbm_indexed;
1291};
1292
97b2e202
AD		 1293/*
1294 * ASIC specific functions.
1295 */
1296struct amdgpu_asic_funcs {
1297 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1298 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1299 u8 *bios, u32 length_bytes);
97b2e202
AD		 1300 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1301 u32 sh_num, u32 reg_offset, u32 *value);
1302 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1303 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1304 /* get the reference clock */
1305 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1306 /* MM block clocks */
1307 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1308 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1309 /* static power management */
1310 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1311 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1312 /* get config memsize register */
1313 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1314};
1315
1316/*
1317 * IOCTL.
1318 */
1319int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *filp);
1321int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *filp);
1323
1324int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1325 struct drm_file *filp);
1326int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *filp);
1328int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1329 struct drm_file *filp);
1330int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1331 struct drm_file *filp);
1332int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1333 struct drm_file *filp);
1334int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1335 struct drm_file *filp);
1336int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1337int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1338 struct drm_file *filp);
97b2e202 1339int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1340int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1341 struct drm_file *filp);
97b2e202
AD		 1342
1343int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1344 struct drm_file *filp);
1345
1346/* VRAM scratch page for HDP bug, default vram page */
1347struct amdgpu_vram_scratch {
1348 struct amdgpu_bo *robj;
1349 volatile uint32_t *ptr;
1350 u64 gpu_addr;
1351};
1352
1353/*
1354 * ACPI
1355 */
1356struct amdgpu_atif_notification_cfg {
1357 bool enabled;
1358 int command_code;
1359};
1360
1361struct amdgpu_atif_notifications {
1362 bool display_switch;
1363 bool expansion_mode_change;
1364 bool thermal_state;
1365 bool forced_power_state;
1366 bool system_power_state;
1367 bool display_conf_change;
1368 bool px_gfx_switch;
1369 bool brightness_change;
1370 bool dgpu_display_event;
1371};
1372
1373struct amdgpu_atif_functions {
1374 bool system_params;
1375 bool sbios_requests;
1376 bool select_active_disp;
1377 bool lid_state;
1378 bool get_tv_standard;
1379 bool set_tv_standard;
1380 bool get_panel_expansion_mode;
1381 bool set_panel_expansion_mode;
1382 bool temperature_change;
1383 bool graphics_device_types;
1384};
1385
1386struct amdgpu_atif {
1387 struct amdgpu_atif_notifications notifications;
1388 struct amdgpu_atif_functions functions;
1389 struct amdgpu_atif_notification_cfg notification_cfg;
1390 struct amdgpu_encoder *encoder_for_bl;
1391};
1392
1393struct amdgpu_atcs_functions {
1394 bool get_ext_state;
1395 bool pcie_perf_req;
1396 bool pcie_dev_rdy;
1397 bool pcie_bus_width;
1398};
1399
1400struct amdgpu_atcs {
1401 struct amdgpu_atcs_functions functions;
1402};
1403
a05502e5
HC		 1404/*
1405 * Firmware VRAM reservation
1406 */
1407struct amdgpu_fw_vram_usage {
1408 u64 start_offset;
1409 u64 size;
1410 struct amdgpu_bo *reserved_bo;
1411 void *va;
1412};
1413
1414int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
1415
d03846af
CZ		 1416/*
1417 * CGS
1418 */
110e6f26
DA		 1419struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1420void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1421
97b2e202
AD		 1422/*
1423 * Core structure, functions and helpers.
1424 */
1425typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1426typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1427
1428typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1429typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1430
11dc9364
RZ		 1431struct amd_powerplay {
1432 struct cgs_device *cgs_device;
1433 void *pp_handle;
1434 const struct amd_ip_funcs *ip_funcs;
1435 const struct amd_pm_funcs *pp_funcs;
1436};
1437
0c49e0b8 1438#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1439struct amdgpu_device {
1440 struct device *dev;
1441 struct drm_device *ddev;
1442 struct pci_dev *pdev;
97b2e202 1443
a8fe58ce
MB		 1444#ifdef CONFIG_DRM_AMD_ACP
1445 struct amdgpu_acp acp;
1446#endif
1447
97b2e202 1448 /* ASIC */
2f7d10b3 1449 enum amd_asic_type asic_type;
97b2e202
AD		 1450 uint32_t family;
1451 uint32_t rev_id;
1452 uint32_t external_rev_id;
1453 unsigned long flags;
1454 int usec_timeout;
1455 const struct amdgpu_asic_funcs *asic_funcs;
1456 bool shutdown;
97b2e202
AD		 1457 bool need_dma32;
1458 bool accel_working;
edf600da 1459 struct work_struct reset_work;
97b2e202
AD		 1460 struct notifier_block acpi_nb;
1461 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1462 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1463 unsigned debugfs_count;
97b2e202 1464#if defined(CONFIG_DEBUG_FS)
adcec288 1465 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1466#endif
1467 struct amdgpu_atif atif;
1468 struct amdgpu_atcs atcs;
1469 struct mutex srbm_mutex;
1470 /* GRBM index mutex. Protects concurrent access to GRBM index */
1471 struct mutex grbm_idx_mutex;
1472 struct dev_pm_domain vga_pm_domain;
1473 bool have_disp_power_ref;
1474
1475 /* BIOS */
0cdd5005 1476 bool is_atom_fw;
97b2e202 1477 uint8_t *bios;
a9f5db9c 1478 uint32_t bios_size;
5af2c10d 1479 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1480 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1481 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1482
1483 /* Register/doorbell mmio */
1484 resource_size_t rmmio_base;
1485 resource_size_t rmmio_size;
1486 void __iomem *rmmio;
1487 /* protects concurrent MM_INDEX/DATA based register access */
1488 spinlock_t mmio_idx_lock;
1489 /* protects concurrent SMC based register access */
1490 spinlock_t smc_idx_lock;
1491 amdgpu_rreg_t smc_rreg;
1492 amdgpu_wreg_t smc_wreg;
1493 /* protects concurrent PCIE register access */
1494 spinlock_t pcie_idx_lock;
1495 amdgpu_rreg_t pcie_rreg;
1496 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1497 amdgpu_rreg_t pciep_rreg;
1498 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1499 /* protects concurrent UVD register access */
1500 spinlock_t uvd_ctx_idx_lock;
1501 amdgpu_rreg_t uvd_ctx_rreg;
1502 amdgpu_wreg_t uvd_ctx_wreg;
1503 /* protects concurrent DIDT register access */
1504 spinlock_t didt_idx_lock;
1505 amdgpu_rreg_t didt_rreg;
1506 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1507 /* protects concurrent gc_cac register access */
1508 spinlock_t gc_cac_idx_lock;
1509 amdgpu_rreg_t gc_cac_rreg;
1510 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1511 /* protects concurrent se_cac register access */
1512 spinlock_t se_cac_idx_lock;
1513 amdgpu_rreg_t se_cac_rreg;
1514 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1515 /* protects concurrent ENDPOINT (audio) register access */
1516 spinlock_t audio_endpt_idx_lock;
1517 amdgpu_block_rreg_t audio_endpt_rreg;
1518 amdgpu_block_wreg_t audio_endpt_wreg;
1519 void __iomem *rio_mem;
1520 resource_size_t rio_mem_size;
1521 struct amdgpu_doorbell doorbell;
1522
1523 /* clock/pll info */
1524 struct amdgpu_clock clock;
1525
1526 /* MC */
1527 struct amdgpu_mc mc;
1528 struct amdgpu_gart gart;
1529 struct amdgpu_dummy_page dummy_page;
1530 struct amdgpu_vm_manager vm_manager;
e60f8db5 1531 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1532
1533 /* memory management */
1534 struct amdgpu_mman mman;
97b2e202
AD		 1535 struct amdgpu_vram_scratch vram_scratch;
1536 struct amdgpu_wb wb;
97b2e202 1537 atomic64_t num_bytes_moved;
dbd5ed60 1538 atomic64_t num_evictions;
68e2c5ff 1539 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1540 atomic_t gpu_reset_counter;
f1892138 1541 atomic_t vram_lost_counter;
97b2e202 1542
95844d20
MO		 1543 /* data for buffer migration throttling */
1544 struct {
1545 spinlock_t lock;
1546 s64 last_update_us;
1547 s64 accum_us; /* accumulated microseconds */
00f06b24 1548 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1549 u32 log2_max_MBps;
1550 } mm_stats;
1551
97b2e202 1552 /* display */
9accf2fd 1553 bool enable_virtual_display;
97b2e202 1554 struct amdgpu_mode_info mode_info;
4562236b 1555 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 1556 struct work_struct hotplug_work;
1557 struct amdgpu_irq_src crtc_irq;
1558 struct amdgpu_irq_src pageflip_irq;
1559 struct amdgpu_irq_src hpd_irq;
1560
1561 /* rings */
76bf0db5 1562 u64 fence_context;
97b2e202
AD		 1563 unsigned num_rings;
1564 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1565 bool ib_pool_ready;
1566 struct amdgpu_sa_manager ring_tmp_bo;
1567
1568 /* interrupts */
1569 struct amdgpu_irq irq;
1570
1f7371b2
AD		 1571 /* powerplay */
1572 struct amd_powerplay powerplay;
f3898ea1 1573 bool pp_force_state_enabled;
1f7371b2 1574
97b2e202
AD		 1575 /* dpm */
1576 struct amdgpu_pm pm;
1577 u32 cg_flags;
1578 u32 pg_flags;
1579
1580 /* amdgpu smumgr */
1581 struct amdgpu_smumgr smu;
1582
1583 /* gfx */
1584 struct amdgpu_gfx gfx;
1585
1586 /* sdma */
c113ea1c 1587 struct amdgpu_sdma sdma;
97b2e202 1588
b43aaee6
LL		 1589 /* uvd */
1590 struct amdgpu_uvd uvd;
1591
1592 /* vce */
1593 struct amdgpu_vce vce;
1594
1595 /* vcn */
1596 struct amdgpu_vcn vcn;
97b2e202
AD		 1597
1598 /* firmwares */
1599 struct amdgpu_firmware firmware;
1600
0e5ca0d1
HR		 1601 /* PSP */
1602 struct psp_context psp;
1603
97b2e202
AD		 1604 /* GDS */
1605 struct amdgpu_gds gds;
1606
4562236b
HW		 1607 /* display related functionality */
1608 struct amdgpu_display_manager dm;
1609
a1255107 1610 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1611 int num_ip_blocks;
97b2e202
AD		 1612 struct mutex mn_lock;
1613 DECLARE_HASHTABLE(mn_hash, 7);
1614
1615 /* tracking pinned memory */
1616 u64 vram_pin_size;
e131b914 1617 u64 invisible_pin_size;
97b2e202 1618 u64 gart_pin_size;
130e0371
OG		 1619
1620 /* amdkfd interface */
1621 struct kfd_dev *kfd;
23ca0e4e 1622
2dc80b00
S		 1623 /* delayed work_func for deferring clockgating during resume */
1624 struct delayed_work late_init_work;
1625
5a5099cb 1626 struct amdgpu_virt virt;
a05502e5
HC		 1627 /* firmware VRAM reservation */
1628 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1629
1630 /* link all shadow bo */
1631 struct list_head shadow_list;
1632 struct mutex shadow_list_lock;
5c1354bd
CZ		 1633 /* link all gtt */
1634 spinlock_t gtt_list_lock;
1635 struct list_head gtt_list;
795f2813
AR		 1636 /* keep an lru list of rings by HW IP */
1637 struct list_head ring_lru_list;
1638 spinlock_t ring_lru_list_lock;
5c1354bd 1639
c836fec5
JQ		 1640 /* record hw reset is performed */
1641 bool has_hw_reset;
0c49e0b8 1642 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1643
47ed4e1c
KW		 1644 /* record last mm index being written through WREG32*/
1645 unsigned long last_mm_index;
13a752e3
ML		 1646 bool in_gpu_reset;
1647 struct mutex lock_reset;
97b2e202
AD		 1648};
1649
a7d64de6
CK		 1650static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1651{
1652 return container_of(bdev, struct amdgpu_device, mman.bdev);
1653}
1654
97b2e202
AD		 1655int amdgpu_device_init(struct amdgpu_device *adev,
1656 struct drm_device *ddev,
1657 struct pci_dev *pdev,
1658 uint32_t flags);
1659void amdgpu_device_fini(struct amdgpu_device *adev);
1660int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1661
1662uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1663 uint32_t acc_flags);
97b2e202 1664void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1665 uint32_t acc_flags);
97b2e202
AD		 1666u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1667void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1668
1669u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1670void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1671u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1672void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1673
4562236b
HW		 1674bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1675bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1676
97b2e202
AD		 1677/*
1678 * Registers read & write functions.
1679 */
15d72fd7
ML		 1680
1681#define AMDGPU_REGS_IDX (1<<0)
1682#define AMDGPU_REGS_NO_KIQ (1<<1)
1683
1684#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1685#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1686
1687#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1688#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1689#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1690#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1691#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1692#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1693#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1694#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1695#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1696#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1697#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1698#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1699#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1700#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1701#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1702#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1703#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1704#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1705#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1706#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1707#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1708#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1709#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1710#define WREG32_P(reg, val, mask) \
1711 do { \
1712 uint32_t tmp_ = RREG32(reg); \
1713 tmp_ &= (mask); \
1714 tmp_ |= ((val) & ~(mask)); \
1715 WREG32(reg, tmp_); \
1716 } while (0)
1717#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1718#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1719#define WREG32_PLL_P(reg, val, mask) \
1720 do { \
1721 uint32_t tmp_ = RREG32_PLL(reg); \
1722 tmp_ &= (mask); \
1723 tmp_ |= ((val) & ~(mask)); \
1724 WREG32_PLL(reg, tmp_); \
1725 } while (0)
1726#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1727#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1728#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1729
1730#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1731#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1732#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1733#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1734
1735#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1736#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1737
1738#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1739 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1740 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1741
1742#define REG_GET_FIELD(value, reg, field) \
1743 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1744
1745#define WREG32_FIELD(reg, field, val) \
1746 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1747
ccaf3574
TSD		 1748#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1749 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1750
97b2e202
AD		 1751/*
1752 * BIOS helpers.
1753 */
1754#define RBIOS8(i) (adev->bios[i])
1755#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1756#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1757
c113ea1c
AD		 1758static inline struct amdgpu_sdma_instance *
1759amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1760{
1761 struct amdgpu_device *adev = ring->adev;
1762 int i;
1763
c113ea1c
AD		 1764 for (i = 0; i < adev->sdma.num_instances; i++)
1765 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1766 break;
1767
1768 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1769 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1770 else
1771 return NULL;
1772}
1773
97b2e202
AD		 1774/*
1775 * ASICs macro.
1776 */
1777#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1778#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1779#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1780#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1781#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1782#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1783#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1784#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1785#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1786#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1787#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1788#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1789#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1790#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
b1166325 1791#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
97b2e202 1792#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1793#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1794#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1795#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1796#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1797#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1798#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1799#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1800#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1801#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1802#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1803#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1804#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1805#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1806#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1807#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1808#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1809#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1810#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1811#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1812#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1813#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1814#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1815#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1816#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1817#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1818#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1819#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1820#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1821#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1822#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1823#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1824#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1825#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1826#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1827#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1828#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1829#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1830#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1831#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1832#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1833#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1834#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1835#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1836#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1837#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1838#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1839
1840/* Common functions */
5740682e 1841int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);
3ad81f16 1842bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1843void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1844bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1845void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1846
00f06b24
JB		 1847void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1848 u64 num_vis_bytes);
765e7fbf 1849void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1850bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1851void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1852void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
97b2e202 1853void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1854int amdgpu_ttm_init(struct amdgpu_device *adev);
1855void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1856void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1857 const u32 *registers,
1858 const u32 array_size);
1859
1860bool amdgpu_device_is_px(struct drm_device *dev);
1861/* atpx handler */
1862#if defined(CONFIG_VGA_SWITCHEROO)
1863void amdgpu_register_atpx_handler(void);
1864void amdgpu_unregister_atpx_handler(void);
a78fe133 1865bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1866bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1867bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1868bool amdgpu_has_atpx(void);
97b2e202
AD		 1869#else
1870static inline void amdgpu_register_atpx_handler(void) {}
1871static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1872static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1873static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1874static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1875static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1876#endif
1877
1878/*
1879 * KMS
1880 */
1881extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1882extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1883
1884int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1885void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1886void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1887int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1888void amdgpu_driver_postclose_kms(struct drm_device *dev,
1889 struct drm_file *file_priv);
faefba95 1890int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1891int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1892int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1893u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1894int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1895void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1896long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1897 unsigned long arg);
1898
97b2e202
AD		 1899/*
1900 * functions used by amdgpu_encoder.c
1901 */
1902struct amdgpu_afmt_acr {
1903 u32 clock;
1904
1905 int n_32khz;
1906 int cts_32khz;
1907
1908 int n_44_1khz;
1909 int cts_44_1khz;
1910
1911 int n_48khz;
1912 int cts_48khz;
1913
1914};
1915
1916struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1917
1918/* amdgpu_acpi.c */
1919#if defined(CONFIG_ACPI)
1920int amdgpu_acpi_init(struct amdgpu_device *adev);
1921void amdgpu_acpi_fini(struct amdgpu_device *adev);
1922bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1923int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1924 u8 perf_req, bool advertise);
1925int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1926#else
1927static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1928static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1929#endif
1930
9cca0b8e
CK		 1931int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1932 uint64_t addr, struct amdgpu_bo **bo,
1933 struct amdgpu_bo_va_mapping **mapping);
97b2e202 1934
4562236b
HW		 1935#if defined(CONFIG_DRM_AMD_DC)
1936int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1937#else
1938static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1939#endif
1940
97b2e202 1941#include "amdgpu_object.h"
97b2e202 1942#endif
Linux 6.x block layer and io_uring tree(s)