projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: use consistent naming for static funcs in amdgpu_device.c
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
a9f87f64 35#include <linux/rbtree.h>
97b2e202 36#include <linux/hashtable.h>
f54d1867 37#include <linux/dma-fence.h>
97b2e202 38
248a1d6f
MY		 39#include <drm/ttm/ttm_bo_api.h>
40#include <drm/ttm/ttm_bo_driver.h>
41#include <drm/ttm/ttm_placement.h>
42#include <drm/ttm/ttm_module.h>
43#include <drm/ttm/ttm_execbuf_util.h>
97b2e202 44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
1b1f42d8 48#include <drm/gpu_scheduler.h>
97b2e202 49
78c16834 50#include <kgd_kfd_interface.h>
c79563a3
RZ		 51#include "dm_pp_interface.h"
52#include "kgd_pp_interface.h"
78c16834 53
5fc3aeeb 54#include "amd_shared.h"
97b2e202
AD		 55#include "amdgpu_mode.h"
56#include "amdgpu_ih.h"
57#include "amdgpu_irq.h"
58#include "amdgpu_ucode.h"
c632d799 59#include "amdgpu_ttm.h"
0e5ca0d1 60#include "amdgpu_psp.h"
97b2e202 61#include "amdgpu_gds.h"
56113504 62#include "amdgpu_sync.h"
78023016 63#include "amdgpu_ring.h"
073440d2 64#include "amdgpu_vm.h"
cf097881 65#include "amdgpu_dpm.h"
a8fe58ce 66#include "amdgpu_acp.h"
4df654d2 67#include "amdgpu_uvd.h"
5e568178 68#include "amdgpu_vce.h"
95aa13f6 69#include "amdgpu_vcn.h"
9a189996 70#include "amdgpu_mn.h"
4562236b 71#include "amdgpu_dm.h"
ceeb50ed 72#include "amdgpu_virt.h"
3490bdb5 73#include "amdgpu_gart.h"
b80d8475 74
c79563a3 75
97b2e202
AD		 76/*
77 * Modules parameters.
78 */
79extern int amdgpu_modeset;
80extern int amdgpu_vram_limit;
218b5dcd 81extern int amdgpu_vis_vram_limit;
83e74db6 82extern int amdgpu_gart_size;
36d38372 83extern int amdgpu_gtt_size;
95844d20 84extern int amdgpu_moverate;
97b2e202
AD		 85extern int amdgpu_benchmarking;
86extern int amdgpu_testing;
87extern int amdgpu_audio;
88extern int amdgpu_disp_priority;
89extern int amdgpu_hw_i2c;
90extern int amdgpu_pcie_gen2;
91extern int amdgpu_msi;
92extern int amdgpu_lockup_timeout;
93extern int amdgpu_dpm;
e635ee07 94extern int amdgpu_fw_load_type;
97b2e202
AD		 95extern int amdgpu_aspm;
96extern int amdgpu_runtime_pm;
0b693f0b 97extern uint amdgpu_ip_block_mask;
97b2e202
AD		 98extern int amdgpu_bapm;
99extern int amdgpu_deep_color;
100extern int amdgpu_vm_size;
101extern int amdgpu_vm_block_size;
d07f14be 102extern int amdgpu_vm_fragment_size;
d9c13156 103extern int amdgpu_vm_fault_stop;
b495bd3a 104extern int amdgpu_vm_debug;
9a4b7d4c 105extern int amdgpu_vm_update_mode;
4562236b 106extern int amdgpu_dc;
02e749dc 107extern int amdgpu_dc_log;
1333f723 108extern int amdgpu_sched_jobs;
4afcb303 109extern int amdgpu_sched_hw_submission;
3ca67300
RZ		 110extern int amdgpu_no_evict;
111extern int amdgpu_direct_gma_size;
0b693f0b
RZ		 112extern uint amdgpu_pcie_gen_cap;
113extern uint amdgpu_pcie_lane_cap;
114extern uint amdgpu_cg_mask;
115extern uint amdgpu_pg_mask;
116extern uint amdgpu_sdma_phase_quantum;
6f8941a2 117extern char *amdgpu_disable_cu;
9accf2fd 118extern char *amdgpu_virtual_display;
0b693f0b 119extern uint amdgpu_pp_feature_mask;
6a7f76e7 120extern int amdgpu_vram_page_split;
bce23e00
AD		 121extern int amdgpu_ngg;
122extern int amdgpu_prim_buf_per_se;
123extern int amdgpu_pos_buf_per_se;
124extern int amdgpu_cntl_sb_buf_per_se;
125extern int amdgpu_param_buf_per_se;
65781c78 126extern int amdgpu_job_hang_limit;
e8835e0e 127extern int amdgpu_lbpw;
4a75aefe 128extern int amdgpu_compute_multipipe;
dcebf026 129extern int amdgpu_gpu_recovery;
97b2e202 130
6dd13096
FK		 131#ifdef CONFIG_DRM_AMDGPU_SI
132extern int amdgpu_si_support;
133#endif
7df28986
FK		 134#ifdef CONFIG_DRM_AMDGPU_CIK
135extern int amdgpu_cik_support;
136#endif
97b2e202 137
55ed8caf 138#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
4b559c90 139#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 140#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
141#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
142/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
143#define AMDGPU_IB_POOL_SIZE 16
144#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
145#define AMDGPUFB_CONN_LIMIT 4
a5bde2f9 146#define AMDGPU_BIOS_NUM_SCRATCH 16
97b2e202 147
36f523a7
JZ		 148/* max number of IP instances */
149#define AMDGPU_MAX_SDMA_INSTANCES 2
150
97b2e202
AD		 151/* hard reset data */
152#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
153
154/* reset flags */
155#define AMDGPU_RESET_GFX (1 << 0)
156#define AMDGPU_RESET_COMPUTE (1 << 1)
157#define AMDGPU_RESET_DMA (1 << 2)
158#define AMDGPU_RESET_CP (1 << 3)
159#define AMDGPU_RESET_GRBM (1 << 4)
160#define AMDGPU_RESET_DMA1 (1 << 5)
161#define AMDGPU_RESET_RLC (1 << 6)
162#define AMDGPU_RESET_SEM (1 << 7)
163#define AMDGPU_RESET_IH (1 << 8)
164#define AMDGPU_RESET_VMC (1 << 9)
165#define AMDGPU_RESET_MC (1 << 10)
166#define AMDGPU_RESET_DISPLAY (1 << 11)
167#define AMDGPU_RESET_UVD (1 << 12)
168#define AMDGPU_RESET_VCE (1 << 13)
169#define AMDGPU_RESET_VCE1 (1 << 14)
170
97b2e202
AD		 171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
5740682e
ML		 182/* GPU RESET flags */
183#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0)
184#define AMDGPU_RESET_INFO_FULLRESET (1 << 1)
185
97b2e202 186struct amdgpu_device;
97b2e202 187struct amdgpu_ib;
97b2e202 188struct amdgpu_cs_parser;
bb977d37 189struct amdgpu_job;
97b2e202 190struct amdgpu_irq_src;
0b492a4c 191struct amdgpu_fpriv;
9cca0b8e 192struct amdgpu_bo_va_mapping;
97b2e202
AD		 193
194enum amdgpu_cp_irq {
195 AMDGPU_CP_IRQ_GFX_EOP = 0,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
204
205 AMDGPU_CP_IRQ_LAST
206};
207
208enum amdgpu_sdma_irq {
209 AMDGPU_SDMA_IRQ_TRAP0 = 0,
210 AMDGPU_SDMA_IRQ_TRAP1,
211
212 AMDGPU_SDMA_IRQ_LAST
213};
214
215enum amdgpu_thermal_irq {
216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
218
219 AMDGPU_THERMAL_IRQ_LAST
220};
221
4e638ae9
XY		 222enum amdgpu_kiq_irq {
223 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
224 AMDGPU_CP_KIQ_IRQ_LAST
225};
226
97b2e202 227int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 228 enum amd_ip_block_type block_type,
229 enum amd_clockgating_state state);
97b2e202 230int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 231 enum amd_ip_block_type block_type,
232 enum amd_powergating_state state);
6cb2d4e4 233void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
5dbbb60b
AD		 234int amdgpu_wait_for_idle(struct amdgpu_device *adev,
235 enum amd_ip_block_type block_type);
236bool amdgpu_is_idle(struct amdgpu_device *adev,
237 enum amd_ip_block_type block_type);
97b2e202 238
a1255107
AD		 239#define AMDGPU_MAX_IP_NUM 16
240
241struct amdgpu_ip_block_status {
242 bool valid;
243 bool sw;
244 bool hw;
245 bool late_initialized;
246 bool hang;
247};
248
97b2e202 249struct amdgpu_ip_block_version {
a1255107
AD		 250 const enum amd_ip_block_type type;
251 const u32 major;
252 const u32 minor;
253 const u32 rev;
5fc3aeeb 254 const struct amd_ip_funcs *funcs;
97b2e202
AD		 255};
256
a1255107
AD		 257struct amdgpu_ip_block {
258 struct amdgpu_ip_block_status status;
259 const struct amdgpu_ip_block_version *version;
260};
261
97b2e202 262int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 263 enum amd_ip_block_type type,
97b2e202
AD		 264 u32 major, u32 minor);
265
a1255107
AD		 266struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
267 enum amd_ip_block_type type);
268
269int amdgpu_ip_block_add(struct amdgpu_device *adev,
270 const struct amdgpu_ip_block_version *ip_block_version);
97b2e202
AD		 271
272/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
273struct amdgpu_buffer_funcs {
274 /* maximum bytes in a single operation */
275 uint32_t copy_max_bytes;
276
277 /* number of dw to reserve per operation */
278 unsigned copy_num_dw;
279
280 /* used for buffer migration */
c7ae72c0 281 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 282 /* src addr in bytes */
283 uint64_t src_offset,
284 /* dst addr in bytes */
285 uint64_t dst_offset,
286 /* number of byte to transfer */
287 uint32_t byte_count);
288
289 /* maximum bytes in a single operation */
290 uint32_t fill_max_bytes;
291
292 /* number of dw to reserve per operation */
293 unsigned fill_num_dw;
294
295 /* used for buffer clearing */
6e7a3840 296 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 297 /* value to write to memory */
298 uint32_t src_data,
299 /* dst addr in bytes */
300 uint64_t dst_offset,
301 /* number of byte to fill */
302 uint32_t byte_count);
303};
304
305/* provided by hw blocks that can write ptes, e.g., sdma */
306struct amdgpu_vm_pte_funcs {
e6d92197
YZ		 307 /* number of dw to reserve per operation */
308 unsigned copy_pte_num_dw;
309
97b2e202
AD		 310 /* copy pte entries from GART */
311 void (*copy_pte)(struct amdgpu_ib *ib,
312 uint64_t pe, uint64_t src,
313 unsigned count);
e6d92197 314
97b2e202 315 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 316 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
317 uint64_t value, unsigned count,
318 uint32_t incr);
7bdc53f9
YZ		 319
320 /* maximum nums of PTEs/PDEs in a single operation */
321 uint32_t set_max_nums_pte_pde;
322
323 /* number of dw to reserve per operation */
324 unsigned set_pte_pde_num_dw;
325
97b2e202
AD		 326 /* for linear pte/pde updates without addr mapping */
327 void (*set_pte_pde)(struct amdgpu_ib *ib,
328 uint64_t pe,
329 uint64_t addr, unsigned count,
6b777607 330 uint32_t incr, uint64_t flags);
97b2e202
AD		 331};
332
333/* provided by the gmc block */
334struct amdgpu_gart_funcs {
335 /* flush the vm tlb via mmio */
336 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
337 uint32_t vmid);
338 /* write pte/pde updates using the cpu */
339 int (*set_pte_pde)(struct amdgpu_device *adev,
340 void *cpu_pt_addr, /* cpu addr of page table */
341 uint32_t gpu_page_idx, /* pte/pde to update */
342 uint64_t addr, /* addr to write into pte/pde */
6b777607 343 uint64_t flags); /* access flags */
284710fa
CK		 344 /* enable/disable PRT support */
345 void (*set_prt)(struct amdgpu_device *adev, bool enable);
5463545b
AX		 346 /* set pte flags based per asic */
347 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
348 uint32_t flags);
b1166325 349 /* get the pde for a given mc addr */
3de676d8
CK		 350 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
351 u64 *dst, u64 *flags);
03f89feb 352 uint32_t (*get_invalidate_req)(unsigned int vm_id);
e60f8db5
AX		 353};
354
97b2e202
AD		 355/* provided by the ih block */
356struct amdgpu_ih_funcs {
357 /* ring read/write ptr handling, called from interrupt context */
358 u32 (*get_wptr)(struct amdgpu_device *adev);
00ecd8a2 359 bool (*prescreen_iv)(struct amdgpu_device *adev);
97b2e202
AD		 360 void (*decode_iv)(struct amdgpu_device *adev,
361 struct amdgpu_iv_entry *entry);
362 void (*set_rptr)(struct amdgpu_device *adev);
363};
364
97b2e202
AD		 365/*
366 * BIOS.
367 */
368bool amdgpu_get_bios(struct amdgpu_device *adev);
369bool amdgpu_read_bios(struct amdgpu_device *adev);
370
371/*
372 * Dummy page
373 */
374struct amdgpu_dummy_page {
375 struct page *page;
376 dma_addr_t addr;
377};
378int amdgpu_dummy_page_init(struct amdgpu_device *adev);
379void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
380
381
382/*
383 * Clocks
384 */
385
386#define AMDGPU_MAX_PPLL 3
387
388struct amdgpu_clock {
389 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
390 struct amdgpu_pll spll;
391 struct amdgpu_pll mpll;
392 /* 10 Khz units */
393 uint32_t default_mclk;
394 uint32_t default_sclk;
395 uint32_t default_dispclk;
396 uint32_t current_dispclk;
397 uint32_t dp_extclk;
398 uint32_t max_pixel_clock;
399};
400
97b2e202 401/*
9124a398 402 * GEM.
97b2e202 403 */
97b2e202 404
7e5a547f 405#define AMDGPU_GEM_DOMAIN_MAX 0x3
97b2e202
AD		 406#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
407
408void amdgpu_gem_object_free(struct drm_gem_object *obj);
409int amdgpu_gem_object_open(struct drm_gem_object *obj,
410 struct drm_file *file_priv);
411void amdgpu_gem_object_close(struct drm_gem_object *obj,
412 struct drm_file *file_priv);
413unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
414struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 415struct drm_gem_object *
416amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
417 struct dma_buf_attachment *attach,
418 struct sg_table *sg);
97b2e202
AD		 419struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
420 struct drm_gem_object *gobj,
421 int flags);
422int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
423void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
424struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
425void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
426void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
dfced2e4 427int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
97b2e202
AD		 428int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
429
430/* sub-allocation manager, it has to be protected by another lock.
431 * By conception this is an helper for other part of the driver
432 * like the indirect buffer or semaphore, which both have their
433 * locking.
434 *
435 * Principe is simple, we keep a list of sub allocation in offset
436 * order (first entry has offset == 0, last entry has the highest
437 * offset).
438 *
439 * When allocating new object we first check if there is room at
440 * the end total_size - (last_object_offset + last_object_size) >=
441 * alloc_size. If so we allocate new object there.
442 *
443 * When there is not enough room at the end, we start waiting for
444 * each sub object until we reach object_offset+object_size >=
445 * alloc_size, this object then become the sub object we return.
446 *
447 * Alignment can't be bigger than page size.
448 *
449 * Hole are not considered for allocation to keep things simple.
450 * Assumption is that there won't be hole (all object on same
451 * alignment).
452 */
6ba60b89
CK		 453
454#define AMDGPU_SA_NUM_FENCE_LISTS 32
455
97b2e202
AD		 456struct amdgpu_sa_manager {
457 wait_queue_head_t wq;
458 struct amdgpu_bo *bo;
459 struct list_head *hole;
6ba60b89 460 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 461 struct list_head olist;
462 unsigned size;
463 uint64_t gpu_addr;
464 void *cpu_ptr;
465 uint32_t domain;
466 uint32_t align;
467};
468
97b2e202
AD		 469/* sub-allocation buffer */
470struct amdgpu_sa_bo {
471 struct list_head olist;
472 struct list_head flist;
473 struct amdgpu_sa_manager *manager;
474 unsigned soffset;
475 unsigned eoffset;
f54d1867 476 struct dma_fence *fence;
97b2e202
AD		 477};
478
479/*
480 * GEM objects.
481 */
418aa0c2 482void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202 483int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
e1eb899b
CK		 484 int alignment, u32 initial_domain,
485 u64 flags, bool kernel,
486 struct reservation_object *resv,
487 struct drm_gem_object **obj);
97b2e202
AD		 488
489int amdgpu_mode_dumb_create(struct drm_file *file_priv,
490 struct drm_device *dev,
491 struct drm_mode_create_dumb *args);
492int amdgpu_mode_dumb_mmap(struct drm_file *filp,
493 struct drm_device *dev,
494 uint32_t handle, uint64_t *offset_p);
d573de2d
RZ		 495int amdgpu_fence_slab_init(void);
496void amdgpu_fence_slab_fini(void);
97b2e202 497
e60f8db5
AX		 498/*
499 * VMHUB structures, functions & helpers
500 */
501struct amdgpu_vmhub {
502 uint32_t ctx0_ptb_addr_lo32;
503 uint32_t ctx0_ptb_addr_hi32;
504 uint32_t vm_inv_eng0_req;
505 uint32_t vm_inv_eng0_ack;
506 uint32_t vm_context0_cntl;
507 uint32_t vm_l2_pro_fault_status;
508 uint32_t vm_l2_pro_fault_cntl;
e60f8db5
AX		 509};
510
97b2e202
AD		 511/*
512 * GPU MC structures, functions & helpers
513 */
514struct amdgpu_mc {
515 resource_size_t aper_size;
516 resource_size_t aper_base;
517 resource_size_t agp_base;
518 /* for some chips with <= 32MB we need to lie
519 * about vram size near mc fb location */
520 u64 mc_vram_size;
521 u64 visible_vram_size;
6f02a696
CK		 522 u64 gart_size;
523 u64 gart_start;
524 u64 gart_end;
97b2e202
AD		 525 u64 vram_start;
526 u64 vram_end;
527 unsigned vram_width;
528 u64 real_vram_size;
529 int vram_mtrr;
97b2e202
AD		 530 u64 mc_mask;
531 const struct firmware *fw; /* MC firmware */
532 uint32_t fw_version;
533 struct amdgpu_irq_src vm_fault;
81c59f54 534 uint32_t vram_type;
50b0197a 535 uint32_t srbm_soft_reset;
f7c35abe 536 bool prt_warning;
916910ad 537 uint64_t stolen_size;
8fe73328
JZ		 538 /* apertures */
539 u64 shared_aperture_start;
540 u64 shared_aperture_end;
541 u64 private_aperture_start;
542 u64 private_aperture_end;
e60f8db5
AX		 543 /* protects concurrent invalidation */
544 spinlock_t invalidate_lock;
97b2e202
AD		 545};
546
547/*
548 * GPU doorbell structures, functions & helpers
549 */
550typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
551{
552 AMDGPU_DOORBELL_KIQ = 0x000,
553 AMDGPU_DOORBELL_HIQ = 0x001,
554 AMDGPU_DOORBELL_DIQ = 0x002,
555 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
556 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
557 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
558 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
559 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
560 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
561 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
562 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
563 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
564 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
565 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
566 AMDGPU_DOORBELL_IH = 0x1E8,
567 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
568 AMDGPU_DOORBELL_INVALID = 0xFFFF
569} AMDGPU_DOORBELL_ASSIGNMENT;
570
571struct amdgpu_doorbell {
572 /* doorbell mmio */
573 resource_size_t base;
574 resource_size_t size;
575 u32 __iomem *ptr;
576 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
577};
578
39807b93
KW		 579/*
580 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
581 */
582typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
583{
584 /*
585 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
586 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
587 * Compute related doorbells are allocated from 0x00 to 0x8a
588 */
589
590
591 /* kernel scheduling */
592 AMDGPU_DOORBELL64_KIQ = 0x00,
593
594 /* HSA interface queue and debug queue */
595 AMDGPU_DOORBELL64_HIQ = 0x01,
596 AMDGPU_DOORBELL64_DIQ = 0x02,
597
598 /* Compute engines */
599 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
600 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
601 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
602 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
603 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
604 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
605 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
606 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
607
608 /* User queue doorbell range (128 doorbells) */
609 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
610 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
611
612 /* Graphics engine */
613 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
614
615 /*
616 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
617 * Graphics voltage island aperture 1
618 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
619 */
620
621 /* sDMA engines */
622 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
623 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
624 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
625 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
626
627 /* Interrupt handler */
628 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
629 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
630 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
631
e6b3ecb4
ML		 632 /* VCN engine use 32 bits doorbell */
633 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
634 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
635 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
636 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
637
638 /* overlap the doorbell assignment with VCN as they are mutually exclusive
639 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
640 */
4ed11d79
FM		 641 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
642 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
643 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
644 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
645
646 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
647 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
648 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
649 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
39807b93
KW		 650
651 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
652 AMDGPU_DOORBELL64_INVALID = 0xFFFF
653} AMDGPU_DOORBELL64_ASSIGNMENT;
654
655
97b2e202
AD		 656void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
657 phys_addr_t *aperture_base,
658 size_t *aperture_size,
659 size_t *start_offset);
660
661/*
662 * IRQS.
663 */
664
665struct amdgpu_flip_work {
325cbba1 666 struct delayed_work flip_work;
97b2e202
AD		 667 struct work_struct unpin_work;
668 struct amdgpu_device *adev;
669 int crtc_id;
325cbba1 670 u32 target_vblank;
97b2e202
AD		 671 uint64_t base;
672 struct drm_pending_vblank_event *event;
765e7fbf 673 struct amdgpu_bo *old_abo;
f54d1867 674 struct dma_fence *excl;
1ffd2652 675 unsigned shared_count;
f54d1867
CW		 676 struct dma_fence **shared;
677 struct dma_fence_cb cb;
cb9e59d7 678 bool async;
97b2e202
AD		 679};
680
681
682/*
683 * CP & rings.
684 */
685
686struct amdgpu_ib {
687 struct amdgpu_sa_bo *sa_bo;
688 uint32_t length_dw;
689 uint64_t gpu_addr;
690 uint32_t *ptr;
de807f81 691 uint32_t flags;
97b2e202
AD		 692};
693
1b1f42d8 694extern const struct drm_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 695
50838c8c 696int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 697 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 698int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
699 struct amdgpu_job **job);
b6723c8d 700
a5fb4ec2 701void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 702void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 703int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
1b1f42d8 704 struct drm_sched_entity *entity, void *owner,
f54d1867 705 struct dma_fence **f);
8b4fb00b 706
effd924d
AR		 707/*
708 * Queue manager
709 */
710struct amdgpu_queue_mapper {
711 int hw_ip;
712 struct mutex lock;
713 /* protected by lock */
714 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
715};
716
717struct amdgpu_queue_mgr {
718 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
719};
720
721int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
722 struct amdgpu_queue_mgr *mgr);
723int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
724 struct amdgpu_queue_mgr *mgr);
725int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
726 struct amdgpu_queue_mgr *mgr,
fa7c7939 727 u32 hw_ip, u32 instance, u32 ring,
effd924d
AR		 728 struct amdgpu_ring **out_ring);
729
97b2e202
AD		 730/*
731 * context related structures
732 */
733
21c16bf6 734struct amdgpu_ctx_ring {
91404fb2 735 uint64_t sequence;
f54d1867 736 struct dma_fence **fences;
1b1f42d8 737 struct drm_sched_entity entity;
21c16bf6
CK		 738};
739
97b2e202 740struct amdgpu_ctx {
0b492a4c 741 struct kref refcount;
9cb7e5a9 742 struct amdgpu_device *adev;
effd924d 743 struct amdgpu_queue_mgr queue_mgr;
0b492a4c 744 unsigned reset_counter;
668ca1b4 745 unsigned reset_counter_query;
e55f2b64 746 uint32_t vram_lost_counter;
21c16bf6 747 spinlock_t ring_lock;
f54d1867 748 struct dma_fence **fences;
21c16bf6 749 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
e55f2b64 750 bool preamble_presented;
1b1f42d8
LS		 751 enum drm_sched_priority init_priority;
752 enum drm_sched_priority override_priority;
0ae94444 753 struct mutex lock;
1102900d 754 atomic_t guilty;
97b2e202
AD		 755};
756
757struct amdgpu_ctx_mgr {
0b492a4c
AD		 758 struct amdgpu_device *adev;
759 struct mutex lock;
760 /* protected by lock */
761 struct idr ctx_handles;
97b2e202
AD		 762};
763
0b492a4c
AD		 764struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
765int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
766
eb01abc7
ML		 767int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
768 struct dma_fence *fence, uint64_t *seq);
f54d1867 769struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
21c16bf6 770 struct amdgpu_ring *ring, uint64_t seq);
c23be4ae 771void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
1b1f42d8 772 enum drm_sched_priority priority);
21c16bf6 773
0b492a4c
AD		 774int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
775 struct drm_file *filp);
776
0ae94444
AG		 777int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
778
efd4ccb5
CK		 779void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
780void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 781
0ae94444 782
97b2e202
AD		 783/*
784 * file private structure
785 */
786
787struct amdgpu_fpriv {
788 struct amdgpu_vm vm;
b85891bd 789 struct amdgpu_bo_va *prt_va;
0f4b3c68 790 struct amdgpu_bo_va *csa_va;
97b2e202
AD		 791 struct mutex bo_list_lock;
792 struct idr bo_list_handles;
0b492a4c 793 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 794};
795
796/*
797 * residency list
798 */
9124a398
CK		 799struct amdgpu_bo_list_entry {
800 struct amdgpu_bo *robj;
801 struct ttm_validate_buffer tv;
802 struct amdgpu_bo_va *bo_va;
803 uint32_t priority;
804 struct page **user_pages;
805 int user_invalidated;
806};
97b2e202
AD		 807
808struct amdgpu_bo_list {
809 struct mutex lock;
5ac55629
AX		 810 struct rcu_head rhead;
811 struct kref refcount;
97b2e202
AD		 812 struct amdgpu_bo *gds_obj;
813 struct amdgpu_bo *gws_obj;
814 struct amdgpu_bo *oa_obj;
211dff55 815 unsigned first_userptr;
97b2e202
AD		 816 unsigned num_entries;
817 struct amdgpu_bo_list_entry *array;
818};
819
820struct amdgpu_bo_list *
821amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 822void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
823 struct list_head *validated);
97b2e202
AD		 824void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
825void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
826
827/*
828 * GFX stuff
829 */
830#include "clearstate_defs.h"
831
79e5412c
AD		 832struct amdgpu_rlc_funcs {
833 void (*enter_safe_mode)(struct amdgpu_device *adev);
834 void (*exit_safe_mode)(struct amdgpu_device *adev);
835};
836
97b2e202
AD		 837struct amdgpu_rlc {
838 /* for power gating */
839 struct amdgpu_bo *save_restore_obj;
840 uint64_t save_restore_gpu_addr;
841 volatile uint32_t *sr_ptr;
842 const u32 *reg_list;
843 u32 reg_list_size;
844 /* for clear state */
845 struct amdgpu_bo *clear_state_obj;
846 uint64_t clear_state_gpu_addr;
847 volatile uint32_t *cs_ptr;
848 const struct cs_section_def *cs_data;
849 u32 clear_state_size;
850 /* for cp tables */
851 struct amdgpu_bo *cp_table_obj;
852 uint64_t cp_table_gpu_addr;
853 volatile uint32_t *cp_table_ptr;
854 u32 cp_table_size;
79e5412c
AD		 855
856 /* safe mode for updating CG/PG state */
857 bool in_safe_mode;
858 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 859
860 /* for firmware data */
861 u32 save_and_restore_offset;
862 u32 clear_state_descriptor_offset;
863 u32 avail_scratch_ram_locations;
864 u32 reg_restore_list_size;
865 u32 reg_list_format_start;
866 u32 reg_list_format_separate_start;
867 u32 starting_offsets_start;
868 u32 reg_list_format_size_bytes;
869 u32 reg_list_size_bytes;
870
871 u32 *register_list_format;
872 u32 *register_restore;
97b2e202
AD		 873};
874
78c16834
AR		 875#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
876
97b2e202
AD		 877struct amdgpu_mec {
878 struct amdgpu_bo *hpd_eop_obj;
879 u64 hpd_eop_gpu_addr;
b1023571
KW		 880 struct amdgpu_bo *mec_fw_obj;
881 u64 mec_fw_gpu_addr;
97b2e202 882 u32 num_mec;
42794b27
AR		 883 u32 num_pipe_per_mec;
884 u32 num_queue_per_pipe;
59a82d7d 885 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
78c16834
AR		 886
887 /* These are the resources for which amdgpu takes ownership */
888 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 889};
890
4e638ae9
XY		 891struct amdgpu_kiq {
892 u64 eop_gpu_addr;
893 struct amdgpu_bo *eop_obj;
43ca8efa 894 spinlock_t ring_lock;
4e638ae9
XY		 895 struct amdgpu_ring ring;
896 struct amdgpu_irq_src irq;
897};
898
97b2e202
AD		 899/*
900 * GPU scratch registers structures, functions & helpers
901 */
902struct amdgpu_scratch {
903 unsigned num_reg;
904 uint32_t reg_base;
50261151 905 uint32_t free_mask;
97b2e202
AD		 906};
907
908/*
909 * GFX configurations
910 */
e3fa7630
AD		 911#define AMDGPU_GFX_MAX_SE 4
912#define AMDGPU_GFX_MAX_SH_PER_SE 2
913
914struct amdgpu_rb_config {
915 uint32_t rb_backend_disable;
916 uint32_t user_rb_backend_disable;
917 uint32_t raster_config;
918 uint32_t raster_config_1;
919};
920
d0e95758
AG		 921struct gb_addr_config {
922 uint16_t pipe_interleave_size;
923 uint8_t num_pipes;
924 uint8_t max_compress_frags;
925 uint8_t num_banks;
926 uint8_t num_se;
927 uint8_t num_rb_per_se;
928};
929
ea323f88 930struct amdgpu_gfx_config {
97b2e202
AD		 931 unsigned max_shader_engines;
932 unsigned max_tile_pipes;
933 unsigned max_cu_per_sh;
934 unsigned max_sh_per_se;
935 unsigned max_backends_per_se;
936 unsigned max_texture_channel_caches;
937 unsigned max_gprs;
938 unsigned max_gs_threads;
939 unsigned max_hw_contexts;
940 unsigned sc_prim_fifo_size_frontend;
941 unsigned sc_prim_fifo_size_backend;
942 unsigned sc_hiz_tile_fifo_size;
943 unsigned sc_earlyz_tile_fifo_size;
944
945 unsigned num_tile_pipes;
946 unsigned backend_enable_mask;
947 unsigned mem_max_burst_length_bytes;
948 unsigned mem_row_size_in_kb;
949 unsigned shader_engine_tile_size;
950 unsigned num_gpus;
951 unsigned multi_gpu_tile_size;
952 unsigned mc_arb_ramcfg;
953 unsigned gb_addr_config;
8f8e00c1 954 unsigned num_rbs;
408bfe7c
JZ		 955 unsigned gs_vgt_table_depth;
956 unsigned gs_prim_buffer_depth;
97b2e202
AD		 957
958 uint32_t tile_mode_array[32];
959 uint32_t macrotile_mode_array[16];
e3fa7630 960
d0e95758 961 struct gb_addr_config gb_addr_config_fields;
e3fa7630 962 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
df6e2c4a
JZ		 963
964 /* gfx configure feature */
965 uint32_t double_offchip_lds_buf;
97b2e202
AD		 966};
967
7dae69a2 968struct amdgpu_cu_info {
51fd0370 969 uint32_t max_waves_per_simd;
408bfe7c 970 uint32_t wave_front_size;
51fd0370
HZ		 971 uint32_t max_scratch_slots_per_cu;
972 uint32_t lds_size;
dbfe85ea
FC		 973
974 /* total active CU number */
975 uint32_t number;
976 uint32_t ao_cu_mask;
977 uint32_t ao_cu_bitmap[4][4];
7dae69a2
AD		 978 uint32_t bitmap[4][4];
979};
980
b95e31fd
AD		 981struct amdgpu_gfx_funcs {
982 /* get the gpu clock counter */
983 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 984 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
472259f0 985 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
c5a60ce8
TSD		 986 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
987 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
b95e31fd
AD		 988};
989
bce23e00
AD		 990struct amdgpu_ngg_buf {
991 struct amdgpu_bo *bo;
992 uint64_t gpu_addr;
993 uint32_t size;
994 uint32_t bo_size;
995};
996
997enum {
af8baf15
GR		 998 NGG_PRIM = 0,
999 NGG_POS,
1000 NGG_CNTL,
1001 NGG_PARAM,
bce23e00
AD		 1002 NGG_BUF_MAX
1003};
1004
1005struct amdgpu_ngg {
1006 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
1007 uint32_t gds_reserve_addr;
1008 uint32_t gds_reserve_size;
1009 bool init;
1010};
1011
97b2e202
AD		 1012struct amdgpu_gfx {
1013 struct mutex gpu_clock_mutex;
ea323f88 1014 struct amdgpu_gfx_config config;
97b2e202
AD		 1015 struct amdgpu_rlc rlc;
1016 struct amdgpu_mec mec;
4e638ae9 1017 struct amdgpu_kiq kiq;
97b2e202
AD		 1018 struct amdgpu_scratch scratch;
1019 const struct firmware *me_fw; /* ME firmware */
1020 uint32_t me_fw_version;
1021 const struct firmware *pfp_fw; /* PFP firmware */
1022 uint32_t pfp_fw_version;
1023 const struct firmware *ce_fw; /* CE firmware */
1024 uint32_t ce_fw_version;
1025 const struct firmware *rlc_fw; /* RLC firmware */
1026 uint32_t rlc_fw_version;
1027 const struct firmware *mec_fw; /* MEC firmware */
1028 uint32_t mec_fw_version;
1029 const struct firmware *mec2_fw; /* MEC2 firmware */
1030 uint32_t mec2_fw_version;
02558a00
KW		 1031 uint32_t me_feature_version;
1032 uint32_t ce_feature_version;
1033 uint32_t pfp_feature_version;
351643d7
JZ		 1034 uint32_t rlc_feature_version;
1035 uint32_t mec_feature_version;
1036 uint32_t mec2_feature_version;
97b2e202
AD		 1037 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1038 unsigned num_gfx_rings;
1039 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1040 unsigned num_compute_rings;
1041 struct amdgpu_irq_src eop_irq;
1042 struct amdgpu_irq_src priv_reg_irq;
1043 struct amdgpu_irq_src priv_inst_irq;
1044 /* gfx status */
7dae69a2 1045 uint32_t gfx_current_status;
a101a899 1046 /* ce ram size*/
7dae69a2
AD		 1047 unsigned ce_ram_size;
1048 struct amdgpu_cu_info cu_info;
b95e31fd 1049 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1050
1051 /* reset mask */
1052 uint32_t grbm_soft_reset;
1053 uint32_t srbm_soft_reset;
b4e40676
DP		 1054 /* s3/s4 mask */
1055 bool in_suspend;
bce23e00
AD		 1056 /* NGG */
1057 struct amdgpu_ngg ngg;
b8866c26
AR		 1058
1059 /* pipe reservation */
1060 struct mutex pipe_reserve_mutex;
1061 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
97b2e202
AD		 1062};
1063
b07c60c0 1064int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1065 unsigned size, struct amdgpu_ib *ib);
4d9c514d 1066void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
f54d1867 1067 struct dma_fence *f);
b07c60c0 1068int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
50ddc75e
JZ		 1069 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1070 struct dma_fence **f);
97b2e202
AD		 1071int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1072void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1073int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202
AD		 1074
1075/*
1076 * CS.
1077 */
1078struct amdgpu_cs_chunk {
1079 uint32_t chunk_id;
1080 uint32_t length_dw;
758ac17f 1081 void *kdata;
97b2e202
AD		 1082};
1083
1084struct amdgpu_cs_parser {
1085 struct amdgpu_device *adev;
1086 struct drm_file *filp;
3cb485f3 1087 struct amdgpu_ctx *ctx;
c3cca41e 1088
97b2e202
AD		 1089 /* chunks */
1090 unsigned nchunks;
1091 struct amdgpu_cs_chunk *chunks;
97b2e202 1092
50838c8c
CK		 1093 /* scheduler job object */
1094 struct amdgpu_job *job;
97b2e202 1095
c3cca41e
CK		 1096 /* buffer objects */
1097 struct ww_acquire_ctx ticket;
1098 struct amdgpu_bo_list *bo_list;
3fe89771 1099 struct amdgpu_mn *mn;
c3cca41e
CK		 1100 struct amdgpu_bo_list_entry vm_pd;
1101 struct list_head validated;
f54d1867 1102 struct dma_fence *fence;
c3cca41e 1103 uint64_t bytes_moved_threshold;
00f06b24 1104 uint64_t bytes_moved_vis_threshold;
c3cca41e 1105 uint64_t bytes_moved;
00f06b24 1106 uint64_t bytes_moved_vis;
662bfa61 1107 struct amdgpu_bo_list_entry *evictable;
97b2e202
AD		 1108
1109 /* user fence */
91acbeb6 1110 struct amdgpu_bo_list_entry uf_entry;
660e8558
DA		 1111
1112 unsigned num_post_dep_syncobjs;
1113 struct drm_syncobj **post_dep_syncobjs;
97b2e202
AD		 1114};
1115
753ad49c
ML		 1116#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1117#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1118#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1119
bb977d37 1120struct amdgpu_job {
1b1f42d8 1121 struct drm_sched_job base;
bb977d37 1122 struct amdgpu_device *adev;
edf600da 1123 struct amdgpu_vm *vm;
b07c60c0 1124 struct amdgpu_ring *ring;
e86f9cee 1125 struct amdgpu_sync sync;
df83d1eb 1126 struct amdgpu_sync sched_sync;
bb977d37 1127 struct amdgpu_ib *ibs;
f54d1867 1128 struct dma_fence *fence; /* the hw fence */
753ad49c 1129 uint32_t preamble_status;
bb977d37 1130 uint32_t num_ibs;
e2840221 1131 void *owner;
3aecd24c 1132 uint64_t fence_ctx; /* the fence_context this job uses */
fd53be30 1133 bool vm_needs_flush;
d88bf583
CK		 1134 unsigned vm_id;
1135 uint64_t vm_pd_addr;
1136 uint32_t gds_base, gds_size;
1137 uint32_t gws_base, gws_size;
1138 uint32_t oa_base, oa_size;
14e47f93 1139 uint32_t vram_lost_counter;
758ac17f
CK		 1140
1141 /* user fence handling */
b5f5acbc 1142 uint64_t uf_addr;
758ac17f
CK		 1143 uint64_t uf_sequence;
1144
bb977d37 1145};
a6db8a33
JZ		 1146#define to_amdgpu_job(sched_job) \
1147 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1148
7270f839
CK		 1149static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1150 uint32_t ib_idx, int idx)
97b2e202 1151{
50838c8c 1152 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1153}
1154
7270f839
CK		 1155static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1156 uint32_t ib_idx, int idx,
1157 uint32_t value)
1158{
50838c8c 1159 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1160}
1161
97b2e202
AD		 1162/*
1163 * Writeback
1164 */
896a664c 1165#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
97b2e202
AD		 1166
1167struct amdgpu_wb {
1168 struct amdgpu_bo *wb_obj;
1169 volatile uint32_t *wb;
1170 uint64_t gpu_addr;
1171 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1172 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1173};
1174
1175int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1176void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1177
d0dd7f0c
AD		 1178void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1179
97b2e202
AD		 1180/*
1181 * SDMA
1182 */
c113ea1c 1183struct amdgpu_sdma_instance {
97b2e202
AD		 1184 /* SDMA firmware */
1185 const struct firmware *fw;
1186 uint32_t fw_version;
cfa2104f 1187 uint32_t feature_version;
97b2e202
AD		 1188
1189 struct amdgpu_ring ring;
18111de0 1190 bool burst_nop;
97b2e202
AD		 1191};
1192
c113ea1c
AD		 1193struct amdgpu_sdma {
1194 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
30d1574f
KW		 1195#ifdef CONFIG_DRM_AMDGPU_SI
1196 //SI DMA has a difference trap irq number for the second engine
1197 struct amdgpu_irq_src trap_irq_1;
1198#endif
c113ea1c
AD		 1199 struct amdgpu_irq_src trap_irq;
1200 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1201 int num_instances;
e702a680 1202 uint32_t srbm_soft_reset;
c113ea1c
AD		 1203};
1204
97b2e202
AD		 1205/*
1206 * Firmware
1207 */
e635ee07
HR		 1208enum amdgpu_firmware_load_type {
1209 AMDGPU_FW_LOAD_DIRECT = 0,
1210 AMDGPU_FW_LOAD_SMU,
1211 AMDGPU_FW_LOAD_PSP,
1212};
1213
97b2e202
AD		 1214struct amdgpu_firmware {
1215 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
e635ee07 1216 enum amdgpu_firmware_load_type load_type;
97b2e202
AD		 1217 struct amdgpu_bo *fw_buf;
1218 unsigned int fw_size;
2445b227 1219 unsigned int max_ucodes;
0e5ca0d1
HR		 1220 /* firmwares are loaded by psp instead of smu from vega10 */
1221 const struct amdgpu_psp_funcs *funcs;
1222 struct amdgpu_bo *rbuf;
1223 struct mutex mutex;
ab4fe3e1
HR		 1224
1225 /* gpu info firmware data pointer */
1226 const struct firmware *gpu_info_fw;
d59c026b
ML		 1227
1228 void *fw_buf_ptr;
1229 uint64_t fw_buf_mc;
97b2e202
AD		 1230};
1231
1232/*
1233 * Benchmarking
1234 */
1235void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1236
1237
1238/*
1239 * Testing
1240 */
1241void amdgpu_test_moves(struct amdgpu_device *adev);
97b2e202 1242
97b2e202
AD		 1243/*
1244 * Debugfs
1245 */
1246struct amdgpu_debugfs {
06ab6832 1247 const struct drm_info_list *files;
97b2e202
AD		 1248 unsigned num_files;
1249};
1250
1251int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1252 const struct drm_info_list *files,
97b2e202
AD		 1253 unsigned nfiles);
1254int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
50ab2533
HR		 1255int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1256
97b2e202
AD		 1257/*
1258 * amdgpu smumgr functions
1259 */
1260struct amdgpu_smumgr_funcs {
1261 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1262 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1263 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1264};
1265
1266/*
1267 * amdgpu smumgr
1268 */
1269struct amdgpu_smumgr {
1270 struct amdgpu_bo *toc_buf;
1271 struct amdgpu_bo *smu_buf;
1272 /* asic priv smu data */
1273 void *priv;
1274 spinlock_t smu_lock;
1275 /* smumgr functions */
1276 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1277 /* ucode loading complete flag */
1278 uint32_t fw_flags;
1279};
1280
1281/*
1282 * ASIC specific register table accessible by UMD
1283 */
1284struct amdgpu_allowed_register_entry {
1285 uint32_t reg_offset;
97b2e202
AD		 1286 bool grbm_indexed;
1287};
1288
97b2e202
AD		 1289/*
1290 * ASIC specific functions.
1291 */
1292struct amdgpu_asic_funcs {
1293 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1294 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1295 u8 *bios, u32 length_bytes);
97b2e202
AD		 1296 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1297 u32 sh_num, u32 reg_offset, u32 *value);
1298 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1299 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1300 /* get the reference clock */
1301 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1302 /* MM block clocks */
1303 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1304 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
841686df
MB		 1305 /* static power management */
1306 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1307 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
bbf282d8
AD		 1308 /* get config memsize register */
1309 u32 (*get_config_memsize)(struct amdgpu_device *adev);
97b2e202
AD		 1310};
1311
1312/*
1313 * IOCTL.
1314 */
1315int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *filp);
1317int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1318 struct drm_file *filp);
1319
1320int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1321 struct drm_file *filp);
1322int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *filp);
1324int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1325 struct drm_file *filp);
1326int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1327 struct drm_file *filp);
1328int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1329 struct drm_file *filp);
1330int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1331 struct drm_file *filp);
1332int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
7ca24cf2
MO		 1333int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *filp);
97b2e202 1335int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
eef18a82
JZ		 1336int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1337 struct drm_file *filp);
97b2e202
AD		 1338
1339int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *filp);
1341
1342/* VRAM scratch page for HDP bug, default vram page */
1343struct amdgpu_vram_scratch {
1344 struct amdgpu_bo *robj;
1345 volatile uint32_t *ptr;
1346 u64 gpu_addr;
1347};
1348
1349/*
1350 * ACPI
1351 */
1352struct amdgpu_atif_notification_cfg {
1353 bool enabled;
1354 int command_code;
1355};
1356
1357struct amdgpu_atif_notifications {
1358 bool display_switch;
1359 bool expansion_mode_change;
1360 bool thermal_state;
1361 bool forced_power_state;
1362 bool system_power_state;
1363 bool display_conf_change;
1364 bool px_gfx_switch;
1365 bool brightness_change;
1366 bool dgpu_display_event;
1367};
1368
1369struct amdgpu_atif_functions {
1370 bool system_params;
1371 bool sbios_requests;
1372 bool select_active_disp;
1373 bool lid_state;
1374 bool get_tv_standard;
1375 bool set_tv_standard;
1376 bool get_panel_expansion_mode;
1377 bool set_panel_expansion_mode;
1378 bool temperature_change;
1379 bool graphics_device_types;
1380};
1381
1382struct amdgpu_atif {
1383 struct amdgpu_atif_notifications notifications;
1384 struct amdgpu_atif_functions functions;
1385 struct amdgpu_atif_notification_cfg notification_cfg;
1386 struct amdgpu_encoder *encoder_for_bl;
1387};
1388
1389struct amdgpu_atcs_functions {
1390 bool get_ext_state;
1391 bool pcie_perf_req;
1392 bool pcie_dev_rdy;
1393 bool pcie_bus_width;
1394};
1395
1396struct amdgpu_atcs {
1397 struct amdgpu_atcs_functions functions;
1398};
1399
a05502e5
HC		 1400/*
1401 * Firmware VRAM reservation
1402 */
1403struct amdgpu_fw_vram_usage {
1404 u64 start_offset;
1405 u64 size;
1406 struct amdgpu_bo *reserved_bo;
1407 void *va;
1408};
1409
1410int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
f59548c8 1411void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);
a05502e5 1412
d03846af
CZ		 1413/*
1414 * CGS
1415 */
110e6f26
DA		 1416struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1417void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce 1418
97b2e202
AD		 1419/*
1420 * Core structure, functions and helpers.
1421 */
1422typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1423typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1424
1425typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1426typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1427
946a4d5b
SL		 1428
1429/*
1430 * amdgpu nbio functions
1431 *
946a4d5b 1432 */
bf383fb6
AD		 1433struct nbio_hdp_flush_reg {
1434 u32 ref_and_mask_cp0;
1435 u32 ref_and_mask_cp1;
1436 u32 ref_and_mask_cp2;
1437 u32 ref_and_mask_cp3;
1438 u32 ref_and_mask_cp4;
1439 u32 ref_and_mask_cp5;
1440 u32 ref_and_mask_cp6;
1441 u32 ref_and_mask_cp7;
1442 u32 ref_and_mask_cp8;
1443 u32 ref_and_mask_cp9;
1444 u32 ref_and_mask_sdma0;
1445 u32 ref_and_mask_sdma1;
1446};
946a4d5b
SL		 1447
1448struct amdgpu_nbio_funcs {
bf383fb6
AD		 1449 const struct nbio_hdp_flush_reg *hdp_flush_reg;
1450 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
1451 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
1452 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
1453 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
1454 u32 (*get_rev_id)(struct amdgpu_device *adev);
bf383fb6
AD		 1455 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
1456 void (*hdp_flush)(struct amdgpu_device *adev);
1457 u32 (*get_memsize)(struct amdgpu_device *adev);
1458 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
1459 bool use_doorbell, int doorbell_index);
1460 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
1461 bool enable);
1462 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
1463 bool enable);
1464 void (*ih_doorbell_range)(struct amdgpu_device *adev,
1465 bool use_doorbell, int doorbell_index);
1466 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
1467 bool enable);
1468 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
1469 bool enable);
1470 void (*get_clockgating_state)(struct amdgpu_device *adev,
1471 u32 *flags);
1472 void (*ih_control)(struct amdgpu_device *adev);
1473 void (*init_registers)(struct amdgpu_device *adev);
1474 void (*detect_hw_virt)(struct amdgpu_device *adev);
946a4d5b
SL		 1475};
1476
1477
4522824c
SL		 1478/* Define the HW IP blocks will be used in driver , add more if necessary */
1479enum amd_hw_ip_block_type {
1480 GC_HWIP = 1,
1481 HDP_HWIP,
1482 SDMA0_HWIP,
1483 SDMA1_HWIP,
1484 MMHUB_HWIP,
1485 ATHUB_HWIP,
1486 NBIO_HWIP,
1487 MP0_HWIP,
1488 UVD_HWIP,
1489 VCN_HWIP = UVD_HWIP,
1490 VCE_HWIP,
1491 DF_HWIP,
1492 DCE_HWIP,
1493 OSSSYS_HWIP,
1494 SMUIO_HWIP,
1495 PWR_HWIP,
1496 NBIF_HWIP,
1497 MAX_HWIP
1498};
1499
1500#define HWIP_MAX_INSTANCE 6
1501
11dc9364
RZ		 1502struct amd_powerplay {
1503 struct cgs_device *cgs_device;
1504 void *pp_handle;
1505 const struct amd_ip_funcs *ip_funcs;
1506 const struct amd_pm_funcs *pp_funcs;
1507};
1508
0c49e0b8 1509#define AMDGPU_RESET_MAGIC_NUM 64
97b2e202
AD		 1510struct amdgpu_device {
1511 struct device *dev;
1512 struct drm_device *ddev;
1513 struct pci_dev *pdev;
97b2e202 1514
a8fe58ce
MB		 1515#ifdef CONFIG_DRM_AMD_ACP
1516 struct amdgpu_acp acp;
1517#endif
1518
97b2e202 1519 /* ASIC */
2f7d10b3 1520 enum amd_asic_type asic_type;
97b2e202
AD		 1521 uint32_t family;
1522 uint32_t rev_id;
1523 uint32_t external_rev_id;
1524 unsigned long flags;
1525 int usec_timeout;
1526 const struct amdgpu_asic_funcs *asic_funcs;
1527 bool shutdown;
97b2e202
AD		 1528 bool need_dma32;
1529 bool accel_working;
edf600da 1530 struct work_struct reset_work;
97b2e202
AD		 1531 struct notifier_block acpi_nb;
1532 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1533 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1534 unsigned debugfs_count;
97b2e202 1535#if defined(CONFIG_DEBUG_FS)
adcec288 1536 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1537#endif
1538 struct amdgpu_atif atif;
1539 struct amdgpu_atcs atcs;
1540 struct mutex srbm_mutex;
1541 /* GRBM index mutex. Protects concurrent access to GRBM index */
1542 struct mutex grbm_idx_mutex;
1543 struct dev_pm_domain vga_pm_domain;
1544 bool have_disp_power_ref;
1545
1546 /* BIOS */
0cdd5005 1547 bool is_atom_fw;
97b2e202 1548 uint8_t *bios;
a9f5db9c 1549 uint32_t bios_size;
5af2c10d 1550 struct amdgpu_bo *stolen_vga_memory;
a5bde2f9 1551 uint32_t bios_scratch_reg_offset;
97b2e202
AD		 1552 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1553
1554 /* Register/doorbell mmio */
1555 resource_size_t rmmio_base;
1556 resource_size_t rmmio_size;
1557 void __iomem *rmmio;
1558 /* protects concurrent MM_INDEX/DATA based register access */
1559 spinlock_t mmio_idx_lock;
1560 /* protects concurrent SMC based register access */
1561 spinlock_t smc_idx_lock;
1562 amdgpu_rreg_t smc_rreg;
1563 amdgpu_wreg_t smc_wreg;
1564 /* protects concurrent PCIE register access */
1565 spinlock_t pcie_idx_lock;
1566 amdgpu_rreg_t pcie_rreg;
1567 amdgpu_wreg_t pcie_wreg;
36b9a952
HR		 1568 amdgpu_rreg_t pciep_rreg;
1569 amdgpu_wreg_t pciep_wreg;
97b2e202
AD		 1570 /* protects concurrent UVD register access */
1571 spinlock_t uvd_ctx_idx_lock;
1572 amdgpu_rreg_t uvd_ctx_rreg;
1573 amdgpu_wreg_t uvd_ctx_wreg;
1574 /* protects concurrent DIDT register access */
1575 spinlock_t didt_idx_lock;
1576 amdgpu_rreg_t didt_rreg;
1577 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 1578 /* protects concurrent gc_cac register access */
1579 spinlock_t gc_cac_idx_lock;
1580 amdgpu_rreg_t gc_cac_rreg;
1581 amdgpu_wreg_t gc_cac_wreg;
16abb5d2
EQ		 1582 /* protects concurrent se_cac register access */
1583 spinlock_t se_cac_idx_lock;
1584 amdgpu_rreg_t se_cac_rreg;
1585 amdgpu_wreg_t se_cac_wreg;
97b2e202
AD		 1586 /* protects concurrent ENDPOINT (audio) register access */
1587 spinlock_t audio_endpt_idx_lock;
1588 amdgpu_block_rreg_t audio_endpt_rreg;
1589 amdgpu_block_wreg_t audio_endpt_wreg;
1590 void __iomem *rio_mem;
1591 resource_size_t rio_mem_size;
1592 struct amdgpu_doorbell doorbell;
1593
1594 /* clock/pll info */
1595 struct amdgpu_clock clock;
1596
1597 /* MC */
1598 struct amdgpu_mc mc;
1599 struct amdgpu_gart gart;
1600 struct amdgpu_dummy_page dummy_page;
1601 struct amdgpu_vm_manager vm_manager;
e60f8db5 1602 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
97b2e202
AD		 1603
1604 /* memory management */
1605 struct amdgpu_mman mman;
97b2e202
AD		 1606 struct amdgpu_vram_scratch vram_scratch;
1607 struct amdgpu_wb wb;
97b2e202 1608 atomic64_t num_bytes_moved;
dbd5ed60 1609 atomic64_t num_evictions;
68e2c5ff 1610 atomic64_t num_vram_cpu_page_faults;
d94aed5a 1611 atomic_t gpu_reset_counter;
f1892138 1612 atomic_t vram_lost_counter;
97b2e202 1613
95844d20
MO		 1614 /* data for buffer migration throttling */
1615 struct {
1616 spinlock_t lock;
1617 s64 last_update_us;
1618 s64 accum_us; /* accumulated microseconds */
00f06b24 1619 s64 accum_us_vis; /* for visible VRAM */
95844d20
MO		 1620 u32 log2_max_MBps;
1621 } mm_stats;
1622
97b2e202 1623 /* display */
9accf2fd 1624 bool enable_virtual_display;
97b2e202 1625 struct amdgpu_mode_info mode_info;
4562236b 1626 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
97b2e202
AD		 1627 struct work_struct hotplug_work;
1628 struct amdgpu_irq_src crtc_irq;
1629 struct amdgpu_irq_src pageflip_irq;
1630 struct amdgpu_irq_src hpd_irq;
1631
1632 /* rings */
76bf0db5 1633 u64 fence_context;
97b2e202
AD		 1634 unsigned num_rings;
1635 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1636 bool ib_pool_ready;
1637 struct amdgpu_sa_manager ring_tmp_bo;
1638
1639 /* interrupts */
1640 struct amdgpu_irq irq;
1641
1f7371b2
AD		 1642 /* powerplay */
1643 struct amd_powerplay powerplay;
f3898ea1 1644 bool pp_force_state_enabled;
1f7371b2 1645
97b2e202
AD		 1646 /* dpm */
1647 struct amdgpu_pm pm;
1648 u32 cg_flags;
1649 u32 pg_flags;
1650
1651 /* amdgpu smumgr */
1652 struct amdgpu_smumgr smu;
1653
1654 /* gfx */
1655 struct amdgpu_gfx gfx;
1656
1657 /* sdma */
c113ea1c 1658 struct amdgpu_sdma sdma;
97b2e202 1659
b43aaee6
LL		 1660 /* uvd */
1661 struct amdgpu_uvd uvd;
1662
1663 /* vce */
1664 struct amdgpu_vce vce;
1665
1666 /* vcn */
1667 struct amdgpu_vcn vcn;
97b2e202
AD		 1668
1669 /* firmwares */
1670 struct amdgpu_firmware firmware;
1671
0e5ca0d1
HR		 1672 /* PSP */
1673 struct psp_context psp;
1674
97b2e202
AD		 1675 /* GDS */
1676 struct amdgpu_gds gds;
1677
4562236b
HW		 1678 /* display related functionality */
1679 struct amdgpu_display_manager dm;
1680
a1255107 1681 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
97b2e202 1682 int num_ip_blocks;
97b2e202
AD		 1683 struct mutex mn_lock;
1684 DECLARE_HASHTABLE(mn_hash, 7);
1685
1686 /* tracking pinned memory */
1687 u64 vram_pin_size;
e131b914 1688 u64 invisible_pin_size;
97b2e202 1689 u64 gart_pin_size;
130e0371
OG		 1690
1691 /* amdkfd interface */
1692 struct kfd_dev *kfd;
23ca0e4e 1693
4522824c
SL		 1694 /* soc15 register offset based on ip, instance and segment */
1695 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1696
946a4d5b
SL		 1697 const struct amdgpu_nbio_funcs *nbio_funcs;
1698
2dc80b00
S		 1699 /* delayed work_func for deferring clockgating during resume */
1700 struct delayed_work late_init_work;
1701
5a5099cb 1702 struct amdgpu_virt virt;
a05502e5
HC		 1703 /* firmware VRAM reservation */
1704 struct amdgpu_fw_vram_usage fw_vram_usage;
0c4e7fa5
CZ		 1705
1706 /* link all shadow bo */
1707 struct list_head shadow_list;
1708 struct mutex shadow_list_lock;
795f2813
AR		 1709 /* keep an lru list of rings by HW IP */
1710 struct list_head ring_lru_list;
1711 spinlock_t ring_lru_list_lock;
5c1354bd 1712
c836fec5
JQ		 1713 /* record hw reset is performed */
1714 bool has_hw_reset;
0c49e0b8 1715 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
c836fec5 1716
47ed4e1c
KW		 1717 /* record last mm index being written through WREG32*/
1718 unsigned long last_mm_index;
13a752e3
ML		 1719 bool in_gpu_reset;
1720 struct mutex lock_reset;
97b2e202
AD		 1721};
1722
a7d64de6
CK		 1723static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1724{
1725 return container_of(bdev, struct amdgpu_device, mman.bdev);
1726}
1727
97b2e202
AD		 1728int amdgpu_device_init(struct amdgpu_device *adev,
1729 struct drm_device *ddev,
1730 struct pci_dev *pdev,
1731 uint32_t flags);
1732void amdgpu_device_fini(struct amdgpu_device *adev);
1733int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1734
1735uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
15d72fd7 1736 uint32_t acc_flags);
97b2e202 1737void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
15d72fd7 1738 uint32_t acc_flags);
97b2e202
AD		 1739u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1740void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1741
1742u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1743void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
832be404
KW		 1744u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1745void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
97b2e202 1746
4562236b
HW		 1747bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1748bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1749
97b2e202
AD		 1750/*
1751 * Registers read & write functions.
1752 */
15d72fd7
ML		 1753
1754#define AMDGPU_REGS_IDX (1<<0)
1755#define AMDGPU_REGS_NO_KIQ (1<<1)
1756
1757#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1758#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1759
1760#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1761#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1762#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1763#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1764#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
97b2e202
AD		 1765#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1766#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1767#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1768#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
36b9a952
HR		 1769#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1770#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
97b2e202
AD		 1771#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1772#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1773#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1774#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1775#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1776#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 1777#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1778#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
16abb5d2
EQ		 1779#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1780#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
97b2e202
AD		 1781#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1782#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1783#define WREG32_P(reg, val, mask) \
1784 do { \
1785 uint32_t tmp_ = RREG32(reg); \
1786 tmp_ &= (mask); \
1787 tmp_ |= ((val) & ~(mask)); \
1788 WREG32(reg, tmp_); \
1789 } while (0)
1790#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1791#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1792#define WREG32_PLL_P(reg, val, mask) \
1793 do { \
1794 uint32_t tmp_ = RREG32_PLL(reg); \
1795 tmp_ &= (mask); \
1796 tmp_ |= ((val) & ~(mask)); \
1797 WREG32_PLL(reg, tmp_); \
1798 } while (0)
1799#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1800#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1801#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1802
1803#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1804#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
832be404
KW		 1805#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1806#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
97b2e202
AD		 1807
1808#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1809#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1810
1811#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1812 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1813 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1814
1815#define REG_GET_FIELD(value, reg, field) \
1816 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
61cb8cef
TSD		 1817
1818#define WREG32_FIELD(reg, field, val) \
1819 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202 1820
ccaf3574
TSD		 1821#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1822 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1823
97b2e202
AD		 1824/*
1825 * BIOS helpers.
1826 */
1827#define RBIOS8(i) (adev->bios[i])
1828#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1829#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1830
c113ea1c
AD		 1831static inline struct amdgpu_sdma_instance *
1832amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 1833{
1834 struct amdgpu_device *adev = ring->adev;
1835 int i;
1836
c113ea1c
AD		 1837 for (i = 0; i < adev->sdma.num_instances; i++)
1838 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 1839 break;
1840
1841 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 1842 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 1843 else
1844 return NULL;
1845}
1846
97b2e202
AD		 1847/*
1848 * ASICs macro.
1849 */
1850#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1851#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 1852#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1853#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1854#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
841686df
MB		 1855#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1856#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1857#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
97b2e202 1858#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 1859#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 1860#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
bbf282d8 1861#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
97b2e202
AD		 1862#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1863#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
3de676d8 1864#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
97b2e202 1865#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 1866#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 1867#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
5463545b 1868#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
97b2e202
AD		 1869#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1870#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 1871#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 1872#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1873#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1874#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 1875#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 1876#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 1877#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 1878#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 1879#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 1880#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 1881#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
c2167a65 1882#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
753ad49c 1883#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
b6091c12
XY		 1884#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1885#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
3b4d68e9 1886#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
9e5d5309 1887#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 1888#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1889#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202 1890#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
00ecd8a2 1891#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
97b2e202
AD		 1892#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1893#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
97b2e202
AD		 1894#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1895#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
97b2e202
AD		 1896#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1897#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1898#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1899#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1900#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1901#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 1902#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 1903#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1904#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1905#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
c7ae72c0 1906#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 1907#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
b95e31fd 1908#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 1909#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
97b2e202 1910#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
0e5ca0d1 1911#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
97b2e202
AD		 1912
1913/* Common functions */
dcebf026 1914int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force);
3ad81f16 1915bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202 1916void amdgpu_pci_config_reset(struct amdgpu_device *adev);
c836fec5 1917bool amdgpu_need_post(struct amdgpu_device *adev);
97b2e202 1918void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 1919
00f06b24
JB		 1920void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1921 u64 num_vis_bytes);
765e7fbf 1922void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
97b2e202 1923bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
97b2e202 1924void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
6f02a696 1925void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
d6895ad3 1926int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
97b2e202 1927void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
9f31a0b0
BX		 1928int amdgpu_ttm_init(struct amdgpu_device *adev);
1929void amdgpu_ttm_fini(struct amdgpu_device *adev);
97b2e202
AD		 1930void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1931 const u32 *registers,
1932 const u32 array_size);
1933
1934bool amdgpu_device_is_px(struct drm_device *dev);
1935/* atpx handler */
1936#if defined(CONFIG_VGA_SWITCHEROO)
1937void amdgpu_register_atpx_handler(void);
1938void amdgpu_unregister_atpx_handler(void);
a78fe133 1939bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 1940bool amdgpu_is_atpx_hybrid(void);
efc83cf4 1941bool amdgpu_atpx_dgpu_req_power_for_displays(void);
714f88e0 1942bool amdgpu_has_atpx(void);
97b2e202
AD		 1943#else
1944static inline void amdgpu_register_atpx_handler(void) {}
1945static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 1946static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 1947static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
efc83cf4 1948static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
714f88e0 1949static inline bool amdgpu_has_atpx(void) { return false; }
97b2e202
AD		 1950#endif
1951
1952/*
1953 * KMS
1954 */
1955extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 1956extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 1957
1958int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
11b3c20b 1959void amdgpu_driver_unload_kms(struct drm_device *dev);
97b2e202
AD		 1960void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1961int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1962void amdgpu_driver_postclose_kms(struct drm_device *dev,
1963 struct drm_file *file_priv);
faefba95 1964int amdgpu_suspend(struct amdgpu_device *adev);
810ddc3a
AD		 1965int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1966int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 1967u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1968int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1969void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
97b2e202
AD		 1970long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1971 unsigned long arg);
1972
97b2e202
AD		 1973/*
1974 * functions used by amdgpu_encoder.c
1975 */
1976struct amdgpu_afmt_acr {
1977 u32 clock;
1978
1979 int n_32khz;
1980 int cts_32khz;
1981
1982 int n_44_1khz;
1983 int cts_44_1khz;
1984
1985 int n_48khz;
1986 int cts_48khz;
1987
1988};
1989
1990struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1991
1992/* amdgpu_acpi.c */
1993#if defined(CONFIG_ACPI)
1994int amdgpu_acpi_init(struct amdgpu_device *adev);
1995void amdgpu_acpi_fini(struct amdgpu_device *adev);
1996bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1997int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1998 u8 perf_req, bool advertise);
1999int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2000#else
2001static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2002static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2003#endif
2004
9cca0b8e
CK		 2005int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2006 uint64_t addr, struct amdgpu_bo **bo,
2007 struct amdgpu_bo_va_mapping **mapping);
97b2e202 2008
4562236b
HW		 2009#if defined(CONFIG_DRM_AMD_DC)
2010int amdgpu_dm_display_resume(struct amdgpu_device *adev );
2011#else
2012static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
2013#endif
2014
97b2e202 2015#include "amdgpu_object.h"
97b2e202 2016#endif
Linux 6.x block layer and io_uring tree(s)