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drm/amdgpu: remove sync_to from sync obj v2
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
97b2e202 56
b80d8475
AD		 57#include "gpu_scheduler.h"
58
97b2e202
AD		 59/*
60 * Modules parameters.
61 */
62extern int amdgpu_modeset;
63extern int amdgpu_vram_limit;
64extern int amdgpu_gart_size;
65extern int amdgpu_benchmarking;
66extern int amdgpu_testing;
67extern int amdgpu_audio;
68extern int amdgpu_disp_priority;
69extern int amdgpu_hw_i2c;
70extern int amdgpu_pcie_gen2;
71extern int amdgpu_msi;
72extern int amdgpu_lockup_timeout;
73extern int amdgpu_dpm;
74extern int amdgpu_smc_load_fw;
75extern int amdgpu_aspm;
76extern int amdgpu_runtime_pm;
77extern int amdgpu_hard_reset;
78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
97b2e202 88
4b559c90 89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
97b2e202
AD		 98/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
36f523a7
JZ		 104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
97b2e202
AD		 107/* number of hw syncs before falling back on blocking */
108#define AMDGPU_NUM_SYNCS 4
109
110/* hardcode that limit for now */
111#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112
113/* hard reset data */
114#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
115
116/* reset flags */
117#define AMDGPU_RESET_GFX (1 << 0)
118#define AMDGPU_RESET_COMPUTE (1 << 1)
119#define AMDGPU_RESET_DMA (1 << 2)
120#define AMDGPU_RESET_CP (1 << 3)
121#define AMDGPU_RESET_GRBM (1 << 4)
122#define AMDGPU_RESET_DMA1 (1 << 5)
123#define AMDGPU_RESET_RLC (1 << 6)
124#define AMDGPU_RESET_SEM (1 << 7)
125#define AMDGPU_RESET_IH (1 << 8)
126#define AMDGPU_RESET_VMC (1 << 9)
127#define AMDGPU_RESET_MC (1 << 10)
128#define AMDGPU_RESET_DISPLAY (1 << 11)
129#define AMDGPU_RESET_UVD (1 << 12)
130#define AMDGPU_RESET_VCE (1 << 13)
131#define AMDGPU_RESET_VCE1 (1 << 14)
132
133/* CG block flags */
134#define AMDGPU_CG_BLOCK_GFX (1 << 0)
135#define AMDGPU_CG_BLOCK_MC (1 << 1)
136#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
137#define AMDGPU_CG_BLOCK_UVD (1 << 3)
138#define AMDGPU_CG_BLOCK_VCE (1 << 4)
139#define AMDGPU_CG_BLOCK_HDP (1 << 5)
140#define AMDGPU_CG_BLOCK_BIF (1 << 6)
141
142/* CG flags */
143#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
144#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
145#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
146#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
147#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
148#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
149#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
150#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
151#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
152#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
153#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
154#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
155#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
156#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
157#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
158#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
159#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
160
161/* PG flags */
162#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
163#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
164#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
165#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
166#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
167#define AMDGPU_PG_SUPPORT_CP (1 << 5)
168#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
169#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
170#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
171#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
172#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173
174/* GFX current status */
175#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
176#define AMDGPU_GFX_SAFE_MODE 0x00000001L
177#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
178#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
179#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180
181/* max cursor sizes (in pixels) */
182#define CIK_CURSOR_WIDTH 128
183#define CIK_CURSOR_HEIGHT 128
184
185struct amdgpu_device;
186struct amdgpu_fence;
187struct amdgpu_ib;
188struct amdgpu_vm;
189struct amdgpu_ring;
97b2e202 190struct amdgpu_cs_parser;
bb977d37 191struct amdgpu_job;
97b2e202 192struct amdgpu_irq_src;
0b492a4c 193struct amdgpu_fpriv;
97b2e202
AD		 194
195enum amdgpu_cp_irq {
196 AMDGPU_CP_IRQ_GFX_EOP = 0,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
205
206 AMDGPU_CP_IRQ_LAST
207};
208
209enum amdgpu_sdma_irq {
210 AMDGPU_SDMA_IRQ_TRAP0 = 0,
211 AMDGPU_SDMA_IRQ_TRAP1,
212
213 AMDGPU_SDMA_IRQ_LAST
214};
215
216enum amdgpu_thermal_irq {
217 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
218 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
219
220 AMDGPU_THERMAL_IRQ_LAST
221};
222
97b2e202 223int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_clockgating_state state);
97b2e202 226int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_powergating_state state);
97b2e202
AD		 229
230struct amdgpu_ip_block_version {
5fc3aeeb 231 enum amd_ip_block_type type;
97b2e202
AD		 232 u32 major;
233 u32 minor;
234 u32 rev;
5fc3aeeb 235 const struct amd_ip_funcs *funcs;
97b2e202
AD		 236};
237
238int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 239 enum amd_ip_block_type type,
97b2e202
AD		 240 u32 major, u32 minor);
241
242const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
243 struct amdgpu_device *adev,
5fc3aeeb 244 enum amd_ip_block_type type);
97b2e202
AD		 245
246/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
247struct amdgpu_buffer_funcs {
248 /* maximum bytes in a single operation */
249 uint32_t copy_max_bytes;
250
251 /* number of dw to reserve per operation */
252 unsigned copy_num_dw;
253
254 /* used for buffer migration */
c7ae72c0 255 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 256 /* src addr in bytes */
257 uint64_t src_offset,
258 /* dst addr in bytes */
259 uint64_t dst_offset,
260 /* number of byte to transfer */
261 uint32_t byte_count);
262
263 /* maximum bytes in a single operation */
264 uint32_t fill_max_bytes;
265
266 /* number of dw to reserve per operation */
267 unsigned fill_num_dw;
268
269 /* used for buffer clearing */
6e7a3840 270 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 271 /* value to write to memory */
272 uint32_t src_data,
273 /* dst addr in bytes */
274 uint64_t dst_offset,
275 /* number of byte to fill */
276 uint32_t byte_count);
277};
278
279/* provided by hw blocks that can write ptes, e.g., sdma */
280struct amdgpu_vm_pte_funcs {
281 /* copy pte entries from GART */
282 void (*copy_pte)(struct amdgpu_ib *ib,
283 uint64_t pe, uint64_t src,
284 unsigned count);
285 /* write pte one entry at a time with addr mapping */
286 void (*write_pte)(struct amdgpu_ib *ib,
287 uint64_t pe,
288 uint64_t addr, unsigned count,
289 uint32_t incr, uint32_t flags);
290 /* for linear pte/pde updates without addr mapping */
291 void (*set_pte_pde)(struct amdgpu_ib *ib,
292 uint64_t pe,
293 uint64_t addr, unsigned count,
294 uint32_t incr, uint32_t flags);
295 /* pad the indirect buffer to the necessary number of dw */
296 void (*pad_ib)(struct amdgpu_ib *ib);
297};
298
299/* provided by the gmc block */
300struct amdgpu_gart_funcs {
301 /* flush the vm tlb via mmio */
302 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
303 uint32_t vmid);
304 /* write pte/pde updates using the cpu */
305 int (*set_pte_pde)(struct amdgpu_device *adev,
306 void *cpu_pt_addr, /* cpu addr of page table */
307 uint32_t gpu_page_idx, /* pte/pde to update */
308 uint64_t addr, /* addr to write into pte/pde */
309 uint32_t flags); /* access flags */
310};
311
312/* provided by the ih block */
313struct amdgpu_ih_funcs {
314 /* ring read/write ptr handling, called from interrupt context */
315 u32 (*get_wptr)(struct amdgpu_device *adev);
316 void (*decode_iv)(struct amdgpu_device *adev,
317 struct amdgpu_iv_entry *entry);
318 void (*set_rptr)(struct amdgpu_device *adev);
319};
320
321/* provided by hw blocks that expose a ring buffer for commands */
322struct amdgpu_ring_funcs {
323 /* ring read/write ptr handling */
324 u32 (*get_rptr)(struct amdgpu_ring *ring);
325 u32 (*get_wptr)(struct amdgpu_ring *ring);
326 void (*set_wptr)(struct amdgpu_ring *ring);
327 /* validating and patching of IBs */
328 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
329 /* command emit functions */
330 void (*emit_ib)(struct amdgpu_ring *ring,
331 struct amdgpu_ib *ib);
332 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 333 uint64_t seq, unsigned flags);
97b2e202
AD		 334 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
335 uint64_t pd_addr);
d2edb07b 336 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 337 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
338 uint32_t gds_base, uint32_t gds_size,
339 uint32_t gws_base, uint32_t gws_size,
340 uint32_t oa_base, uint32_t oa_size);
341 /* testing functions */
342 int (*test_ring)(struct amdgpu_ring *ring);
343 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 344 /* insert NOP packets */
345 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 346};
347
348/*
349 * BIOS.
350 */
351bool amdgpu_get_bios(struct amdgpu_device *adev);
352bool amdgpu_read_bios(struct amdgpu_device *adev);
353
354/*
355 * Dummy page
356 */
357struct amdgpu_dummy_page {
358 struct page *page;
359 dma_addr_t addr;
360};
361int amdgpu_dummy_page_init(struct amdgpu_device *adev);
362void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
363
364
365/*
366 * Clocks
367 */
368
369#define AMDGPU_MAX_PPLL 3
370
371struct amdgpu_clock {
372 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
373 struct amdgpu_pll spll;
374 struct amdgpu_pll mpll;
375 /* 10 Khz units */
376 uint32_t default_mclk;
377 uint32_t default_sclk;
378 uint32_t default_dispclk;
379 uint32_t current_dispclk;
380 uint32_t dp_extclk;
381 uint32_t max_pixel_clock;
382};
383
384/*
385 * Fences.
386 */
387struct amdgpu_fence_driver {
97b2e202
AD		 388 uint64_t gpu_addr;
389 volatile uint32_t *cpu_addr;
390 /* sync_seq is protected by ring emission lock */
391 uint64_t sync_seq[AMDGPU_MAX_RINGS];
392 atomic64_t last_seq;
393 bool initialized;
97b2e202
AD		 394 struct amdgpu_irq_src *irq_src;
395 unsigned irq_type;
c2776afe 396 struct timer_list fallback_timer;
7f06c236 397 wait_queue_head_t fence_queue;
97b2e202
AD		 398};
399
400/* some special values for the owner field */
401#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
402#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 403
890ee23f
CZ		 404#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
405#define AMDGPU_FENCE_FLAG_INT (1 << 1)
406
97b2e202
AD		 407struct amdgpu_fence {
408 struct fence base;
4cef9267 409
97b2e202
AD		 410 /* RB, DMA, etc. */
411 struct amdgpu_ring *ring;
412 uint64_t seq;
413
414 /* filp or special value for fence creator */
415 void *owner;
416
417 wait_queue_t fence_wake;
418};
419
420struct amdgpu_user_fence {
421 /* write-back bo */
422 struct amdgpu_bo *bo;
423 /* write-back address offset to bo start */
424 uint32_t offset;
425};
426
427int amdgpu_fence_driver_init(struct amdgpu_device *adev);
428void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
429void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
430
4f839a24 431int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 432int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
433 struct amdgpu_irq_src *irq_src,
434 unsigned irq_type);
5ceb54c6
AD		 435void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
436void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 437int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
438 struct amdgpu_fence **fence);
439void amdgpu_fence_process(struct amdgpu_ring *ring);
440int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
441int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
442unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
443
97b2e202
AD		 444bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
445 struct amdgpu_ring *ring);
446void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
447 struct amdgpu_ring *ring);
448
97b2e202
AD		 449/*
450 * TTM.
451 */
452struct amdgpu_mman {
453 struct ttm_bo_global_ref bo_global_ref;
454 struct drm_global_reference mem_global_ref;
455 struct ttm_bo_device bdev;
456 bool mem_global_referenced;
457 bool initialized;
458
459#if defined(CONFIG_DEBUG_FS)
460 struct dentry *vram;
461 struct dentry *gtt;
462#endif
463
464 /* buffer handling */
465 const struct amdgpu_buffer_funcs *buffer_funcs;
466 struct amdgpu_ring *buffer_funcs_ring;
467};
468
469int amdgpu_copy_buffer(struct amdgpu_ring *ring,
470 uint64_t src_offset,
471 uint64_t dst_offset,
472 uint32_t byte_count,
473 struct reservation_object *resv,
c7ae72c0 474 struct fence **fence);
97b2e202
AD		 475int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
476
477struct amdgpu_bo_list_entry {
478 struct amdgpu_bo *robj;
479 struct ttm_validate_buffer tv;
480 struct amdgpu_bo_va *bo_va;
97b2e202
AD		 481 uint32_t priority;
482};
483
484struct amdgpu_bo_va_mapping {
485 struct list_head list;
486 struct interval_tree_node it;
487 uint64_t offset;
488 uint32_t flags;
489};
490
491/* bo virtual addresses in a specific vm */
492struct amdgpu_bo_va {
69b576a1 493 struct mutex mutex;
97b2e202
AD		 494 /* protected by bo being reserved */
495 struct list_head bo_list;
bb1e38a4 496 struct fence *last_pt_update;
97b2e202
AD		 497 unsigned ref_count;
498
7fc11959 499 /* protected by vm mutex and spinlock */
97b2e202
AD		 500 struct list_head vm_status;
501
7fc11959
CK		 502 /* mappings for this bo_va */
503 struct list_head invalids;
504 struct list_head valids;
505
97b2e202
AD		 506 /* constant after initialization */
507 struct amdgpu_vm *vm;
508 struct amdgpu_bo *bo;
509};
510
7e5a547f
CZ		 511#define AMDGPU_GEM_DOMAIN_MAX 0x3
512
97b2e202
AD		 513struct amdgpu_bo {
514 /* Protected by gem.mutex */
515 struct list_head list;
516 /* Protected by tbo.reserved */
1ea863fd
CK		 517 u32 prefered_domains;
518 u32 allowed_domains;
7e5a547f 519 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 520 struct ttm_placement placement;
521 struct ttm_buffer_object tbo;
522 struct ttm_bo_kmap_obj kmap;
523 u64 flags;
524 unsigned pin_count;
525 void *kptr;
526 u64 tiling_flags;
527 u64 metadata_flags;
528 void *metadata;
529 u32 metadata_size;
530 /* list of all virtual address to which this bo
531 * is associated to
532 */
533 struct list_head va;
534 /* Constant after initialization */
535 struct amdgpu_device *adev;
536 struct drm_gem_object gem_base;
82b9c55b 537 struct amdgpu_bo *parent;
97b2e202
AD		 538
539 struct ttm_bo_kmap_obj dma_buf_vmap;
540 pid_t pid;
541 struct amdgpu_mn *mn;
542 struct list_head mn_list;
543};
544#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
545
546void amdgpu_gem_object_free(struct drm_gem_object *obj);
547int amdgpu_gem_object_open(struct drm_gem_object *obj,
548 struct drm_file *file_priv);
549void amdgpu_gem_object_close(struct drm_gem_object *obj,
550 struct drm_file *file_priv);
551unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
552struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
553struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
554 struct dma_buf_attachment *attach,
555 struct sg_table *sg);
556struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
557 struct drm_gem_object *gobj,
558 int flags);
559int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
560void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
561struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
562void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
563void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
564int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
565
566/* sub-allocation manager, it has to be protected by another lock.
567 * By conception this is an helper for other part of the driver
568 * like the indirect buffer or semaphore, which both have their
569 * locking.
570 *
571 * Principe is simple, we keep a list of sub allocation in offset
572 * order (first entry has offset == 0, last entry has the highest
573 * offset).
574 *
575 * When allocating new object we first check if there is room at
576 * the end total_size - (last_object_offset + last_object_size) >=
577 * alloc_size. If so we allocate new object there.
578 *
579 * When there is not enough room at the end, we start waiting for
580 * each sub object until we reach object_offset+object_size >=
581 * alloc_size, this object then become the sub object we return.
582 *
583 * Alignment can't be bigger than page size.
584 *
585 * Hole are not considered for allocation to keep things simple.
586 * Assumption is that there won't be hole (all object on same
587 * alignment).
588 */
589struct amdgpu_sa_manager {
590 wait_queue_head_t wq;
591 struct amdgpu_bo *bo;
592 struct list_head *hole;
593 struct list_head flist[AMDGPU_MAX_RINGS];
594 struct list_head olist;
595 unsigned size;
596 uint64_t gpu_addr;
597 void *cpu_ptr;
598 uint32_t domain;
599 uint32_t align;
600};
601
602struct amdgpu_sa_bo;
603
604/* sub-allocation buffer */
605struct amdgpu_sa_bo {
606 struct list_head olist;
607 struct list_head flist;
608 struct amdgpu_sa_manager *manager;
609 unsigned soffset;
610 unsigned eoffset;
4ce9891e 611 struct fence *fence;
97b2e202
AD		 612};
613
614/*
615 * GEM objects.
616 */
617struct amdgpu_gem {
618 struct mutex mutex;
619 struct list_head objects;
620};
621
622int amdgpu_gem_init(struct amdgpu_device *adev);
623void amdgpu_gem_fini(struct amdgpu_device *adev);
624int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
625 int alignment, u32 initial_domain,
626 u64 flags, bool kernel,
627 struct drm_gem_object **obj);
628
629int amdgpu_mode_dumb_create(struct drm_file *file_priv,
630 struct drm_device *dev,
631 struct drm_mode_create_dumb *args);
632int amdgpu_mode_dumb_mmap(struct drm_file *filp,
633 struct drm_device *dev,
634 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 635/*
636 * Synchronization
637 */
638struct amdgpu_sync {
f91b3a69 639 DECLARE_HASHTABLE(fences, 4);
3c62338c 640 struct fence *last_vm_update;
97b2e202
AD		 641};
642
643void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 644int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
645 struct fence *f);
97b2e202
AD		 646int amdgpu_sync_resv(struct amdgpu_device *adev,
647 struct amdgpu_sync *sync,
648 struct reservation_object *resv,
649 void *owner);
e61235db 650struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 651int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 652void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 653 struct fence *fence);
97b2e202
AD		 654
655/*
656 * GART structures, functions & helpers
657 */
658struct amdgpu_mc;
659
660#define AMDGPU_GPU_PAGE_SIZE 4096
661#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
662#define AMDGPU_GPU_PAGE_SHIFT 12
663#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
664
665struct amdgpu_gart {
666 dma_addr_t table_addr;
667 struct amdgpu_bo *robj;
668 void *ptr;
669 unsigned num_gpu_pages;
670 unsigned num_cpu_pages;
671 unsigned table_size;
672 struct page **pages;
673 dma_addr_t *pages_addr;
674 bool ready;
675 const struct amdgpu_gart_funcs *gart_funcs;
676};
677
678int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
679void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
680int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
681void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
682int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
683void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
684int amdgpu_gart_init(struct amdgpu_device *adev);
685void amdgpu_gart_fini(struct amdgpu_device *adev);
686void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
687 int pages);
688int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
689 int pages, struct page **pagelist,
690 dma_addr_t *dma_addr, uint32_t flags);
691
692/*
693 * GPU MC structures, functions & helpers
694 */
695struct amdgpu_mc {
696 resource_size_t aper_size;
697 resource_size_t aper_base;
698 resource_size_t agp_base;
699 /* for some chips with <= 32MB we need to lie
700 * about vram size near mc fb location */
701 u64 mc_vram_size;
702 u64 visible_vram_size;
703 u64 gtt_size;
704 u64 gtt_start;
705 u64 gtt_end;
706 u64 vram_start;
707 u64 vram_end;
708 unsigned vram_width;
709 u64 real_vram_size;
710 int vram_mtrr;
711 u64 gtt_base_align;
712 u64 mc_mask;
713 const struct firmware *fw; /* MC firmware */
714 uint32_t fw_version;
715 struct amdgpu_irq_src vm_fault;
81c59f54 716 uint32_t vram_type;
97b2e202
AD		 717};
718
719/*
720 * GPU doorbell structures, functions & helpers
721 */
722typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
723{
724 AMDGPU_DOORBELL_KIQ = 0x000,
725 AMDGPU_DOORBELL_HIQ = 0x001,
726 AMDGPU_DOORBELL_DIQ = 0x002,
727 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
728 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
729 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
730 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
731 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
732 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
733 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
734 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
735 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
736 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
737 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
738 AMDGPU_DOORBELL_IH = 0x1E8,
739 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
740 AMDGPU_DOORBELL_INVALID = 0xFFFF
741} AMDGPU_DOORBELL_ASSIGNMENT;
742
743struct amdgpu_doorbell {
744 /* doorbell mmio */
745 resource_size_t base;
746 resource_size_t size;
747 u32 __iomem *ptr;
748 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
749};
750
751void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
752 phys_addr_t *aperture_base,
753 size_t *aperture_size,
754 size_t *start_offset);
755
756/*
757 * IRQS.
758 */
759
760struct amdgpu_flip_work {
761 struct work_struct flip_work;
762 struct work_struct unpin_work;
763 struct amdgpu_device *adev;
764 int crtc_id;
765 uint64_t base;
766 struct drm_pending_vblank_event *event;
767 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 768 struct fence *excl;
769 unsigned shared_count;
770 struct fence **shared;
97b2e202
AD		 771};
772
773
774/*
775 * CP & rings.
776 */
777
778struct amdgpu_ib {
779 struct amdgpu_sa_bo *sa_bo;
780 uint32_t length_dw;
781 uint64_t gpu_addr;
782 uint32_t *ptr;
783 struct amdgpu_ring *ring;
784 struct amdgpu_fence *fence;
785 struct amdgpu_user_fence *user;
786 struct amdgpu_vm *vm;
3cb485f3 787 struct amdgpu_ctx *ctx;
97b2e202 788 struct amdgpu_sync sync;
97b2e202
AD		 789 uint32_t gds_base, gds_size;
790 uint32_t gws_base, gws_size;
791 uint32_t oa_base, oa_size;
de807f81 792 uint32_t flags;
5430a3ff
CK		 793 /* resulting sequence number */
794 uint64_t sequence;
97b2e202
AD		 795};
796
797enum amdgpu_ring_type {
798 AMDGPU_RING_TYPE_GFX,
799 AMDGPU_RING_TYPE_COMPUTE,
800 AMDGPU_RING_TYPE_SDMA,
801 AMDGPU_RING_TYPE_UVD,
802 AMDGPU_RING_TYPE_VCE
803};
804
c1b69ed0
CZ		 805extern struct amd_sched_backend_ops amdgpu_sched_ops;
806
3c704e93
CZ		 807int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
808 struct amdgpu_ring *ring,
809 struct amdgpu_ib *ibs,
810 unsigned num_ibs,
bb977d37 811 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 812 void *owner,
813 struct fence **fence);
3c704e93 814
97b2e202
AD		 815struct amdgpu_ring {
816 struct amdgpu_device *adev;
817 const struct amdgpu_ring_funcs *funcs;
818 struct amdgpu_fence_driver fence_drv;
4f839a24 819 struct amd_gpu_scheduler sched;
97b2e202 820
176e1ab1 821 spinlock_t fence_lock;
97b2e202
AD		 822 struct mutex *ring_lock;
823 struct amdgpu_bo *ring_obj;
824 volatile uint32_t *ring;
825 unsigned rptr_offs;
826 u64 next_rptr_gpu_addr;
827 volatile u32 *next_rptr_cpu_addr;
828 unsigned wptr;
829 unsigned wptr_old;
830 unsigned ring_size;
831 unsigned ring_free_dw;
832 int count_dw;
97b2e202
AD		 833 uint64_t gpu_addr;
834 uint32_t align_mask;
835 uint32_t ptr_mask;
836 bool ready;
837 u32 nop;
838 u32 idx;
97b2e202
AD		 839 u32 me;
840 u32 pipe;
841 u32 queue;
842 struct amdgpu_bo *mqd_obj;
843 u32 doorbell_index;
844 bool use_doorbell;
845 unsigned wptr_offs;
846 unsigned next_rptr_offs;
847 unsigned fence_offs;
3cb485f3 848 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 849 enum amdgpu_ring_type type;
850 char name[16];
4274f5d4 851 bool is_pte_ring;
97b2e202
AD		 852};
853
854/*
855 * VM
856 */
857
858/* maximum number of VMIDs */
859#define AMDGPU_NUM_VM 16
860
861/* number of entries in page table */
862#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
863
864/* PTBs (Page Table Blocks) need to be aligned to 32K */
865#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
866#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
867#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
868
869#define AMDGPU_PTE_VALID (1 << 0)
870#define AMDGPU_PTE_SYSTEM (1 << 1)
871#define AMDGPU_PTE_SNOOPED (1 << 2)
872
873/* VI only */
874#define AMDGPU_PTE_EXECUTABLE (1 << 4)
875
876#define AMDGPU_PTE_READABLE (1 << 5)
877#define AMDGPU_PTE_WRITEABLE (1 << 6)
878
879/* PTE (Page Table Entry) fragment field for different page sizes */
880#define AMDGPU_PTE_FRAG_4KB (0 << 7)
881#define AMDGPU_PTE_FRAG_64KB (4 << 7)
882#define AMDGPU_LOG2_PAGES_PER_FRAG 4
883
d9c13156
CK		 884/* How to programm VM fault handling */
885#define AMDGPU_VM_FAULT_STOP_NEVER 0
886#define AMDGPU_VM_FAULT_STOP_FIRST 1
887#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
888
97b2e202 889struct amdgpu_vm_pt {
ee1782c3
CK		 890 struct amdgpu_bo_list_entry entry;
891 uint64_t addr;
97b2e202
AD		 892};
893
894struct amdgpu_vm_id {
895 unsigned id;
896 uint64_t pd_gpu_addr;
897 /* last flushed PD/PT update */
3c62338c 898 struct fence *flushed_updates;
97b2e202
AD		 899};
900
901struct amdgpu_vm {
25cfc3c2
CK		 902 /* tree of virtual addresses mapped */
903 spinlock_t it_lock;
97b2e202
AD		 904 struct rb_root va;
905
7fc11959 906 /* protecting invalidated */
97b2e202
AD		 907 spinlock_t status_lock;
908
909 /* BOs moved, but not yet updated in the PT */
910 struct list_head invalidated;
911
7fc11959
CK		 912 /* BOs cleared in the PT because of a move */
913 struct list_head cleared;
914
915 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 916 struct list_head freed;
917
918 /* contains the page directory */
919 struct amdgpu_bo *page_directory;
920 unsigned max_pde_used;
05906dec 921 struct fence *page_directory_fence;
97b2e202
AD		 922
923 /* array of page tables, one for each page directory entry */
924 struct amdgpu_vm_pt *page_tables;
925
926 /* for id and flush management per ring */
927 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 928
81d75a30 929 /* protecting freed */
930 spinlock_t freed_lock;
97b2e202
AD		 931};
932
933struct amdgpu_vm_manager {
1c16c0a7
CK		 934 struct {
935 struct fence *active;
936 atomic_long_t owner;
937 } ids[AMDGPU_NUM_VM];
938
8b4fb00b 939 uint32_t max_pfn;
97b2e202 940 /* number of VMIDs */
8b4fb00b 941 unsigned nvm;
97b2e202 942 /* vram base address for page table entry */
8b4fb00b 943 u64 vram_base_offset;
97b2e202 944 /* is vm enabled? */
8b4fb00b 945 bool enabled;
97b2e202
AD		 946 /* vm pte handling */
947 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
948 struct amdgpu_ring *vm_pte_funcs_ring;
949};
950
ea89f8c9 951void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 952int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
953void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 954void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
955 struct list_head *validated,
956 struct amdgpu_bo_list_entry *entry);
ee1782c3 957void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 958void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm);
8b4fb00b
CK		 960int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
961 struct amdgpu_sync *sync);
962void amdgpu_vm_flush(struct amdgpu_ring *ring,
963 struct amdgpu_vm *vm,
964 struct fence *updates);
965void amdgpu_vm_fence(struct amdgpu_device *adev,
966 struct amdgpu_vm *vm,
967 struct fence *fence);
968uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
969int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
970 struct amdgpu_vm *vm);
971int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
972 struct amdgpu_vm *vm);
973int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
974 struct amdgpu_sync *sync);
975int amdgpu_vm_bo_update(struct amdgpu_device *adev,
976 struct amdgpu_bo_va *bo_va,
977 struct ttm_mem_reg *mem);
978void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
979 struct amdgpu_bo *bo);
980struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
981 struct amdgpu_bo *bo);
982struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
983 struct amdgpu_vm *vm,
984 struct amdgpu_bo *bo);
985int amdgpu_vm_bo_map(struct amdgpu_device *adev,
986 struct amdgpu_bo_va *bo_va,
987 uint64_t addr, uint64_t offset,
988 uint64_t size, uint32_t flags);
989int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
990 struct amdgpu_bo_va *bo_va,
991 uint64_t addr);
992void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
993 struct amdgpu_bo_va *bo_va);
994int amdgpu_vm_free_job(struct amdgpu_job *job);
995
97b2e202
AD		 996/*
997 * context related structures
998 */
999
21c16bf6 1000struct amdgpu_ctx_ring {
91404fb2 1001 uint64_t sequence;
37cd0ca2 1002 struct fence **fences;
91404fb2 1003 struct amd_sched_entity entity;
21c16bf6
CK		 1004};
1005
97b2e202 1006struct amdgpu_ctx {
0b492a4c 1007 struct kref refcount;
9cb7e5a9 1008 struct amdgpu_device *adev;
0b492a4c 1009 unsigned reset_counter;
21c16bf6 1010 spinlock_t ring_lock;
37cd0ca2 1011 struct fence **fences;
21c16bf6 1012 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1013};
1014
1015struct amdgpu_ctx_mgr {
0b492a4c
AD		 1016 struct amdgpu_device *adev;
1017 struct mutex lock;
1018 /* protected by lock */
1019 struct idr ctx_handles;
97b2e202
AD		 1020};
1021
d033a6de 1022int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
47f38501
CK		 1023 struct amdgpu_ctx *ctx);
1024void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1025
0b492a4c
AD		 1026struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1027int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1028
21c16bf6 1029uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1030 struct fence *fence);
21c16bf6
CK		 1031struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1032 struct amdgpu_ring *ring, uint64_t seq);
1033
0b492a4c
AD		 1034int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1035 struct drm_file *filp);
1036
efd4ccb5
CK		 1037void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1038void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1039
97b2e202
AD		 1040/*
1041 * file private structure
1042 */
1043
1044struct amdgpu_fpriv {
1045 struct amdgpu_vm vm;
1046 struct mutex bo_list_lock;
1047 struct idr bo_list_handles;
0b492a4c 1048 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1049};
1050
1051/*
1052 * residency list
1053 */
1054
1055struct amdgpu_bo_list {
1056 struct mutex lock;
1057 struct amdgpu_bo *gds_obj;
1058 struct amdgpu_bo *gws_obj;
1059 struct amdgpu_bo *oa_obj;
1060 bool has_userptr;
1061 unsigned num_entries;
1062 struct amdgpu_bo_list_entry *array;
1063};
1064
1065struct amdgpu_bo_list *
1066amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1067void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1068 struct list_head *validated);
97b2e202
AD		 1069void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1070void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1071
1072/*
1073 * GFX stuff
1074 */
1075#include "clearstate_defs.h"
1076
1077struct amdgpu_rlc {
1078 /* for power gating */
1079 struct amdgpu_bo *save_restore_obj;
1080 uint64_t save_restore_gpu_addr;
1081 volatile uint32_t *sr_ptr;
1082 const u32 *reg_list;
1083 u32 reg_list_size;
1084 /* for clear state */
1085 struct amdgpu_bo *clear_state_obj;
1086 uint64_t clear_state_gpu_addr;
1087 volatile uint32_t *cs_ptr;
1088 const struct cs_section_def *cs_data;
1089 u32 clear_state_size;
1090 /* for cp tables */
1091 struct amdgpu_bo *cp_table_obj;
1092 uint64_t cp_table_gpu_addr;
1093 volatile uint32_t *cp_table_ptr;
1094 u32 cp_table_size;
1095};
1096
1097struct amdgpu_mec {
1098 struct amdgpu_bo *hpd_eop_obj;
1099 u64 hpd_eop_gpu_addr;
1100 u32 num_pipe;
1101 u32 num_mec;
1102 u32 num_queue;
1103};
1104
1105/*
1106 * GPU scratch registers structures, functions & helpers
1107 */
1108struct amdgpu_scratch {
1109 unsigned num_reg;
1110 uint32_t reg_base;
1111 bool free[32];
1112 uint32_t reg[32];
1113};
1114
1115/*
1116 * GFX configurations
1117 */
1118struct amdgpu_gca_config {
1119 unsigned max_shader_engines;
1120 unsigned max_tile_pipes;
1121 unsigned max_cu_per_sh;
1122 unsigned max_sh_per_se;
1123 unsigned max_backends_per_se;
1124 unsigned max_texture_channel_caches;
1125 unsigned max_gprs;
1126 unsigned max_gs_threads;
1127 unsigned max_hw_contexts;
1128 unsigned sc_prim_fifo_size_frontend;
1129 unsigned sc_prim_fifo_size_backend;
1130 unsigned sc_hiz_tile_fifo_size;
1131 unsigned sc_earlyz_tile_fifo_size;
1132
1133 unsigned num_tile_pipes;
1134 unsigned backend_enable_mask;
1135 unsigned mem_max_burst_length_bytes;
1136 unsigned mem_row_size_in_kb;
1137 unsigned shader_engine_tile_size;
1138 unsigned num_gpus;
1139 unsigned multi_gpu_tile_size;
1140 unsigned mc_arb_ramcfg;
1141 unsigned gb_addr_config;
1142
1143 uint32_t tile_mode_array[32];
1144 uint32_t macrotile_mode_array[16];
1145};
1146
1147struct amdgpu_gfx {
1148 struct mutex gpu_clock_mutex;
1149 struct amdgpu_gca_config config;
1150 struct amdgpu_rlc rlc;
1151 struct amdgpu_mec mec;
1152 struct amdgpu_scratch scratch;
1153 const struct firmware *me_fw; /* ME firmware */
1154 uint32_t me_fw_version;
1155 const struct firmware *pfp_fw; /* PFP firmware */
1156 uint32_t pfp_fw_version;
1157 const struct firmware *ce_fw; /* CE firmware */
1158 uint32_t ce_fw_version;
1159 const struct firmware *rlc_fw; /* RLC firmware */
1160 uint32_t rlc_fw_version;
1161 const struct firmware *mec_fw; /* MEC firmware */
1162 uint32_t mec_fw_version;
1163 const struct firmware *mec2_fw; /* MEC2 firmware */
1164 uint32_t mec2_fw_version;
02558a00
KW		 1165 uint32_t me_feature_version;
1166 uint32_t ce_feature_version;
1167 uint32_t pfp_feature_version;
351643d7
JZ		 1168 uint32_t rlc_feature_version;
1169 uint32_t mec_feature_version;
1170 uint32_t mec2_feature_version;
97b2e202
AD		 1171 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1172 unsigned num_gfx_rings;
1173 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1174 unsigned num_compute_rings;
1175 struct amdgpu_irq_src eop_irq;
1176 struct amdgpu_irq_src priv_reg_irq;
1177 struct amdgpu_irq_src priv_inst_irq;
1178 /* gfx status */
1179 uint32_t gfx_current_status;
a101a899
KW		 1180 /* ce ram size*/
1181 unsigned ce_ram_size;
97b2e202
AD		 1182};
1183
1184int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1185 unsigned size, struct amdgpu_ib *ib);
1186void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1187int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1188 struct amdgpu_ib *ib, void *owner);
1189int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1190void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1191int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1192/* Ring access between begin & end cannot sleep */
1193void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1194int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1195int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1196void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 1197void amdgpu_ring_commit(struct amdgpu_ring *ring);
1198void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1199void amdgpu_ring_undo(struct amdgpu_ring *ring);
1200void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1201unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1202 uint32_t **data);
1203int amdgpu_ring_restore(struct amdgpu_ring *ring,
1204 unsigned size, uint32_t *data);
1205int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1206 unsigned ring_size, u32 nop, u32 align_mask,
1207 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1208 enum amdgpu_ring_type ring_type);
1209void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1210struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1211
1212/*
1213 * CS.
1214 */
1215struct amdgpu_cs_chunk {
1216 uint32_t chunk_id;
1217 uint32_t length_dw;
1218 uint32_t *kdata;
97b2e202
AD		 1219};
1220
1221struct amdgpu_cs_parser {
1222 struct amdgpu_device *adev;
1223 struct drm_file *filp;
3cb485f3 1224 struct amdgpu_ctx *ctx;
c3cca41e 1225
97b2e202
AD		 1226 /* chunks */
1227 unsigned nchunks;
1228 struct amdgpu_cs_chunk *chunks;
97b2e202 1229
c3cca41e 1230 /* indirect buffers */
97b2e202 1231 uint32_t num_ibs;
c3cca41e 1232 struct amdgpu_ib *ibs;
97b2e202 1233
c3cca41e
CK		 1234 /* buffer objects */
1235 struct ww_acquire_ctx ticket;
1236 struct amdgpu_bo_list *bo_list;
1237 struct amdgpu_bo_list_entry vm_pd;
1238 struct list_head validated;
1239 struct fence *fence;
1240 uint64_t bytes_moved_threshold;
1241 uint64_t bytes_moved;
97b2e202
AD		 1242
1243 /* user fence */
91acbeb6
CK		 1244 struct amdgpu_user_fence uf;
1245 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1246};
1247
bb977d37
CZ		 1248struct amdgpu_job {
1249 struct amd_sched_job base;
1250 struct amdgpu_device *adev;
bb977d37
CZ		 1251 struct amdgpu_ib *ibs;
1252 uint32_t num_ibs;
e2840221 1253 void *owner;
bb977d37 1254 struct amdgpu_user_fence uf;
4c7eb91c 1255 int (*free_job)(struct amdgpu_job *job);
bb977d37 1256};
a6db8a33
JZ		 1257#define to_amdgpu_job(sched_job) \
1258 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1259
97b2e202
AD		 1260static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1261{
1262 return p->ibs[ib_idx].ptr[idx];
1263}
1264
1265/*
1266 * Writeback
1267 */
1268#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1269
1270struct amdgpu_wb {
1271 struct amdgpu_bo *wb_obj;
1272 volatile uint32_t *wb;
1273 uint64_t gpu_addr;
1274 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1275 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1276};
1277
1278int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1279void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1280
97b2e202 1281
97b2e202
AD		 1282
1283enum amdgpu_int_thermal_type {
1284 THERMAL_TYPE_NONE,
1285 THERMAL_TYPE_EXTERNAL,
1286 THERMAL_TYPE_EXTERNAL_GPIO,
1287 THERMAL_TYPE_RV6XX,
1288 THERMAL_TYPE_RV770,
1289 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1290 THERMAL_TYPE_EVERGREEN,
1291 THERMAL_TYPE_SUMO,
1292 THERMAL_TYPE_NI,
1293 THERMAL_TYPE_SI,
1294 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1295 THERMAL_TYPE_CI,
1296 THERMAL_TYPE_KV,
1297};
1298
1299enum amdgpu_dpm_auto_throttle_src {
1300 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1301 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1302};
1303
1304enum amdgpu_dpm_event_src {
1305 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1306 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1307 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1308 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1309 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1310};
1311
1312#define AMDGPU_MAX_VCE_LEVELS 6
1313
1314enum amdgpu_vce_level {
1315 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1316 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1317 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1318 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1319 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1320 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1321};
1322
1323struct amdgpu_ps {
1324 u32 caps; /* vbios flags */
1325 u32 class; /* vbios flags */
1326 u32 class2; /* vbios flags */
1327 /* UVD clocks */
1328 u32 vclk;
1329 u32 dclk;
1330 /* VCE clocks */
1331 u32 evclk;
1332 u32 ecclk;
1333 bool vce_active;
1334 enum amdgpu_vce_level vce_level;
1335 /* asic priv */
1336 void *ps_priv;
1337};
1338
1339struct amdgpu_dpm_thermal {
1340 /* thermal interrupt work */
1341 struct work_struct work;
1342 /* low temperature threshold */
1343 int min_temp;
1344 /* high temperature threshold */
1345 int max_temp;
1346 /* was last interrupt low to high or high to low */
1347 bool high_to_low;
1348 /* interrupt source */
1349 struct amdgpu_irq_src irq;
1350};
1351
1352enum amdgpu_clk_action
1353{
1354 AMDGPU_SCLK_UP = 1,
1355 AMDGPU_SCLK_DOWN
1356};
1357
1358struct amdgpu_blacklist_clocks
1359{
1360 u32 sclk;
1361 u32 mclk;
1362 enum amdgpu_clk_action action;
1363};
1364
1365struct amdgpu_clock_and_voltage_limits {
1366 u32 sclk;
1367 u32 mclk;
1368 u16 vddc;
1369 u16 vddci;
1370};
1371
1372struct amdgpu_clock_array {
1373 u32 count;
1374 u32 *values;
1375};
1376
1377struct amdgpu_clock_voltage_dependency_entry {
1378 u32 clk;
1379 u16 v;
1380};
1381
1382struct amdgpu_clock_voltage_dependency_table {
1383 u32 count;
1384 struct amdgpu_clock_voltage_dependency_entry *entries;
1385};
1386
1387union amdgpu_cac_leakage_entry {
1388 struct {
1389 u16 vddc;
1390 u32 leakage;
1391 };
1392 struct {
1393 u16 vddc1;
1394 u16 vddc2;
1395 u16 vddc3;
1396 };
1397};
1398
1399struct amdgpu_cac_leakage_table {
1400 u32 count;
1401 union amdgpu_cac_leakage_entry *entries;
1402};
1403
1404struct amdgpu_phase_shedding_limits_entry {
1405 u16 voltage;
1406 u32 sclk;
1407 u32 mclk;
1408};
1409
1410struct amdgpu_phase_shedding_limits_table {
1411 u32 count;
1412 struct amdgpu_phase_shedding_limits_entry *entries;
1413};
1414
1415struct amdgpu_uvd_clock_voltage_dependency_entry {
1416 u32 vclk;
1417 u32 dclk;
1418 u16 v;
1419};
1420
1421struct amdgpu_uvd_clock_voltage_dependency_table {
1422 u8 count;
1423 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1424};
1425
1426struct amdgpu_vce_clock_voltage_dependency_entry {
1427 u32 ecclk;
1428 u32 evclk;
1429 u16 v;
1430};
1431
1432struct amdgpu_vce_clock_voltage_dependency_table {
1433 u8 count;
1434 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1435};
1436
1437struct amdgpu_ppm_table {
1438 u8 ppm_design;
1439 u16 cpu_core_number;
1440 u32 platform_tdp;
1441 u32 small_ac_platform_tdp;
1442 u32 platform_tdc;
1443 u32 small_ac_platform_tdc;
1444 u32 apu_tdp;
1445 u32 dgpu_tdp;
1446 u32 dgpu_ulv_power;
1447 u32 tj_max;
1448};
1449
1450struct amdgpu_cac_tdp_table {
1451 u16 tdp;
1452 u16 configurable_tdp;
1453 u16 tdc;
1454 u16 battery_power_limit;
1455 u16 small_power_limit;
1456 u16 low_cac_leakage;
1457 u16 high_cac_leakage;
1458 u16 maximum_power_delivery_limit;
1459};
1460
1461struct amdgpu_dpm_dynamic_state {
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1463 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1465 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1466 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1467 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1468 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1470 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1471 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1472 struct amdgpu_clock_array valid_sclk_values;
1473 struct amdgpu_clock_array valid_mclk_values;
1474 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1475 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1476 u32 mclk_sclk_ratio;
1477 u32 sclk_mclk_delta;
1478 u16 vddc_vddci_delta;
1479 u16 min_vddc_for_pcie_gen2;
1480 struct amdgpu_cac_leakage_table cac_leakage_table;
1481 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1482 struct amdgpu_ppm_table *ppm_table;
1483 struct amdgpu_cac_tdp_table *cac_tdp_table;
1484};
1485
1486struct amdgpu_dpm_fan {
1487 u16 t_min;
1488 u16 t_med;
1489 u16 t_high;
1490 u16 pwm_min;
1491 u16 pwm_med;
1492 u16 pwm_high;
1493 u8 t_hyst;
1494 u32 cycle_delay;
1495 u16 t_max;
1496 u8 control_mode;
1497 u16 default_max_fan_pwm;
1498 u16 default_fan_output_sensitivity;
1499 u16 fan_output_sensitivity;
1500 bool ucode_fan_control;
1501};
1502
1503enum amdgpu_pcie_gen {
1504 AMDGPU_PCIE_GEN1 = 0,
1505 AMDGPU_PCIE_GEN2 = 1,
1506 AMDGPU_PCIE_GEN3 = 2,
1507 AMDGPU_PCIE_GEN_INVALID = 0xffff
1508};
1509
1510enum amdgpu_dpm_forced_level {
1511 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1512 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1513 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1514};
1515
1516struct amdgpu_vce_state {
1517 /* vce clocks */
1518 u32 evclk;
1519 u32 ecclk;
1520 /* gpu clocks */
1521 u32 sclk;
1522 u32 mclk;
1523 u8 clk_idx;
1524 u8 pstate;
1525};
1526
1527struct amdgpu_dpm_funcs {
1528 int (*get_temperature)(struct amdgpu_device *adev);
1529 int (*pre_set_power_state)(struct amdgpu_device *adev);
1530 int (*set_power_state)(struct amdgpu_device *adev);
1531 void (*post_set_power_state)(struct amdgpu_device *adev);
1532 void (*display_configuration_changed)(struct amdgpu_device *adev);
1533 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1534 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1535 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1536 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1537 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1538 bool (*vblank_too_short)(struct amdgpu_device *adev);
1539 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1540 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1541 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1542 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1543 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1544 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1545 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1546};
1547
1548struct amdgpu_dpm {
1549 struct amdgpu_ps *ps;
1550 /* number of valid power states */
1551 int num_ps;
1552 /* current power state that is active */
1553 struct amdgpu_ps *current_ps;
1554 /* requested power state */
1555 struct amdgpu_ps *requested_ps;
1556 /* boot up power state */
1557 struct amdgpu_ps *boot_ps;
1558 /* default uvd power state */
1559 struct amdgpu_ps *uvd_ps;
1560 /* vce requirements */
1561 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1562 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1563 enum amd_pm_state_type state;
1564 enum amd_pm_state_type user_state;
97b2e202
AD		 1565 u32 platform_caps;
1566 u32 voltage_response_time;
1567 u32 backbias_response_time;
1568 void *priv;
1569 u32 new_active_crtcs;
1570 int new_active_crtc_count;
1571 u32 current_active_crtcs;
1572 int current_active_crtc_count;
1573 struct amdgpu_dpm_dynamic_state dyn_state;
1574 struct amdgpu_dpm_fan fan;
1575 u32 tdp_limit;
1576 u32 near_tdp_limit;
1577 u32 near_tdp_limit_adjusted;
1578 u32 sq_ramping_threshold;
1579 u32 cac_leakage;
1580 u16 tdp_od_limit;
1581 u32 tdp_adjustment;
1582 u16 load_line_slope;
1583 bool power_control;
1584 bool ac_power;
1585 /* special states active */
1586 bool thermal_active;
1587 bool uvd_active;
1588 bool vce_active;
1589 /* thermal handling */
1590 struct amdgpu_dpm_thermal thermal;
1591 /* forced levels */
1592 enum amdgpu_dpm_forced_level forced_level;
1593};
1594
1595struct amdgpu_pm {
1596 struct mutex mutex;
97b2e202
AD		 1597 u32 current_sclk;
1598 u32 current_mclk;
1599 u32 default_sclk;
1600 u32 default_mclk;
1601 struct amdgpu_i2c_chan *i2c_bus;
1602 /* internal thermal controller on rv6xx+ */
1603 enum amdgpu_int_thermal_type int_thermal_type;
1604 struct device *int_hwmon_dev;
1605 /* fan control parameters */
1606 bool no_fan;
1607 u8 fan_pulses_per_revolution;
1608 u8 fan_min_rpm;
1609 u8 fan_max_rpm;
1610 /* dpm */
1611 bool dpm_enabled;
c86f5ebf 1612 bool sysfs_initialized;
97b2e202
AD		 1613 struct amdgpu_dpm dpm;
1614 const struct firmware *fw; /* SMC firmware */
1615 uint32_t fw_version;
1616 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1617 uint32_t pcie_gen_mask;
1618 uint32_t pcie_mlw_mask;
7fb72a1f 1619 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1620};
1621
d0dd7f0c
AD		 1622void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1623
97b2e202
AD		 1624/*
1625 * UVD
1626 */
1627#define AMDGPU_MAX_UVD_HANDLES 10
1628#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1629#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1630#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1631
1632struct amdgpu_uvd {
1633 struct amdgpu_bo *vcpu_bo;
1634 void *cpu_addr;
1635 uint64_t gpu_addr;
97b2e202
AD		 1636 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1637 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1638 struct delayed_work idle_work;
1639 const struct firmware *fw; /* UVD firmware */
1640 struct amdgpu_ring ring;
1641 struct amdgpu_irq_src irq;
1642 bool address_64_bit;
1643};
1644
1645/*
1646 * VCE
1647 */
1648#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1649#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1650
6a585777
AD		 1651#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1652#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1653
97b2e202
AD		 1654struct amdgpu_vce {
1655 struct amdgpu_bo *vcpu_bo;
1656 uint64_t gpu_addr;
1657 unsigned fw_version;
1658 unsigned fb_version;
1659 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1660 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1661 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1662 struct delayed_work idle_work;
1663 const struct firmware *fw; /* VCE firmware */
1664 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1665 struct amdgpu_irq_src irq;
6a585777 1666 unsigned harvest_config;
97b2e202
AD		 1667};
1668
1669/*
1670 * SDMA
1671 */
c113ea1c 1672struct amdgpu_sdma_instance {
97b2e202
AD		 1673 /* SDMA firmware */
1674 const struct firmware *fw;
1675 uint32_t fw_version;
cfa2104f 1676 uint32_t feature_version;
97b2e202
AD		 1677
1678 struct amdgpu_ring ring;
18111de0 1679 bool burst_nop;
97b2e202
AD		 1680};
1681
c113ea1c
AD		 1682struct amdgpu_sdma {
1683 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1684 struct amdgpu_irq_src trap_irq;
1685 struct amdgpu_irq_src illegal_inst_irq;
1686 int num_instances;
1687};
1688
97b2e202
AD		 1689/*
1690 * Firmware
1691 */
1692struct amdgpu_firmware {
1693 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1694 bool smu_load;
1695 struct amdgpu_bo *fw_buf;
1696 unsigned int fw_size;
1697};
1698
1699/*
1700 * Benchmarking
1701 */
1702void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1703
1704
1705/*
1706 * Testing
1707 */
1708void amdgpu_test_moves(struct amdgpu_device *adev);
1709void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1710 struct amdgpu_ring *cpA,
1711 struct amdgpu_ring *cpB);
1712void amdgpu_test_syncing(struct amdgpu_device *adev);
1713
1714/*
1715 * MMU Notifier
1716 */
1717#if defined(CONFIG_MMU_NOTIFIER)
1718int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1719void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1720#else
1d1106b0 1721static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1722{
1723 return -ENODEV;
1724}
1d1106b0 1725static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1726#endif
1727
1728/*
1729 * Debugfs
1730 */
1731struct amdgpu_debugfs {
1732 struct drm_info_list *files;
1733 unsigned num_files;
1734};
1735
1736int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1737 struct drm_info_list *files,
1738 unsigned nfiles);
1739int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1740
1741#if defined(CONFIG_DEBUG_FS)
1742int amdgpu_debugfs_init(struct drm_minor *minor);
1743void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1744#endif
1745
1746/*
1747 * amdgpu smumgr functions
1748 */
1749struct amdgpu_smumgr_funcs {
1750 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1751 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1752 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1753};
1754
1755/*
1756 * amdgpu smumgr
1757 */
1758struct amdgpu_smumgr {
1759 struct amdgpu_bo *toc_buf;
1760 struct amdgpu_bo *smu_buf;
1761 /* asic priv smu data */
1762 void *priv;
1763 spinlock_t smu_lock;
1764 /* smumgr functions */
1765 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1766 /* ucode loading complete flag */
1767 uint32_t fw_flags;
1768};
1769
1770/*
1771 * ASIC specific register table accessible by UMD
1772 */
1773struct amdgpu_allowed_register_entry {
1774 uint32_t reg_offset;
1775 bool untouched;
1776 bool grbm_indexed;
1777};
1778
1779struct amdgpu_cu_info {
1780 uint32_t number; /* total active CU number */
1781 uint32_t ao_cu_mask;
1782 uint32_t bitmap[4][4];
1783};
1784
1785
1786/*
1787 * ASIC specific functions.
1788 */
1789struct amdgpu_asic_funcs {
1790 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1791 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1792 u8 *bios, u32 length_bytes);
97b2e202
AD		 1793 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1794 u32 sh_num, u32 reg_offset, u32 *value);
1795 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1796 int (*reset)(struct amdgpu_device *adev);
1797 /* wait for mc_idle */
1798 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1799 /* get the reference clock */
1800 u32 (*get_xclk)(struct amdgpu_device *adev);
1801 /* get the gpu clock counter */
1802 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1803 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1804 /* MM block clocks */
1805 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1806 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1807};
1808
1809/*
1810 * IOCTL.
1811 */
1812int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1813 struct drm_file *filp);
1814int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1815 struct drm_file *filp);
1816
1817int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1822 struct drm_file *filp);
1823int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1824 struct drm_file *filp);
1825int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1828 struct drm_file *filp);
1829int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1830int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1831
1832int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1834
1835/* VRAM scratch page for HDP bug, default vram page */
1836struct amdgpu_vram_scratch {
1837 struct amdgpu_bo *robj;
1838 volatile uint32_t *ptr;
1839 u64 gpu_addr;
1840};
1841
1842/*
1843 * ACPI
1844 */
1845struct amdgpu_atif_notification_cfg {
1846 bool enabled;
1847 int command_code;
1848};
1849
1850struct amdgpu_atif_notifications {
1851 bool display_switch;
1852 bool expansion_mode_change;
1853 bool thermal_state;
1854 bool forced_power_state;
1855 bool system_power_state;
1856 bool display_conf_change;
1857 bool px_gfx_switch;
1858 bool brightness_change;
1859 bool dgpu_display_event;
1860};
1861
1862struct amdgpu_atif_functions {
1863 bool system_params;
1864 bool sbios_requests;
1865 bool select_active_disp;
1866 bool lid_state;
1867 bool get_tv_standard;
1868 bool set_tv_standard;
1869 bool get_panel_expansion_mode;
1870 bool set_panel_expansion_mode;
1871 bool temperature_change;
1872 bool graphics_device_types;
1873};
1874
1875struct amdgpu_atif {
1876 struct amdgpu_atif_notifications notifications;
1877 struct amdgpu_atif_functions functions;
1878 struct amdgpu_atif_notification_cfg notification_cfg;
1879 struct amdgpu_encoder *encoder_for_bl;
1880};
1881
1882struct amdgpu_atcs_functions {
1883 bool get_ext_state;
1884 bool pcie_perf_req;
1885 bool pcie_dev_rdy;
1886 bool pcie_bus_width;
1887};
1888
1889struct amdgpu_atcs {
1890 struct amdgpu_atcs_functions functions;
1891};
1892
d03846af
CZ		 1893/*
1894 * CGS
1895 */
1896void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1897void amdgpu_cgs_destroy_device(void *cgs_device);
1898
1899
97b2e202
AD		 1900/*
1901 * Core structure, functions and helpers.
1902 */
1903typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1904typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1905
1906typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1907typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1908
8faf0e08
AD		 1909struct amdgpu_ip_block_status {
1910 bool valid;
1911 bool sw;
1912 bool hw;
1913};
1914
97b2e202
AD		 1915struct amdgpu_device {
1916 struct device *dev;
1917 struct drm_device *ddev;
1918 struct pci_dev *pdev;
97b2e202
AD		 1919
1920 /* ASIC */
2f7d10b3 1921 enum amd_asic_type asic_type;
97b2e202
AD		 1922 uint32_t family;
1923 uint32_t rev_id;
1924 uint32_t external_rev_id;
1925 unsigned long flags;
1926 int usec_timeout;
1927 const struct amdgpu_asic_funcs *asic_funcs;
1928 bool shutdown;
1929 bool suspend;
1930 bool need_dma32;
1931 bool accel_working;
97b2e202
AD		 1932 struct work_struct reset_work;
1933 struct notifier_block acpi_nb;
1934 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1935 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1936 unsigned debugfs_count;
1937#if defined(CONFIG_DEBUG_FS)
1938 struct dentry *debugfs_regs;
1939#endif
1940 struct amdgpu_atif atif;
1941 struct amdgpu_atcs atcs;
1942 struct mutex srbm_mutex;
1943 /* GRBM index mutex. Protects concurrent access to GRBM index */
1944 struct mutex grbm_idx_mutex;
1945 struct dev_pm_domain vga_pm_domain;
1946 bool have_disp_power_ref;
1947
1948 /* BIOS */
1949 uint8_t *bios;
1950 bool is_atom_bios;
1951 uint16_t bios_header_start;
1952 struct amdgpu_bo *stollen_vga_memory;
1953 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1954
1955 /* Register/doorbell mmio */
1956 resource_size_t rmmio_base;
1957 resource_size_t rmmio_size;
1958 void __iomem *rmmio;
1959 /* protects concurrent MM_INDEX/DATA based register access */
1960 spinlock_t mmio_idx_lock;
1961 /* protects concurrent SMC based register access */
1962 spinlock_t smc_idx_lock;
1963 amdgpu_rreg_t smc_rreg;
1964 amdgpu_wreg_t smc_wreg;
1965 /* protects concurrent PCIE register access */
1966 spinlock_t pcie_idx_lock;
1967 amdgpu_rreg_t pcie_rreg;
1968 amdgpu_wreg_t pcie_wreg;
1969 /* protects concurrent UVD register access */
1970 spinlock_t uvd_ctx_idx_lock;
1971 amdgpu_rreg_t uvd_ctx_rreg;
1972 amdgpu_wreg_t uvd_ctx_wreg;
1973 /* protects concurrent DIDT register access */
1974 spinlock_t didt_idx_lock;
1975 amdgpu_rreg_t didt_rreg;
1976 amdgpu_wreg_t didt_wreg;
1977 /* protects concurrent ENDPOINT (audio) register access */
1978 spinlock_t audio_endpt_idx_lock;
1979 amdgpu_block_rreg_t audio_endpt_rreg;
1980 amdgpu_block_wreg_t audio_endpt_wreg;
1981 void __iomem *rio_mem;
1982 resource_size_t rio_mem_size;
1983 struct amdgpu_doorbell doorbell;
1984
1985 /* clock/pll info */
1986 struct amdgpu_clock clock;
1987
1988 /* MC */
1989 struct amdgpu_mc mc;
1990 struct amdgpu_gart gart;
1991 struct amdgpu_dummy_page dummy_page;
1992 struct amdgpu_vm_manager vm_manager;
1993
1994 /* memory management */
1995 struct amdgpu_mman mman;
1996 struct amdgpu_gem gem;
1997 struct amdgpu_vram_scratch vram_scratch;
1998 struct amdgpu_wb wb;
1999 atomic64_t vram_usage;
2000 atomic64_t vram_vis_usage;
2001 atomic64_t gtt_usage;
2002 atomic64_t num_bytes_moved;
d94aed5a 2003 atomic_t gpu_reset_counter;
97b2e202
AD		 2004
2005 /* display */
2006 struct amdgpu_mode_info mode_info;
2007 struct work_struct hotplug_work;
2008 struct amdgpu_irq_src crtc_irq;
2009 struct amdgpu_irq_src pageflip_irq;
2010 struct amdgpu_irq_src hpd_irq;
2011
2012 /* rings */
97b2e202
AD		 2013 unsigned fence_context;
2014 struct mutex ring_lock;
2015 unsigned num_rings;
2016 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2017 bool ib_pool_ready;
2018 struct amdgpu_sa_manager ring_tmp_bo;
2019
2020 /* interrupts */
2021 struct amdgpu_irq irq;
2022
1f7371b2
AD		 2023 /* powerplay */
2024 struct amd_powerplay powerplay;
e61710c5 2025 bool pp_enabled;
1f7371b2 2026
97b2e202
AD		 2027 /* dpm */
2028 struct amdgpu_pm pm;
2029 u32 cg_flags;
2030 u32 pg_flags;
2031
2032 /* amdgpu smumgr */
2033 struct amdgpu_smumgr smu;
2034
2035 /* gfx */
2036 struct amdgpu_gfx gfx;
2037
2038 /* sdma */
c113ea1c 2039 struct amdgpu_sdma sdma;
97b2e202
AD		 2040
2041 /* uvd */
2042 bool has_uvd;
2043 struct amdgpu_uvd uvd;
2044
2045 /* vce */
2046 struct amdgpu_vce vce;
2047
2048 /* firmwares */
2049 struct amdgpu_firmware firmware;
2050
2051 /* GDS */
2052 struct amdgpu_gds gds;
2053
2054 const struct amdgpu_ip_block_version *ip_blocks;
2055 int num_ip_blocks;
8faf0e08 2056 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2057 struct mutex mn_lock;
2058 DECLARE_HASHTABLE(mn_hash, 7);
2059
2060 /* tracking pinned memory */
2061 u64 vram_pin_size;
2062 u64 gart_pin_size;
130e0371
OG		 2063
2064 /* amdkfd interface */
2065 struct kfd_dev *kfd;
23ca0e4e
CZ		 2066
2067 /* kernel conext for IB submission */
47f38501 2068 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2069};
2070
2071bool amdgpu_device_is_px(struct drm_device *dev);
2072int amdgpu_device_init(struct amdgpu_device *adev,
2073 struct drm_device *ddev,
2074 struct pci_dev *pdev,
2075 uint32_t flags);
2076void amdgpu_device_fini(struct amdgpu_device *adev);
2077int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2078
2079uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2080 bool always_indirect);
2081void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2082 bool always_indirect);
2083u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2084void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2085
2086u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2087void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2088
2089/*
2090 * Cast helper
2091 */
2092extern const struct fence_ops amdgpu_fence_ops;
2093static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2094{
2095 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2096
2097 if (__f->base.ops == &amdgpu_fence_ops)
2098 return __f;
2099
2100 return NULL;
2101}
2102
2103/*
2104 * Registers read & write functions.
2105 */
2106#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2107#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2108#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2109#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2110#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2111#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2112#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2113#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2114#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2115#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2116#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2117#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2118#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2119#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2120#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2121#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2122#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2123#define WREG32_P(reg, val, mask) \
2124 do { \
2125 uint32_t tmp_ = RREG32(reg); \
2126 tmp_ &= (mask); \
2127 tmp_ |= ((val) & ~(mask)); \
2128 WREG32(reg, tmp_); \
2129 } while (0)
2130#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2131#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2132#define WREG32_PLL_P(reg, val, mask) \
2133 do { \
2134 uint32_t tmp_ = RREG32_PLL(reg); \
2135 tmp_ &= (mask); \
2136 tmp_ |= ((val) & ~(mask)); \
2137 WREG32_PLL(reg, tmp_); \
2138 } while (0)
2139#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2140#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2141#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2142
2143#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2144#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2145
2146#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2147#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2148
2149#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2150 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2151 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2152
2153#define REG_GET_FIELD(value, reg, field) \
2154 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2155
2156/*
2157 * BIOS helpers.
2158 */
2159#define RBIOS8(i) (adev->bios[i])
2160#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2161#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2162
2163/*
2164 * RING helpers.
2165 */
2166static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2167{
2168 if (ring->count_dw <= 0)
86c2b790 2169 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2170 ring->ring[ring->wptr++] = v;
2171 ring->wptr &= ring->ptr_mask;
2172 ring->count_dw--;
2173 ring->ring_free_dw--;
2174}
2175
c113ea1c
AD		 2176static inline struct amdgpu_sdma_instance *
2177amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2178{
2179 struct amdgpu_device *adev = ring->adev;
2180 int i;
2181
c113ea1c
AD		 2182 for (i = 0; i < adev->sdma.num_instances; i++)
2183 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2184 break;
2185
2186 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2187 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2188 else
2189 return NULL;
2190}
2191
97b2e202
AD		 2192/*
2193 * ASICs macro.
2194 */
2195#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2196#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2197#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2198#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2199#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2200#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2201#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2202#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2203#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2204#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2205#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2206#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2207#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2208#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2209#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2210#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2211#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2212#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2213#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2214#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2215#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2216#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2217#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2218#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2219#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2220#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2221#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2222#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2223#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2224#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2225#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2226#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2227#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2228#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2229#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2230#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2231#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2232#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2233#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2234#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2235#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2236#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2237#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2238#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2239#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2240#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2241#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2242#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2243#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2244#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2245#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2246#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2247#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2248#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2249#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2250#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2251
2252#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2253 ((adev)->pp_enabled ? \
e61710c5 2254 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2255 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2256
2257#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2258 ((adev)->pp_enabled ? \
e61710c5 2259 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2260 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2261
2262#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2263 ((adev)->pp_enabled ? \
e61710c5 2264 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2265 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2266
2267#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2268 ((adev)->pp_enabled ? \
e61710c5 2269 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2270 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2271
2272#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2273 ((adev)->pp_enabled ? \
e61710c5 2274 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2275 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2276
1b5708ff 2277#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2278 ((adev)->pp_enabled ? \
e61710c5 2279 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2280 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2281
2282#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2283 ((adev)->pp_enabled ? \
e61710c5 2284 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2285 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2286
2287
2288#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2289 ((adev)->pp_enabled ? \
e61710c5 2290 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2291 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2292
2293#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2294 ((adev)->pp_enabled ? \
e61710c5 2295 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2296 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2297
2298#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2299 ((adev)->pp_enabled ? \
e61710c5 2300 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2301 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2302
2303#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2304 ((adev)->pp_enabled ? \
e61710c5 2305 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2306 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2307
2308#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2309 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2310
2311#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2312 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2313
e61710c5 2314#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2315 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2316
2317#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2318
2319/* Common functions */
2320int amdgpu_gpu_reset(struct amdgpu_device *adev);
2321void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2322bool amdgpu_card_posted(struct amdgpu_device *adev);
2323void amdgpu_update_display_priority(struct amdgpu_device *adev);
2324bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82 2325
97b2e202
AD		 2326int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2327int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2328 u32 ip_instance, u32 ring,
2329 struct amdgpu_ring **out_ring);
2330void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2331bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2332int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2333 uint32_t flags);
2334bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
d7006964
CK		 2335bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2336 unsigned long end);
97b2e202
AD		 2337bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2338uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2339 struct ttm_mem_reg *mem);
2340void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2341void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2342void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2343void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2344 const u32 *registers,
2345 const u32 array_size);
2346
2347bool amdgpu_device_is_px(struct drm_device *dev);
2348/* atpx handler */
2349#if defined(CONFIG_VGA_SWITCHEROO)
2350void amdgpu_register_atpx_handler(void);
2351void amdgpu_unregister_atpx_handler(void);
2352#else
2353static inline void amdgpu_register_atpx_handler(void) {}
2354static inline void amdgpu_unregister_atpx_handler(void) {}
2355#endif
2356
2357/*
2358 * KMS
2359 */
2360extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2361extern int amdgpu_max_kms_ioctl;
2362
2363int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2364int amdgpu_driver_unload_kms(struct drm_device *dev);
2365void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2366int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2367void amdgpu_driver_postclose_kms(struct drm_device *dev,
2368 struct drm_file *file_priv);
2369void amdgpu_driver_preclose_kms(struct drm_device *dev,
2370 struct drm_file *file_priv);
2371int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2372int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2373u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2374int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2375void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2376int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2377 int *max_error,
2378 struct timeval *vblank_time,
2379 unsigned flags);
2380long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2381 unsigned long arg);
2382
97b2e202
AD		 2383/*
2384 * functions used by amdgpu_encoder.c
2385 */
2386struct amdgpu_afmt_acr {
2387 u32 clock;
2388
2389 int n_32khz;
2390 int cts_32khz;
2391
2392 int n_44_1khz;
2393 int cts_44_1khz;
2394
2395 int n_48khz;
2396 int cts_48khz;
2397
2398};
2399
2400struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2401
2402/* amdgpu_acpi.c */
2403#if defined(CONFIG_ACPI)
2404int amdgpu_acpi_init(struct amdgpu_device *adev);
2405void amdgpu_acpi_fini(struct amdgpu_device *adev);
2406bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2407int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2408 u8 perf_req, bool advertise);
2409int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2410#else
2411static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2412static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2413#endif
2414
2415struct amdgpu_bo_va_mapping *
2416amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2417 uint64_t addr, struct amdgpu_bo **bo);
2418
2419#include "amdgpu_object.h"
2420
2421#endif
Linux 6.x block layer and io_uring tree(s)