Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3242ba11 HK |
2 | /* |
3 | * Xilinx Zynq GPIO device driver | |
4 | * | |
5 | * Copyright (C) 2009 - 2014 Xilinx, Inc. | |
3242ba11 HK |
6 | */ |
7 | ||
8 | #include <linux/bitops.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/gpio/driver.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
fdcfec11 | 13 | #include <linux/spinlock.h> |
3242ba11 HK |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pm_runtime.h> | |
bdf7a4ae | 18 | #include <linux/of.h> |
3242ba11 HK |
19 | |
20 | #define DRIVER_NAME "zynq-gpio" | |
21 | ||
22 | /* Maximum banks */ | |
23 | #define ZYNQ_GPIO_MAX_BANK 4 | |
bdf7a4ae | 24 | #define ZYNQMP_GPIO_MAX_BANK 6 |
67500244 | 25 | #define VERSAL_GPIO_MAX_BANK 4 |
73c612fe | 26 | #define PMC_GPIO_MAX_BANK 5 |
67500244 | 27 | #define VERSAL_UNUSED_BANKS 2 |
3242ba11 HK |
28 | |
29 | #define ZYNQ_GPIO_BANK0_NGPIO 32 | |
30 | #define ZYNQ_GPIO_BANK1_NGPIO 22 | |
31 | #define ZYNQ_GPIO_BANK2_NGPIO 32 | |
32 | #define ZYNQ_GPIO_BANK3_NGPIO 32 | |
33 | ||
bdf7a4ae AKV |
34 | #define ZYNQMP_GPIO_BANK0_NGPIO 26 |
35 | #define ZYNQMP_GPIO_BANK1_NGPIO 26 | |
36 | #define ZYNQMP_GPIO_BANK2_NGPIO 26 | |
37 | #define ZYNQMP_GPIO_BANK3_NGPIO 32 | |
38 | #define ZYNQMP_GPIO_BANK4_NGPIO 32 | |
39 | #define ZYNQMP_GPIO_BANK5_NGPIO 32 | |
40 | ||
41 | #define ZYNQ_GPIO_NR_GPIOS 118 | |
42 | #define ZYNQMP_GPIO_NR_GPIOS 174 | |
43 | ||
44 | #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 | |
45 | #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ | |
46 | ZYNQ##str##_GPIO_BANK0_NGPIO - 1) | |
47 | #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) | |
48 | #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ | |
49 | ZYNQ##str##_GPIO_BANK1_NGPIO - 1) | |
50 | #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) | |
51 | #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ | |
52 | ZYNQ##str##_GPIO_BANK2_NGPIO - 1) | |
53 | #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) | |
54 | #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ | |
55 | ZYNQ##str##_GPIO_BANK3_NGPIO - 1) | |
56 | #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) | |
57 | #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ | |
58 | ZYNQ##str##_GPIO_BANK4_NGPIO - 1) | |
59 | #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) | |
60 | #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ | |
61 | ZYNQ##str##_GPIO_BANK5_NGPIO - 1) | |
3242ba11 | 62 | |
3242ba11 HK |
63 | /* Register offsets for the GPIO device */ |
64 | /* LSW Mask & Data -WO */ | |
65 | #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) | |
66 | /* MSW Mask & Data -WO */ | |
67 | #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) | |
68 | /* Data Register-RW */ | |
06aa0908 | 69 | #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) |
3242ba11 HK |
70 | #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) |
71 | /* Direction mode reg-RW */ | |
72 | #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) | |
73 | /* Output enable reg-RW */ | |
74 | #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) | |
75 | /* Interrupt mask reg-RO */ | |
76 | #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) | |
77 | /* Interrupt enable reg-WO */ | |
78 | #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) | |
79 | /* Interrupt disable reg-WO */ | |
80 | #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) | |
81 | /* Interrupt status reg-RO */ | |
82 | #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) | |
83 | /* Interrupt type reg-RW */ | |
84 | #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) | |
85 | /* Interrupt polarity reg-RW */ | |
86 | #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) | |
87 | /* Interrupt on any, reg-RW */ | |
88 | #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) | |
89 | ||
90 | /* Disable all interrupts mask */ | |
91 | #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF | |
92 | ||
93 | /* Mid pin number of a bank */ | |
94 | #define ZYNQ_GPIO_MID_PIN_NUM 16 | |
95 | ||
96 | /* GPIO upper 16 bit mask */ | |
97 | #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 | |
98 | ||
3638bd4a SB |
99 | /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ |
100 | #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) | |
06aa0908 | 101 | #define GPIO_QUIRK_DATA_RO_BUG BIT(1) |
67500244 | 102 | #define GPIO_QUIRK_VERSAL BIT(2) |
e3296f19 | 103 | |
e11de4de SD |
104 | struct gpio_regs { |
105 | u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; | |
106 | u32 datalsw[ZYNQMP_GPIO_MAX_BANK]; | |
107 | u32 dirm[ZYNQMP_GPIO_MAX_BANK]; | |
108 | u32 outen[ZYNQMP_GPIO_MAX_BANK]; | |
109 | u32 int_en[ZYNQMP_GPIO_MAX_BANK]; | |
110 | u32 int_dis[ZYNQMP_GPIO_MAX_BANK]; | |
111 | u32 int_type[ZYNQMP_GPIO_MAX_BANK]; | |
112 | u32 int_polarity[ZYNQMP_GPIO_MAX_BANK]; | |
113 | u32 int_any[ZYNQMP_GPIO_MAX_BANK]; | |
114 | }; | |
eb73d6ea | 115 | |
3242ba11 HK |
116 | /** |
117 | * struct zynq_gpio - gpio device private data structure | |
118 | * @chip: instance of the gpio_chip | |
119 | * @base_addr: base address of the GPIO device | |
120 | * @clk: clock resource for this controller | |
59e22114 | 121 | * @irq: interrupt for the GPIO device |
bdf7a4ae | 122 | * @p_data: pointer to platform data |
e11de4de | 123 | * @context: context registers |
fdcfec11 | 124 | * @dirlock: lock used for direction in/out synchronization |
3242ba11 HK |
125 | */ |
126 | struct zynq_gpio { | |
127 | struct gpio_chip chip; | |
128 | void __iomem *base_addr; | |
129 | struct clk *clk; | |
59e22114 | 130 | int irq; |
bdf7a4ae | 131 | const struct zynq_platform_data *p_data; |
e11de4de | 132 | struct gpio_regs context; |
fdcfec11 | 133 | spinlock_t dirlock; /* lock */ |
bdf7a4ae AKV |
134 | }; |
135 | ||
136 | /** | |
137 | * struct zynq_platform_data - zynq gpio platform data structure | |
138 | * @label: string to store in gpio->label | |
6ae5104c | 139 | * @quirks: Flags is used to identify the platform |
bdf7a4ae AKV |
140 | * @ngpio: max number of gpio pins |
141 | * @max_bank: maximum number of gpio banks | |
142 | * @bank_min: this array represents bank's min pin | |
143 | * @bank_max: this array represents bank's max pin | |
6ae5104c | 144 | */ |
bdf7a4ae AKV |
145 | struct zynq_platform_data { |
146 | const char *label; | |
e3296f19 | 147 | u32 quirks; |
bdf7a4ae AKV |
148 | u16 ngpio; |
149 | int max_bank; | |
150 | int bank_min[ZYNQMP_GPIO_MAX_BANK]; | |
151 | int bank_max[ZYNQMP_GPIO_MAX_BANK]; | |
3242ba11 HK |
152 | }; |
153 | ||
6dd85950 LPC |
154 | static struct irq_chip zynq_gpio_level_irqchip; |
155 | static struct irq_chip zynq_gpio_edge_irqchip; | |
fa9795d1 | 156 | |
3638bd4a SB |
157 | /** |
158 | * zynq_gpio_is_zynq - test if HW is zynq or zynqmp | |
159 | * @gpio: Pointer to driver data struct | |
160 | * | |
161 | * Return: 0 if zynqmp, 1 if zynq. | |
162 | */ | |
163 | static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) | |
164 | { | |
165 | return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); | |
166 | } | |
167 | ||
06aa0908 SM |
168 | /** |
169 | * gpio_data_ro_bug - test if HW bug exists or not | |
170 | * @gpio: Pointer to driver data struct | |
171 | * | |
172 | * Return: 0 if bug doesnot exist, 1 if bug exists. | |
173 | */ | |
174 | static int gpio_data_ro_bug(struct zynq_gpio *gpio) | |
175 | { | |
176 | return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); | |
177 | } | |
178 | ||
3242ba11 HK |
179 | /** |
180 | * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank | |
181 | * for a given pin in the GPIO device | |
182 | * @pin_num: gpio pin number within the device | |
183 | * @bank_num: an output parameter used to return the bank number of the gpio | |
184 | * pin | |
185 | * @bank_pin_num: an output parameter used to return pin number within a bank | |
186 | * for the given gpio pin | |
6ae5104c | 187 | * @gpio: gpio device data structure |
3242ba11 HK |
188 | * |
189 | * Returns the bank number and pin offset within the bank. | |
190 | */ | |
191 | static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, | |
192 | unsigned int *bank_num, | |
bdf7a4ae AKV |
193 | unsigned int *bank_pin_num, |
194 | struct zynq_gpio *gpio) | |
3242ba11 | 195 | { |
bdf7a4ae AKV |
196 | int bank; |
197 | ||
198 | for (bank = 0; bank < gpio->p_data->max_bank; bank++) { | |
199 | if ((pin_num >= gpio->p_data->bank_min[bank]) && | |
16ee62e5 | 200 | (pin_num <= gpio->p_data->bank_max[bank])) { |
2717cfca NM |
201 | *bank_num = bank; |
202 | *bank_pin_num = pin_num - | |
203 | gpio->p_data->bank_min[bank]; | |
204 | return; | |
bdf7a4ae | 205 | } |
67500244 SD |
206 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
207 | bank = bank + VERSAL_UNUSED_BANKS; | |
3242ba11 | 208 | } |
3242ba11 | 209 | |
bdf7a4ae AKV |
210 | /* default */ |
211 | WARN(true, "invalid GPIO pin number: %u", pin_num); | |
212 | *bank_num = 0; | |
213 | *bank_pin_num = 0; | |
214 | } | |
016da144 | 215 | |
3242ba11 HK |
216 | /** |
217 | * zynq_gpio_get_value - Get the state of the specified pin of GPIO device | |
218 | * @chip: gpio_chip instance to be worked on | |
219 | * @pin: gpio pin number within the device | |
220 | * | |
221 | * This function reads the state of the specified pin of the GPIO device. | |
222 | * | |
223 | * Return: 0 if the pin is low, 1 if pin is high. | |
224 | */ | |
225 | static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) | |
226 | { | |
227 | u32 data; | |
228 | unsigned int bank_num, bank_pin_num; | |
31a89447 | 229 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 230 | |
bdf7a4ae | 231 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 | 232 | |
06aa0908 SM |
233 | if (gpio_data_ro_bug(gpio)) { |
234 | if (zynq_gpio_is_zynq(gpio)) { | |
235 | if (bank_num <= 1) { | |
236 | data = readl_relaxed(gpio->base_addr + | |
237 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
238 | } else { | |
239 | data = readl_relaxed(gpio->base_addr + | |
240 | ZYNQ_GPIO_DATA_OFFSET(bank_num)); | |
241 | } | |
242 | } else { | |
243 | if (bank_num <= 2) { | |
244 | data = readl_relaxed(gpio->base_addr + | |
245 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
246 | } else { | |
247 | data = readl_relaxed(gpio->base_addr + | |
248 | ZYNQ_GPIO_DATA_OFFSET(bank_num)); | |
249 | } | |
250 | } | |
251 | } else { | |
252 | data = readl_relaxed(gpio->base_addr + | |
253 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
254 | } | |
3242ba11 HK |
255 | return (data >> bank_pin_num) & 1; |
256 | } | |
257 | ||
258 | /** | |
259 | * zynq_gpio_set_value - Modify the state of the pin with specified value | |
260 | * @chip: gpio_chip instance to be worked on | |
261 | * @pin: gpio pin number within the device | |
262 | * @state: value used to modify the state of the specified pin | |
263 | * | |
264 | * This function calculates the register offset (i.e to lower 16 bits or | |
265 | * upper 16 bits) based on the given pin number and sets the state of a | |
266 | * gpio pin to the specified value. The state is either 0 or non-zero. | |
267 | */ | |
268 | static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, | |
269 | int state) | |
270 | { | |
271 | unsigned int reg_offset, bank_num, bank_pin_num; | |
31a89447 | 272 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 273 | |
bdf7a4ae | 274 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
275 | |
276 | if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { | |
277 | /* only 16 data bits in bit maskable reg */ | |
278 | bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; | |
279 | reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); | |
280 | } else { | |
281 | reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); | |
282 | } | |
283 | ||
284 | /* | |
285 | * get the 32 bit value to be written to the mask/data register where | |
286 | * the upper 16 bits is the mask and lower 16 bits is the data | |
287 | */ | |
288 | state = !!state; | |
289 | state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & | |
290 | ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); | |
291 | ||
292 | writel_relaxed(state, gpio->base_addr + reg_offset); | |
293 | } | |
294 | ||
295 | /** | |
296 | * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input | |
297 | * @chip: gpio_chip instance to be worked on | |
298 | * @pin: gpio pin number within the device | |
299 | * | |
300 | * This function uses the read-modify-write sequence to set the direction of | |
301 | * the gpio pin as input. | |
302 | * | |
303 | * Return: 0 always | |
304 | */ | |
305 | static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) | |
306 | { | |
307 | u32 reg; | |
308 | unsigned int bank_num, bank_pin_num; | |
fdcfec11 | 309 | unsigned long flags; |
31a89447 | 310 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 311 | |
bdf7a4ae | 312 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 | 313 | |
e3296f19 NM |
314 | /* |
315 | * On zynq bank 0 pins 7 and 8 are special and cannot be used | |
316 | * as inputs. | |
317 | */ | |
3638bd4a | 318 | if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && |
16ee62e5 | 319 | (bank_pin_num == 7 || bank_pin_num == 8)) |
3242ba11 HK |
320 | return -EINVAL; |
321 | ||
322 | /* clear the bit in direction mode reg to set the pin as input */ | |
fdcfec11 | 323 | spin_lock_irqsave(&gpio->dirlock, flags); |
3242ba11 HK |
324 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
325 | reg &= ~BIT(bank_pin_num); | |
326 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
fdcfec11 | 327 | spin_unlock_irqrestore(&gpio->dirlock, flags); |
3242ba11 HK |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
332 | /** | |
333 | * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output | |
334 | * @chip: gpio_chip instance to be worked on | |
335 | * @pin: gpio pin number within the device | |
336 | * @state: value to be written to specified pin | |
337 | * | |
338 | * This function sets the direction of specified GPIO pin as output, configures | |
339 | * the Output Enable register for the pin and uses zynq_gpio_set to set | |
340 | * the state of the pin to the value specified. | |
341 | * | |
342 | * Return: 0 always | |
343 | */ | |
344 | static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, | |
345 | int state) | |
346 | { | |
347 | u32 reg; | |
348 | unsigned int bank_num, bank_pin_num; | |
fdcfec11 | 349 | unsigned long flags; |
31a89447 | 350 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 351 | |
bdf7a4ae | 352 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
353 | |
354 | /* set the GPIO pin as output */ | |
fdcfec11 | 355 | spin_lock_irqsave(&gpio->dirlock, flags); |
3242ba11 HK |
356 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
357 | reg |= BIT(bank_pin_num); | |
358 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
359 | ||
360 | /* configure the output enable reg for the pin */ | |
361 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); | |
362 | reg |= BIT(bank_pin_num); | |
363 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); | |
fdcfec11 | 364 | spin_unlock_irqrestore(&gpio->dirlock, flags); |
3242ba11 HK |
365 | |
366 | /* set the state of the pin */ | |
367 | zynq_gpio_set_value(chip, pin, state); | |
368 | return 0; | |
369 | } | |
370 | ||
6169005c BM |
371 | /** |
372 | * zynq_gpio_get_direction - Read the direction of the specified GPIO pin | |
373 | * @chip: gpio_chip instance to be worked on | |
374 | * @pin: gpio pin number within the device | |
375 | * | |
376 | * This function returns the direction of the specified GPIO. | |
377 | * | |
e42615ec | 378 | * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN |
6169005c BM |
379 | */ |
380 | static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) | |
381 | { | |
382 | u32 reg; | |
383 | unsigned int bank_num, bank_pin_num; | |
384 | struct zynq_gpio *gpio = gpiochip_get_data(chip); | |
385 | ||
386 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); | |
387 | ||
388 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
389 | ||
e42615ec MV |
390 | if (reg & BIT(bank_pin_num)) |
391 | return GPIO_LINE_DIRECTION_OUT; | |
392 | ||
393 | return GPIO_LINE_DIRECTION_IN; | |
6169005c BM |
394 | } |
395 | ||
3242ba11 HK |
396 | /** |
397 | * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin | |
398 | * @irq_data: per irq and chip data passed down to chip functions | |
399 | * | |
400 | * This function calculates gpio pin number from irq number and sets the | |
401 | * bit in the Interrupt Disable register of the corresponding bank to disable | |
402 | * interrupts for that pin. | |
403 | */ | |
404 | static void zynq_gpio_irq_mask(struct irq_data *irq_data) | |
405 | { | |
406 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 407 | struct zynq_gpio *gpio = |
31a89447 | 408 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
409 | |
410 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 411 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
412 | writel_relaxed(BIT(bank_pin_num), |
413 | gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
414 | } | |
415 | ||
416 | /** | |
417 | * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin | |
418 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
419 | * to enable | |
420 | * | |
421 | * This function calculates the gpio pin number from irq number and sets the | |
422 | * bit in the Interrupt Enable register of the corresponding bank to enable | |
423 | * interrupts for that pin. | |
424 | */ | |
425 | static void zynq_gpio_irq_unmask(struct irq_data *irq_data) | |
426 | { | |
427 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 428 | struct zynq_gpio *gpio = |
31a89447 | 429 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
430 | |
431 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 432 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
433 | writel_relaxed(BIT(bank_pin_num), |
434 | gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); | |
435 | } | |
436 | ||
190dc2e6 LPC |
437 | /** |
438 | * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin | |
439 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
440 | * to ack | |
441 | * | |
442 | * This function calculates gpio pin number from irq number and sets the bit | |
443 | * in the Interrupt Status Register of the corresponding bank, to ACK the irq. | |
444 | */ | |
445 | static void zynq_gpio_irq_ack(struct irq_data *irq_data) | |
446 | { | |
447 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 448 | struct zynq_gpio *gpio = |
31a89447 | 449 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
190dc2e6 LPC |
450 | |
451 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 452 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
190dc2e6 LPC |
453 | writel_relaxed(BIT(bank_pin_num), |
454 | gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); | |
455 | } | |
456 | ||
457 | /** | |
458 | * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin | |
459 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
460 | * to enable | |
461 | * | |
20a8a968 | 462 | * Clears the INTSTS bit and unmasks the given interrupt. |
190dc2e6 LPC |
463 | */ |
464 | static void zynq_gpio_irq_enable(struct irq_data *irq_data) | |
465 | { | |
466 | /* | |
467 | * The Zynq GPIO controller does not disable interrupt detection when | |
468 | * the interrupt is masked and only disables the propagation of the | |
469 | * interrupt. This means when the controller detects an interrupt | |
470 | * condition while the interrupt is logically disabled it will propagate | |
471 | * that interrupt event once the interrupt is enabled. This will cause | |
472 | * the interrupt consumer to see spurious interrupts to prevent this | |
473 | * first make sure that the interrupt is not asserted and then enable | |
474 | * it. | |
475 | */ | |
476 | zynq_gpio_irq_ack(irq_data); | |
477 | zynq_gpio_irq_unmask(irq_data); | |
478 | } | |
479 | ||
3242ba11 HK |
480 | /** |
481 | * zynq_gpio_set_irq_type - Set the irq type for a gpio pin | |
482 | * @irq_data: irq data containing irq number of gpio pin | |
483 | * @type: interrupt type that is to be set for the gpio pin | |
484 | * | |
485 | * This function gets the gpio pin number and its bank from the gpio pin number | |
486 | * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. | |
487 | * | |
488 | * Return: 0, negative error otherwise. | |
489 | * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; | |
490 | * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; | |
491 | * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; | |
492 | * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; | |
493 | * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA | |
494 | */ | |
495 | static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) | |
496 | { | |
497 | u32 int_type, int_pol, int_any; | |
498 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 499 | struct zynq_gpio *gpio = |
31a89447 | 500 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
501 | |
502 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 503 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
504 | |
505 | int_type = readl_relaxed(gpio->base_addr + | |
506 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
507 | int_pol = readl_relaxed(gpio->base_addr + | |
508 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
509 | int_any = readl_relaxed(gpio->base_addr + | |
510 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
511 | ||
512 | /* | |
513 | * based on the type requested, configure the INT_TYPE, INT_POLARITY | |
514 | * and INT_ANY registers | |
515 | */ | |
516 | switch (type) { | |
517 | case IRQ_TYPE_EDGE_RISING: | |
518 | int_type |= BIT(bank_pin_num); | |
519 | int_pol |= BIT(bank_pin_num); | |
520 | int_any &= ~BIT(bank_pin_num); | |
521 | break; | |
522 | case IRQ_TYPE_EDGE_FALLING: | |
523 | int_type |= BIT(bank_pin_num); | |
524 | int_pol &= ~BIT(bank_pin_num); | |
525 | int_any &= ~BIT(bank_pin_num); | |
526 | break; | |
527 | case IRQ_TYPE_EDGE_BOTH: | |
528 | int_type |= BIT(bank_pin_num); | |
529 | int_any |= BIT(bank_pin_num); | |
530 | break; | |
531 | case IRQ_TYPE_LEVEL_HIGH: | |
532 | int_type &= ~BIT(bank_pin_num); | |
533 | int_pol |= BIT(bank_pin_num); | |
534 | break; | |
535 | case IRQ_TYPE_LEVEL_LOW: | |
536 | int_type &= ~BIT(bank_pin_num); | |
537 | int_pol &= ~BIT(bank_pin_num); | |
538 | break; | |
539 | default: | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | writel_relaxed(int_type, | |
544 | gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
545 | writel_relaxed(int_pol, | |
546 | gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
547 | writel_relaxed(int_any, | |
548 | gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
6dd85950 | 549 | |
16ee62e5 | 550 | if (type & IRQ_TYPE_LEVEL_MASK) |
47c08462 | 551 | irq_set_chip_handler_name_locked(irq_data, |
16ee62e5 MS |
552 | &zynq_gpio_level_irqchip, |
553 | handle_fasteoi_irq, NULL); | |
554 | else | |
47c08462 | 555 | irq_set_chip_handler_name_locked(irq_data, |
16ee62e5 MS |
556 | &zynq_gpio_edge_irqchip, |
557 | handle_level_irq, NULL); | |
6dd85950 | 558 | |
3242ba11 HK |
559 | return 0; |
560 | } | |
561 | ||
562 | static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) | |
563 | { | |
fa9795d1 | 564 | struct zynq_gpio *gpio = |
31a89447 | 565 | gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
59e22114 ES |
566 | |
567 | irq_set_irq_wake(gpio->irq, on); | |
3242ba11 HK |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
c2df3de0 TP |
572 | static int zynq_gpio_irq_reqres(struct irq_data *d) |
573 | { | |
574 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); | |
575 | int ret; | |
576 | ||
7f57b295 | 577 | ret = pm_runtime_resume_and_get(chip->parent); |
c2df3de0 TP |
578 | if (ret < 0) |
579 | return ret; | |
580 | ||
581 | return gpiochip_reqres_irq(chip, d->hwirq); | |
582 | } | |
583 | ||
584 | static void zynq_gpio_irq_relres(struct irq_data *d) | |
585 | { | |
586 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); | |
587 | ||
588 | gpiochip_relres_irq(chip, d->hwirq); | |
589 | pm_runtime_put(chip->parent); | |
590 | } | |
591 | ||
3242ba11 | 592 | /* irq chip descriptor */ |
6dd85950 | 593 | static struct irq_chip zynq_gpio_level_irqchip = { |
3242ba11 | 594 | .name = DRIVER_NAME, |
190dc2e6 | 595 | .irq_enable = zynq_gpio_irq_enable, |
6dd85950 LPC |
596 | .irq_eoi = zynq_gpio_irq_ack, |
597 | .irq_mask = zynq_gpio_irq_mask, | |
598 | .irq_unmask = zynq_gpio_irq_unmask, | |
599 | .irq_set_type = zynq_gpio_set_irq_type, | |
600 | .irq_set_wake = zynq_gpio_set_wake, | |
c2df3de0 TP |
601 | .irq_request_resources = zynq_gpio_irq_reqres, |
602 | .irq_release_resources = zynq_gpio_irq_relres, | |
a1946778 ES |
603 | .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | |
604 | IRQCHIP_MASK_ON_SUSPEND, | |
6dd85950 LPC |
605 | }; |
606 | ||
607 | static struct irq_chip zynq_gpio_edge_irqchip = { | |
608 | .name = DRIVER_NAME, | |
609 | .irq_enable = zynq_gpio_irq_enable, | |
610 | .irq_ack = zynq_gpio_irq_ack, | |
3242ba11 HK |
611 | .irq_mask = zynq_gpio_irq_mask, |
612 | .irq_unmask = zynq_gpio_irq_unmask, | |
613 | .irq_set_type = zynq_gpio_set_irq_type, | |
614 | .irq_set_wake = zynq_gpio_set_wake, | |
c2df3de0 TP |
615 | .irq_request_resources = zynq_gpio_irq_reqres, |
616 | .irq_release_resources = zynq_gpio_irq_relres, | |
a1946778 | 617 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
3242ba11 HK |
618 | }; |
619 | ||
5a2533a7 LPC |
620 | static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, |
621 | unsigned int bank_num, | |
622 | unsigned long pending) | |
623 | { | |
bdf7a4ae | 624 | unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; |
f0fbe7bc | 625 | struct irq_domain *irqdomain = gpio->chip.irq.domain; |
5a2533a7 LPC |
626 | int offset; |
627 | ||
628 | if (!pending) | |
629 | return; | |
630 | ||
dbd1c54f MZ |
631 | for_each_set_bit(offset, &pending, 32) |
632 | generic_handle_domain_irq(irqdomain, offset + bank_offset); | |
5a2533a7 LPC |
633 | } |
634 | ||
3242ba11 HK |
635 | /** |
636 | * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device | |
3242ba11 HK |
637 | * @desc: irq descriptor instance of the 'irq' |
638 | * | |
639 | * This function reads the Interrupt Status Register of each bank to get the | |
640 | * gpio pin number which has triggered an interrupt. It then acks the triggered | |
641 | * interrupt and calls the pin specific handler set by the higher layer | |
642 | * application for that pin. | |
643 | * Note: A bug is reported if no handler is set for the gpio pin. | |
644 | */ | |
bd0b9ac4 | 645 | static void zynq_gpio_irqhandler(struct irq_desc *desc) |
3242ba11 HK |
646 | { |
647 | u32 int_sts, int_enb; | |
648 | unsigned int bank_num; | |
fa9795d1 | 649 | struct zynq_gpio *gpio = |
31a89447 | 650 | gpiochip_get_data(irq_desc_get_handler_data(desc)); |
3242ba11 HK |
651 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
652 | ||
653 | chained_irq_enter(irqchip, desc); | |
654 | ||
bdf7a4ae | 655 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { |
3242ba11 HK |
656 | int_sts = readl_relaxed(gpio->base_addr + |
657 | ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); | |
658 | int_enb = readl_relaxed(gpio->base_addr + | |
659 | ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); | |
5a2533a7 | 660 | zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); |
67500244 SD |
661 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
662 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
3242ba11 HK |
663 | } |
664 | ||
665 | chained_irq_exit(irqchip, desc); | |
666 | } | |
667 | ||
e11de4de SD |
668 | static void zynq_gpio_save_context(struct zynq_gpio *gpio) |
669 | { | |
670 | unsigned int bank_num; | |
671 | ||
672 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { | |
673 | gpio->context.datalsw[bank_num] = | |
674 | readl_relaxed(gpio->base_addr + | |
675 | ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); | |
676 | gpio->context.datamsw[bank_num] = | |
677 | readl_relaxed(gpio->base_addr + | |
678 | ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); | |
679 | gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + | |
680 | ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
681 | gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + | |
682 | ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); | |
683 | gpio->context.int_type[bank_num] = | |
684 | readl_relaxed(gpio->base_addr + | |
685 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
686 | gpio->context.int_polarity[bank_num] = | |
687 | readl_relaxed(gpio->base_addr + | |
688 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
689 | gpio->context.int_any[bank_num] = | |
690 | readl_relaxed(gpio->base_addr + | |
691 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
67500244 SD |
692 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
693 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
e11de4de SD |
694 | } |
695 | } | |
696 | ||
697 | static void zynq_gpio_restore_context(struct zynq_gpio *gpio) | |
698 | { | |
699 | unsigned int bank_num; | |
700 | ||
701 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { | |
36f2e720 SM |
702 | writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + |
703 | ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
e11de4de SD |
704 | writel_relaxed(gpio->context.datalsw[bank_num], |
705 | gpio->base_addr + | |
706 | ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); | |
707 | writel_relaxed(gpio->context.datamsw[bank_num], | |
708 | gpio->base_addr + | |
709 | ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); | |
710 | writel_relaxed(gpio->context.dirm[bank_num], | |
711 | gpio->base_addr + | |
712 | ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
e11de4de SD |
713 | writel_relaxed(gpio->context.int_type[bank_num], |
714 | gpio->base_addr + | |
715 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
716 | writel_relaxed(gpio->context.int_polarity[bank_num], | |
717 | gpio->base_addr + | |
718 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
719 | writel_relaxed(gpio->context.int_any[bank_num], | |
720 | gpio->base_addr + | |
721 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
36f2e720 SM |
722 | writel_relaxed(~(gpio->context.int_en[bank_num]), |
723 | gpio->base_addr + | |
724 | ZYNQ_GPIO_INTEN_OFFSET(bank_num)); | |
67500244 SD |
725 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
726 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
e11de4de SD |
727 | } |
728 | } | |
eb73d6ea | 729 | |
3242ba11 HK |
730 | static int __maybe_unused zynq_gpio_suspend(struct device *dev) |
731 | { | |
a76e865e | 732 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
5e3a8ecd | 733 | struct irq_data *data = irq_get_irq_data(gpio->irq); |
59e22114 | 734 | |
35d7b72a SN |
735 | if (!data) { |
736 | dev_err(dev, "irq_get_irq_data() failed\n"); | |
737 | return -EINVAL; | |
738 | } | |
739 | ||
26ebdbf8 SD |
740 | if (!device_may_wakeup(dev)) |
741 | disable_irq(gpio->irq); | |
742 | ||
e11de4de SD |
743 | if (!irqd_is_wakeup_set(data)) { |
744 | zynq_gpio_save_context(gpio); | |
3242ba11 | 745 | return pm_runtime_force_suspend(dev); |
e11de4de | 746 | } |
3242ba11 HK |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static int __maybe_unused zynq_gpio_resume(struct device *dev) | |
752 | { | |
a76e865e | 753 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
5e3a8ecd | 754 | struct irq_data *data = irq_get_irq_data(gpio->irq); |
e11de4de | 755 | int ret; |
59e22114 | 756 | |
35d7b72a SN |
757 | if (!data) { |
758 | dev_err(dev, "irq_get_irq_data() failed\n"); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
26ebdbf8 SD |
762 | if (!device_may_wakeup(dev)) |
763 | enable_irq(gpio->irq); | |
764 | ||
e11de4de SD |
765 | if (!irqd_is_wakeup_set(data)) { |
766 | ret = pm_runtime_force_resume(dev); | |
767 | zynq_gpio_restore_context(gpio); | |
768 | return ret; | |
769 | } | |
3242ba11 HK |
770 | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) | |
775 | { | |
38ccad02 | 776 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
3242ba11 HK |
777 | |
778 | clk_disable_unprepare(gpio->clk); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) | |
784 | { | |
38ccad02 | 785 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
3242ba11 HK |
786 | |
787 | return clk_prepare_enable(gpio->clk); | |
788 | } | |
789 | ||
2717cfca | 790 | static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset) |
3242ba11 HK |
791 | { |
792 | int ret; | |
793 | ||
58383c78 | 794 | ret = pm_runtime_get_sync(chip->parent); |
3242ba11 HK |
795 | |
796 | /* | |
797 | * If the device is already active pm_runtime_get() will return 1 on | |
798 | * success, but gpio_request still needs to return 0. | |
799 | */ | |
800 | return ret < 0 ? ret : 0; | |
801 | } | |
802 | ||
2717cfca | 803 | static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset) |
3242ba11 | 804 | { |
58383c78 | 805 | pm_runtime_put(chip->parent); |
3242ba11 HK |
806 | } |
807 | ||
808 | static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { | |
809 | SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) | |
6ed23b80 | 810 | SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, |
16ee62e5 | 811 | zynq_gpio_runtime_resume, NULL) |
3242ba11 HK |
812 | }; |
813 | ||
67500244 SD |
814 | static const struct zynq_platform_data versal_gpio_def = { |
815 | .label = "versal_gpio", | |
816 | .quirks = GPIO_QUIRK_VERSAL, | |
817 | .ngpio = 58, | |
818 | .max_bank = VERSAL_GPIO_MAX_BANK, | |
819 | .bank_min[0] = 0, | |
820 | .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ | |
821 | .bank_min[3] = 26, | |
822 | .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ | |
823 | }; | |
824 | ||
73c612fe SD |
825 | static const struct zynq_platform_data pmc_gpio_def = { |
826 | .label = "pmc_gpio", | |
827 | .ngpio = 116, | |
828 | .max_bank = PMC_GPIO_MAX_BANK, | |
829 | .bank_min[0] = 0, | |
830 | .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ | |
831 | .bank_min[1] = 26, | |
832 | .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */ | |
833 | .bank_min[3] = 52, | |
834 | .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */ | |
835 | .bank_min[4] = 84, | |
836 | .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */ | |
837 | }; | |
838 | ||
bdf7a4ae AKV |
839 | static const struct zynq_platform_data zynqmp_gpio_def = { |
840 | .label = "zynqmp_gpio", | |
06aa0908 | 841 | .quirks = GPIO_QUIRK_DATA_RO_BUG, |
bdf7a4ae AKV |
842 | .ngpio = ZYNQMP_GPIO_NR_GPIOS, |
843 | .max_bank = ZYNQMP_GPIO_MAX_BANK, | |
844 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), | |
845 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), | |
846 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), | |
847 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), | |
848 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), | |
849 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), | |
850 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), | |
851 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), | |
852 | .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), | |
853 | .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), | |
854 | .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), | |
855 | .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), | |
856 | }; | |
857 | ||
858 | static const struct zynq_platform_data zynq_gpio_def = { | |
859 | .label = "zynq_gpio", | |
06aa0908 | 860 | .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, |
bdf7a4ae AKV |
861 | .ngpio = ZYNQ_GPIO_NR_GPIOS, |
862 | .max_bank = ZYNQ_GPIO_MAX_BANK, | |
863 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), | |
864 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), | |
865 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), | |
866 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), | |
867 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), | |
868 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), | |
869 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), | |
870 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), | |
871 | }; | |
872 | ||
873 | static const struct of_device_id zynq_gpio_of_match[] = { | |
7808c42b MY |
874 | { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, |
875 | { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, | |
67500244 | 876 | { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, |
73c612fe | 877 | { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def }, |
bdf7a4ae AKV |
878 | { /* end of table */ } |
879 | }; | |
880 | MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); | |
881 | ||
3242ba11 HK |
882 | /** |
883 | * zynq_gpio_probe - Initialization method for a zynq_gpio device | |
884 | * @pdev: platform device instance | |
885 | * | |
886 | * This function allocates memory resources for the gpio device and registers | |
887 | * all the banks of the device. It will also set up interrupts for the gpio | |
888 | * pins. | |
889 | * Note: Interrupts are disabled for all the banks during initialization. | |
890 | * | |
891 | * Return: 0 on success, negative error otherwise. | |
892 | */ | |
893 | static int zynq_gpio_probe(struct platform_device *pdev) | |
894 | { | |
59e22114 | 895 | int ret, bank_num; |
3242ba11 HK |
896 | struct zynq_gpio *gpio; |
897 | struct gpio_chip *chip; | |
f6a7053d | 898 | struct gpio_irq_chip *girq; |
bdf7a4ae | 899 | const struct of_device_id *match; |
3242ba11 HK |
900 | |
901 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
902 | if (!gpio) | |
903 | return -ENOMEM; | |
904 | ||
bdf7a4ae AKV |
905 | match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); |
906 | if (!match) { | |
907 | dev_err(&pdev->dev, "of_match_node() failed\n"); | |
908 | return -EINVAL; | |
909 | } | |
910 | gpio->p_data = match->data; | |
3242ba11 HK |
911 | platform_set_drvdata(pdev, gpio); |
912 | ||
77bc0e69 | 913 | gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); |
3242ba11 HK |
914 | if (IS_ERR(gpio->base_addr)) |
915 | return PTR_ERR(gpio->base_addr); | |
916 | ||
59e22114 | 917 | gpio->irq = platform_get_irq(pdev, 0); |
15bddb7d | 918 | if (gpio->irq < 0) |
59e22114 | 919 | return gpio->irq; |
3242ba11 HK |
920 | |
921 | /* configure the gpio chip */ | |
922 | chip = &gpio->chip; | |
bdf7a4ae | 923 | chip->label = gpio->p_data->label; |
3242ba11 | 924 | chip->owner = THIS_MODULE; |
58383c78 | 925 | chip->parent = &pdev->dev; |
3242ba11 HK |
926 | chip->get = zynq_gpio_get_value; |
927 | chip->set = zynq_gpio_set_value; | |
928 | chip->request = zynq_gpio_request; | |
929 | chip->free = zynq_gpio_free; | |
930 | chip->direction_input = zynq_gpio_dir_in; | |
931 | chip->direction_output = zynq_gpio_dir_out; | |
6169005c | 932 | chip->get_direction = zynq_gpio_get_direction; |
060f3ebf | 933 | chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); |
bdf7a4ae | 934 | chip->ngpio = gpio->p_data->ngpio; |
3242ba11 | 935 | |
3773c195 | 936 | /* Retrieve GPIO clock */ |
3242ba11 | 937 | gpio->clk = devm_clk_get(&pdev->dev, NULL); |
805a6ef8 KK |
938 | if (IS_ERR(gpio->clk)) |
939 | return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n"); | |
940 | ||
0f84f29f HG |
941 | ret = clk_prepare_enable(gpio->clk); |
942 | if (ret) { | |
943 | dev_err(&pdev->dev, "Unable to enable clock.\n"); | |
944 | return ret; | |
945 | } | |
3773c195 | 946 | |
fdcfec11 GL |
947 | spin_lock_init(&gpio->dirlock); |
948 | ||
0f84f29f | 949 | pm_runtime_set_active(&pdev->dev); |
3773c195 | 950 | pm_runtime_enable(&pdev->dev); |
7f57b295 | 951 | ret = pm_runtime_resume_and_get(&pdev->dev); |
3773c195 | 952 | if (ret < 0) |
615d23f8 | 953 | goto err_pm_dis; |
3242ba11 | 954 | |
3242ba11 | 955 | /* disable interrupts for all banks */ |
67500244 | 956 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { |
3242ba11 HK |
957 | writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + |
958 | ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
67500244 SD |
959 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
960 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
961 | } | |
3242ba11 | 962 | |
f6a7053d LW |
963 | /* Set up the GPIO irqchip */ |
964 | girq = &chip->irq; | |
965 | girq->chip = &zynq_gpio_edge_irqchip; | |
966 | girq->parent_handler = zynq_gpio_irqhandler; | |
967 | girq->num_parents = 1; | |
968 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
969 | sizeof(*girq->parents), | |
970 | GFP_KERNEL); | |
971 | if (!girq->parents) { | |
972 | ret = -ENOMEM; | |
973 | goto err_pm_put; | |
3242ba11 | 974 | } |
f6a7053d LW |
975 | girq->parents[0] = gpio->irq; |
976 | girq->default_type = IRQ_TYPE_NONE; | |
977 | girq->handler = handle_level_irq; | |
3242ba11 | 978 | |
f6a7053d LW |
979 | /* report a bug if gpio chip registration fails */ |
980 | ret = gpiochip_add_data(chip, gpio); | |
981 | if (ret) { | |
982 | dev_err(&pdev->dev, "Failed to add gpio chip\n"); | |
983 | goto err_pm_put; | |
984 | } | |
3242ba11 | 985 | |
26ebdbf8 SD |
986 | irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY); |
987 | device_init_wakeup(&pdev->dev, 1); | |
3773c195 | 988 | pm_runtime_put(&pdev->dev); |
3242ba11 | 989 | |
3242ba11 HK |
990 | return 0; |
991 | ||
3773c195 MS |
992 | err_pm_put: |
993 | pm_runtime_put(&pdev->dev); | |
615d23f8 SD |
994 | err_pm_dis: |
995 | pm_runtime_disable(&pdev->dev); | |
0f84f29f | 996 | clk_disable_unprepare(gpio->clk); |
3242ba11 HK |
997 | |
998 | return ret; | |
999 | } | |
1000 | ||
1001 | /** | |
1002 | * zynq_gpio_remove - Driver removal function | |
1003 | * @pdev: platform device instance | |
1004 | * | |
1005 | * Return: 0 always | |
1006 | */ | |
1007 | static int zynq_gpio_remove(struct platform_device *pdev) | |
1008 | { | |
3242ba11 | 1009 | struct zynq_gpio *gpio = platform_get_drvdata(pdev); |
a51b2fb9 | 1010 | int ret; |
3242ba11 | 1011 | |
a51b2fb9 SN |
1012 | ret = pm_runtime_get_sync(&pdev->dev); |
1013 | if (ret < 0) | |
1014 | dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n"); | |
da26d5d8 | 1015 | gpiochip_remove(&gpio->chip); |
3242ba11 HK |
1016 | clk_disable_unprepare(gpio->clk); |
1017 | device_set_wakeup_capable(&pdev->dev, 0); | |
6b956af0 | 1018 | pm_runtime_disable(&pdev->dev); |
3242ba11 HK |
1019 | return 0; |
1020 | } | |
1021 | ||
3242ba11 HK |
1022 | static struct platform_driver zynq_gpio_driver = { |
1023 | .driver = { | |
1024 | .name = DRIVER_NAME, | |
3242ba11 HK |
1025 | .pm = &zynq_gpio_dev_pm_ops, |
1026 | .of_match_table = zynq_gpio_of_match, | |
1027 | }, | |
1028 | .probe = zynq_gpio_probe, | |
1029 | .remove = zynq_gpio_remove, | |
1030 | }; | |
1031 | ||
c43ce474 | 1032 | module_platform_driver(zynq_gpio_driver); |
80d2bf55 | 1033 | |
3242ba11 HK |
1034 | MODULE_AUTHOR("Xilinx Inc."); |
1035 | MODULE_DESCRIPTION("Zynq GPIO driver"); | |
1036 | MODULE_LICENSE("GPL"); |