Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3242ba11 HK |
2 | /* |
3 | * Xilinx Zynq GPIO device driver | |
4 | * | |
5 | * Copyright (C) 2009 - 2014 Xilinx, Inc. | |
3242ba11 HK |
6 | */ |
7 | ||
8 | #include <linux/bitops.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/gpio/driver.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
fdcfec11 | 13 | #include <linux/spinlock.h> |
3242ba11 HK |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pm_runtime.h> | |
bdf7a4ae | 18 | #include <linux/of.h> |
3242ba11 HK |
19 | |
20 | #define DRIVER_NAME "zynq-gpio" | |
21 | ||
22 | /* Maximum banks */ | |
23 | #define ZYNQ_GPIO_MAX_BANK 4 | |
bdf7a4ae | 24 | #define ZYNQMP_GPIO_MAX_BANK 6 |
67500244 SD |
25 | #define VERSAL_GPIO_MAX_BANK 4 |
26 | #define VERSAL_UNUSED_BANKS 2 | |
3242ba11 HK |
27 | |
28 | #define ZYNQ_GPIO_BANK0_NGPIO 32 | |
29 | #define ZYNQ_GPIO_BANK1_NGPIO 22 | |
30 | #define ZYNQ_GPIO_BANK2_NGPIO 32 | |
31 | #define ZYNQ_GPIO_BANK3_NGPIO 32 | |
32 | ||
bdf7a4ae AKV |
33 | #define ZYNQMP_GPIO_BANK0_NGPIO 26 |
34 | #define ZYNQMP_GPIO_BANK1_NGPIO 26 | |
35 | #define ZYNQMP_GPIO_BANK2_NGPIO 26 | |
36 | #define ZYNQMP_GPIO_BANK3_NGPIO 32 | |
37 | #define ZYNQMP_GPIO_BANK4_NGPIO 32 | |
38 | #define ZYNQMP_GPIO_BANK5_NGPIO 32 | |
39 | ||
40 | #define ZYNQ_GPIO_NR_GPIOS 118 | |
41 | #define ZYNQMP_GPIO_NR_GPIOS 174 | |
42 | ||
43 | #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 | |
44 | #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ | |
45 | ZYNQ##str##_GPIO_BANK0_NGPIO - 1) | |
46 | #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) | |
47 | #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ | |
48 | ZYNQ##str##_GPIO_BANK1_NGPIO - 1) | |
49 | #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) | |
50 | #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ | |
51 | ZYNQ##str##_GPIO_BANK2_NGPIO - 1) | |
52 | #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) | |
53 | #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ | |
54 | ZYNQ##str##_GPIO_BANK3_NGPIO - 1) | |
55 | #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) | |
56 | #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ | |
57 | ZYNQ##str##_GPIO_BANK4_NGPIO - 1) | |
58 | #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) | |
59 | #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ | |
60 | ZYNQ##str##_GPIO_BANK5_NGPIO - 1) | |
3242ba11 | 61 | |
3242ba11 HK |
62 | /* Register offsets for the GPIO device */ |
63 | /* LSW Mask & Data -WO */ | |
64 | #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) | |
65 | /* MSW Mask & Data -WO */ | |
66 | #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) | |
67 | /* Data Register-RW */ | |
06aa0908 | 68 | #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) |
3242ba11 HK |
69 | #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) |
70 | /* Direction mode reg-RW */ | |
71 | #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) | |
72 | /* Output enable reg-RW */ | |
73 | #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) | |
74 | /* Interrupt mask reg-RO */ | |
75 | #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) | |
76 | /* Interrupt enable reg-WO */ | |
77 | #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) | |
78 | /* Interrupt disable reg-WO */ | |
79 | #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) | |
80 | /* Interrupt status reg-RO */ | |
81 | #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) | |
82 | /* Interrupt type reg-RW */ | |
83 | #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) | |
84 | /* Interrupt polarity reg-RW */ | |
85 | #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) | |
86 | /* Interrupt on any, reg-RW */ | |
87 | #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) | |
88 | ||
89 | /* Disable all interrupts mask */ | |
90 | #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF | |
91 | ||
92 | /* Mid pin number of a bank */ | |
93 | #define ZYNQ_GPIO_MID_PIN_NUM 16 | |
94 | ||
95 | /* GPIO upper 16 bit mask */ | |
96 | #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 | |
97 | ||
3638bd4a SB |
98 | /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ |
99 | #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) | |
06aa0908 | 100 | #define GPIO_QUIRK_DATA_RO_BUG BIT(1) |
67500244 | 101 | #define GPIO_QUIRK_VERSAL BIT(2) |
e3296f19 | 102 | |
e11de4de SD |
103 | struct gpio_regs { |
104 | u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; | |
105 | u32 datalsw[ZYNQMP_GPIO_MAX_BANK]; | |
106 | u32 dirm[ZYNQMP_GPIO_MAX_BANK]; | |
107 | u32 outen[ZYNQMP_GPIO_MAX_BANK]; | |
108 | u32 int_en[ZYNQMP_GPIO_MAX_BANK]; | |
109 | u32 int_dis[ZYNQMP_GPIO_MAX_BANK]; | |
110 | u32 int_type[ZYNQMP_GPIO_MAX_BANK]; | |
111 | u32 int_polarity[ZYNQMP_GPIO_MAX_BANK]; | |
112 | u32 int_any[ZYNQMP_GPIO_MAX_BANK]; | |
113 | }; | |
eb73d6ea | 114 | |
3242ba11 HK |
115 | /** |
116 | * struct zynq_gpio - gpio device private data structure | |
117 | * @chip: instance of the gpio_chip | |
118 | * @base_addr: base address of the GPIO device | |
119 | * @clk: clock resource for this controller | |
59e22114 | 120 | * @irq: interrupt for the GPIO device |
bdf7a4ae | 121 | * @p_data: pointer to platform data |
e11de4de | 122 | * @context: context registers |
fdcfec11 | 123 | * @dirlock: lock used for direction in/out synchronization |
3242ba11 HK |
124 | */ |
125 | struct zynq_gpio { | |
126 | struct gpio_chip chip; | |
127 | void __iomem *base_addr; | |
128 | struct clk *clk; | |
59e22114 | 129 | int irq; |
bdf7a4ae | 130 | const struct zynq_platform_data *p_data; |
e11de4de | 131 | struct gpio_regs context; |
fdcfec11 | 132 | spinlock_t dirlock; /* lock */ |
bdf7a4ae AKV |
133 | }; |
134 | ||
135 | /** | |
136 | * struct zynq_platform_data - zynq gpio platform data structure | |
137 | * @label: string to store in gpio->label | |
6ae5104c | 138 | * @quirks: Flags is used to identify the platform |
bdf7a4ae AKV |
139 | * @ngpio: max number of gpio pins |
140 | * @max_bank: maximum number of gpio banks | |
141 | * @bank_min: this array represents bank's min pin | |
142 | * @bank_max: this array represents bank's max pin | |
6ae5104c | 143 | */ |
bdf7a4ae AKV |
144 | struct zynq_platform_data { |
145 | const char *label; | |
e3296f19 | 146 | u32 quirks; |
bdf7a4ae AKV |
147 | u16 ngpio; |
148 | int max_bank; | |
149 | int bank_min[ZYNQMP_GPIO_MAX_BANK]; | |
150 | int bank_max[ZYNQMP_GPIO_MAX_BANK]; | |
3242ba11 HK |
151 | }; |
152 | ||
6dd85950 LPC |
153 | static struct irq_chip zynq_gpio_level_irqchip; |
154 | static struct irq_chip zynq_gpio_edge_irqchip; | |
fa9795d1 | 155 | |
3638bd4a SB |
156 | /** |
157 | * zynq_gpio_is_zynq - test if HW is zynq or zynqmp | |
158 | * @gpio: Pointer to driver data struct | |
159 | * | |
160 | * Return: 0 if zynqmp, 1 if zynq. | |
161 | */ | |
162 | static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) | |
163 | { | |
164 | return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); | |
165 | } | |
166 | ||
06aa0908 SM |
167 | /** |
168 | * gpio_data_ro_bug - test if HW bug exists or not | |
169 | * @gpio: Pointer to driver data struct | |
170 | * | |
171 | * Return: 0 if bug doesnot exist, 1 if bug exists. | |
172 | */ | |
173 | static int gpio_data_ro_bug(struct zynq_gpio *gpio) | |
174 | { | |
175 | return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); | |
176 | } | |
177 | ||
3242ba11 HK |
178 | /** |
179 | * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank | |
180 | * for a given pin in the GPIO device | |
181 | * @pin_num: gpio pin number within the device | |
182 | * @bank_num: an output parameter used to return the bank number of the gpio | |
183 | * pin | |
184 | * @bank_pin_num: an output parameter used to return pin number within a bank | |
185 | * for the given gpio pin | |
6ae5104c | 186 | * @gpio: gpio device data structure |
3242ba11 HK |
187 | * |
188 | * Returns the bank number and pin offset within the bank. | |
189 | */ | |
190 | static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, | |
191 | unsigned int *bank_num, | |
bdf7a4ae AKV |
192 | unsigned int *bank_pin_num, |
193 | struct zynq_gpio *gpio) | |
3242ba11 | 194 | { |
bdf7a4ae AKV |
195 | int bank; |
196 | ||
197 | for (bank = 0; bank < gpio->p_data->max_bank; bank++) { | |
198 | if ((pin_num >= gpio->p_data->bank_min[bank]) && | |
16ee62e5 | 199 | (pin_num <= gpio->p_data->bank_max[bank])) { |
2717cfca NM |
200 | *bank_num = bank; |
201 | *bank_pin_num = pin_num - | |
202 | gpio->p_data->bank_min[bank]; | |
203 | return; | |
bdf7a4ae | 204 | } |
67500244 SD |
205 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
206 | bank = bank + VERSAL_UNUSED_BANKS; | |
3242ba11 | 207 | } |
3242ba11 | 208 | |
bdf7a4ae AKV |
209 | /* default */ |
210 | WARN(true, "invalid GPIO pin number: %u", pin_num); | |
211 | *bank_num = 0; | |
212 | *bank_pin_num = 0; | |
213 | } | |
016da144 | 214 | |
3242ba11 HK |
215 | /** |
216 | * zynq_gpio_get_value - Get the state of the specified pin of GPIO device | |
217 | * @chip: gpio_chip instance to be worked on | |
218 | * @pin: gpio pin number within the device | |
219 | * | |
220 | * This function reads the state of the specified pin of the GPIO device. | |
221 | * | |
222 | * Return: 0 if the pin is low, 1 if pin is high. | |
223 | */ | |
224 | static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) | |
225 | { | |
226 | u32 data; | |
227 | unsigned int bank_num, bank_pin_num; | |
31a89447 | 228 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 229 | |
bdf7a4ae | 230 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 | 231 | |
06aa0908 SM |
232 | if (gpio_data_ro_bug(gpio)) { |
233 | if (zynq_gpio_is_zynq(gpio)) { | |
234 | if (bank_num <= 1) { | |
235 | data = readl_relaxed(gpio->base_addr + | |
236 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
237 | } else { | |
238 | data = readl_relaxed(gpio->base_addr + | |
239 | ZYNQ_GPIO_DATA_OFFSET(bank_num)); | |
240 | } | |
241 | } else { | |
242 | if (bank_num <= 2) { | |
243 | data = readl_relaxed(gpio->base_addr + | |
244 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
245 | } else { | |
246 | data = readl_relaxed(gpio->base_addr + | |
247 | ZYNQ_GPIO_DATA_OFFSET(bank_num)); | |
248 | } | |
249 | } | |
250 | } else { | |
251 | data = readl_relaxed(gpio->base_addr + | |
252 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); | |
253 | } | |
3242ba11 HK |
254 | return (data >> bank_pin_num) & 1; |
255 | } | |
256 | ||
257 | /** | |
258 | * zynq_gpio_set_value - Modify the state of the pin with specified value | |
259 | * @chip: gpio_chip instance to be worked on | |
260 | * @pin: gpio pin number within the device | |
261 | * @state: value used to modify the state of the specified pin | |
262 | * | |
263 | * This function calculates the register offset (i.e to lower 16 bits or | |
264 | * upper 16 bits) based on the given pin number and sets the state of a | |
265 | * gpio pin to the specified value. The state is either 0 or non-zero. | |
266 | */ | |
267 | static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, | |
268 | int state) | |
269 | { | |
270 | unsigned int reg_offset, bank_num, bank_pin_num; | |
31a89447 | 271 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 272 | |
bdf7a4ae | 273 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
274 | |
275 | if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { | |
276 | /* only 16 data bits in bit maskable reg */ | |
277 | bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; | |
278 | reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); | |
279 | } else { | |
280 | reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); | |
281 | } | |
282 | ||
283 | /* | |
284 | * get the 32 bit value to be written to the mask/data register where | |
285 | * the upper 16 bits is the mask and lower 16 bits is the data | |
286 | */ | |
287 | state = !!state; | |
288 | state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & | |
289 | ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); | |
290 | ||
291 | writel_relaxed(state, gpio->base_addr + reg_offset); | |
292 | } | |
293 | ||
294 | /** | |
295 | * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input | |
296 | * @chip: gpio_chip instance to be worked on | |
297 | * @pin: gpio pin number within the device | |
298 | * | |
299 | * This function uses the read-modify-write sequence to set the direction of | |
300 | * the gpio pin as input. | |
301 | * | |
302 | * Return: 0 always | |
303 | */ | |
304 | static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) | |
305 | { | |
306 | u32 reg; | |
307 | unsigned int bank_num, bank_pin_num; | |
fdcfec11 | 308 | unsigned long flags; |
31a89447 | 309 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 310 | |
bdf7a4ae | 311 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 | 312 | |
e3296f19 NM |
313 | /* |
314 | * On zynq bank 0 pins 7 and 8 are special and cannot be used | |
315 | * as inputs. | |
316 | */ | |
3638bd4a | 317 | if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && |
16ee62e5 | 318 | (bank_pin_num == 7 || bank_pin_num == 8)) |
3242ba11 HK |
319 | return -EINVAL; |
320 | ||
321 | /* clear the bit in direction mode reg to set the pin as input */ | |
fdcfec11 | 322 | spin_lock_irqsave(&gpio->dirlock, flags); |
3242ba11 HK |
323 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
324 | reg &= ~BIT(bank_pin_num); | |
325 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
fdcfec11 | 326 | spin_unlock_irqrestore(&gpio->dirlock, flags); |
3242ba11 HK |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | /** | |
332 | * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output | |
333 | * @chip: gpio_chip instance to be worked on | |
334 | * @pin: gpio pin number within the device | |
335 | * @state: value to be written to specified pin | |
336 | * | |
337 | * This function sets the direction of specified GPIO pin as output, configures | |
338 | * the Output Enable register for the pin and uses zynq_gpio_set to set | |
339 | * the state of the pin to the value specified. | |
340 | * | |
341 | * Return: 0 always | |
342 | */ | |
343 | static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, | |
344 | int state) | |
345 | { | |
346 | u32 reg; | |
347 | unsigned int bank_num, bank_pin_num; | |
fdcfec11 | 348 | unsigned long flags; |
31a89447 | 349 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
3242ba11 | 350 | |
bdf7a4ae | 351 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
352 | |
353 | /* set the GPIO pin as output */ | |
fdcfec11 | 354 | spin_lock_irqsave(&gpio->dirlock, flags); |
3242ba11 HK |
355 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
356 | reg |= BIT(bank_pin_num); | |
357 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
358 | ||
359 | /* configure the output enable reg for the pin */ | |
360 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); | |
361 | reg |= BIT(bank_pin_num); | |
362 | writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); | |
fdcfec11 | 363 | spin_unlock_irqrestore(&gpio->dirlock, flags); |
3242ba11 HK |
364 | |
365 | /* set the state of the pin */ | |
366 | zynq_gpio_set_value(chip, pin, state); | |
367 | return 0; | |
368 | } | |
369 | ||
6169005c BM |
370 | /** |
371 | * zynq_gpio_get_direction - Read the direction of the specified GPIO pin | |
372 | * @chip: gpio_chip instance to be worked on | |
373 | * @pin: gpio pin number within the device | |
374 | * | |
375 | * This function returns the direction of the specified GPIO. | |
376 | * | |
e42615ec | 377 | * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN |
6169005c BM |
378 | */ |
379 | static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) | |
380 | { | |
381 | u32 reg; | |
382 | unsigned int bank_num, bank_pin_num; | |
383 | struct zynq_gpio *gpio = gpiochip_get_data(chip); | |
384 | ||
385 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); | |
386 | ||
387 | reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
388 | ||
e42615ec MV |
389 | if (reg & BIT(bank_pin_num)) |
390 | return GPIO_LINE_DIRECTION_OUT; | |
391 | ||
392 | return GPIO_LINE_DIRECTION_IN; | |
6169005c BM |
393 | } |
394 | ||
3242ba11 HK |
395 | /** |
396 | * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin | |
397 | * @irq_data: per irq and chip data passed down to chip functions | |
398 | * | |
399 | * This function calculates gpio pin number from irq number and sets the | |
400 | * bit in the Interrupt Disable register of the corresponding bank to disable | |
401 | * interrupts for that pin. | |
402 | */ | |
403 | static void zynq_gpio_irq_mask(struct irq_data *irq_data) | |
404 | { | |
405 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 406 | struct zynq_gpio *gpio = |
31a89447 | 407 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
408 | |
409 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 410 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
411 | writel_relaxed(BIT(bank_pin_num), |
412 | gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
413 | } | |
414 | ||
415 | /** | |
416 | * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin | |
417 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
418 | * to enable | |
419 | * | |
420 | * This function calculates the gpio pin number from irq number and sets the | |
421 | * bit in the Interrupt Enable register of the corresponding bank to enable | |
422 | * interrupts for that pin. | |
423 | */ | |
424 | static void zynq_gpio_irq_unmask(struct irq_data *irq_data) | |
425 | { | |
426 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 427 | struct zynq_gpio *gpio = |
31a89447 | 428 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
429 | |
430 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 431 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
432 | writel_relaxed(BIT(bank_pin_num), |
433 | gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); | |
434 | } | |
435 | ||
190dc2e6 LPC |
436 | /** |
437 | * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin | |
438 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
439 | * to ack | |
440 | * | |
441 | * This function calculates gpio pin number from irq number and sets the bit | |
442 | * in the Interrupt Status Register of the corresponding bank, to ACK the irq. | |
443 | */ | |
444 | static void zynq_gpio_irq_ack(struct irq_data *irq_data) | |
445 | { | |
446 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 447 | struct zynq_gpio *gpio = |
31a89447 | 448 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
190dc2e6 LPC |
449 | |
450 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 451 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
190dc2e6 LPC |
452 | writel_relaxed(BIT(bank_pin_num), |
453 | gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); | |
454 | } | |
455 | ||
456 | /** | |
457 | * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin | |
458 | * @irq_data: irq data containing irq number of gpio pin for the interrupt | |
459 | * to enable | |
460 | * | |
20a8a968 | 461 | * Clears the INTSTS bit and unmasks the given interrupt. |
190dc2e6 LPC |
462 | */ |
463 | static void zynq_gpio_irq_enable(struct irq_data *irq_data) | |
464 | { | |
465 | /* | |
466 | * The Zynq GPIO controller does not disable interrupt detection when | |
467 | * the interrupt is masked and only disables the propagation of the | |
468 | * interrupt. This means when the controller detects an interrupt | |
469 | * condition while the interrupt is logically disabled it will propagate | |
470 | * that interrupt event once the interrupt is enabled. This will cause | |
471 | * the interrupt consumer to see spurious interrupts to prevent this | |
472 | * first make sure that the interrupt is not asserted and then enable | |
473 | * it. | |
474 | */ | |
475 | zynq_gpio_irq_ack(irq_data); | |
476 | zynq_gpio_irq_unmask(irq_data); | |
477 | } | |
478 | ||
3242ba11 HK |
479 | /** |
480 | * zynq_gpio_set_irq_type - Set the irq type for a gpio pin | |
481 | * @irq_data: irq data containing irq number of gpio pin | |
482 | * @type: interrupt type that is to be set for the gpio pin | |
483 | * | |
484 | * This function gets the gpio pin number and its bank from the gpio pin number | |
485 | * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. | |
486 | * | |
487 | * Return: 0, negative error otherwise. | |
488 | * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; | |
489 | * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; | |
490 | * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; | |
491 | * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; | |
492 | * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA | |
493 | */ | |
494 | static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) | |
495 | { | |
496 | u32 int_type, int_pol, int_any; | |
497 | unsigned int device_pin_num, bank_num, bank_pin_num; | |
fa9795d1 | 498 | struct zynq_gpio *gpio = |
31a89447 | 499 | gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); |
3242ba11 HK |
500 | |
501 | device_pin_num = irq_data->hwirq; | |
bdf7a4ae | 502 | zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); |
3242ba11 HK |
503 | |
504 | int_type = readl_relaxed(gpio->base_addr + | |
505 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
506 | int_pol = readl_relaxed(gpio->base_addr + | |
507 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
508 | int_any = readl_relaxed(gpio->base_addr + | |
509 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
510 | ||
511 | /* | |
512 | * based on the type requested, configure the INT_TYPE, INT_POLARITY | |
513 | * and INT_ANY registers | |
514 | */ | |
515 | switch (type) { | |
516 | case IRQ_TYPE_EDGE_RISING: | |
517 | int_type |= BIT(bank_pin_num); | |
518 | int_pol |= BIT(bank_pin_num); | |
519 | int_any &= ~BIT(bank_pin_num); | |
520 | break; | |
521 | case IRQ_TYPE_EDGE_FALLING: | |
522 | int_type |= BIT(bank_pin_num); | |
523 | int_pol &= ~BIT(bank_pin_num); | |
524 | int_any &= ~BIT(bank_pin_num); | |
525 | break; | |
526 | case IRQ_TYPE_EDGE_BOTH: | |
527 | int_type |= BIT(bank_pin_num); | |
528 | int_any |= BIT(bank_pin_num); | |
529 | break; | |
530 | case IRQ_TYPE_LEVEL_HIGH: | |
531 | int_type &= ~BIT(bank_pin_num); | |
532 | int_pol |= BIT(bank_pin_num); | |
533 | break; | |
534 | case IRQ_TYPE_LEVEL_LOW: | |
535 | int_type &= ~BIT(bank_pin_num); | |
536 | int_pol &= ~BIT(bank_pin_num); | |
537 | break; | |
538 | default: | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | writel_relaxed(int_type, | |
543 | gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
544 | writel_relaxed(int_pol, | |
545 | gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
546 | writel_relaxed(int_any, | |
547 | gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
6dd85950 | 548 | |
16ee62e5 | 549 | if (type & IRQ_TYPE_LEVEL_MASK) |
47c08462 | 550 | irq_set_chip_handler_name_locked(irq_data, |
16ee62e5 MS |
551 | &zynq_gpio_level_irqchip, |
552 | handle_fasteoi_irq, NULL); | |
553 | else | |
47c08462 | 554 | irq_set_chip_handler_name_locked(irq_data, |
16ee62e5 MS |
555 | &zynq_gpio_edge_irqchip, |
556 | handle_level_irq, NULL); | |
6dd85950 | 557 | |
3242ba11 HK |
558 | return 0; |
559 | } | |
560 | ||
561 | static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) | |
562 | { | |
fa9795d1 | 563 | struct zynq_gpio *gpio = |
31a89447 | 564 | gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
59e22114 ES |
565 | |
566 | irq_set_irq_wake(gpio->irq, on); | |
3242ba11 HK |
567 | |
568 | return 0; | |
569 | } | |
570 | ||
c2df3de0 TP |
571 | static int zynq_gpio_irq_reqres(struct irq_data *d) |
572 | { | |
573 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); | |
574 | int ret; | |
575 | ||
576 | ret = pm_runtime_get_sync(chip->parent); | |
577 | if (ret < 0) | |
578 | return ret; | |
579 | ||
580 | return gpiochip_reqres_irq(chip, d->hwirq); | |
581 | } | |
582 | ||
583 | static void zynq_gpio_irq_relres(struct irq_data *d) | |
584 | { | |
585 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); | |
586 | ||
587 | gpiochip_relres_irq(chip, d->hwirq); | |
588 | pm_runtime_put(chip->parent); | |
589 | } | |
590 | ||
3242ba11 | 591 | /* irq chip descriptor */ |
6dd85950 | 592 | static struct irq_chip zynq_gpio_level_irqchip = { |
3242ba11 | 593 | .name = DRIVER_NAME, |
190dc2e6 | 594 | .irq_enable = zynq_gpio_irq_enable, |
6dd85950 LPC |
595 | .irq_eoi = zynq_gpio_irq_ack, |
596 | .irq_mask = zynq_gpio_irq_mask, | |
597 | .irq_unmask = zynq_gpio_irq_unmask, | |
598 | .irq_set_type = zynq_gpio_set_irq_type, | |
599 | .irq_set_wake = zynq_gpio_set_wake, | |
c2df3de0 TP |
600 | .irq_request_resources = zynq_gpio_irq_reqres, |
601 | .irq_release_resources = zynq_gpio_irq_relres, | |
a1946778 ES |
602 | .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | |
603 | IRQCHIP_MASK_ON_SUSPEND, | |
6dd85950 LPC |
604 | }; |
605 | ||
606 | static struct irq_chip zynq_gpio_edge_irqchip = { | |
607 | .name = DRIVER_NAME, | |
608 | .irq_enable = zynq_gpio_irq_enable, | |
609 | .irq_ack = zynq_gpio_irq_ack, | |
3242ba11 HK |
610 | .irq_mask = zynq_gpio_irq_mask, |
611 | .irq_unmask = zynq_gpio_irq_unmask, | |
612 | .irq_set_type = zynq_gpio_set_irq_type, | |
613 | .irq_set_wake = zynq_gpio_set_wake, | |
c2df3de0 TP |
614 | .irq_request_resources = zynq_gpio_irq_reqres, |
615 | .irq_release_resources = zynq_gpio_irq_relres, | |
a1946778 | 616 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
3242ba11 HK |
617 | }; |
618 | ||
5a2533a7 LPC |
619 | static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, |
620 | unsigned int bank_num, | |
621 | unsigned long pending) | |
622 | { | |
bdf7a4ae | 623 | unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; |
f0fbe7bc | 624 | struct irq_domain *irqdomain = gpio->chip.irq.domain; |
5a2533a7 LPC |
625 | int offset; |
626 | ||
627 | if (!pending) | |
628 | return; | |
629 | ||
630 | for_each_set_bit(offset, &pending, 32) { | |
631 | unsigned int gpio_irq; | |
632 | ||
016da144 | 633 | gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset); |
5a2533a7 LPC |
634 | generic_handle_irq(gpio_irq); |
635 | } | |
636 | } | |
637 | ||
3242ba11 HK |
638 | /** |
639 | * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device | |
3242ba11 HK |
640 | * @desc: irq descriptor instance of the 'irq' |
641 | * | |
642 | * This function reads the Interrupt Status Register of each bank to get the | |
643 | * gpio pin number which has triggered an interrupt. It then acks the triggered | |
644 | * interrupt and calls the pin specific handler set by the higher layer | |
645 | * application for that pin. | |
646 | * Note: A bug is reported if no handler is set for the gpio pin. | |
647 | */ | |
bd0b9ac4 | 648 | static void zynq_gpio_irqhandler(struct irq_desc *desc) |
3242ba11 HK |
649 | { |
650 | u32 int_sts, int_enb; | |
651 | unsigned int bank_num; | |
fa9795d1 | 652 | struct zynq_gpio *gpio = |
31a89447 | 653 | gpiochip_get_data(irq_desc_get_handler_data(desc)); |
3242ba11 HK |
654 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
655 | ||
656 | chained_irq_enter(irqchip, desc); | |
657 | ||
bdf7a4ae | 658 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { |
3242ba11 HK |
659 | int_sts = readl_relaxed(gpio->base_addr + |
660 | ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); | |
661 | int_enb = readl_relaxed(gpio->base_addr + | |
662 | ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); | |
5a2533a7 | 663 | zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); |
67500244 SD |
664 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
665 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
3242ba11 HK |
666 | } |
667 | ||
668 | chained_irq_exit(irqchip, desc); | |
669 | } | |
670 | ||
e11de4de SD |
671 | static void zynq_gpio_save_context(struct zynq_gpio *gpio) |
672 | { | |
673 | unsigned int bank_num; | |
674 | ||
675 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { | |
676 | gpio->context.datalsw[bank_num] = | |
677 | readl_relaxed(gpio->base_addr + | |
678 | ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); | |
679 | gpio->context.datamsw[bank_num] = | |
680 | readl_relaxed(gpio->base_addr + | |
681 | ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); | |
682 | gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + | |
683 | ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
684 | gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + | |
685 | ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); | |
686 | gpio->context.int_type[bank_num] = | |
687 | readl_relaxed(gpio->base_addr + | |
688 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
689 | gpio->context.int_polarity[bank_num] = | |
690 | readl_relaxed(gpio->base_addr + | |
691 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
692 | gpio->context.int_any[bank_num] = | |
693 | readl_relaxed(gpio->base_addr + | |
694 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
67500244 SD |
695 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
696 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
e11de4de SD |
697 | } |
698 | } | |
699 | ||
700 | static void zynq_gpio_restore_context(struct zynq_gpio *gpio) | |
701 | { | |
702 | unsigned int bank_num; | |
703 | ||
704 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { | |
36f2e720 SM |
705 | writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + |
706 | ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
e11de4de SD |
707 | writel_relaxed(gpio->context.datalsw[bank_num], |
708 | gpio->base_addr + | |
709 | ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); | |
710 | writel_relaxed(gpio->context.datamsw[bank_num], | |
711 | gpio->base_addr + | |
712 | ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); | |
713 | writel_relaxed(gpio->context.dirm[bank_num], | |
714 | gpio->base_addr + | |
715 | ZYNQ_GPIO_DIRM_OFFSET(bank_num)); | |
e11de4de SD |
716 | writel_relaxed(gpio->context.int_type[bank_num], |
717 | gpio->base_addr + | |
718 | ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); | |
719 | writel_relaxed(gpio->context.int_polarity[bank_num], | |
720 | gpio->base_addr + | |
721 | ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); | |
722 | writel_relaxed(gpio->context.int_any[bank_num], | |
723 | gpio->base_addr + | |
724 | ZYNQ_GPIO_INTANY_OFFSET(bank_num)); | |
36f2e720 SM |
725 | writel_relaxed(~(gpio->context.int_en[bank_num]), |
726 | gpio->base_addr + | |
727 | ZYNQ_GPIO_INTEN_OFFSET(bank_num)); | |
67500244 SD |
728 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
729 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
e11de4de SD |
730 | } |
731 | } | |
eb73d6ea | 732 | |
3242ba11 HK |
733 | static int __maybe_unused zynq_gpio_suspend(struct device *dev) |
734 | { | |
a76e865e | 735 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
5e3a8ecd | 736 | struct irq_data *data = irq_get_irq_data(gpio->irq); |
59e22114 | 737 | |
26ebdbf8 SD |
738 | if (!device_may_wakeup(dev)) |
739 | disable_irq(gpio->irq); | |
740 | ||
e11de4de SD |
741 | if (!irqd_is_wakeup_set(data)) { |
742 | zynq_gpio_save_context(gpio); | |
3242ba11 | 743 | return pm_runtime_force_suspend(dev); |
e11de4de | 744 | } |
3242ba11 HK |
745 | |
746 | return 0; | |
747 | } | |
748 | ||
749 | static int __maybe_unused zynq_gpio_resume(struct device *dev) | |
750 | { | |
a76e865e | 751 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
5e3a8ecd | 752 | struct irq_data *data = irq_get_irq_data(gpio->irq); |
e11de4de | 753 | int ret; |
59e22114 | 754 | |
26ebdbf8 SD |
755 | if (!device_may_wakeup(dev)) |
756 | enable_irq(gpio->irq); | |
757 | ||
e11de4de SD |
758 | if (!irqd_is_wakeup_set(data)) { |
759 | ret = pm_runtime_force_resume(dev); | |
760 | zynq_gpio_restore_context(gpio); | |
761 | return ret; | |
762 | } | |
3242ba11 HK |
763 | |
764 | return 0; | |
765 | } | |
766 | ||
767 | static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) | |
768 | { | |
38ccad02 | 769 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
3242ba11 HK |
770 | |
771 | clk_disable_unprepare(gpio->clk); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) | |
777 | { | |
38ccad02 | 778 | struct zynq_gpio *gpio = dev_get_drvdata(dev); |
3242ba11 HK |
779 | |
780 | return clk_prepare_enable(gpio->clk); | |
781 | } | |
782 | ||
2717cfca | 783 | static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset) |
3242ba11 HK |
784 | { |
785 | int ret; | |
786 | ||
58383c78 | 787 | ret = pm_runtime_get_sync(chip->parent); |
3242ba11 HK |
788 | |
789 | /* | |
790 | * If the device is already active pm_runtime_get() will return 1 on | |
791 | * success, but gpio_request still needs to return 0. | |
792 | */ | |
793 | return ret < 0 ? ret : 0; | |
794 | } | |
795 | ||
2717cfca | 796 | static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset) |
3242ba11 | 797 | { |
58383c78 | 798 | pm_runtime_put(chip->parent); |
3242ba11 HK |
799 | } |
800 | ||
801 | static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { | |
802 | SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) | |
6ed23b80 | 803 | SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, |
16ee62e5 | 804 | zynq_gpio_runtime_resume, NULL) |
3242ba11 HK |
805 | }; |
806 | ||
67500244 SD |
807 | static const struct zynq_platform_data versal_gpio_def = { |
808 | .label = "versal_gpio", | |
809 | .quirks = GPIO_QUIRK_VERSAL, | |
810 | .ngpio = 58, | |
811 | .max_bank = VERSAL_GPIO_MAX_BANK, | |
812 | .bank_min[0] = 0, | |
813 | .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ | |
814 | .bank_min[3] = 26, | |
815 | .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ | |
816 | }; | |
817 | ||
bdf7a4ae AKV |
818 | static const struct zynq_platform_data zynqmp_gpio_def = { |
819 | .label = "zynqmp_gpio", | |
06aa0908 | 820 | .quirks = GPIO_QUIRK_DATA_RO_BUG, |
bdf7a4ae AKV |
821 | .ngpio = ZYNQMP_GPIO_NR_GPIOS, |
822 | .max_bank = ZYNQMP_GPIO_MAX_BANK, | |
823 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), | |
824 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), | |
825 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), | |
826 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), | |
827 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), | |
828 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), | |
829 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), | |
830 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), | |
831 | .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), | |
832 | .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), | |
833 | .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), | |
834 | .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), | |
835 | }; | |
836 | ||
837 | static const struct zynq_platform_data zynq_gpio_def = { | |
838 | .label = "zynq_gpio", | |
06aa0908 | 839 | .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, |
bdf7a4ae AKV |
840 | .ngpio = ZYNQ_GPIO_NR_GPIOS, |
841 | .max_bank = ZYNQ_GPIO_MAX_BANK, | |
842 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), | |
843 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), | |
844 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), | |
845 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), | |
846 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), | |
847 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), | |
848 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), | |
849 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), | |
850 | }; | |
851 | ||
852 | static const struct of_device_id zynq_gpio_of_match[] = { | |
7808c42b MY |
853 | { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, |
854 | { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, | |
67500244 | 855 | { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, |
bdf7a4ae AKV |
856 | { /* end of table */ } |
857 | }; | |
858 | MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); | |
859 | ||
3242ba11 HK |
860 | /** |
861 | * zynq_gpio_probe - Initialization method for a zynq_gpio device | |
862 | * @pdev: platform device instance | |
863 | * | |
864 | * This function allocates memory resources for the gpio device and registers | |
865 | * all the banks of the device. It will also set up interrupts for the gpio | |
866 | * pins. | |
867 | * Note: Interrupts are disabled for all the banks during initialization. | |
868 | * | |
869 | * Return: 0 on success, negative error otherwise. | |
870 | */ | |
871 | static int zynq_gpio_probe(struct platform_device *pdev) | |
872 | { | |
59e22114 | 873 | int ret, bank_num; |
3242ba11 HK |
874 | struct zynq_gpio *gpio; |
875 | struct gpio_chip *chip; | |
f6a7053d | 876 | struct gpio_irq_chip *girq; |
bdf7a4ae | 877 | const struct of_device_id *match; |
3242ba11 HK |
878 | |
879 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
880 | if (!gpio) | |
881 | return -ENOMEM; | |
882 | ||
bdf7a4ae AKV |
883 | match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); |
884 | if (!match) { | |
885 | dev_err(&pdev->dev, "of_match_node() failed\n"); | |
886 | return -EINVAL; | |
887 | } | |
888 | gpio->p_data = match->data; | |
3242ba11 HK |
889 | platform_set_drvdata(pdev, gpio); |
890 | ||
77bc0e69 | 891 | gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); |
3242ba11 HK |
892 | if (IS_ERR(gpio->base_addr)) |
893 | return PTR_ERR(gpio->base_addr); | |
894 | ||
59e22114 | 895 | gpio->irq = platform_get_irq(pdev, 0); |
15bddb7d | 896 | if (gpio->irq < 0) |
59e22114 | 897 | return gpio->irq; |
3242ba11 HK |
898 | |
899 | /* configure the gpio chip */ | |
900 | chip = &gpio->chip; | |
bdf7a4ae | 901 | chip->label = gpio->p_data->label; |
3242ba11 | 902 | chip->owner = THIS_MODULE; |
58383c78 | 903 | chip->parent = &pdev->dev; |
3242ba11 HK |
904 | chip->get = zynq_gpio_get_value; |
905 | chip->set = zynq_gpio_set_value; | |
906 | chip->request = zynq_gpio_request; | |
907 | chip->free = zynq_gpio_free; | |
908 | chip->direction_input = zynq_gpio_dir_in; | |
909 | chip->direction_output = zynq_gpio_dir_out; | |
6169005c | 910 | chip->get_direction = zynq_gpio_get_direction; |
060f3ebf | 911 | chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); |
bdf7a4ae | 912 | chip->ngpio = gpio->p_data->ngpio; |
3242ba11 | 913 | |
3773c195 | 914 | /* Retrieve GPIO clock */ |
3242ba11 HK |
915 | gpio->clk = devm_clk_get(&pdev->dev, NULL); |
916 | if (IS_ERR(gpio->clk)) { | |
917 | dev_err(&pdev->dev, "input clock not found.\n"); | |
918 | return PTR_ERR(gpio->clk); | |
919 | } | |
0f84f29f HG |
920 | ret = clk_prepare_enable(gpio->clk); |
921 | if (ret) { | |
922 | dev_err(&pdev->dev, "Unable to enable clock.\n"); | |
923 | return ret; | |
924 | } | |
3773c195 | 925 | |
fdcfec11 GL |
926 | spin_lock_init(&gpio->dirlock); |
927 | ||
0f84f29f | 928 | pm_runtime_set_active(&pdev->dev); |
3773c195 MS |
929 | pm_runtime_enable(&pdev->dev); |
930 | ret = pm_runtime_get_sync(&pdev->dev); | |
931 | if (ret < 0) | |
615d23f8 | 932 | goto err_pm_dis; |
3242ba11 | 933 | |
3242ba11 | 934 | /* disable interrupts for all banks */ |
67500244 | 935 | for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { |
3242ba11 HK |
936 | writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + |
937 | ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); | |
67500244 SD |
938 | if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) |
939 | bank_num = bank_num + VERSAL_UNUSED_BANKS; | |
940 | } | |
3242ba11 | 941 | |
f6a7053d LW |
942 | /* Set up the GPIO irqchip */ |
943 | girq = &chip->irq; | |
944 | girq->chip = &zynq_gpio_edge_irqchip; | |
945 | girq->parent_handler = zynq_gpio_irqhandler; | |
946 | girq->num_parents = 1; | |
947 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
948 | sizeof(*girq->parents), | |
949 | GFP_KERNEL); | |
950 | if (!girq->parents) { | |
951 | ret = -ENOMEM; | |
952 | goto err_pm_put; | |
3242ba11 | 953 | } |
f6a7053d LW |
954 | girq->parents[0] = gpio->irq; |
955 | girq->default_type = IRQ_TYPE_NONE; | |
956 | girq->handler = handle_level_irq; | |
3242ba11 | 957 | |
f6a7053d LW |
958 | /* report a bug if gpio chip registration fails */ |
959 | ret = gpiochip_add_data(chip, gpio); | |
960 | if (ret) { | |
961 | dev_err(&pdev->dev, "Failed to add gpio chip\n"); | |
962 | goto err_pm_put; | |
963 | } | |
3242ba11 | 964 | |
26ebdbf8 SD |
965 | irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY); |
966 | device_init_wakeup(&pdev->dev, 1); | |
3773c195 | 967 | pm_runtime_put(&pdev->dev); |
3242ba11 | 968 | |
3242ba11 HK |
969 | return 0; |
970 | ||
3773c195 MS |
971 | err_pm_put: |
972 | pm_runtime_put(&pdev->dev); | |
615d23f8 SD |
973 | err_pm_dis: |
974 | pm_runtime_disable(&pdev->dev); | |
0f84f29f | 975 | clk_disable_unprepare(gpio->clk); |
3242ba11 HK |
976 | |
977 | return ret; | |
978 | } | |
979 | ||
980 | /** | |
981 | * zynq_gpio_remove - Driver removal function | |
982 | * @pdev: platform device instance | |
983 | * | |
984 | * Return: 0 always | |
985 | */ | |
986 | static int zynq_gpio_remove(struct platform_device *pdev) | |
987 | { | |
3242ba11 HK |
988 | struct zynq_gpio *gpio = platform_get_drvdata(pdev); |
989 | ||
990 | pm_runtime_get_sync(&pdev->dev); | |
da26d5d8 | 991 | gpiochip_remove(&gpio->chip); |
3242ba11 HK |
992 | clk_disable_unprepare(gpio->clk); |
993 | device_set_wakeup_capable(&pdev->dev, 0); | |
6b956af0 | 994 | pm_runtime_disable(&pdev->dev); |
3242ba11 HK |
995 | return 0; |
996 | } | |
997 | ||
3242ba11 HK |
998 | static struct platform_driver zynq_gpio_driver = { |
999 | .driver = { | |
1000 | .name = DRIVER_NAME, | |
3242ba11 HK |
1001 | .pm = &zynq_gpio_dev_pm_ops, |
1002 | .of_match_table = zynq_gpio_of_match, | |
1003 | }, | |
1004 | .probe = zynq_gpio_probe, | |
1005 | .remove = zynq_gpio_remove, | |
1006 | }; | |
1007 | ||
1008 | /** | |
1009 | * zynq_gpio_init - Initial driver registration call | |
1010 | * | |
1011 | * Return: value from platform_driver_register | |
1012 | */ | |
1013 | static int __init zynq_gpio_init(void) | |
1014 | { | |
1015 | return platform_driver_register(&zynq_gpio_driver); | |
1016 | } | |
1017 | postcore_initcall(zynq_gpio_init); | |
1018 | ||
80d2bf55 MY |
1019 | static void __exit zynq_gpio_exit(void) |
1020 | { | |
1021 | platform_driver_unregister(&zynq_gpio_driver); | |
1022 | } | |
1023 | module_exit(zynq_gpio_exit); | |
1024 | ||
3242ba11 HK |
1025 | MODULE_AUTHOR("Xilinx Inc."); |
1026 | MODULE_DESCRIPTION("Zynq GPIO driver"); | |
1027 | MODULE_LICENSE("GPL"); |