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gpio: zynq: Provided workaround for GPIO
[linux-block.git] / drivers / gpio / gpio-zynq.c
CommitLineData
3242ba11
HK		 1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
bdf7a4ae 21#include <linux/of.h>
3242ba11
HK		 22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
bdf7a4ae 27#define ZYNQMP_GPIO_MAX_BANK 6
3242ba11
HK		 28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
bdf7a4ae
AKV		 34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
3242ba11
HK		 62
63
64/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */
06aa0908 70#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
3242ba11
HK		 71#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
72/* Direction mode reg-RW */
73#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
74/* Output enable reg-RW */
75#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
76/* Interrupt mask reg-RO */
77#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
78/* Interrupt enable reg-WO */
79#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
80/* Interrupt disable reg-WO */
81#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
82/* Interrupt status reg-RO */
83#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
84/* Interrupt type reg-RW */
85#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
86/* Interrupt polarity reg-RW */
87#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
88/* Interrupt on any, reg-RW */
89#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
90
91/* Disable all interrupts mask */
92#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
93
94/* Mid pin number of a bank */
95#define ZYNQ_GPIO_MID_PIN_NUM 16
96
97/* GPIO upper 16 bit mask */
98#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
99
3638bd4a
SB		 100/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
101#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
06aa0908 102#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
e3296f19 103
e11de4de
SD		 104struct gpio_regs {
105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
107 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
108 u32 outen[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
114};
3242ba11
HK		 115/**
116 * struct zynq_gpio - gpio device private data structure
117 * @chip: instance of the gpio_chip
118 * @base_addr: base address of the GPIO device
119 * @clk: clock resource for this controller
59e22114 120 * @irq: interrupt for the GPIO device
bdf7a4ae 121 * @p_data: pointer to platform data
e11de4de 122 * @context: context registers
3242ba11
HK		 123 */
124struct zynq_gpio {
125 struct gpio_chip chip;
126 void __iomem *base_addr;
127 struct clk *clk;
59e22114 128 int irq;
bdf7a4ae 129 const struct zynq_platform_data *p_data;
e11de4de 130 struct gpio_regs context;
bdf7a4ae
AKV		 131};
132
133/**
134 * struct zynq_platform_data - zynq gpio platform data structure
135 * @label: string to store in gpio->label
136 * @ngpio: max number of gpio pins
137 * @max_bank: maximum number of gpio banks
138 * @bank_min: this array represents bank's min pin
139 * @bank_max: this array represents bank's max pin
140*/
141struct zynq_platform_data {
142 const char *label;
e3296f19 143 u32 quirks;
bdf7a4ae
AKV		 144 u16 ngpio;
145 int max_bank;
146 int bank_min[ZYNQMP_GPIO_MAX_BANK];
147 int bank_max[ZYNQMP_GPIO_MAX_BANK];
3242ba11
HK		 148};
149
6dd85950
LPC		 150static struct irq_chip zynq_gpio_level_irqchip;
151static struct irq_chip zynq_gpio_edge_irqchip;
fa9795d1 152
3638bd4a
SB		 153/**
154 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
155 * @gpio: Pointer to driver data struct
156 *
157 * Return: 0 if zynqmp, 1 if zynq.
158 */
159static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
160{
161 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
162}
163
06aa0908
SM		 164/**
165 * gpio_data_ro_bug - test if HW bug exists or not
166 * @gpio: Pointer to driver data struct
167 *
168 * Return: 0 if bug doesnot exist, 1 if bug exists.
169 */
170static int gpio_data_ro_bug(struct zynq_gpio *gpio)
171{
172 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
173}
174
3242ba11
HK		 175/**
176 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
177 * for a given pin in the GPIO device
178 * @pin_num: gpio pin number within the device
179 * @bank_num: an output parameter used to return the bank number of the gpio
180 * pin
181 * @bank_pin_num: an output parameter used to return pin number within a bank
182 * for the given gpio pin
183 *
184 * Returns the bank number and pin offset within the bank.
185 */
186static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
187 unsigned int *bank_num,
bdf7a4ae
AKV		 188 unsigned int *bank_pin_num,
189 struct zynq_gpio *gpio)
3242ba11 190{
bdf7a4ae
AKV		 191 int bank;
192
193 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
194 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
195 (pin_num <= gpio->p_data->bank_max[bank])) {
196 *bank_num = bank;
197 *bank_pin_num = pin_num -
198 gpio->p_data->bank_min[bank];
199 return;
200 }
3242ba11 201 }
3242ba11 202
bdf7a4ae
AKV		 203 /* default */
204 WARN(true, "invalid GPIO pin number: %u", pin_num);
205 *bank_num = 0;
206 *bank_pin_num = 0;
207}
016da144 208
3242ba11
HK		 209/**
210 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
211 * @chip: gpio_chip instance to be worked on
212 * @pin: gpio pin number within the device
213 *
214 * This function reads the state of the specified pin of the GPIO device.
215 *
216 * Return: 0 if the pin is low, 1 if pin is high.
217 */
218static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
219{
220 u32 data;
221 unsigned int bank_num, bank_pin_num;
31a89447 222 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 223
bdf7a4ae 224 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 225
06aa0908
SM		 226 if (gpio_data_ro_bug(gpio)) {
227 if (zynq_gpio_is_zynq(gpio)) {
228 if (bank_num <= 1) {
229 data = readl_relaxed(gpio->base_addr +
230 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
231 } else {
232 data = readl_relaxed(gpio->base_addr +
233 ZYNQ_GPIO_DATA_OFFSET(bank_num));
234 }
235 } else {
236 if (bank_num <= 2) {
237 data = readl_relaxed(gpio->base_addr +
238 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
239 } else {
240 data = readl_relaxed(gpio->base_addr +
241 ZYNQ_GPIO_DATA_OFFSET(bank_num));
242 }
243 }
244 } else {
245 data = readl_relaxed(gpio->base_addr +
246 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
247 }
3242ba11
HK		 248 return (data >> bank_pin_num) & 1;
249}
250
251/**
252 * zynq_gpio_set_value - Modify the state of the pin with specified value
253 * @chip: gpio_chip instance to be worked on
254 * @pin: gpio pin number within the device
255 * @state: value used to modify the state of the specified pin
256 *
257 * This function calculates the register offset (i.e to lower 16 bits or
258 * upper 16 bits) based on the given pin number and sets the state of a
259 * gpio pin to the specified value. The state is either 0 or non-zero.
260 */
261static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
262 int state)
263{
264 unsigned int reg_offset, bank_num, bank_pin_num;
31a89447 265 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 266
bdf7a4ae 267 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 268
269 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
270 /* only 16 data bits in bit maskable reg */
271 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
272 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
273 } else {
274 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
275 }
276
277 /*
278 * get the 32 bit value to be written to the mask/data register where
279 * the upper 16 bits is the mask and lower 16 bits is the data
280 */
281 state = !!state;
282 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
283 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
284
285 writel_relaxed(state, gpio->base_addr + reg_offset);
286}
287
288/**
289 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
290 * @chip: gpio_chip instance to be worked on
291 * @pin: gpio pin number within the device
292 *
293 * This function uses the read-modify-write sequence to set the direction of
294 * the gpio pin as input.
295 *
296 * Return: 0 always
297 */
298static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
299{
300 u32 reg;
301 unsigned int bank_num, bank_pin_num;
31a89447 302 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 303
bdf7a4ae 304 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 305
e3296f19
NM		 306 /*
307 * On zynq bank 0 pins 7 and 8 are special and cannot be used
308 * as inputs.
309 */
3638bd4a 310 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
e3296f19 311 (bank_pin_num == 7 || bank_pin_num == 8))
3242ba11
HK		 312 return -EINVAL;
313
314 /* clear the bit in direction mode reg to set the pin as input */
315 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
316 reg &= ~BIT(bank_pin_num);
317 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
318
319 return 0;
320}
321
322/**
323 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
324 * @chip: gpio_chip instance to be worked on
325 * @pin: gpio pin number within the device
326 * @state: value to be written to specified pin
327 *
328 * This function sets the direction of specified GPIO pin as output, configures
329 * the Output Enable register for the pin and uses zynq_gpio_set to set
330 * the state of the pin to the value specified.
331 *
332 * Return: 0 always
333 */
334static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
335 int state)
336{
337 u32 reg;
338 unsigned int bank_num, bank_pin_num;
31a89447 339 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 340
bdf7a4ae 341 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 342
343 /* set the GPIO pin as output */
344 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
345 reg |= BIT(bank_pin_num);
346 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
347
348 /* configure the output enable reg for the pin */
349 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
350 reg |= BIT(bank_pin_num);
351 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
352
353 /* set the state of the pin */
354 zynq_gpio_set_value(chip, pin, state);
355 return 0;
356}
357
358/**
359 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
360 * @irq_data: per irq and chip data passed down to chip functions
361 *
362 * This function calculates gpio pin number from irq number and sets the
363 * bit in the Interrupt Disable register of the corresponding bank to disable
364 * interrupts for that pin.
365 */
366static void zynq_gpio_irq_mask(struct irq_data *irq_data)
367{
368 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 369 struct zynq_gpio *gpio =
31a89447 370 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 371
372 device_pin_num = irq_data->hwirq;
bdf7a4ae 373 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 374 writel_relaxed(BIT(bank_pin_num),
375 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
376}
377
378/**
379 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
380 * @irq_data: irq data containing irq number of gpio pin for the interrupt
381 * to enable
382 *
383 * This function calculates the gpio pin number from irq number and sets the
384 * bit in the Interrupt Enable register of the corresponding bank to enable
385 * interrupts for that pin.
386 */
387static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
388{
389 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 390 struct zynq_gpio *gpio =
31a89447 391 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 392
393 device_pin_num = irq_data->hwirq;
bdf7a4ae 394 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 395 writel_relaxed(BIT(bank_pin_num),
396 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
397}
398
190dc2e6
LPC		 399/**
400 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
401 * @irq_data: irq data containing irq number of gpio pin for the interrupt
402 * to ack
403 *
404 * This function calculates gpio pin number from irq number and sets the bit
405 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
406 */
407static void zynq_gpio_irq_ack(struct irq_data *irq_data)
408{
409 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 410 struct zynq_gpio *gpio =
31a89447 411 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
190dc2e6
LPC		 412
413 device_pin_num = irq_data->hwirq;
bdf7a4ae 414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
190dc2e6
LPC		 415 writel_relaxed(BIT(bank_pin_num),
416 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
417}
418
419/**
420 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
421 * @irq_data: irq data containing irq number of gpio pin for the interrupt
422 * to enable
423 *
20a8a968 424 * Clears the INTSTS bit and unmasks the given interrupt.
190dc2e6
LPC		 425 */
426static void zynq_gpio_irq_enable(struct irq_data *irq_data)
427{
428 /*
429 * The Zynq GPIO controller does not disable interrupt detection when
430 * the interrupt is masked and only disables the propagation of the
431 * interrupt. This means when the controller detects an interrupt
432 * condition while the interrupt is logically disabled it will propagate
433 * that interrupt event once the interrupt is enabled. This will cause
434 * the interrupt consumer to see spurious interrupts to prevent this
435 * first make sure that the interrupt is not asserted and then enable
436 * it.
437 */
438 zynq_gpio_irq_ack(irq_data);
439 zynq_gpio_irq_unmask(irq_data);
440}
441
3242ba11
HK		 442/**
443 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
444 * @irq_data: irq data containing irq number of gpio pin
445 * @type: interrupt type that is to be set for the gpio pin
446 *
447 * This function gets the gpio pin number and its bank from the gpio pin number
448 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
449 *
450 * Return: 0, negative error otherwise.
451 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
452 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
453 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
454 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
455 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
456 */
457static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
458{
459 u32 int_type, int_pol, int_any;
460 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 461 struct zynq_gpio *gpio =
31a89447 462 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 463
464 device_pin_num = irq_data->hwirq;
bdf7a4ae 465 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 466
467 int_type = readl_relaxed(gpio->base_addr +
468 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
469 int_pol = readl_relaxed(gpio->base_addr +
470 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
471 int_any = readl_relaxed(gpio->base_addr +
472 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
473
474 /*
475 * based on the type requested, configure the INT_TYPE, INT_POLARITY
476 * and INT_ANY registers
477 */
478 switch (type) {
479 case IRQ_TYPE_EDGE_RISING:
480 int_type |= BIT(bank_pin_num);
481 int_pol |= BIT(bank_pin_num);
482 int_any &= ~BIT(bank_pin_num);
483 break;
484 case IRQ_TYPE_EDGE_FALLING:
485 int_type |= BIT(bank_pin_num);
486 int_pol &= ~BIT(bank_pin_num);
487 int_any &= ~BIT(bank_pin_num);
488 break;
489 case IRQ_TYPE_EDGE_BOTH:
490 int_type |= BIT(bank_pin_num);
491 int_any |= BIT(bank_pin_num);
492 break;
493 case IRQ_TYPE_LEVEL_HIGH:
494 int_type &= ~BIT(bank_pin_num);
495 int_pol |= BIT(bank_pin_num);
496 break;
497 case IRQ_TYPE_LEVEL_LOW:
498 int_type &= ~BIT(bank_pin_num);
499 int_pol &= ~BIT(bank_pin_num);
500 break;
501 default:
502 return -EINVAL;
503 }
504
505 writel_relaxed(int_type,
506 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
507 writel_relaxed(int_pol,
508 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
509 writel_relaxed(int_any,
510 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950
LPC		 511
512 if (type & IRQ_TYPE_LEVEL_MASK) {
47c08462 513 irq_set_chip_handler_name_locked(irq_data,
6dd85950
LPC		 514 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
515 } else {
47c08462 516 irq_set_chip_handler_name_locked(irq_data,
6dd85950
LPC		 517 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
518 }
519
3242ba11
HK		 520 return 0;
521}
522
523static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
524{
fa9795d1 525 struct zynq_gpio *gpio =
31a89447 526 gpiochip_get_data(irq_data_get_irq_chip_data(data));
59e22114
ES		 527
528 irq_set_irq_wake(gpio->irq, on);
3242ba11
HK		 529
530 return 0;
531}
532
533/* irq chip descriptor */
6dd85950 534static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 535 .name = DRIVER_NAME,
190dc2e6 536 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 537 .irq_eoi = zynq_gpio_irq_ack,
538 .irq_mask = zynq_gpio_irq_mask,
539 .irq_unmask = zynq_gpio_irq_unmask,
540 .irq_set_type = zynq_gpio_set_irq_type,
541 .irq_set_wake = zynq_gpio_set_wake,
a1946778
ES		 542 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
543 IRQCHIP_MASK_ON_SUSPEND,
6dd85950
LPC		 544};
545
546static struct irq_chip zynq_gpio_edge_irqchip = {
547 .name = DRIVER_NAME,
548 .irq_enable = zynq_gpio_irq_enable,
549 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 550 .irq_mask = zynq_gpio_irq_mask,
551 .irq_unmask = zynq_gpio_irq_unmask,
552 .irq_set_type = zynq_gpio_set_irq_type,
553 .irq_set_wake = zynq_gpio_set_wake,
a1946778 554 .flags = IRQCHIP_MASK_ON_SUSPEND,
3242ba11
HK		 555};
556
5a2533a7
LPC		 557static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
558 unsigned int bank_num,
559 unsigned long pending)
560{
bdf7a4ae 561 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
5a2533a7
LPC		 562 struct irq_domain *irqdomain = gpio->chip.irqdomain;
563 int offset;
564
565 if (!pending)
566 return;
567
568 for_each_set_bit(offset, &pending, 32) {
569 unsigned int gpio_irq;
570
016da144 571 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 572 generic_handle_irq(gpio_irq);
573 }
574}
575
3242ba11
HK		 576/**
577 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
578 * @irq: irq number of the gpio bank where interrupt has occurred
579 * @desc: irq descriptor instance of the 'irq'
580 *
581 * This function reads the Interrupt Status Register of each bank to get the
582 * gpio pin number which has triggered an interrupt. It then acks the triggered
583 * interrupt and calls the pin specific handler set by the higher layer
584 * application for that pin.
585 * Note: A bug is reported if no handler is set for the gpio pin.
586 */
bd0b9ac4 587static void zynq_gpio_irqhandler(struct irq_desc *desc)
3242ba11
HK		 588{
589 u32 int_sts, int_enb;
590 unsigned int bank_num;
fa9795d1 591 struct zynq_gpio *gpio =
31a89447 592 gpiochip_get_data(irq_desc_get_handler_data(desc));
3242ba11
HK		 593 struct irq_chip *irqchip = irq_desc_get_chip(desc);
594
595 chained_irq_enter(irqchip, desc);
596
bdf7a4ae 597 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
3242ba11
HK		 598 int_sts = readl_relaxed(gpio->base_addr +
599 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
600 int_enb = readl_relaxed(gpio->base_addr +
601 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 602 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
3242ba11
HK		 603 }
604
605 chained_irq_exit(irqchip, desc);
606}
607
e11de4de
SD		 608static void zynq_gpio_save_context(struct zynq_gpio *gpio)
609{
610 unsigned int bank_num;
611
612 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
613 gpio->context.datalsw[bank_num] =
614 readl_relaxed(gpio->base_addr +
615 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
616 gpio->context.datamsw[bank_num] =
617 readl_relaxed(gpio->base_addr +
618 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
619 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
620 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
621 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
622 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
623 gpio->context.int_type[bank_num] =
624 readl_relaxed(gpio->base_addr +
625 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
626 gpio->context.int_polarity[bank_num] =
627 readl_relaxed(gpio->base_addr +
628 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
629 gpio->context.int_any[bank_num] =
630 readl_relaxed(gpio->base_addr +
631 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
632 }
633}
634
635static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
636{
637 unsigned int bank_num;
638
639 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
640 writel_relaxed(gpio->context.datalsw[bank_num],
641 gpio->base_addr +
642 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
643 writel_relaxed(gpio->context.datamsw[bank_num],
644 gpio->base_addr +
645 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
646 writel_relaxed(gpio->context.dirm[bank_num],
647 gpio->base_addr +
648 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
649 writel_relaxed(gpio->context.int_en[bank_num],
650 gpio->base_addr +
651 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
652 writel_relaxed(gpio->context.int_type[bank_num],
653 gpio->base_addr +
654 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
655 writel_relaxed(gpio->context.int_polarity[bank_num],
656 gpio->base_addr +
657 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
658 writel_relaxed(gpio->context.int_any[bank_num],
659 gpio->base_addr +
660 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
661 }
662}
3242ba11
HK		 663static int __maybe_unused zynq_gpio_suspend(struct device *dev)
664{
59e22114
ES		 665 struct platform_device *pdev = to_platform_device(dev);
666 int irq = platform_get_irq(pdev, 0);
667 struct irq_data *data = irq_get_irq_data(irq);
e11de4de 668 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
59e22114 669
e11de4de
SD		 670 if (!irqd_is_wakeup_set(data)) {
671 zynq_gpio_save_context(gpio);
3242ba11 672 return pm_runtime_force_suspend(dev);
e11de4de 673 }
3242ba11
HK		 674
675 return 0;
676}
677
678static int __maybe_unused zynq_gpio_resume(struct device *dev)
679{
59e22114
ES		 680 struct platform_device *pdev = to_platform_device(dev);
681 int irq = platform_get_irq(pdev, 0);
682 struct irq_data *data = irq_get_irq_data(irq);
e11de4de
SD		 683 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
684 int ret;
59e22114 685
e11de4de
SD		 686 if (!irqd_is_wakeup_set(data)) {
687 ret = pm_runtime_force_resume(dev);
688 zynq_gpio_restore_context(gpio);
689 return ret;
690 }
3242ba11
HK		 691
692 return 0;
693}
694
695static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
696{
697 struct platform_device *pdev = to_platform_device(dev);
698 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
699
700 clk_disable_unprepare(gpio->clk);
701
702 return 0;
703}
704
705static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
706{
707 struct platform_device *pdev = to_platform_device(dev);
708 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
709
710 return clk_prepare_enable(gpio->clk);
711}
712
713static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
714{
715 int ret;
716
58383c78 717 ret = pm_runtime_get_sync(chip->parent);
3242ba11
HK		 718
719 /*
720 * If the device is already active pm_runtime_get() will return 1 on
721 * success, but gpio_request still needs to return 0.
722 */
723 return ret < 0 ? ret : 0;
724}
725
726static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
727{
58383c78 728 pm_runtime_put(chip->parent);
3242ba11
HK		 729}
730
731static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
732 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
6ed23b80 733 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
3242ba11
HK		 734 zynq_gpio_runtime_resume, NULL)
735};
736
bdf7a4ae
AKV		 737static const struct zynq_platform_data zynqmp_gpio_def = {
738 .label = "zynqmp_gpio",
06aa0908 739 .quirks = GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 740 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
741 .max_bank = ZYNQMP_GPIO_MAX_BANK,
742 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
743 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
744 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
745 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
746 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
747 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
748 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
749 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
750 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
751 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
752 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
753 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
754};
755
756static const struct zynq_platform_data zynq_gpio_def = {
757 .label = "zynq_gpio",
06aa0908 758 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 759 .ngpio = ZYNQ_GPIO_NR_GPIOS,
760 .max_bank = ZYNQ_GPIO_MAX_BANK,
761 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
762 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
763 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
764 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
765 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
766 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
767 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
768 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
769};
770
771static const struct of_device_id zynq_gpio_of_match[] = {
7808c42b
MY		 772 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
773 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
bdf7a4ae
AKV		 774 { /* end of table */ }
775};
776MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
777
3242ba11
HK		 778/**
779 * zynq_gpio_probe - Initialization method for a zynq_gpio device
780 * @pdev: platform device instance
781 *
782 * This function allocates memory resources for the gpio device and registers
783 * all the banks of the device. It will also set up interrupts for the gpio
784 * pins.
785 * Note: Interrupts are disabled for all the banks during initialization.
786 *
787 * Return: 0 on success, negative error otherwise.
788 */
789static int zynq_gpio_probe(struct platform_device *pdev)
790{
59e22114 791 int ret, bank_num;
3242ba11
HK		 792 struct zynq_gpio *gpio;
793 struct gpio_chip *chip;
794 struct resource *res;
bdf7a4ae 795 const struct of_device_id *match;
3242ba11
HK		 796
797 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
798 if (!gpio)
799 return -ENOMEM;
800
bdf7a4ae
AKV		 801 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
802 if (!match) {
803 dev_err(&pdev->dev, "of_match_node() failed\n");
804 return -EINVAL;
805 }
806 gpio->p_data = match->data;
3242ba11
HK		 807 platform_set_drvdata(pdev, gpio);
808
809 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
810 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
811 if (IS_ERR(gpio->base_addr))
812 return PTR_ERR(gpio->base_addr);
813
59e22114
ES		 814 gpio->irq = platform_get_irq(pdev, 0);
815 if (gpio->irq < 0) {
3242ba11 816 dev_err(&pdev->dev, "invalid IRQ\n");
59e22114 817 return gpio->irq;
3242ba11
HK		 818 }
819
820 /* configure the gpio chip */
821 chip = &gpio->chip;
bdf7a4ae 822 chip->label = gpio->p_data->label;
3242ba11 823 chip->owner = THIS_MODULE;
58383c78 824 chip->parent = &pdev->dev;
3242ba11
HK		 825 chip->get = zynq_gpio_get_value;
826 chip->set = zynq_gpio_set_value;
827 chip->request = zynq_gpio_request;
828 chip->free = zynq_gpio_free;
829 chip->direction_input = zynq_gpio_dir_in;
830 chip->direction_output = zynq_gpio_dir_out;
831 chip->base = -1;
bdf7a4ae 832 chip->ngpio = gpio->p_data->ngpio;
3242ba11 833
3773c195 834 /* Retrieve GPIO clock */
3242ba11
HK		 835 gpio->clk = devm_clk_get(&pdev->dev, NULL);
836 if (IS_ERR(gpio->clk)) {
837 dev_err(&pdev->dev, "input clock not found.\n");
838 return PTR_ERR(gpio->clk);
839 }
0f84f29f
HG		 840 ret = clk_prepare_enable(gpio->clk);
841 if (ret) {
842 dev_err(&pdev->dev, "Unable to enable clock.\n");
843 return ret;
844 }
3773c195 845
0f84f29f 846 pm_runtime_set_active(&pdev->dev);
3773c195
MS		 847 pm_runtime_enable(&pdev->dev);
848 ret = pm_runtime_get_sync(&pdev->dev);
849 if (ret < 0)
615d23f8 850 goto err_pm_dis;
3242ba11
HK		 851
852 /* report a bug if gpio chip registration fails */
31a89447 853 ret = gpiochip_add_data(chip, gpio);
3242ba11
HK		 854 if (ret) {
855 dev_err(&pdev->dev, "Failed to add gpio chip\n");
3773c195 856 goto err_pm_put;
3242ba11
HK		 857 }
858
859 /* disable interrupts for all banks */
bdf7a4ae 860 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
3242ba11
HK		 861 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
862 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
863
6dd85950
LPC		 864 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
865 handle_level_irq, IRQ_TYPE_NONE);
3242ba11
HK		 866 if (ret) {
867 dev_err(&pdev->dev, "Failed to add irq chip\n");
868 goto err_rm_gpiochip;
869 }
870
59e22114 871 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
3242ba11
HK		 872 zynq_gpio_irqhandler);
873
3773c195 874 pm_runtime_put(&pdev->dev);
3242ba11 875
3242ba11
HK		 876 return 0;
877
878err_rm_gpiochip:
88d5e520 879 gpiochip_remove(chip);
3773c195
MS		 880err_pm_put:
881 pm_runtime_put(&pdev->dev);
615d23f8
SD		 882err_pm_dis:
883 pm_runtime_disable(&pdev->dev);
0f84f29f 884 clk_disable_unprepare(gpio->clk);
3242ba11
HK		 885
886 return ret;
887}
888
889/**
890 * zynq_gpio_remove - Driver removal function
891 * @pdev: platform device instance
892 *
893 * Return: 0 always
894 */
895static int zynq_gpio_remove(struct platform_device *pdev)
896{
3242ba11
HK		 897 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
898
899 pm_runtime_get_sync(&pdev->dev);
da26d5d8 900 gpiochip_remove(&gpio->chip);
3242ba11
HK		 901 clk_disable_unprepare(gpio->clk);
902 device_set_wakeup_capable(&pdev->dev, 0);
6b956af0 903 pm_runtime_disable(&pdev->dev);
3242ba11
HK		 904 return 0;
905}
906
3242ba11
HK		 907static struct platform_driver zynq_gpio_driver = {
908 .driver = {
909 .name = DRIVER_NAME,
3242ba11
HK		 910 .pm = &zynq_gpio_dev_pm_ops,
911 .of_match_table = zynq_gpio_of_match,
912 },
913 .probe = zynq_gpio_probe,
914 .remove = zynq_gpio_remove,
915};
916
917/**
918 * zynq_gpio_init - Initial driver registration call
919 *
920 * Return: value from platform_driver_register
921 */
922static int __init zynq_gpio_init(void)
923{
924 return platform_driver_register(&zynq_gpio_driver);
925}
926postcore_initcall(zynq_gpio_init);
927
80d2bf55
MY		 928static void __exit zynq_gpio_exit(void)
929{
930 platform_driver_unregister(&zynq_gpio_driver);
931}
932module_exit(zynq_gpio_exit);
933
3242ba11
HK		 934MODULE_AUTHOR("Xilinx Inc.");
935MODULE_DESCRIPTION("Zynq GPIO driver");
936MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)