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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-2.6-block.git] / drivers / gpio / gpio-zynq.c
CommitLineData
3242ba11
HK		 1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
bdf7a4ae 21#include <linux/of.h>
3242ba11
HK		 22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
bdf7a4ae 27#define ZYNQMP_GPIO_MAX_BANK 6
3242ba11
HK		 28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
bdf7a4ae
AKV		 34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
3242ba11 62
3242ba11
HK		 63/* Register offsets for the GPIO device */
64/* LSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
66/* MSW Mask & Data -WO */
67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
68/* Data Register-RW */
06aa0908 69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
3242ba11
HK		 70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
3638bd4a
SB		 99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
06aa0908 101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
e3296f19 102
e11de4de
SD		 103struct gpio_regs {
104 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
105 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
107 u32 outen[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
113};
eb73d6ea 114
3242ba11
HK		 115/**
116 * struct zynq_gpio - gpio device private data structure
117 * @chip: instance of the gpio_chip
118 * @base_addr: base address of the GPIO device
119 * @clk: clock resource for this controller
59e22114 120 * @irq: interrupt for the GPIO device
bdf7a4ae 121 * @p_data: pointer to platform data
e11de4de 122 * @context: context registers
3242ba11
HK		 123 */
124struct zynq_gpio {
125 struct gpio_chip chip;
126 void __iomem *base_addr;
127 struct clk *clk;
59e22114 128 int irq;
bdf7a4ae 129 const struct zynq_platform_data *p_data;
e11de4de 130 struct gpio_regs context;
bdf7a4ae
AKV		 131};
132
133/**
134 * struct zynq_platform_data - zynq gpio platform data structure
135 * @label: string to store in gpio->label
6ae5104c 136 * @quirks: Flags is used to identify the platform
bdf7a4ae
AKV		 137 * @ngpio: max number of gpio pins
138 * @max_bank: maximum number of gpio banks
139 * @bank_min: this array represents bank's min pin
140 * @bank_max: this array represents bank's max pin
6ae5104c 141 */
bdf7a4ae
AKV		 142struct zynq_platform_data {
143 const char *label;
e3296f19 144 u32 quirks;
bdf7a4ae
AKV		 145 u16 ngpio;
146 int max_bank;
147 int bank_min[ZYNQMP_GPIO_MAX_BANK];
148 int bank_max[ZYNQMP_GPIO_MAX_BANK];
3242ba11
HK		 149};
150
6dd85950
LPC		 151static struct irq_chip zynq_gpio_level_irqchip;
152static struct irq_chip zynq_gpio_edge_irqchip;
fa9795d1 153
3638bd4a
SB		 154/**
155 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
156 * @gpio: Pointer to driver data struct
157 *
158 * Return: 0 if zynqmp, 1 if zynq.
159 */
160static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
161{
162 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
163}
164
06aa0908
SM		 165/**
166 * gpio_data_ro_bug - test if HW bug exists or not
167 * @gpio: Pointer to driver data struct
168 *
169 * Return: 0 if bug doesnot exist, 1 if bug exists.
170 */
171static int gpio_data_ro_bug(struct zynq_gpio *gpio)
172{
173 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
174}
175
3242ba11
HK		 176/**
177 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
178 * for a given pin in the GPIO device
179 * @pin_num: gpio pin number within the device
180 * @bank_num: an output parameter used to return the bank number of the gpio
181 * pin
182 * @bank_pin_num: an output parameter used to return pin number within a bank
183 * for the given gpio pin
6ae5104c 184 * @gpio: gpio device data structure
3242ba11
HK		 185 *
186 * Returns the bank number and pin offset within the bank.
187 */
188static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
189 unsigned int *bank_num,
bdf7a4ae
AKV		 190 unsigned int *bank_pin_num,
191 struct zynq_gpio *gpio)
3242ba11 192{
bdf7a4ae
AKV		 193 int bank;
194
195 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
196 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
16ee62e5 197 (pin_num <= gpio->p_data->bank_max[bank])) {
2717cfca
NM		 198 *bank_num = bank;
199 *bank_pin_num = pin_num -
200 gpio->p_data->bank_min[bank];
201 return;
bdf7a4ae 202 }
3242ba11 203 }
3242ba11 204
bdf7a4ae
AKV		 205 /* default */
206 WARN(true, "invalid GPIO pin number: %u", pin_num);
207 *bank_num = 0;
208 *bank_pin_num = 0;
209}
016da144 210
3242ba11
HK		 211/**
212 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
213 * @chip: gpio_chip instance to be worked on
214 * @pin: gpio pin number within the device
215 *
216 * This function reads the state of the specified pin of the GPIO device.
217 *
218 * Return: 0 if the pin is low, 1 if pin is high.
219 */
220static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
221{
222 u32 data;
223 unsigned int bank_num, bank_pin_num;
31a89447 224 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 225
bdf7a4ae 226 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 227
06aa0908
SM		 228 if (gpio_data_ro_bug(gpio)) {
229 if (zynq_gpio_is_zynq(gpio)) {
230 if (bank_num <= 1) {
231 data = readl_relaxed(gpio->base_addr +
232 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
233 } else {
234 data = readl_relaxed(gpio->base_addr +
235 ZYNQ_GPIO_DATA_OFFSET(bank_num));
236 }
237 } else {
238 if (bank_num <= 2) {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
241 } else {
242 data = readl_relaxed(gpio->base_addr +
243 ZYNQ_GPIO_DATA_OFFSET(bank_num));
244 }
245 }
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
249 }
3242ba11
HK		 250 return (data >> bank_pin_num) & 1;
251}
252
253/**
254 * zynq_gpio_set_value - Modify the state of the pin with specified value
255 * @chip: gpio_chip instance to be worked on
256 * @pin: gpio pin number within the device
257 * @state: value used to modify the state of the specified pin
258 *
259 * This function calculates the register offset (i.e to lower 16 bits or
260 * upper 16 bits) based on the given pin number and sets the state of a
261 * gpio pin to the specified value. The state is either 0 or non-zero.
262 */
263static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
264 int state)
265{
266 unsigned int reg_offset, bank_num, bank_pin_num;
31a89447 267 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 268
bdf7a4ae 269 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 270
271 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
272 /* only 16 data bits in bit maskable reg */
273 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
274 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
275 } else {
276 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
277 }
278
279 /*
280 * get the 32 bit value to be written to the mask/data register where
281 * the upper 16 bits is the mask and lower 16 bits is the data
282 */
283 state = !!state;
284 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
285 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
286
287 writel_relaxed(state, gpio->base_addr + reg_offset);
288}
289
290/**
291 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
292 * @chip: gpio_chip instance to be worked on
293 * @pin: gpio pin number within the device
294 *
295 * This function uses the read-modify-write sequence to set the direction of
296 * the gpio pin as input.
297 *
298 * Return: 0 always
299 */
300static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
301{
302 u32 reg;
303 unsigned int bank_num, bank_pin_num;
31a89447 304 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 305
bdf7a4ae 306 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11 307
e3296f19
NM		 308 /*
309 * On zynq bank 0 pins 7 and 8 are special and cannot be used
310 * as inputs.
311 */
3638bd4a 312 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
16ee62e5 313 (bank_pin_num == 7 || bank_pin_num == 8))
3242ba11
HK		 314 return -EINVAL;
315
316 /* clear the bit in direction mode reg to set the pin as input */
317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
318 reg &= ~BIT(bank_pin_num);
319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
320
321 return 0;
322}
323
324/**
325 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
326 * @chip: gpio_chip instance to be worked on
327 * @pin: gpio pin number within the device
328 * @state: value to be written to specified pin
329 *
330 * This function sets the direction of specified GPIO pin as output, configures
331 * the Output Enable register for the pin and uses zynq_gpio_set to set
332 * the state of the pin to the value specified.
333 *
334 * Return: 0 always
335 */
336static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
337 int state)
338{
339 u32 reg;
340 unsigned int bank_num, bank_pin_num;
31a89447 341 struct zynq_gpio *gpio = gpiochip_get_data(chip);
3242ba11 342
bdf7a4ae 343 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 344
345 /* set the GPIO pin as output */
346 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
347 reg |= BIT(bank_pin_num);
348 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
349
350 /* configure the output enable reg for the pin */
351 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
352 reg |= BIT(bank_pin_num);
353 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
354
355 /* set the state of the pin */
356 zynq_gpio_set_value(chip, pin, state);
357 return 0;
358}
359
6169005c
BM		 360/**
361 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
362 * @chip: gpio_chip instance to be worked on
363 * @pin: gpio pin number within the device
364 *
365 * This function returns the direction of the specified GPIO.
366 *
367 * Return: 0 for output, 1 for input
368 */
369static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
370{
371 u32 reg;
372 unsigned int bank_num, bank_pin_num;
373 struct zynq_gpio *gpio = gpiochip_get_data(chip);
374
375 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
376
377 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
378
379 return !(reg & BIT(bank_pin_num));
380}
381
3242ba11
HK		 382/**
383 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
384 * @irq_data: per irq and chip data passed down to chip functions
385 *
386 * This function calculates gpio pin number from irq number and sets the
387 * bit in the Interrupt Disable register of the corresponding bank to disable
388 * interrupts for that pin.
389 */
390static void zynq_gpio_irq_mask(struct irq_data *irq_data)
391{
392 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 393 struct zynq_gpio *gpio =
31a89447 394 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 395
396 device_pin_num = irq_data->hwirq;
bdf7a4ae 397 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 398 writel_relaxed(BIT(bank_pin_num),
399 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
400}
401
402/**
403 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
404 * @irq_data: irq data containing irq number of gpio pin for the interrupt
405 * to enable
406 *
407 * This function calculates the gpio pin number from irq number and sets the
408 * bit in the Interrupt Enable register of the corresponding bank to enable
409 * interrupts for that pin.
410 */
411static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
412{
413 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 414 struct zynq_gpio *gpio =
31a89447 415 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 416
417 device_pin_num = irq_data->hwirq;
bdf7a4ae 418 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 419 writel_relaxed(BIT(bank_pin_num),
420 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
421}
422
190dc2e6
LPC		 423/**
424 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
425 * @irq_data: irq data containing irq number of gpio pin for the interrupt
426 * to ack
427 *
428 * This function calculates gpio pin number from irq number and sets the bit
429 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
430 */
431static void zynq_gpio_irq_ack(struct irq_data *irq_data)
432{
433 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 434 struct zynq_gpio *gpio =
31a89447 435 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
190dc2e6
LPC		 436
437 device_pin_num = irq_data->hwirq;
bdf7a4ae 438 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
190dc2e6
LPC		 439 writel_relaxed(BIT(bank_pin_num),
440 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
441}
442
443/**
444 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
445 * @irq_data: irq data containing irq number of gpio pin for the interrupt
446 * to enable
447 *
20a8a968 448 * Clears the INTSTS bit and unmasks the given interrupt.
190dc2e6
LPC		 449 */
450static void zynq_gpio_irq_enable(struct irq_data *irq_data)
451{
452 /*
453 * The Zynq GPIO controller does not disable interrupt detection when
454 * the interrupt is masked and only disables the propagation of the
455 * interrupt. This means when the controller detects an interrupt
456 * condition while the interrupt is logically disabled it will propagate
457 * that interrupt event once the interrupt is enabled. This will cause
458 * the interrupt consumer to see spurious interrupts to prevent this
459 * first make sure that the interrupt is not asserted and then enable
460 * it.
461 */
462 zynq_gpio_irq_ack(irq_data);
463 zynq_gpio_irq_unmask(irq_data);
464}
465
3242ba11
HK		 466/**
467 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
468 * @irq_data: irq data containing irq number of gpio pin
469 * @type: interrupt type that is to be set for the gpio pin
470 *
471 * This function gets the gpio pin number and its bank from the gpio pin number
472 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
473 *
474 * Return: 0, negative error otherwise.
475 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
476 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
477 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
478 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
479 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
480 */
481static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
482{
483 u32 int_type, int_pol, int_any;
484 unsigned int device_pin_num, bank_num, bank_pin_num;
fa9795d1 485 struct zynq_gpio *gpio =
31a89447 486 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
3242ba11
HK		 487
488 device_pin_num = irq_data->hwirq;
bdf7a4ae 489 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
3242ba11
HK		 490
491 int_type = readl_relaxed(gpio->base_addr +
492 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
493 int_pol = readl_relaxed(gpio->base_addr +
494 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
495 int_any = readl_relaxed(gpio->base_addr +
496 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
497
498 /*
499 * based on the type requested, configure the INT_TYPE, INT_POLARITY
500 * and INT_ANY registers
501 */
502 switch (type) {
503 case IRQ_TYPE_EDGE_RISING:
504 int_type |= BIT(bank_pin_num);
505 int_pol |= BIT(bank_pin_num);
506 int_any &= ~BIT(bank_pin_num);
507 break;
508 case IRQ_TYPE_EDGE_FALLING:
509 int_type |= BIT(bank_pin_num);
510 int_pol &= ~BIT(bank_pin_num);
511 int_any &= ~BIT(bank_pin_num);
512 break;
513 case IRQ_TYPE_EDGE_BOTH:
514 int_type |= BIT(bank_pin_num);
515 int_any |= BIT(bank_pin_num);
516 break;
517 case IRQ_TYPE_LEVEL_HIGH:
518 int_type &= ~BIT(bank_pin_num);
519 int_pol |= BIT(bank_pin_num);
520 break;
521 case IRQ_TYPE_LEVEL_LOW:
522 int_type &= ~BIT(bank_pin_num);
523 int_pol &= ~BIT(bank_pin_num);
524 break;
525 default:
526 return -EINVAL;
527 }
528
529 writel_relaxed(int_type,
530 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
531 writel_relaxed(int_pol,
532 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
533 writel_relaxed(int_any,
534 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
6dd85950 535
16ee62e5 536 if (type & IRQ_TYPE_LEVEL_MASK)
47c08462 537 irq_set_chip_handler_name_locked(irq_data,
16ee62e5
MS		 538 &zynq_gpio_level_irqchip,
539 handle_fasteoi_irq, NULL);
540 else
47c08462 541 irq_set_chip_handler_name_locked(irq_data,
16ee62e5
MS		 542 &zynq_gpio_edge_irqchip,
543 handle_level_irq, NULL);
6dd85950 544
3242ba11
HK		 545 return 0;
546}
547
548static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
549{
fa9795d1 550 struct zynq_gpio *gpio =
31a89447 551 gpiochip_get_data(irq_data_get_irq_chip_data(data));
59e22114
ES		 552
553 irq_set_irq_wake(gpio->irq, on);
3242ba11
HK		 554
555 return 0;
556}
557
558/* irq chip descriptor */
6dd85950 559static struct irq_chip zynq_gpio_level_irqchip = {
3242ba11 560 .name = DRIVER_NAME,
190dc2e6 561 .irq_enable = zynq_gpio_irq_enable,
6dd85950
LPC		 562 .irq_eoi = zynq_gpio_irq_ack,
563 .irq_mask = zynq_gpio_irq_mask,
564 .irq_unmask = zynq_gpio_irq_unmask,
565 .irq_set_type = zynq_gpio_set_irq_type,
566 .irq_set_wake = zynq_gpio_set_wake,
a1946778
ES		 567 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
568 IRQCHIP_MASK_ON_SUSPEND,
6dd85950
LPC		 569};
570
571static struct irq_chip zynq_gpio_edge_irqchip = {
572 .name = DRIVER_NAME,
573 .irq_enable = zynq_gpio_irq_enable,
574 .irq_ack = zynq_gpio_irq_ack,
3242ba11
HK		 575 .irq_mask = zynq_gpio_irq_mask,
576 .irq_unmask = zynq_gpio_irq_unmask,
577 .irq_set_type = zynq_gpio_set_irq_type,
578 .irq_set_wake = zynq_gpio_set_wake,
a1946778 579 .flags = IRQCHIP_MASK_ON_SUSPEND,
3242ba11
HK		 580};
581
5a2533a7
LPC		 582static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
583 unsigned int bank_num,
584 unsigned long pending)
585{
bdf7a4ae 586 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
f0fbe7bc 587 struct irq_domain *irqdomain = gpio->chip.irq.domain;
5a2533a7
LPC		 588 int offset;
589
590 if (!pending)
591 return;
592
593 for_each_set_bit(offset, &pending, 32) {
594 unsigned int gpio_irq;
595
016da144 596 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
5a2533a7
LPC		 597 generic_handle_irq(gpio_irq);
598 }
599}
600
3242ba11
HK		 601/**
602 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
3242ba11
HK		 603 * @desc: irq descriptor instance of the 'irq'
604 *
605 * This function reads the Interrupt Status Register of each bank to get the
606 * gpio pin number which has triggered an interrupt. It then acks the triggered
607 * interrupt and calls the pin specific handler set by the higher layer
608 * application for that pin.
609 * Note: A bug is reported if no handler is set for the gpio pin.
610 */
bd0b9ac4 611static void zynq_gpio_irqhandler(struct irq_desc *desc)
3242ba11
HK		 612{
613 u32 int_sts, int_enb;
614 unsigned int bank_num;
fa9795d1 615 struct zynq_gpio *gpio =
31a89447 616 gpiochip_get_data(irq_desc_get_handler_data(desc));
3242ba11
HK		 617 struct irq_chip *irqchip = irq_desc_get_chip(desc);
618
619 chained_irq_enter(irqchip, desc);
620
bdf7a4ae 621 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
3242ba11
HK		 622 int_sts = readl_relaxed(gpio->base_addr +
623 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
624 int_enb = readl_relaxed(gpio->base_addr +
625 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
5a2533a7 626 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
3242ba11
HK		 627 }
628
629 chained_irq_exit(irqchip, desc);
630}
631
e11de4de
SD		 632static void zynq_gpio_save_context(struct zynq_gpio *gpio)
633{
634 unsigned int bank_num;
635
636 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
637 gpio->context.datalsw[bank_num] =
638 readl_relaxed(gpio->base_addr +
639 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
640 gpio->context.datamsw[bank_num] =
641 readl_relaxed(gpio->base_addr +
642 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
643 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
644 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
645 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
646 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
647 gpio->context.int_type[bank_num] =
648 readl_relaxed(gpio->base_addr +
649 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
650 gpio->context.int_polarity[bank_num] =
651 readl_relaxed(gpio->base_addr +
652 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
653 gpio->context.int_any[bank_num] =
654 readl_relaxed(gpio->base_addr +
655 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
656 }
657}
658
659static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
660{
661 unsigned int bank_num;
662
663 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
664 writel_relaxed(gpio->context.datalsw[bank_num],
665 gpio->base_addr +
666 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
667 writel_relaxed(gpio->context.datamsw[bank_num],
668 gpio->base_addr +
669 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
670 writel_relaxed(gpio->context.dirm[bank_num],
671 gpio->base_addr +
672 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
673 writel_relaxed(gpio->context.int_en[bank_num],
674 gpio->base_addr +
675 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
676 writel_relaxed(gpio->context.int_type[bank_num],
677 gpio->base_addr +
678 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
679 writel_relaxed(gpio->context.int_polarity[bank_num],
680 gpio->base_addr +
681 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
682 writel_relaxed(gpio->context.int_any[bank_num],
683 gpio->base_addr +
684 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
685 }
686}
eb73d6ea 687
3242ba11
HK		 688static int __maybe_unused zynq_gpio_suspend(struct device *dev)
689{
a76e865e 690 struct zynq_gpio *gpio = dev_get_drvdata(dev);
5e3a8ecd 691 struct irq_data *data = irq_get_irq_data(gpio->irq);
59e22114 692
e11de4de
SD		 693 if (!irqd_is_wakeup_set(data)) {
694 zynq_gpio_save_context(gpio);
3242ba11 695 return pm_runtime_force_suspend(dev);
e11de4de 696 }
3242ba11
HK		 697
698 return 0;
699}
700
701static int __maybe_unused zynq_gpio_resume(struct device *dev)
702{
a76e865e 703 struct zynq_gpio *gpio = dev_get_drvdata(dev);
5e3a8ecd 704 struct irq_data *data = irq_get_irq_data(gpio->irq);
e11de4de 705 int ret;
59e22114 706
e11de4de
SD		 707 if (!irqd_is_wakeup_set(data)) {
708 ret = pm_runtime_force_resume(dev);
709 zynq_gpio_restore_context(gpio);
710 return ret;
711 }
3242ba11
HK		 712
713 return 0;
714}
715
716static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
717{
38ccad02 718 struct zynq_gpio *gpio = dev_get_drvdata(dev);
3242ba11
HK		 719
720 clk_disable_unprepare(gpio->clk);
721
722 return 0;
723}
724
725static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
726{
38ccad02 727 struct zynq_gpio *gpio = dev_get_drvdata(dev);
3242ba11
HK		 728
729 return clk_prepare_enable(gpio->clk);
730}
731
2717cfca 732static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
3242ba11
HK		 733{
734 int ret;
735
58383c78 736 ret = pm_runtime_get_sync(chip->parent);
3242ba11
HK		 737
738 /*
739 * If the device is already active pm_runtime_get() will return 1 on
740 * success, but gpio_request still needs to return 0.
741 */
742 return ret < 0 ? ret : 0;
743}
744
2717cfca 745static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
3242ba11 746{
58383c78 747 pm_runtime_put(chip->parent);
3242ba11
HK		 748}
749
750static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
751 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
6ed23b80 752 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
16ee62e5 753 zynq_gpio_runtime_resume, NULL)
3242ba11
HK		 754};
755
bdf7a4ae
AKV		 756static const struct zynq_platform_data zynqmp_gpio_def = {
757 .label = "zynqmp_gpio",
06aa0908 758 .quirks = GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 759 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
760 .max_bank = ZYNQMP_GPIO_MAX_BANK,
761 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
762 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
763 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
764 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
765 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
766 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
767 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
768 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
769 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
770 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
771 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
772 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
773};
774
775static const struct zynq_platform_data zynq_gpio_def = {
776 .label = "zynq_gpio",
06aa0908 777 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
bdf7a4ae
AKV		 778 .ngpio = ZYNQ_GPIO_NR_GPIOS,
779 .max_bank = ZYNQ_GPIO_MAX_BANK,
780 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
781 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
782 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
783 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
784 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
785 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
786 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
787 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
788};
789
790static const struct of_device_id zynq_gpio_of_match[] = {
7808c42b
MY		 791 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
792 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
bdf7a4ae
AKV		 793 { /* end of table */ }
794};
795MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
796
3242ba11
HK		 797/**
798 * zynq_gpio_probe - Initialization method for a zynq_gpio device
799 * @pdev: platform device instance
800 *
801 * This function allocates memory resources for the gpio device and registers
802 * all the banks of the device. It will also set up interrupts for the gpio
803 * pins.
804 * Note: Interrupts are disabled for all the banks during initialization.
805 *
806 * Return: 0 on success, negative error otherwise.
807 */
808static int zynq_gpio_probe(struct platform_device *pdev)
809{
59e22114 810 int ret, bank_num;
3242ba11
HK		 811 struct zynq_gpio *gpio;
812 struct gpio_chip *chip;
813 struct resource *res;
bdf7a4ae 814 const struct of_device_id *match;
3242ba11
HK		 815
816 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
817 if (!gpio)
818 return -ENOMEM;
819
bdf7a4ae
AKV		 820 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
821 if (!match) {
822 dev_err(&pdev->dev, "of_match_node() failed\n");
823 return -EINVAL;
824 }
825 gpio->p_data = match->data;
3242ba11
HK		 826 platform_set_drvdata(pdev, gpio);
827
828 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
829 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
830 if (IS_ERR(gpio->base_addr))
831 return PTR_ERR(gpio->base_addr);
832
59e22114
ES		 833 gpio->irq = platform_get_irq(pdev, 0);
834 if (gpio->irq < 0) {
3242ba11 835 dev_err(&pdev->dev, "invalid IRQ\n");
59e22114 836 return gpio->irq;
3242ba11
HK		 837 }
838
839 /* configure the gpio chip */
840 chip = &gpio->chip;
bdf7a4ae 841 chip->label = gpio->p_data->label;
3242ba11 842 chip->owner = THIS_MODULE;
58383c78 843 chip->parent = &pdev->dev;
3242ba11
HK		 844 chip->get = zynq_gpio_get_value;
845 chip->set = zynq_gpio_set_value;
846 chip->request = zynq_gpio_request;
847 chip->free = zynq_gpio_free;
848 chip->direction_input = zynq_gpio_dir_in;
849 chip->direction_output = zynq_gpio_dir_out;
6169005c 850 chip->get_direction = zynq_gpio_get_direction;
060f3ebf 851 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
bdf7a4ae 852 chip->ngpio = gpio->p_data->ngpio;
3242ba11 853
3773c195 854 /* Retrieve GPIO clock */
3242ba11
HK		 855 gpio->clk = devm_clk_get(&pdev->dev, NULL);
856 if (IS_ERR(gpio->clk)) {
857 dev_err(&pdev->dev, "input clock not found.\n");
858 return PTR_ERR(gpio->clk);
859 }
0f84f29f
HG		 860 ret = clk_prepare_enable(gpio->clk);
861 if (ret) {
862 dev_err(&pdev->dev, "Unable to enable clock.\n");
863 return ret;
864 }
3773c195 865
0f84f29f 866 pm_runtime_set_active(&pdev->dev);
3773c195
MS		 867 pm_runtime_enable(&pdev->dev);
868 ret = pm_runtime_get_sync(&pdev->dev);
869 if (ret < 0)
615d23f8 870 goto err_pm_dis;
3242ba11
HK		 871
872 /* report a bug if gpio chip registration fails */
31a89447 873 ret = gpiochip_add_data(chip, gpio);
3242ba11
HK		 874 if (ret) {
875 dev_err(&pdev->dev, "Failed to add gpio chip\n");
3773c195 876 goto err_pm_put;
3242ba11
HK		 877 }
878
879 /* disable interrupts for all banks */
bdf7a4ae 880 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
3242ba11
HK		 881 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
882 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
883
6dd85950
LPC		 884 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
885 handle_level_irq, IRQ_TYPE_NONE);
3242ba11
HK		 886 if (ret) {
887 dev_err(&pdev->dev, "Failed to add irq chip\n");
888 goto err_rm_gpiochip;
889 }
890
59e22114 891 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
3242ba11
HK		 892 zynq_gpio_irqhandler);
893
3773c195 894 pm_runtime_put(&pdev->dev);
3242ba11 895
3242ba11
HK		 896 return 0;
897
898err_rm_gpiochip:
88d5e520 899 gpiochip_remove(chip);
3773c195
MS		 900err_pm_put:
901 pm_runtime_put(&pdev->dev);
615d23f8
SD		 902err_pm_dis:
903 pm_runtime_disable(&pdev->dev);
0f84f29f 904 clk_disable_unprepare(gpio->clk);
3242ba11
HK		 905
906 return ret;
907}
908
909/**
910 * zynq_gpio_remove - Driver removal function
911 * @pdev: platform device instance
912 *
913 * Return: 0 always
914 */
915static int zynq_gpio_remove(struct platform_device *pdev)
916{
3242ba11
HK		 917 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
918
919 pm_runtime_get_sync(&pdev->dev);
da26d5d8 920 gpiochip_remove(&gpio->chip);
3242ba11
HK		 921 clk_disable_unprepare(gpio->clk);
922 device_set_wakeup_capable(&pdev->dev, 0);
6b956af0 923 pm_runtime_disable(&pdev->dev);
3242ba11
HK		 924 return 0;
925}
926
3242ba11
HK		 927static struct platform_driver zynq_gpio_driver = {
928 .driver = {
929 .name = DRIVER_NAME,
3242ba11
HK		 930 .pm = &zynq_gpio_dev_pm_ops,
931 .of_match_table = zynq_gpio_of_match,
932 },
933 .probe = zynq_gpio_probe,
934 .remove = zynq_gpio_remove,
935};
936
937/**
938 * zynq_gpio_init - Initial driver registration call
939 *
940 * Return: value from platform_driver_register
941 */
942static int __init zynq_gpio_init(void)
943{
944 return platform_driver_register(&zynq_gpio_driver);
945}
946postcore_initcall(zynq_gpio_init);
947
80d2bf55
MY		 948static void __exit zynq_gpio_exit(void)
949{
950 platform_driver_unregister(&zynq_gpio_driver);
951}
952module_exit(zynq_gpio_exit);
953
3242ba11
HK		 954MODULE_AUTHOR("Xilinx Inc.");
955MODULE_DESCRIPTION("Zynq GPIO driver");
956MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)