[linux-block.git] / drivers / gpio / gpio-zevio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO controller in LSI ZEVIO SoCs.
 *
 * Author: Fabian Vogt <fabian@ritter-vogt.de>
 */

#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/gpio/driver.h>

/*
 * Memory layout:
 * This chip has four gpio sections, each controls 8 GPIOs.
 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
 * Disclaimer: Reverse engineered!
 * For more information refer to:
 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
 *
 * 0x00-0x3F: Section 0
 *     +0x00: Masked interrupt status (read-only)
 *     +0x04: R: Interrupt status W: Reset interrupt status
 *     +0x08: R: Interrupt mask W: Mask interrupt
 *     +0x0C: W: Unmask interrupt (write-only)
 *     +0x10: Direction: I/O=1/0
 *     +0x14: Output
 *     +0x18: Input (read-only)
 *     +0x20: R: Level interrupt W: Set as level interrupt
 * 0x40-0x7F: Section 1
 * 0x80-0xBF: Section 2
 * 0xC0-0xFF: Section 3
 */

#define ZEVIO_GPIO_SECTION_SIZE			0x40

/* Offsets to various registers */
#define ZEVIO_GPIO_INT_MASKED_STATUS	0x00
#define ZEVIO_GPIO_INT_STATUS		0x04
#define ZEVIO_GPIO_INT_UNMASK		0x08
#define ZEVIO_GPIO_INT_MASK		0x0C
#define ZEVIO_GPIO_DIRECTION		0x10
#define ZEVIO_GPIO_OUTPUT		0x14
#define ZEVIO_GPIO_INPUT			0x18
#define ZEVIO_GPIO_INT_STICKY		0x20

/* Bit number of GPIO in its section */
#define ZEVIO_GPIO_BIT(gpio) (gpio&7)

struct zevio_gpio {
	struct gpio_chip        chip;
	spinlock_t		lock;
	void __iomem		*regs;
};

static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
					unsigned port_offset)
{
	unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
	return readl(IOMEM(c->regs + section_offset + port_offset));
}

static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
					unsigned port_offset, u32 val)
{
	unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
	writel(val, IOMEM(c->regs + section_offset + port_offset));
}

/* Functions for struct gpio_chip */
static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
{
	struct zevio_gpio *controller = gpiochip_get_data(chip);
	u32 val, dir;

	spin_lock(&controller->lock);
	dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
		val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
	else
		val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	spin_unlock(&controller->lock);

	return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
}

static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
{
	struct zevio_gpio *controller = gpiochip_get_data(chip);
	u32 val;

	spin_lock(&controller->lock);
	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	if (value)
		val |= BIT(ZEVIO_GPIO_BIT(pin));
	else
		val &= ~BIT(ZEVIO_GPIO_BIT(pin));

	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
	spin_unlock(&controller->lock);
}

static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
{
	struct zevio_gpio *controller = gpiochip_get_data(chip);
	u32 val;

	spin_lock(&controller->lock);

	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	val |= BIT(ZEVIO_GPIO_BIT(pin));
	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);

	spin_unlock(&controller->lock);

	return 0;
}

static int zevio_gpio_direction_output(struct gpio_chip *chip,
				       unsigned pin, int value)
{
	struct zevio_gpio *controller = gpiochip_get_data(chip);
	u32 val;

	spin_lock(&controller->lock);
	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	if (value)
		val |= BIT(ZEVIO_GPIO_BIT(pin));
	else
		val &= ~BIT(ZEVIO_GPIO_BIT(pin));

	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	val &= ~BIT(ZEVIO_GPIO_BIT(pin));
	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);

	spin_unlock(&controller->lock);

	return 0;
}

static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
{
	/*
	 * TODO: Implement IRQs.
	 * Not implemented yet due to weird lockups
	 */

	return -ENXIO;
}

static const struct gpio_chip zevio_gpio_chip = {
	.direction_input	= zevio_gpio_direction_input,
	.direction_output	= zevio_gpio_direction_output,
	.set			= zevio_gpio_set,
	.get			= zevio_gpio_get,
	.to_irq			= zevio_gpio_to_irq,
	.base			= 0,
	.owner			= THIS_MODULE,
	.ngpio			= 32,
};

/* Initialization */
static int zevio_gpio_probe(struct platform_device *pdev)
{
	struct zevio_gpio *controller;
	int status, i;

	controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return -ENOMEM;

	platform_set_drvdata(pdev, controller);

	/* Copy our reference */
	controller->chip = zevio_gpio_chip;
	controller->chip.parent = &pdev->dev;

	controller->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(controller->regs))
		return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
				     "failed to ioremap memory resource\n");

	status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
	if (status) {
		dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
		return status;
	}

	spin_lock_init(&controller->lock);

	/* Disable interrupts, they only cause errors */
	for (i = 0; i < controller->chip.ngpio; i += 8)
		zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);

	dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");

	return 0;
}

static const struct of_device_id zevio_gpio_of_match[] = {
	{ .compatible = "lsi,zevio-gpio", },
	{ },
};

static struct platform_driver zevio_gpio_driver = {
	.driver		= {
		.name	= "gpio-zevio",
		.of_match_table = zevio_gpio_of_match,
		.suppress_bind_attrs = true,
	},
	.probe		= zevio_gpio_probe,
};
builtin_platform_driver(zevio_gpio_driver);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
9af4d80b FV	2	/*
	3	* GPIO controller in LSI ZEVIO SoCs.
	4	*
	5	* Author: Fabian Vogt <fabian@ritter-vogt.de>
9af4d80b FV	6	*/
9af4d80b FV	7
9c8224d0	8	#include <linux/bitops.h>
9af4d80b	9	#include <linux/errno.h>
a90295b4	10	#include <linux/init.h>
9af4d80b	11	#include <linux/io.h>
9c8224d0	12	#include <linux/mod_devicetable.h>
fd648e10	13	#include <linux/platform_device.h>
9af4d80b	14	#include <linux/slab.h>
9c8224d0 AS	15	#include <linux/spinlock.h>
9c8224d0 AS	16
f0916167	17	#include <linux/gpio/driver.h>
9af4d80b FV	18
	19	/*
	20	* Memory layout:
	21	* This chip has four gpio sections, each controls 8 GPIOs.
	22	* Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
	23	* Disclaimer: Reverse engineered!
	24	* For more information refer to:
	25	* http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
	26	*
	27	* 0x00-0x3F: Section 0
	28	* +0x00: Masked interrupt status (read-only)
	29	* +0x04: R: Interrupt status W: Reset interrupt status
	30	* +0x08: R: Interrupt mask W: Mask interrupt
	31	* +0x0C: W: Unmask interrupt (write-only)
	32	* +0x10: Direction: I/O=1/0
	33	* +0x14: Output
	34	* +0x18: Input (read-only)
	35	* +0x20: R: Level interrupt W: Set as level interrupt
	36	* 0x40-0x7F: Section 1
	37	* 0x80-0xBF: Section 2
	38	* 0xC0-0xFF: Section 3
	39	*/
	40
	41	#define ZEVIO_GPIO_SECTION_SIZE 0x40
	42
	43	/* Offsets to various registers */
	44	#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
	45	#define ZEVIO_GPIO_INT_STATUS 0x04
	46	#define ZEVIO_GPIO_INT_UNMASK 0x08
	47	#define ZEVIO_GPIO_INT_MASK 0x0C
	48	#define ZEVIO_GPIO_DIRECTION 0x10
	49	#define ZEVIO_GPIO_OUTPUT 0x14
	50	#define ZEVIO_GPIO_INPUT 0x18
	51	#define ZEVIO_GPIO_INT_STICKY 0x20
	52
9af4d80b FV	53	/* Bit number of GPIO in its section */
	54	#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
	55
	56	struct zevio_gpio {
cf8f4462	57	struct gpio_chip chip;
9af4d80b	58	spinlock_t lock;
cf8f4462	59	void __iomem *regs;
9af4d80b FV	60	};
	61
	62	static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
	63	unsigned port_offset)
	64	{
	65	unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
cf8f4462	66	return readl(IOMEM(c->regs + section_offset + port_offset));
9af4d80b FV	67	}
	68
	69	static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
	70	unsigned port_offset, u32 val)
	71	{
	72	unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
cf8f4462	73	writel(val, IOMEM(c->regs + section_offset + port_offset));
9af4d80b FV	74	}
	75
	76	/* Functions for struct gpio_chip */
	77	static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
	78	{
9a3ad668	79	struct zevio_gpio *controller = gpiochip_get_data(chip);
ef7de262	80	u32 val, dir;
9af4d80b	81
ef7de262 AL	82	spin_lock(&controller->lock);
	83	dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	84	if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
	85	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
	86	else
	87	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	88	spin_unlock(&controller->lock);
9af4d80b FV	89
	90	return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
	91	}
	92
	93	static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
	94	{
9a3ad668	95	struct zevio_gpio *controller = gpiochip_get_data(chip);
9af4d80b FV	96	u32 val;
	97
	98	spin_lock(&controller->lock);
	99	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	100	if (value)
	101	val \|= BIT(ZEVIO_GPIO_BIT(pin));
	102	else
	103	val &= ~BIT(ZEVIO_GPIO_BIT(pin));
	104
	105	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
	106	spin_unlock(&controller->lock);
	107	}
	108
	109	static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
	110	{
9a3ad668	111	struct zevio_gpio *controller = gpiochip_get_data(chip);
9af4d80b FV	112	u32 val;
	113
	114	spin_lock(&controller->lock);
	115
	116	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	117	val \|= BIT(ZEVIO_GPIO_BIT(pin));
	118	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
	119
	120	spin_unlock(&controller->lock);
	121
	122	return 0;
	123	}
	124
	125	static int zevio_gpio_direction_output(struct gpio_chip *chip,
	126	unsigned pin, int value)
	127	{
9a3ad668	128	struct zevio_gpio *controller = gpiochip_get_data(chip);
9af4d80b FV	129	u32 val;
	130
	131	spin_lock(&controller->lock);
	132	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
	133	if (value)
	134	val \|= BIT(ZEVIO_GPIO_BIT(pin));
	135	else
	136	val &= ~BIT(ZEVIO_GPIO_BIT(pin));
	137
	138	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
	139	val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
	140	val &= ~BIT(ZEVIO_GPIO_BIT(pin));
	141	zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
	142
	143	spin_unlock(&controller->lock);
	144
	145	return 0;
	146	}
	147
	148	static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
	149	{
	150	/*
	151	* TODO: Implement IRQs.
	152	* Not implemented yet due to weird lockups
	153	*/
	154
	155	return -ENXIO;
	156	}
	157
4a14af45	158	static const struct gpio_chip zevio_gpio_chip = {
9af4d80b FV	159	.direction_input = zevio_gpio_direction_input,
	160	.direction_output = zevio_gpio_direction_output,
	161	.set = zevio_gpio_set,
	162	.get = zevio_gpio_get,
	163	.to_irq = zevio_gpio_to_irq,
	164	.base = 0,
	165	.owner = THIS_MODULE,
	166	.ngpio = 32,
9af4d80b FV	167	};
	168
	169	/* Initialization */
	170	static int zevio_gpio_probe(struct platform_device *pdev)
	171	{
	172	struct zevio_gpio *controller;
	173	int status, i;
	174
	175	controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
50908d61	176	if (!controller)
9af4d80b	177	return -ENOMEM;
9af4d80b	178
ff00be69 RRD	179	platform_set_drvdata(pdev, controller);
ff00be69 RRD	180
9af4d80b	181	/* Copy our reference */
cf8f4462 MCB	182	controller->chip = zevio_gpio_chip;
cf8f4462 MCB	183	controller->chip.parent = &pdev->dev;
9af4d80b	184
cf8f4462 MCB	185	controller->regs = devm_platform_ioremap_resource(pdev, 0);
	186	if (IS_ERR(controller->regs))
	187	return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
	188	"failed to ioremap memory resource\n");
	189
	190	status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
9af4d80b FV	191	if (status) {
	192	dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
	193	return status;
	194	}
	195
	196	spin_lock_init(&controller->lock);
	197
	198	/* Disable interrupts, they only cause errors */
cf8f4462	199	for (i = 0; i < controller->chip.ngpio; i += 8)
9af4d80b FV	200	zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
9af4d80b FV	201
cf8f4462	202	dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");
9af4d80b FV	203
	204	return 0;
	205	}
	206
a49f2e74	207	static const struct of_device_id zevio_gpio_of_match[] = {
9af4d80b FV	208	{ .compatible = "lsi,zevio-gpio", },
	209	{ },
	210	};
	211
9af4d80b FV	212	static struct platform_driver zevio_gpio_driver = {
	213	.driver = {
	214	.name = "gpio-zevio",
9ea8d810	215	.of_match_table = zevio_gpio_of_match,
a90295b4	216	.suppress_bind_attrs = true,
9af4d80b FV	217	},
	218	.probe = zevio_gpio_probe,
	219	};
a90295b4	220	builtin_platform_driver(zevio_gpio_driver);