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130a990b | 1 | // SPDX-License-Identifier: GPL-2.0 |
ff718800 KP |
2 | /* |
3 | * Copyright (C) 2003-2015 Broadcom Corporation | |
4 | * All Rights Reserved | |
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5 | */ |
6 | ||
121111d7 | 7 | #include <linux/gpio/driver.h> |
ff718800 | 8 | #include <linux/platform_device.h> |
ff718800 KP |
9 | #include <linux/module.h> |
10 | #include <linux/irq.h> | |
11 | #include <linux/interrupt.h> | |
83ea24fd | 12 | #include <linux/irqchip/chained_irq.h> |
baa1b920 | 13 | #include <linux/acpi.h> |
ff718800 KP |
14 | |
15 | /* | |
16 | * XLP GPIO has multiple 32 bit registers for each feature where each register | |
17 | * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 | |
18 | * require 3 32-bit registers for each feature. | |
19 | * Here we only define offset of the first register for each feature. Offset of | |
20 | * the registers for pins greater than 32 can be calculated as following(Use | |
21 | * GPIO_INT_STAT as example): | |
22 | * | |
23 | * offset = (gpio / XLP_GPIO_REGSZ) * 4; | |
24 | * reg_addr = addr + offset; | |
25 | * | |
26 | * where addr is base address of the that feature register and gpio is the pin. | |
27 | */ | |
ff718800 KP |
28 | #define GPIO_9XX_BYTESWAP 0X00 |
29 | #define GPIO_9XX_CTRL 0X04 | |
30 | #define GPIO_9XX_OUTPUT_EN 0x14 | |
31 | #define GPIO_9XX_PADDRV 0x24 | |
32 | /* | |
33 | * Only for 4 interrupt enable reg are defined for now, | |
34 | * total reg available are 12. | |
35 | */ | |
36 | #define GPIO_9XX_INT_EN00 0x44 | |
37 | #define GPIO_9XX_INT_EN10 0x54 | |
38 | #define GPIO_9XX_INT_EN20 0x64 | |
39 | #define GPIO_9XX_INT_EN30 0x74 | |
40 | #define GPIO_9XX_INT_POL 0x104 | |
41 | #define GPIO_9XX_INT_TYPE 0x114 | |
42 | #define GPIO_9XX_INT_STAT 0x124 | |
43 | ||
ff718800 KP |
44 | /* Interrupt type register mask */ |
45 | #define XLP_GPIO_IRQ_TYPE_LVL 0x0 | |
46 | #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 | |
47 | ||
48 | /* Interrupt polarity register mask */ | |
49 | #define XLP_GPIO_IRQ_POL_HIGH 0x0 | |
50 | #define XLP_GPIO_IRQ_POL_LOW 0x1 | |
51 | ||
52 | #define XLP_GPIO_REGSZ 32 | |
53 | #define XLP_GPIO_IRQ_BASE 768 | |
54 | #define XLP_MAX_NR_GPIO 96 | |
55 | ||
ff718800 KP |
56 | struct xlp_gpio_priv { |
57 | struct gpio_chip chip; | |
58 | DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); | |
59 | void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ | |
60 | void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ | |
61 | void __iomem *gpio_intr_type; /* pointer to first intr type reg */ | |
62 | void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ | |
63 | void __iomem *gpio_out_en; /* pointer to first output enable reg */ | |
64 | void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ | |
65 | spinlock_t lock; | |
66 | }; | |
67 | ||
ff718800 KP |
68 | static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) |
69 | { | |
70 | u32 pos, regset; | |
71 | ||
72 | pos = gpio % XLP_GPIO_REGSZ; | |
73 | regset = (gpio / XLP_GPIO_REGSZ) * 4; | |
74 | return !!(readl(addr + regset) & BIT(pos)); | |
75 | } | |
76 | ||
77 | static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) | |
78 | { | |
79 | u32 value, pos, regset; | |
80 | ||
81 | pos = gpio % XLP_GPIO_REGSZ; | |
82 | regset = (gpio / XLP_GPIO_REGSZ) * 4; | |
83 | value = readl(addr + regset); | |
84 | ||
85 | if (state) | |
86 | value |= BIT(pos); | |
87 | else | |
88 | value &= ~BIT(pos); | |
89 | ||
90 | writel(value, addr + regset); | |
91 | } | |
92 | ||
93 | static void xlp_gpio_irq_disable(struct irq_data *d) | |
94 | { | |
95 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
e730a595 | 96 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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97 | unsigned long flags; |
98 | ||
99 | spin_lock_irqsave(&priv->lock, flags); | |
100 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); | |
101 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); | |
102 | spin_unlock_irqrestore(&priv->lock, flags); | |
103 | } | |
104 | ||
105 | static void xlp_gpio_irq_mask_ack(struct irq_data *d) | |
106 | { | |
107 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
e730a595 | 108 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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109 | unsigned long flags; |
110 | ||
111 | spin_lock_irqsave(&priv->lock, flags); | |
112 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); | |
113 | xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); | |
114 | __clear_bit(d->hwirq, priv->gpio_enabled_mask); | |
115 | spin_unlock_irqrestore(&priv->lock, flags); | |
116 | } | |
117 | ||
118 | static void xlp_gpio_irq_unmask(struct irq_data *d) | |
119 | { | |
120 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
e730a595 | 121 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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122 | unsigned long flags; |
123 | ||
124 | spin_lock_irqsave(&priv->lock, flags); | |
125 | xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); | |
126 | __set_bit(d->hwirq, priv->gpio_enabled_mask); | |
127 | spin_unlock_irqrestore(&priv->lock, flags); | |
128 | } | |
129 | ||
130 | static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) | |
131 | { | |
132 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
e730a595 | 133 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
ff718800 KP |
134 | int pol, irq_type; |
135 | ||
136 | switch (type) { | |
137 | case IRQ_TYPE_EDGE_RISING: | |
138 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; | |
139 | pol = XLP_GPIO_IRQ_POL_HIGH; | |
140 | break; | |
141 | case IRQ_TYPE_EDGE_FALLING: | |
142 | irq_type = XLP_GPIO_IRQ_TYPE_EDGE; | |
143 | pol = XLP_GPIO_IRQ_POL_LOW; | |
144 | break; | |
145 | case IRQ_TYPE_LEVEL_HIGH: | |
146 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; | |
147 | pol = XLP_GPIO_IRQ_POL_HIGH; | |
148 | break; | |
149 | case IRQ_TYPE_LEVEL_LOW: | |
150 | irq_type = XLP_GPIO_IRQ_TYPE_LVL; | |
151 | pol = XLP_GPIO_IRQ_POL_LOW; | |
152 | break; | |
153 | default: | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); | |
158 | xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static struct irq_chip xlp_gpio_irq_chip = { | |
164 | .name = "XLP-GPIO", | |
165 | .irq_mask_ack = xlp_gpio_irq_mask_ack, | |
166 | .irq_disable = xlp_gpio_irq_disable, | |
167 | .irq_set_type = xlp_gpio_set_irq_type, | |
168 | .irq_unmask = xlp_gpio_irq_unmask, | |
169 | .flags = IRQCHIP_ONESHOT_SAFE, | |
170 | }; | |
171 | ||
83ea24fd | 172 | static void xlp_gpio_generic_handler(struct irq_desc *desc) |
ff718800 | 173 | { |
83ea24fd KP |
174 | struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); |
175 | struct irq_chip *irqchip = irq_desc_get_chip(desc); | |
ff718800 KP |
176 | int gpio, regoff; |
177 | u32 gpio_stat; | |
178 | ||
179 | regoff = -1; | |
180 | gpio_stat = 0; | |
83ea24fd KP |
181 | |
182 | chained_irq_enter(irqchip, desc); | |
ff718800 KP |
183 | for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { |
184 | if (regoff != gpio / XLP_GPIO_REGSZ) { | |
185 | regoff = gpio / XLP_GPIO_REGSZ; | |
186 | gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); | |
187 | } | |
83ea24fd | 188 | |
ff718800 | 189 | if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) |
dbd1c54f | 190 | generic_handle_domain_irq(priv->chip.irq.domain, gpio); |
ff718800 | 191 | } |
83ea24fd | 192 | chained_irq_exit(irqchip, desc); |
ff718800 KP |
193 | } |
194 | ||
195 | static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) | |
196 | { | |
e730a595 | 197 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
ff718800 KP |
198 | |
199 | BUG_ON(gpio >= gc->ngpio); | |
200 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) | |
206 | { | |
e730a595 | 207 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
ff718800 KP |
208 | |
209 | BUG_ON(gpio >= gc->ngpio); | |
210 | xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) | |
216 | { | |
e730a595 | 217 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
ff718800 KP |
218 | |
219 | BUG_ON(gpio >= gc->ngpio); | |
220 | return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); | |
221 | } | |
222 | ||
223 | static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) | |
224 | { | |
e730a595 | 225 | struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
ff718800 KP |
226 | |
227 | BUG_ON(gpio >= gc->ngpio); | |
228 | xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); | |
229 | } | |
230 | ||
ff718800 KP |
231 | static int xlp_gpio_probe(struct platform_device *pdev) |
232 | { | |
233 | struct gpio_chip *gc; | |
c7e66e48 | 234 | struct gpio_irq_chip *girq; |
ff718800 | 235 | struct xlp_gpio_priv *priv; |
ff718800 | 236 | void __iomem *gpio_base; |
ea708ac5 | 237 | int irq, err; |
ff718800 | 238 | |
ff718800 KP |
239 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
240 | if (!priv) | |
241 | return -ENOMEM; | |
242 | ||
3883de02 | 243 | gpio_base = devm_platform_ioremap_resource(pdev, 0); |
ff718800 KP |
244 | if (IS_ERR(gpio_base)) |
245 | return PTR_ERR(gpio_base); | |
246 | ||
247 | irq = platform_get_irq(pdev, 0); | |
248 | if (irq < 0) | |
249 | return irq; | |
250 | ||
ea708ac5 RH |
251 | priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; |
252 | priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; | |
253 | priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; | |
254 | priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; | |
255 | priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; | |
256 | priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; | |
ff718800 KP |
257 | |
258 | bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); | |
259 | ||
260 | gc = &priv->chip; | |
261 | ||
b8a3f52e AL |
262 | gc->owner = THIS_MODULE; |
263 | gc->label = dev_name(&pdev->dev); | |
ff718800 | 264 | gc->base = 0; |
58383c78 | 265 | gc->parent = &pdev->dev; |
ea708ac5 | 266 | gc->ngpio = 70; |
ff718800 KP |
267 | gc->of_node = pdev->dev.of_node; |
268 | gc->direction_output = xlp_gpio_dir_output; | |
269 | gc->direction_input = xlp_gpio_dir_input; | |
270 | gc->set = xlp_gpio_set; | |
271 | gc->get = xlp_gpio_get; | |
272 | ||
273 | spin_lock_init(&priv->lock); | |
1630a062 | 274 | |
c7e66e48 LW |
275 | girq = &gc->irq; |
276 | girq->chip = &xlp_gpio_irq_chip; | |
277 | girq->parent_handler = xlp_gpio_generic_handler; | |
278 | girq->num_parents = 1; | |
279 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
280 | sizeof(*girq->parents), | |
281 | GFP_KERNEL); | |
282 | if (!girq->parents) | |
283 | return -ENOMEM; | |
284 | girq->parents[0] = irq; | |
ea708ac5 | 285 | girq->first = 0; |
c7e66e48 LW |
286 | girq->default_type = IRQ_TYPE_NONE; |
287 | girq->handler = handle_level_irq; | |
288 | ||
e730a595 | 289 | err = gpiochip_add_data(gc, priv); |
ff718800 | 290 | if (err < 0) |
31bd86d9 | 291 | return err; |
ff718800 | 292 | |
ff718800 KP |
293 | dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); |
294 | ||
295 | return 0; | |
ff718800 KP |
296 | } |
297 | ||
baa1b920 KP |
298 | #ifdef CONFIG_ACPI |
299 | static const struct acpi_device_id xlp_gpio_acpi_match[] = { | |
300 | { "BRCM9006", GPIO_VARIANT_VULCAN }, | |
529f75d8 | 301 | { "CAV9006", GPIO_VARIANT_VULCAN }, |
baa1b920 KP |
302 | {}, |
303 | }; | |
304 | MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); | |
305 | #endif | |
306 | ||
ff718800 KP |
307 | static struct platform_driver xlp_gpio_driver = { |
308 | .driver = { | |
309 | .name = "xlp-gpio", | |
baa1b920 | 310 | .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match), |
ff718800 KP |
311 | }, |
312 | .probe = xlp_gpio_probe, | |
313 | }; | |
314 | module_platform_driver(xlp_gpio_driver); | |
315 | ||
316 | MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); | |
317 | MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); | |
318 | MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); | |
319 | MODULE_LICENSE("GPL v2"); |