[linux-2.6-block.git] / drivers / gpio / gpio-xlp.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2003-2015 Broadcom Corporation
 * All Rights Reserved
 */

#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/acpi.h>

/*
 * XLP GPIO has multiple 32 bit registers for each feature where each register
 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
 * require 3 32-bit registers for each feature.
 * Here we only define offset of the first register for each feature. Offset of
 * the registers for pins greater than 32 can be calculated as following(Use
 * GPIO_INT_STAT as example):
 *
 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
 * reg_addr = addr + offset;
 *
 * where addr is base address of the that feature register and gpio is the pin.
 */
#define GPIO_9XX_BYTESWAP	0X00
#define GPIO_9XX_CTRL		0X04
#define GPIO_9XX_OUTPUT_EN	0x14
#define GPIO_9XX_PADDRV		0x24
/*
 * Only for 4 interrupt enable reg are defined for now,
 * total reg available are 12.
 */
#define GPIO_9XX_INT_EN00	0x44
#define GPIO_9XX_INT_EN10	0x54
#define GPIO_9XX_INT_EN20	0x64
#define GPIO_9XX_INT_EN30	0x74
#define GPIO_9XX_INT_POL	0x104
#define GPIO_9XX_INT_TYPE	0x114
#define GPIO_9XX_INT_STAT	0x124

/* Interrupt type register mask */
#define XLP_GPIO_IRQ_TYPE_LVL	0x0
#define XLP_GPIO_IRQ_TYPE_EDGE	0x1

/* Interrupt polarity register mask */
#define XLP_GPIO_IRQ_POL_HIGH	0x0
#define XLP_GPIO_IRQ_POL_LOW	0x1

#define XLP_GPIO_REGSZ		32
#define XLP_GPIO_IRQ_BASE	768
#define XLP_MAX_NR_GPIO		96

struct xlp_gpio_priv {
	struct gpio_chip chip;
	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
	void __iomem *gpio_intr_en;	/* pointer to first intr enable reg */
	void __iomem *gpio_intr_stat;	/* pointer to first intr status reg */
	void __iomem *gpio_intr_type;	/* pointer to first intr type reg */
	void __iomem *gpio_intr_pol;	/* pointer to first intr polarity reg */
	void __iomem *gpio_out_en;	/* pointer to first output enable reg */
	void __iomem *gpio_paddrv;	/* pointer to first pad drive reg */
	spinlock_t lock;
};

static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
{
	u32 pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	return !!(readl(addr + regset) & BIT(pos));
}

static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
{
	u32 value, pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	value = readl(addr + regset);

	if (state)
		value |= BIT(pos);
	else
		value &= ~BIT(pos);

	writel(value, addr + regset);
}

static void xlp_gpio_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);

	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
}

static void xlp_gpio_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
}

static void xlp_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void xlp_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
	__set_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	int pol, irq_type;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	default:
		return -EINVAL;
	}

	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);

	return 0;
}

static struct irq_chip xlp_gpio_irq_chip = {
	.name		= "XLP-GPIO",
	.irq_mask_ack	= xlp_gpio_irq_mask_ack,
	.irq_enable	= xlp_gpio_irq_enable,
	.irq_disable	= xlp_gpio_irq_disable,
	.irq_set_type	= xlp_gpio_set_irq_type,
	.irq_unmask	= xlp_gpio_irq_unmask,
	.flags		= IRQCHIP_ONESHOT_SAFE | IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void xlp_gpio_generic_handler(struct irq_desc *desc)
{
	struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	int gpio, regoff;
	u32 gpio_stat;

	regoff = -1;
	gpio_stat = 0;

	chained_irq_enter(irqchip, desc);
	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
		if (regoff != gpio / XLP_GPIO_REGSZ) {
			regoff = gpio / XLP_GPIO_REGSZ;
			gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
		}

		if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
			generic_handle_domain_irq(priv->chip.irq.domain, gpio);
	}
	chained_irq_exit(irqchip, desc);
}

static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);

	return 0;
}

static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);

	return 0;
}

static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
}

static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
}

static int xlp_gpio_probe(struct platform_device *pdev)
{
	struct gpio_chip *gc;
	struct gpio_irq_chip *girq;
	struct xlp_gpio_priv *priv;
	void __iomem *gpio_base;
	int irq, err;

	priv = devm_kzalloc(&pdev->dev,	sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	gpio_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(gpio_base))
		return PTR_ERR(gpio_base);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
	priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
	priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
	priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
	priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
	priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;

	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);

	gc = &priv->chip;

	gc->owner = THIS_MODULE;
	gc->label = dev_name(&pdev->dev);
	gc->base = 0;
	gc->parent = &pdev->dev;
	gc->ngpio = 70;
	gc->direction_output = xlp_gpio_dir_output;
	gc->direction_input = xlp_gpio_dir_input;
	gc->set = xlp_gpio_set;
	gc->get = xlp_gpio_get;

	spin_lock_init(&priv->lock);

	girq = &gc->irq;
	gpio_irq_chip_set_chip(girq, &xlp_gpio_irq_chip);
	girq->parent_handler = xlp_gpio_generic_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1,
				     sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = irq;
	girq->first = 0;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_level_irq;

	err = gpiochip_add_data(gc, priv);
	if (err < 0)
		return err;

	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);

	return 0;
}

#ifdef CONFIG_ACPI
static const struct acpi_device_id xlp_gpio_acpi_match[] = {
	{ "BRCM9006" },
	{ "CAV9006" },
	{},
};
MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
#endif

static struct platform_driver xlp_gpio_driver = {
	.driver		= {
		.name	= "xlp-gpio",
		.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
	},
	.probe		= xlp_gpio_probe,
};
module_platform_driver(xlp_gpio_driver);

MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
130a990b	1	// SPDX-License-Identifier: GPL-2.0
ff718800 KP	2	/*
	3	* Copyright (C) 2003-2015 Broadcom Corporation
	4	* All Rights Reserved
ff718800 KP	5	*/
ff718800 KP	6
121111d7	7	#include <linux/gpio/driver.h>
ff718800	8	#include <linux/platform_device.h>
ff718800 KP	9	#include <linux/module.h>
	10	#include <linux/irq.h>
	11	#include <linux/interrupt.h>
83ea24fd	12	#include <linux/irqchip/chained_irq.h>
baa1b920	13	#include <linux/acpi.h>
ff718800 KP	14
	15	/*
	16	* XLP GPIO has multiple 32 bit registers for each feature where each register
	17	* controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
	18	* require 3 32-bit registers for each feature.
	19	* Here we only define offset of the first register for each feature. Offset of
	20	* the registers for pins greater than 32 can be calculated as following(Use
	21	* GPIO_INT_STAT as example):
	22	*
	23	* offset = (gpio / XLP_GPIO_REGSZ) * 4;
	24	* reg_addr = addr + offset;
	25	*
	26	* where addr is base address of the that feature register and gpio is the pin.
	27	*/
ff718800 KP	28	#define GPIO_9XX_BYTESWAP 0X00
	29	#define GPIO_9XX_CTRL 0X04
	30	#define GPIO_9XX_OUTPUT_EN 0x14
	31	#define GPIO_9XX_PADDRV 0x24
	32	/*
	33	* Only for 4 interrupt enable reg are defined for now,
	34	* total reg available are 12.
	35	*/
	36	#define GPIO_9XX_INT_EN00 0x44
	37	#define GPIO_9XX_INT_EN10 0x54
	38	#define GPIO_9XX_INT_EN20 0x64
	39	#define GPIO_9XX_INT_EN30 0x74
	40	#define GPIO_9XX_INT_POL 0x104
	41	#define GPIO_9XX_INT_TYPE 0x114
	42	#define GPIO_9XX_INT_STAT 0x124
	43
ff718800 KP	44	/* Interrupt type register mask */
	45	#define XLP_GPIO_IRQ_TYPE_LVL 0x0
	46	#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
	47
	48	/* Interrupt polarity register mask */
	49	#define XLP_GPIO_IRQ_POL_HIGH 0x0
	50	#define XLP_GPIO_IRQ_POL_LOW 0x1
	51
	52	#define XLP_GPIO_REGSZ 32
	53	#define XLP_GPIO_IRQ_BASE 768
	54	#define XLP_MAX_NR_GPIO 96
	55
ff718800 KP	56	struct xlp_gpio_priv {
	57	struct gpio_chip chip;
	58	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
	59	void __iomem gpio_intr_en; / pointer to first intr enable reg */
	60	void __iomem gpio_intr_stat; / pointer to first intr status reg */
	61	void __iomem gpio_intr_type; / pointer to first intr type reg */
	62	void __iomem gpio_intr_pol; / pointer to first intr polarity reg */
	63	void __iomem gpio_out_en; / pointer to first output enable reg */
	64	void __iomem gpio_paddrv; / pointer to first pad drive reg */
	65	spinlock_t lock;
	66	};
	67
ff718800 KP	68	static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
	69	{
	70	u32 pos, regset;
	71
	72	pos = gpio % XLP_GPIO_REGSZ;
	73	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	74	return !!(readl(addr + regset) & BIT(pos));
	75	}
	76
	77	static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
	78	{
	79	u32 value, pos, regset;
	80
	81	pos = gpio % XLP_GPIO_REGSZ;
	82	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	83	value = readl(addr + regset);
	84
	85	if (state)
	86	value \|= BIT(pos);
	87	else
	88	value &= ~BIT(pos);
	89
	90	writel(value, addr + regset);
	91	}
	92
2093bcd8 LW	93	static void xlp_gpio_irq_enable(struct irq_data *d)
	94	{
	95	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	96
	97	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
	98	}
	99
ff718800 KP	100	static void xlp_gpio_irq_disable(struct irq_data *d)
	101	{
	102	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	103	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	104	unsigned long flags;
	105
	106	spin_lock_irqsave(&priv->lock, flags);
	107	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	108	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	109	spin_unlock_irqrestore(&priv->lock, flags);
2093bcd8	110	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
ff718800 KP	111	}
	112
	113	static void xlp_gpio_irq_mask_ack(struct irq_data *d)
	114	{
	115	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	116	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	117	unsigned long flags;
	118
	119	spin_lock_irqsave(&priv->lock, flags);
	120	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	121	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
	122	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	123	spin_unlock_irqrestore(&priv->lock, flags);
	124	}
	125
	126	static void xlp_gpio_irq_unmask(struct irq_data *d)
	127	{
	128	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	129	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	130	unsigned long flags;
	131
	132	spin_lock_irqsave(&priv->lock, flags);
	133	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
	134	__set_bit(d->hwirq, priv->gpio_enabled_mask);
	135	spin_unlock_irqrestore(&priv->lock, flags);
	136	}
	137
	138	static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
	139	{
	140	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	141	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	142	int pol, irq_type;
	143
	144	switch (type) {
	145	case IRQ_TYPE_EDGE_RISING:
	146	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
	147	pol = XLP_GPIO_IRQ_POL_HIGH;
	148	break;
	149	case IRQ_TYPE_EDGE_FALLING:
	150	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
	151	pol = XLP_GPIO_IRQ_POL_LOW;
	152	break;
	153	case IRQ_TYPE_LEVEL_HIGH:
	154	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
	155	pol = XLP_GPIO_IRQ_POL_HIGH;
	156	break;
	157	case IRQ_TYPE_LEVEL_LOW:
	158	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
	159	pol = XLP_GPIO_IRQ_POL_LOW;
	160	break;
	161	default:
	162	return -EINVAL;
	163	}
	164
	165	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
	166	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
	167
	168	return 0;
	169	}
	170
	171	static struct irq_chip xlp_gpio_irq_chip = {
	172	.name = "XLP-GPIO",
	173	.irq_mask_ack = xlp_gpio_irq_mask_ack,
2093bcd8	174	.irq_enable = xlp_gpio_irq_enable,
ff718800 KP	175	.irq_disable = xlp_gpio_irq_disable,
	176	.irq_set_type = xlp_gpio_set_irq_type,
	177	.irq_unmask = xlp_gpio_irq_unmask,
2093bcd8 LW	178	.flags = IRQCHIP_ONESHOT_SAFE \| IRQCHIP_IMMUTABLE,
2093bcd8 LW	179	GPIOCHIP_IRQ_RESOURCE_HELPERS,
ff718800 KP	180	};
ff718800 KP	181
83ea24fd	182	static void xlp_gpio_generic_handler(struct irq_desc *desc)
ff718800	183	{
83ea24fd KP	184	struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
83ea24fd KP	185	struct irq_chip *irqchip = irq_desc_get_chip(desc);
ff718800 KP	186	int gpio, regoff;
	187	u32 gpio_stat;
	188
	189	regoff = -1;
	190	gpio_stat = 0;
83ea24fd KP	191
83ea24fd KP	192	chained_irq_enter(irqchip, desc);
ff718800 KP	193	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
	194	if (regoff != gpio / XLP_GPIO_REGSZ) {
	195	regoff = gpio / XLP_GPIO_REGSZ;
	196	gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
	197	}
83ea24fd	198
ff718800	199	if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
dbd1c54f	200	generic_handle_domain_irq(priv->chip.irq.domain, gpio);
ff718800	201	}
83ea24fd	202	chained_irq_exit(irqchip, desc);
ff718800 KP	203	}
	204
	205	static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
	206	{
e730a595	207	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	208
	209	BUG_ON(gpio >= gc->ngpio);
	210	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
	211
	212	return 0;
	213	}
	214
	215	static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
	216	{
e730a595	217	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	218
	219	BUG_ON(gpio >= gc->ngpio);
	220	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
	221
	222	return 0;
	223	}
	224
	225	static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
	226	{
e730a595	227	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	228
	229	BUG_ON(gpio >= gc->ngpio);
	230	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
	231	}
	232
	233	static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
	234	{
e730a595	235	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	236
	237	BUG_ON(gpio >= gc->ngpio);
	238	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
	239	}
	240
ff718800 KP	241	static int xlp_gpio_probe(struct platform_device *pdev)
	242	{
	243	struct gpio_chip *gc;
c7e66e48	244	struct gpio_irq_chip *girq;
ff718800	245	struct xlp_gpio_priv *priv;
ff718800	246	void __iomem *gpio_base;
ea708ac5	247	int irq, err;
ff718800	248
ff718800 KP	249	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	250	if (!priv)
	251	return -ENOMEM;
	252
3883de02	253	gpio_base = devm_platform_ioremap_resource(pdev, 0);
ff718800 KP	254	if (IS_ERR(gpio_base))
	255	return PTR_ERR(gpio_base);
	256
	257	irq = platform_get_irq(pdev, 0);
	258	if (irq < 0)
	259	return irq;
	260
ea708ac5 RH	261	priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
	262	priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
	263	priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
	264	priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
	265	priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
	266	priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
ff718800 KP	267
	268	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
	269
	270	gc = &priv->chip;
	271
b8a3f52e AL	272	gc->owner = THIS_MODULE;
b8a3f52e AL	273	gc->label = dev_name(&pdev->dev);
ff718800	274	gc->base = 0;
58383c78	275	gc->parent = &pdev->dev;
ea708ac5	276	gc->ngpio = 70;
ff718800 KP	277	gc->direction_output = xlp_gpio_dir_output;
	278	gc->direction_input = xlp_gpio_dir_input;
	279	gc->set = xlp_gpio_set;
	280	gc->get = xlp_gpio_get;
	281
	282	spin_lock_init(&priv->lock);
1630a062	283
c7e66e48	284	girq = &gc->irq;
2093bcd8	285	gpio_irq_chip_set_chip(girq, &xlp_gpio_irq_chip);
c7e66e48 LW	286	girq->parent_handler = xlp_gpio_generic_handler;
	287	girq->num_parents = 1;
	288	girq->parents = devm_kcalloc(&pdev->dev, 1,
	289	sizeof(*girq->parents),
	290	GFP_KERNEL);
	291	if (!girq->parents)
	292	return -ENOMEM;
	293	girq->parents[0] = irq;
ea708ac5	294	girq->first = 0;
c7e66e48 LW	295	girq->default_type = IRQ_TYPE_NONE;
	296	girq->handler = handle_level_irq;
	297
e730a595	298	err = gpiochip_add_data(gc, priv);
ff718800	299	if (err < 0)
31bd86d9	300	return err;
ff718800	301
ff718800 KP	302	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
	303
	304	return 0;
ff718800 KP	305	}
ff718800 KP	306
baa1b920 KP	307	#ifdef CONFIG_ACPI
baa1b920 KP	308	static const struct acpi_device_id xlp_gpio_acpi_match[] = {
e320d9c2 RH	309	{ "BRCM9006" },
e320d9c2 RH	310	{ "CAV9006" },
baa1b920 KP	311	{},
	312	};
	313	MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
	314	#endif
	315
ff718800 KP	316	static struct platform_driver xlp_gpio_driver = {
	317	.driver = {
	318	.name = "xlp-gpio",
baa1b920	319	.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
ff718800 KP	320	},
	321	.probe = xlp_gpio_probe,
	322	};
	323	module_platform_driver(xlp_gpio_driver);
	324
	325	MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
	326	MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
	327	MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
	328	MODULE_LICENSE("GPL v2");