[linux-block.git] / drivers / gpio / gpio-xilinx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Xilinx gpio driver for xps/axi_gpio IP.
 *
 * Copyright 2008 - 2013 Xilinx, Inc.
 */

#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>

/* Register Offset Definitions */
#define XGPIO_DATA_OFFSET   (0x0)	/* Data register  */
#define XGPIO_TRI_OFFSET    (0x4)	/* I/O direction register  */

#define XGPIO_CHANNEL_OFFSET	0x8

/* Read/Write access to the GPIO registers */
#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
# define xgpio_readreg(offset)		readl(offset)
# define xgpio_writereg(offset, val)	writel(val, offset)
#else
# define xgpio_readreg(offset)		__raw_readl(offset)
# define xgpio_writereg(offset, val)	__raw_writel(val, offset)
#endif

/**
 * struct xgpio_instance - Stores information about GPIO device
 * @gc: GPIO chip
 * @regs: register block
 * @gpio_width: GPIO width for every channel
 * @gpio_state: GPIO state shadow register
 * @gpio_dir: GPIO direction shadow register
 * @gpio_lock: Lock used for synchronization
 */
struct xgpio_instance {
	struct gpio_chip gc;
	void __iomem *regs;
	unsigned int gpio_width[2];
	u32 gpio_state[2];
	u32 gpio_dir[2];
	spinlock_t gpio_lock[2];
};

static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
{
	if (gpio >= chip->gpio_width[0])
		return 1;

	return 0;
}

static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
{
	if (xgpio_index(chip, gpio))
		return XGPIO_CHANNEL_OFFSET;

	return 0;
}

static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
{
	if (xgpio_index(chip, gpio))
		return gpio - chip->gpio_width[0];

	return gpio;
}

/**
 * xgpio_get - Read the specified signal of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * This function reads the specified signal of the GPIO device.
 *
 * Return:
 * 0 if direction of GPIO signals is set as input otherwise it
 * returns negative error value.
 */
static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	u32 val;

	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
			    xgpio_regoffset(chip, gpio));

	return !!(val & BIT(xgpio_offset(chip, gpio)));
}

/**
 * xgpio_set - Write the specified signal of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * This function writes the specified value in to the specified signal of the
 * GPIO device.
 */
static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write to GPIO signal and set its direction to output */
	if (val)
		chip->gpio_state[index] |= BIT(offset);
	else
		chip->gpio_state[index] &= ~BIT(offset);

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
		       xgpio_regoffset(chip, gpio), chip->gpio_state[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
}

/**
 * xgpio_set_multiple - Write the specified signals of the GPIO device.
 * @gc:     Pointer to gpio_chip device structure.
 * @mask:   Mask of the GPIOS to modify.
 * @bits:   Value to be wrote on each GPIO
 *
 * This function writes the specified values into the specified signals of the
 * GPIO devices.
 */
static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
			       unsigned long *bits)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index = xgpio_index(chip, 0);
	int offset, i;

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write to GPIO signals */
	for (i = 0; i < gc->ngpio; i++) {
		if (*mask == 0)
			break;
		/* Once finished with an index write it out to the register */
		if (index !=  xgpio_index(chip, i)) {
			xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
				       index * XGPIO_CHANNEL_OFFSET,
				       chip->gpio_state[index]);
			spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
			index =  xgpio_index(chip, i);
			spin_lock_irqsave(&chip->gpio_lock[index], flags);
		}
		if (__test_and_clear_bit(i, mask)) {
			offset =  xgpio_offset(chip, i);
			if (test_bit(i, bits))
				chip->gpio_state[index] |= BIT(offset);
			else
				chip->gpio_state[index] &= ~BIT(offset);
		}
	}

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
		       index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
}

/**
 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * Return:
 * 0 - if direction of GPIO signals is set as input
 * otherwise it returns negative error value.
 */
static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Set the GPIO bit in shadow register and set direction as input */
	chip->gpio_dir[index] |= BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
		       xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);

	return 0;
}

/**
 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * This function sets the direction of specified GPIO signal as output.
 *
 * Return:
 * If all GPIO signals of GPIO chip is configured as input then it returns
 * error otherwise it returns 0.
 */
static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	unsigned long flags;
	struct xgpio_instance *chip = gpiochip_get_data(gc);
	int index =  xgpio_index(chip, gpio);
	int offset =  xgpio_offset(chip, gpio);

	spin_lock_irqsave(&chip->gpio_lock[index], flags);

	/* Write state of GPIO signal */
	if (val)
		chip->gpio_state[index] |= BIT(offset);
	else
		chip->gpio_state[index] &= ~BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
			xgpio_regoffset(chip, gpio), chip->gpio_state[index]);

	/* Clear the GPIO bit in shadow register and set direction as output */
	chip->gpio_dir[index] &= ~BIT(offset);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
			xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);

	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);

	return 0;
}

/**
 * xgpio_save_regs - Set initial values of GPIO pins
 * @chip: Pointer to GPIO instance
 */
static void xgpio_save_regs(struct xgpio_instance *chip)
{
	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET,	chip->gpio_state[0]);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);

	if (!chip->gpio_width[1])
		return;

	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
		       chip->gpio_state[1]);
	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
		       chip->gpio_dir[1]);
}

/**
 * xgpio_of_probe - Probe method for the GPIO device.
 * @pdev: pointer to the platform device
 *
 * Return:
 * It returns 0, if the driver is bound to the GPIO device, or
 * a negative value if there is an error.
 */
static int xgpio_probe(struct platform_device *pdev)
{
	struct xgpio_instance *chip;
	int status = 0;
	struct device_node *np = pdev->dev.of_node;
	u32 is_dual;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);

	/* Update GPIO state shadow register with default value */
	of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);

	/* Update GPIO direction shadow register with default value */
	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
		chip->gpio_dir[0] = 0xFFFFFFFF;

	/*
	 * Check device node and parent device node for device width
	 * and assume default width of 32
	 */
	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
		chip->gpio_width[0] = 32;

	spin_lock_init(&chip->gpio_lock[0]);

	if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
		is_dual = 0;

	if (is_dual) {
		/* Update GPIO state shadow register with default value */
		of_property_read_u32(np, "xlnx,dout-default-2",
				     &chip->gpio_state[1]);

		/* Update GPIO direction shadow register with default value */
		if (of_property_read_u32(np, "xlnx,tri-default-2",
					 &chip->gpio_dir[1]))
			chip->gpio_dir[1] = 0xFFFFFFFF;

		/*
		 * Check device node and parent device node for device width
		 * and assume default width of 32
		 */
		if (of_property_read_u32(np, "xlnx,gpio2-width",
					 &chip->gpio_width[1]))
			chip->gpio_width[1] = 32;

		spin_lock_init(&chip->gpio_lock[1]);
	}

	chip->gc.base = -1;
	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
	chip->gc.parent = &pdev->dev;
	chip->gc.direction_input = xgpio_dir_in;
	chip->gc.direction_output = xgpio_dir_out;
	chip->gc.get = xgpio_get;
	chip->gc.set = xgpio_set;
	chip->gc.set_multiple = xgpio_set_multiple;

	chip->gc.label = dev_name(&pdev->dev);

	chip->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(chip->regs)) {
		dev_err(&pdev->dev, "failed to ioremap memory resource\n");
		return PTR_ERR(chip->regs);
	}

	xgpio_save_regs(chip);

	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
	if (status) {
		dev_err(&pdev->dev, "failed to add GPIO chip\n");
		return status;
	}

	return 0;
}

static const struct of_device_id xgpio_of_match[] = {
	{ .compatible = "xlnx,xps-gpio-1.00.a", },
	{ /* end of list */ },
};

MODULE_DEVICE_TABLE(of, xgpio_of_match);

static struct platform_driver xgpio_plat_driver = {
	.probe		= xgpio_probe,
	.driver		= {
			.name = "gpio-xilinx",
			.of_match_table	= xgpio_of_match,
	},
};

static int __init xgpio_init(void)
{
	return platform_driver_register(&xgpio_plat_driver);
}

subsys_initcall(xgpio_init);

static void __exit xgpio_exit(void)
{
	platform_driver_unregister(&xgpio_plat_driver);
}
module_exit(xgpio_exit);

MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION("Xilinx GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6e75fc04	1	// SPDX-License-Identifier: GPL-2.0-only
0bcb6069	2	/*
74600ee0	3	* Xilinx gpio driver for xps/axi_gpio IP.
0bcb6069	4	*
74600ee0	5	* Copyright 2008 - 2013 Xilinx, Inc.
0bcb6069 JL	6	*/
0bcb6069 JL	7
74600ee0	8	#include <linux/bitops.h>
0bcb6069 JL	9	#include <linux/init.h>
0bcb6069 JL	10	#include <linux/errno.h>
bb207ef1	11	#include <linux/module.h>
0bcb6069 JL	12	#include <linux/of_device.h>
0bcb6069 JL	13	#include <linux/of_platform.h>
0bcb6069	14	#include <linux/io.h>
516df4eb	15	#include <linux/gpio/driver.h>
5a0e3ad6	16	#include <linux/slab.h>
0bcb6069 JL	17
	18	/* Register Offset Definitions */
	19	#define XGPIO_DATA_OFFSET (0x0) /* Data register */
	20	#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
	21
74600ee0 MS	22	#define XGPIO_CHANNEL_OFFSET 0x8
	23
	24	/* Read/Write access to the GPIO registers */
c54c58ba	25	#if defined(CONFIG_ARCH_ZYNQ) \|\| defined(CONFIG_X86)
cc090d61 MS	26	# define xgpio_readreg(offset) readl(offset)
	27	# define xgpio_writereg(offset, val) writel(val, offset)
	28	#else
	29	# define xgpio_readreg(offset) __raw_readl(offset)
	30	# define xgpio_writereg(offset, val) __raw_writel(val, offset)
	31	#endif
74600ee0 MS	32
	33	/**
	34	* struct xgpio_instance - Stores information about GPIO device
1ebd0687 RH	35	* @gc: GPIO chip
1ebd0687 RH	36	* @regs: register block
3c1b5c9b	37	* @gpio_width: GPIO width for every channel
4ae798fa RRD	38	* @gpio_state: GPIO state shadow register
	39	* @gpio_dir: GPIO direction shadow register
	40	* @gpio_lock: Lock used for synchronization
74600ee0	41	*/
0bcb6069	42	struct xgpio_instance {
1ebd0687 RH	43	struct gpio_chip gc;
1ebd0687 RH	44	void __iomem *regs;
1d6902d3 RRD	45	unsigned int gpio_width[2];
	46	u32 gpio_state[2];
	47	u32 gpio_dir[2];
	48	spinlock_t gpio_lock[2];
749564ff RRD	49	};
749564ff RRD	50
1d6902d3 RRD	51	static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
	52	{
	53	if (gpio >= chip->gpio_width[0])
	54	return 1;
	55
	56	return 0;
	57	}
	58
	59	static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
	60	{
	61	if (xgpio_index(chip, gpio))
	62	return XGPIO_CHANNEL_OFFSET;
	63
	64	return 0;
	65	}
	66
	67	static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
	68	{
	69	if (xgpio_index(chip, gpio))
	70	return gpio - chip->gpio_width[0];
	71
	72	return gpio;
	73	}
0bcb6069 JL	74
	75	/**
	76	* xgpio_get - Read the specified signal of the GPIO device.
	77	* @gc: Pointer to gpio_chip device structure.
	78	* @gpio: GPIO signal number.
	79	*
4ae798fa RRD	80	* This function reads the specified signal of the GPIO device.
	81	*
	82	* Return:
	83	* 0 if direction of GPIO signals is set as input otherwise it
	84	* returns negative error value.
0bcb6069 JL	85	*/
	86	static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
	87	{
097d88e9	88	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3	89	u32 val;
0bcb6069	90
1ebd0687	91	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3 RRD	92	xgpio_regoffset(chip, gpio));
	93
	94	return !!(val & BIT(xgpio_offset(chip, gpio)));
0bcb6069 JL	95	}
	96
	97	/**
	98	* xgpio_set - Write the specified signal of the GPIO device.
	99	* @gc: Pointer to gpio_chip device structure.
	100	* @gpio: GPIO signal number.
	101	* @val: Value to be written to specified signal.
	102	*
	103	* This function writes the specified value in to the specified signal of the
	104	* GPIO device.
	105	*/
	106	static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	107	{
	108	unsigned long flags;
097d88e9	109	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RRD	110	int index = xgpio_index(chip, gpio);
1d6902d3 RRD	111	int offset = xgpio_offset(chip, gpio);
0bcb6069	112
1d6902d3	113	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	114
	115	/* Write to GPIO signal and set its direction to output */
	116	if (val)
1d6902d3	117	chip->gpio_state[index] \|= BIT(offset);
0bcb6069	118	else
1d6902d3	119	chip->gpio_state[index] &= ~BIT(offset);
74600ee0	120
1ebd0687	121	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3	122	xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
0bcb6069	123
1d6902d3	124	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	125	}
0bcb6069 JL	126
8e7c1b80 IR	127	/**
	128	* xgpio_set_multiple - Write the specified signals of the GPIO device.
	129	* @gc: Pointer to gpio_chip device structure.
	130	* @mask: Mask of the GPIOS to modify.
	131	* @bits: Value to be wrote on each GPIO
	132	*
	133	* This function writes the specified values into the specified signals of the
	134	* GPIO devices.
	135	*/
	136	static void xgpio_set_multiple(struct gpio_chip gc, unsigned long mask,
	137	unsigned long *bits)
	138	{
	139	unsigned long flags;
8e7c1b80 IR	140	struct xgpio_instance *chip = gpiochip_get_data(gc);
	141	int index = xgpio_index(chip, 0);
	142	int offset, i;
	143
	144	spin_lock_irqsave(&chip->gpio_lock[index], flags);
	145
	146	/* Write to GPIO signals */
	147	for (i = 0; i < gc->ngpio; i++) {
	148	if (*mask == 0)
	149	break;
c3afa804	150	/* Once finished with an index write it out to the register */
8e7c1b80	151	if (index != xgpio_index(chip, i)) {
1ebd0687	152	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
c3afa804	153	index * XGPIO_CHANNEL_OFFSET,
8e7c1b80 IR	154	chip->gpio_state[index]);
	155	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
	156	index = xgpio_index(chip, i);
	157	spin_lock_irqsave(&chip->gpio_lock[index], flags);
	158	}
	159	if (__test_and_clear_bit(i, mask)) {
	160	offset = xgpio_offset(chip, i);
	161	if (test_bit(i, bits))
	162	chip->gpio_state[index] \|= BIT(offset);
	163	else
	164	chip->gpio_state[index] &= ~BIT(offset);
	165	}
	166	}
	167
1ebd0687	168	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
c3afa804	169	index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
8e7c1b80 IR	170
	171	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
	172	}
	173
0bcb6069 JL	174	/**
	175	* xgpio_dir_in - Set the direction of the specified GPIO signal as input.
	176	* @gc: Pointer to gpio_chip device structure.
	177	* @gpio: GPIO signal number.
	178	*
4ae798fa RRD	179	* Return:
	180	* 0 - if direction of GPIO signals is set as input
	181	* otherwise it returns negative error value.
0bcb6069 JL	182	*/
	183	static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	184	{
	185	unsigned long flags;
097d88e9	186	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RRD	187	int index = xgpio_index(chip, gpio);
1d6902d3 RRD	188	int offset = xgpio_offset(chip, gpio);
0bcb6069	189
1d6902d3	190	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	191
0bcb6069 JL	192	/* Set the GPIO bit in shadow register and set direction as input */
1d6902d3	193	chip->gpio_dir[index] \|= BIT(offset);
1ebd0687	194	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
1d6902d3	195	xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
0bcb6069	196
1d6902d3	197	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	198
	199	return 0;
	200	}
	201
	202	/**
	203	* xgpio_dir_out - Set the direction of the specified GPIO signal as output.
	204	* @gc: Pointer to gpio_chip device structure.
	205	* @gpio: GPIO signal number.
	206	* @val: Value to be written to specified signal.
	207	*
4ae798fa RRD	208	* This function sets the direction of specified GPIO signal as output.
	209	*
	210	* Return:
	211	* If all GPIO signals of GPIO chip is configured as input then it returns
0bcb6069 JL	212	* error otherwise it returns 0.
	213	*/
	214	static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	215	{
	216	unsigned long flags;
097d88e9	217	struct xgpio_instance *chip = gpiochip_get_data(gc);
1d6902d3 RRD	218	int index = xgpio_index(chip, gpio);
1d6902d3 RRD	219	int offset = xgpio_offset(chip, gpio);
0bcb6069	220
1d6902d3	221	spin_lock_irqsave(&chip->gpio_lock[index], flags);
0bcb6069 JL	222
	223	/* Write state of GPIO signal */
	224	if (val)
1d6902d3	225	chip->gpio_state[index] \|= BIT(offset);
0bcb6069	226	else
1d6902d3	227	chip->gpio_state[index] &= ~BIT(offset);
1ebd0687	228	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
1d6902d3	229	xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
0bcb6069 JL	230
0bcb6069 JL	231	/* Clear the GPIO bit in shadow register and set direction as output */
1d6902d3	232	chip->gpio_dir[index] &= ~BIT(offset);
1ebd0687	233	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
1d6902d3	234	xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
0bcb6069	235
1d6902d3	236	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
0bcb6069 JL	237
	238	return 0;
	239	}
	240
	241	/**
	242	* xgpio_save_regs - Set initial values of GPIO pins
1ebd0687	243	* @chip: Pointer to GPIO instance
0bcb6069	244	*/
1ebd0687	245	static void xgpio_save_regs(struct xgpio_instance *chip)
0bcb6069	246	{
1ebd0687 RH	247	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
1ebd0687 RH	248	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
1d6902d3 RRD	249
	250	if (!chip->gpio_width[1])
	251	return;
	252
1ebd0687	253	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
1d6902d3	254	chip->gpio_state[1]);
1ebd0687	255	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
1d6902d3	256	chip->gpio_dir[1]);
0bcb6069 JL	257	}
	258
	259	/**
	260	* xgpio_of_probe - Probe method for the GPIO device.
749564ff	261	* @pdev: pointer to the platform device
0bcb6069	262	*
4ae798fa RRD	263	* Return:
	264	* It returns 0, if the driver is bound to the GPIO device, or
	265	* a negative value if there is an error.
0bcb6069	266	*/
749564ff	267	static int xgpio_probe(struct platform_device *pdev)
0bcb6069 JL	268	{
0bcb6069 JL	269	struct xgpio_instance *chip;
0bcb6069	270	int status = 0;
749564ff	271	struct device_node *np = pdev->dev.of_node;
1d6902d3	272	u32 is_dual;
0bcb6069	273
1d6902d3 RRD	274	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1d6902d3 RRD	275	if (!chip)
0bcb6069	276	return -ENOMEM;
0bcb6069	277
1d6902d3	278	platform_set_drvdata(pdev, chip);
749564ff	279
0bcb6069	280	/* Update GPIO state shadow register with default value */
1d6902d3	281	of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
0bcb6069 JL	282
0bcb6069 JL	283	/* Update GPIO direction shadow register with default value */
1d6902d3 RRD	284	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
1d6902d3 RRD	285	chip->gpio_dir[0] = 0xFFFFFFFF;
6f8bf500	286
1b4c5a6e GV	287	/*
	288	* Check device node and parent device node for device width
	289	* and assume default width of 32
	290	*/
1d6902d3 RRD	291	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
	292	chip->gpio_width[0] = 32;
	293
	294	spin_lock_init(&chip->gpio_lock[0]);
	295
	296	if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
	297	is_dual = 0;
0bcb6069	298
1d6902d3 RRD	299	if (is_dual) {
	300	/* Update GPIO state shadow register with default value */
	301	of_property_read_u32(np, "xlnx,dout-default-2",
	302	&chip->gpio_state[1]);
	303
	304	/* Update GPIO direction shadow register with default value */
	305	if (of_property_read_u32(np, "xlnx,tri-default-2",
	306	&chip->gpio_dir[1]))
	307	chip->gpio_dir[1] = 0xFFFFFFFF;
0bcb6069	308
1d6902d3 RRD	309	/*
	310	* Check device node and parent device node for device width
	311	* and assume default width of 32
	312	*/
	313	if (of_property_read_u32(np, "xlnx,gpio2-width",
	314	&chip->gpio_width[1]))
	315	chip->gpio_width[1] = 32;
	316
	317	spin_lock_init(&chip->gpio_lock[1]);
	318	}
	319
1ebd0687 RH	320	chip->gc.base = -1;
	321	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
	322	chip->gc.parent = &pdev->dev;
	323	chip->gc.direction_input = xgpio_dir_in;
	324	chip->gc.direction_output = xgpio_dir_out;
	325	chip->gc.get = xgpio_get;
	326	chip->gc.set = xgpio_set;
	327	chip->gc.set_multiple = xgpio_set_multiple;
	328
	329	chip->gc.label = dev_name(&pdev->dev);
	330
	331	chip->regs = devm_platform_ioremap_resource(pdev, 0);
	332	if (IS_ERR(chip->regs)) {
	333	dev_err(&pdev->dev, "failed to ioremap memory resource\n");
	334	return PTR_ERR(chip->regs);
	335	}
0bcb6069	336
1ebd0687	337	xgpio_save_regs(chip);
0bcb6069	338
1ebd0687	339	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
0bcb6069	340	if (status) {
1ebd0687	341	dev_err(&pdev->dev, "failed to add GPIO chip\n");
0bcb6069 JL	342	return status;
0bcb6069 JL	343	}
74600ee0	344
0bcb6069 JL	345	return 0;
	346	}
	347
9992bc95	348	static const struct of_device_id xgpio_of_match[] = {
0bcb6069 JL	349	{ .compatible = "xlnx,xps-gpio-1.00.a", },
	350	{ /* end of list */ },
	351	};
	352
749564ff	353	MODULE_DEVICE_TABLE(of, xgpio_of_match);
0bcb6069	354
749564ff RRD	355	static struct platform_driver xgpio_plat_driver = {
749564ff RRD	356	.probe = xgpio_probe,
749564ff RRD	357	.driver = {
	358	.name = "gpio-xilinx",
	359	.of_match_table = xgpio_of_match,
	360	},
	361	};
0bcb6069	362
749564ff RRD	363	static int __init xgpio_init(void)
	364	{
	365	return platform_driver_register(&xgpio_plat_driver);
0bcb6069 JL	366	}
0bcb6069 JL	367
0bcb6069	368	subsys_initcall(xgpio_init);
749564ff RRD	369
	370	static void __exit xgpio_exit(void)
	371	{
	372	platform_driver_unregister(&xgpio_plat_driver);
	373	}
	374	module_exit(xgpio_exit);
0bcb6069 JL	375
	376	MODULE_AUTHOR("Xilinx, Inc.");
	377	MODULE_DESCRIPTION("Xilinx GPIO driver");
	378	MODULE_LICENSE("GPL");