Commit | Line | Data |
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6e75fc04 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0bcb6069 | 2 | /* |
74600ee0 | 3 | * Xilinx gpio driver for xps/axi_gpio IP. |
0bcb6069 | 4 | * |
74600ee0 | 5 | * Copyright 2008 - 2013 Xilinx, Inc. |
0bcb6069 JL |
6 | */ |
7 | ||
02b3f84d | 8 | #include <linux/bitmap.h> |
74600ee0 | 9 | #include <linux/bitops.h> |
65bbe531 | 10 | #include <linux/clk.h> |
0bcb6069 | 11 | #include <linux/errno.h> |
8c669fe6 SN |
12 | #include <linux/gpio/driver.h> |
13 | #include <linux/init.h> | |
a32c7cae | 14 | #include <linux/interrupt.h> |
8c669fe6 | 15 | #include <linux/io.h> |
a32c7cae | 16 | #include <linux/irq.h> |
bb207ef1 | 17 | #include <linux/module.h> |
0bcb6069 JL |
18 | #include <linux/of_device.h> |
19 | #include <linux/of_platform.h> | |
26b04774 | 20 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0bcb6069 JL |
22 | |
23 | /* Register Offset Definitions */ | |
24 | #define XGPIO_DATA_OFFSET (0x0) /* Data register */ | |
25 | #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ | |
26 | ||
043aa3db AS |
27 | #define XGPIO_CHANNEL0_OFFSET 0x0 |
28 | #define XGPIO_CHANNEL1_OFFSET 0x8 | |
74600ee0 | 29 | |
a32c7cae SN |
30 | #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ |
31 | #define XGPIO_GIER_IE BIT(31) | |
32 | #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ | |
33 | #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ | |
34 | ||
74600ee0 | 35 | /* Read/Write access to the GPIO registers */ |
c54c58ba | 36 | #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) |
cc090d61 MS |
37 | # define xgpio_readreg(offset) readl(offset) |
38 | # define xgpio_writereg(offset, val) writel(val, offset) | |
39 | #else | |
40 | # define xgpio_readreg(offset) __raw_readl(offset) | |
41 | # define xgpio_writereg(offset, val) __raw_writel(val, offset) | |
42 | #endif | |
74600ee0 MS |
43 | |
44 | /** | |
45 | * struct xgpio_instance - Stores information about GPIO device | |
1ebd0687 RH |
46 | * @gc: GPIO chip |
47 | * @regs: register block | |
02b3f84d AS |
48 | * @hw_map: GPIO pin mapping on hardware side |
49 | * @sw_map: GPIO pin mapping on software side | |
50 | * @state: GPIO write state shadow register | |
51 | * @last_irq_read: GPIO read state register from last interrupt | |
52 | * @dir: GPIO direction shadow register | |
4ae798fa | 53 | * @gpio_lock: Lock used for synchronization |
a32c7cae SN |
54 | * @irq: IRQ used by GPIO device |
55 | * @irqchip: IRQ chip | |
02b3f84d AS |
56 | * @enable: GPIO IRQ enable/disable bitfield |
57 | * @rising_edge: GPIO IRQ rising edge enable/disable bitfield | |
58 | * @falling_edge: GPIO IRQ falling edge enable/disable bitfield | |
65bbe531 | 59 | * @clk: clock resource for this driver |
74600ee0 | 60 | */ |
0bcb6069 | 61 | struct xgpio_instance { |
1ebd0687 RH |
62 | struct gpio_chip gc; |
63 | void __iomem *regs; | |
02b3f84d AS |
64 | DECLARE_BITMAP(hw_map, 64); |
65 | DECLARE_BITMAP(sw_map, 64); | |
66 | DECLARE_BITMAP(state, 64); | |
67 | DECLARE_BITMAP(last_irq_read, 64); | |
68 | DECLARE_BITMAP(dir, 64); | |
37ef3346 | 69 | spinlock_t gpio_lock; /* For serializing operations */ |
a32c7cae SN |
70 | int irq; |
71 | struct irq_chip irqchip; | |
02b3f84d AS |
72 | DECLARE_BITMAP(enable, 64); |
73 | DECLARE_BITMAP(rising_edge, 64); | |
74 | DECLARE_BITMAP(falling_edge, 64); | |
65bbe531 | 75 | struct clk *clk; |
749564ff RRD |
76 | }; |
77 | ||
02b3f84d | 78 | static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) |
1d6902d3 | 79 | { |
02b3f84d AS |
80 | return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); |
81 | } | |
1d6902d3 | 82 | |
02b3f84d AS |
83 | static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) |
84 | { | |
85 | return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); | |
86 | } | |
87 | ||
88 | static inline u32 xgpio_get_value32(const unsigned long *map, int bit) | |
89 | { | |
90 | const size_t index = BIT_WORD(bit); | |
91 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); | |
92 | ||
93 | return (map[index] >> offset) & 0xFFFFFFFFul; | |
94 | } | |
95 | ||
96 | static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) | |
97 | { | |
98 | const size_t index = BIT_WORD(bit); | |
99 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); | |
100 | ||
101 | map[index] &= ~(0xFFFFFFFFul << offset); | |
102 | map[index] |= v << offset; | |
1d6902d3 RRD |
103 | } |
104 | ||
043aa3db | 105 | static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) |
1d6902d3 | 106 | { |
043aa3db AS |
107 | switch (ch) { |
108 | case 0: | |
109 | return XGPIO_CHANNEL0_OFFSET; | |
110 | case 1: | |
111 | return XGPIO_CHANNEL1_OFFSET; | |
112 | default: | |
113 | return -EINVAL; | |
114 | } | |
115 | } | |
1d6902d3 | 116 | |
02b3f84d | 117 | static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
043aa3db | 118 | { |
02b3f84d AS |
119 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); |
120 | xgpio_set_value32(a, bit, xgpio_readreg(addr)); | |
043aa3db AS |
121 | } |
122 | ||
02b3f84d | 123 | static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
043aa3db | 124 | { |
02b3f84d AS |
125 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); |
126 | xgpio_writereg(addr, xgpio_get_value32(a, bit)); | |
1d6902d3 RRD |
127 | } |
128 | ||
02b3f84d | 129 | static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) |
1d6902d3 | 130 | { |
02b3f84d | 131 | int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); |
1d6902d3 | 132 | |
02b3f84d AS |
133 | for (bit = 0; bit <= lastbit ; bit += 32) |
134 | xgpio_read_ch(chip, reg, bit, a); | |
135 | } | |
136 | ||
137 | static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) | |
138 | { | |
139 | int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); | |
140 | ||
141 | for (bit = 0; bit <= lastbit ; bit += 32) | |
142 | xgpio_write_ch(chip, reg, bit, a); | |
1d6902d3 | 143 | } |
0bcb6069 JL |
144 | |
145 | /** | |
146 | * xgpio_get - Read the specified signal of the GPIO device. | |
147 | * @gc: Pointer to gpio_chip device structure. | |
148 | * @gpio: GPIO signal number. | |
149 | * | |
4ae798fa RRD |
150 | * This function reads the specified signal of the GPIO device. |
151 | * | |
152 | * Return: | |
153 | * 0 if direction of GPIO signals is set as input otherwise it | |
154 | * returns negative error value. | |
0bcb6069 JL |
155 | */ |
156 | static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) | |
157 | { | |
097d88e9 | 158 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d AS |
159 | int bit = xgpio_to_bit(chip, gpio); |
160 | DECLARE_BITMAP(state, 64); | |
0bcb6069 | 161 | |
02b3f84d | 162 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); |
1d6902d3 | 163 | |
02b3f84d | 164 | return test_bit(bit, state); |
0bcb6069 JL |
165 | } |
166 | ||
167 | /** | |
168 | * xgpio_set - Write the specified signal of the GPIO device. | |
169 | * @gc: Pointer to gpio_chip device structure. | |
170 | * @gpio: GPIO signal number. | |
171 | * @val: Value to be written to specified signal. | |
172 | * | |
173 | * This function writes the specified value in to the specified signal of the | |
174 | * GPIO device. | |
175 | */ | |
176 | static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
177 | { | |
178 | unsigned long flags; | |
097d88e9 | 179 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 180 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 181 | |
37ef3346 | 182 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
183 | |
184 | /* Write to GPIO signal and set its direction to output */ | |
02b3f84d | 185 | __assign_bit(bit, chip->state, val); |
74600ee0 | 186 | |
02b3f84d | 187 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); |
0bcb6069 | 188 | |
37ef3346 | 189 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
190 | } |
191 | ||
8e7c1b80 IR |
192 | /** |
193 | * xgpio_set_multiple - Write the specified signals of the GPIO device. | |
194 | * @gc: Pointer to gpio_chip device structure. | |
195 | * @mask: Mask of the GPIOS to modify. | |
196 | * @bits: Value to be wrote on each GPIO | |
197 | * | |
198 | * This function writes the specified values into the specified signals of the | |
199 | * GPIO devices. | |
200 | */ | |
201 | static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
202 | unsigned long *bits) | |
203 | { | |
02b3f84d AS |
204 | DECLARE_BITMAP(hw_mask, 64); |
205 | DECLARE_BITMAP(hw_bits, 64); | |
206 | DECLARE_BITMAP(state, 64); | |
8e7c1b80 | 207 | unsigned long flags; |
8e7c1b80 | 208 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d AS |
209 | |
210 | bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); | |
211 | bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); | |
8e7c1b80 | 212 | |
37ef3346 | 213 | spin_lock_irqsave(&chip->gpio_lock, flags); |
8e7c1b80 | 214 | |
02b3f84d | 215 | bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); |
8e7c1b80 | 216 | |
02b3f84d AS |
217 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); |
218 | ||
219 | bitmap_copy(chip->state, state, 64); | |
8e7c1b80 | 220 | |
37ef3346 | 221 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
8e7c1b80 IR |
222 | } |
223 | ||
0bcb6069 JL |
224 | /** |
225 | * xgpio_dir_in - Set the direction of the specified GPIO signal as input. | |
226 | * @gc: Pointer to gpio_chip device structure. | |
227 | * @gpio: GPIO signal number. | |
228 | * | |
4ae798fa RRD |
229 | * Return: |
230 | * 0 - if direction of GPIO signals is set as input | |
231 | * otherwise it returns negative error value. | |
0bcb6069 JL |
232 | */ |
233 | static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
234 | { | |
235 | unsigned long flags; | |
097d88e9 | 236 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 237 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 238 | |
37ef3346 | 239 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
240 | |
241 | /* Set the GPIO bit in shadow register and set direction as input */ | |
02b3f84d AS |
242 | __set_bit(bit, chip->dir); |
243 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); | |
0bcb6069 | 244 | |
37ef3346 | 245 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
246 | |
247 | return 0; | |
248 | } | |
249 | ||
250 | /** | |
251 | * xgpio_dir_out - Set the direction of the specified GPIO signal as output. | |
252 | * @gc: Pointer to gpio_chip device structure. | |
253 | * @gpio: GPIO signal number. | |
254 | * @val: Value to be written to specified signal. | |
255 | * | |
4ae798fa RRD |
256 | * This function sets the direction of specified GPIO signal as output. |
257 | * | |
258 | * Return: | |
259 | * If all GPIO signals of GPIO chip is configured as input then it returns | |
0bcb6069 JL |
260 | * error otherwise it returns 0. |
261 | */ | |
262 | static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
263 | { | |
264 | unsigned long flags; | |
097d88e9 | 265 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 266 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 267 | |
37ef3346 | 268 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
269 | |
270 | /* Write state of GPIO signal */ | |
02b3f84d AS |
271 | __assign_bit(bit, chip->state, val); |
272 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); | |
0bcb6069 JL |
273 | |
274 | /* Clear the GPIO bit in shadow register and set direction as output */ | |
02b3f84d AS |
275 | __clear_bit(bit, chip->dir); |
276 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); | |
0bcb6069 | 277 | |
37ef3346 | 278 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
279 | |
280 | return 0; | |
281 | } | |
282 | ||
283 | /** | |
284 | * xgpio_save_regs - Set initial values of GPIO pins | |
1ebd0687 | 285 | * @chip: Pointer to GPIO instance |
0bcb6069 | 286 | */ |
1ebd0687 | 287 | static void xgpio_save_regs(struct xgpio_instance *chip) |
0bcb6069 | 288 | { |
02b3f84d AS |
289 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); |
290 | xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); | |
0bcb6069 JL |
291 | } |
292 | ||
26b04774 SN |
293 | static int xgpio_request(struct gpio_chip *chip, unsigned int offset) |
294 | { | |
295 | int ret; | |
296 | ||
297 | ret = pm_runtime_get_sync(chip->parent); | |
298 | /* | |
299 | * If the device is already active pm_runtime_get() will return 1 on | |
300 | * success, but gpio_request still needs to return 0. | |
301 | */ | |
302 | return ret < 0 ? ret : 0; | |
303 | } | |
304 | ||
305 | static void xgpio_free(struct gpio_chip *chip, unsigned int offset) | |
306 | { | |
307 | pm_runtime_put(chip->parent); | |
308 | } | |
309 | ||
310 | static int __maybe_unused xgpio_suspend(struct device *dev) | |
311 | { | |
312 | struct xgpio_instance *gpio = dev_get_drvdata(dev); | |
313 | struct irq_data *data = irq_get_irq_data(gpio->irq); | |
314 | ||
315 | if (!data) { | |
316 | dev_err(dev, "irq_get_irq_data() failed\n"); | |
317 | return -EINVAL; | |
318 | } | |
319 | ||
320 | if (!irqd_is_wakeup_set(data)) | |
321 | return pm_runtime_force_suspend(dev); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
0230a41e SN |
326 | /** |
327 | * xgpio_remove - Remove method for the GPIO device. | |
328 | * @pdev: pointer to the platform device | |
329 | * | |
330 | * This function remove gpiochips and frees all the allocated resources. | |
331 | * | |
332 | * Return: 0 always | |
333 | */ | |
334 | static int xgpio_remove(struct platform_device *pdev) | |
335 | { | |
336 | struct xgpio_instance *gpio = platform_get_drvdata(pdev); | |
337 | ||
26b04774 SN |
338 | pm_runtime_get_sync(&pdev->dev); |
339 | pm_runtime_put_noidle(&pdev->dev); | |
340 | pm_runtime_disable(&pdev->dev); | |
0230a41e SN |
341 | clk_disable_unprepare(gpio->clk); |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
a32c7cae SN |
346 | /** |
347 | * xgpio_irq_ack - Acknowledge a child GPIO interrupt. | |
348 | * @irq_data: per IRQ and chip data passed down to chip functions | |
349 | * This currently does nothing, but irq_ack is unconditionally called by | |
350 | * handle_edge_irq and therefore must be defined. | |
351 | */ | |
352 | static void xgpio_irq_ack(struct irq_data *irq_data) | |
353 | { | |
354 | } | |
355 | ||
26b04774 SN |
356 | static int __maybe_unused xgpio_resume(struct device *dev) |
357 | { | |
358 | struct xgpio_instance *gpio = dev_get_drvdata(dev); | |
359 | struct irq_data *data = irq_get_irq_data(gpio->irq); | |
360 | ||
361 | if (!data) { | |
362 | dev_err(dev, "irq_get_irq_data() failed\n"); | |
363 | return -EINVAL; | |
364 | } | |
365 | ||
366 | if (!irqd_is_wakeup_set(data)) | |
367 | return pm_runtime_force_resume(dev); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int __maybe_unused xgpio_runtime_suspend(struct device *dev) | |
373 | { | |
374 | struct platform_device *pdev = to_platform_device(dev); | |
375 | struct xgpio_instance *gpio = platform_get_drvdata(pdev); | |
376 | ||
377 | clk_disable(gpio->clk); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int __maybe_unused xgpio_runtime_resume(struct device *dev) | |
383 | { | |
384 | struct platform_device *pdev = to_platform_device(dev); | |
385 | struct xgpio_instance *gpio = platform_get_drvdata(pdev); | |
386 | ||
387 | return clk_enable(gpio->clk); | |
388 | } | |
389 | ||
390 | static const struct dev_pm_ops xgpio_dev_pm_ops = { | |
391 | SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) | |
392 | SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, | |
393 | xgpio_runtime_resume, NULL) | |
394 | }; | |
395 | ||
a32c7cae SN |
396 | /** |
397 | * xgpio_irq_mask - Write the specified signal of the GPIO device. | |
398 | * @irq_data: per IRQ and chip data passed down to chip functions | |
399 | */ | |
400 | static void xgpio_irq_mask(struct irq_data *irq_data) | |
401 | { | |
402 | unsigned long flags; | |
403 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
404 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d AS |
405 | int bit = xgpio_to_bit(chip, irq_offset); |
406 | u32 mask = BIT(bit / 32), temp; | |
a32c7cae SN |
407 | |
408 | spin_lock_irqsave(&chip->gpio_lock, flags); | |
409 | ||
02b3f84d | 410 | __clear_bit(bit, chip->enable); |
a32c7cae | 411 | |
02b3f84d | 412 | if (xgpio_get_value32(chip->enable, bit) == 0) { |
a32c7cae | 413 | /* Disable per channel interrupt */ |
02b3f84d AS |
414 | temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
415 | temp &= ~mask; | |
a32c7cae SN |
416 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); |
417 | } | |
418 | spin_unlock_irqrestore(&chip->gpio_lock, flags); | |
419 | } | |
420 | ||
421 | /** | |
422 | * xgpio_irq_unmask - Write the specified signal of the GPIO device. | |
423 | * @irq_data: per IRQ and chip data passed down to chip functions | |
424 | */ | |
425 | static void xgpio_irq_unmask(struct irq_data *irq_data) | |
426 | { | |
427 | unsigned long flags; | |
428 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
429 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d AS |
430 | int bit = xgpio_to_bit(chip, irq_offset); |
431 | u32 old_enable = xgpio_get_value32(chip->enable, bit); | |
432 | u32 mask = BIT(bit / 32), val; | |
a32c7cae SN |
433 | |
434 | spin_lock_irqsave(&chip->gpio_lock, flags); | |
435 | ||
02b3f84d | 436 | __set_bit(bit, chip->enable); |
a32c7cae | 437 | |
02b3f84d | 438 | if (old_enable == 0) { |
a32c7cae | 439 | /* Clear any existing per-channel interrupts */ |
02b3f84d AS |
440 | val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
441 | val &= mask; | |
442 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); | |
a32c7cae SN |
443 | |
444 | /* Update GPIO IRQ read data before enabling interrupt*/ | |
02b3f84d | 445 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); |
a32c7cae SN |
446 | |
447 | /* Enable per channel interrupt */ | |
448 | val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); | |
02b3f84d | 449 | val |= mask; |
a32c7cae SN |
450 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); |
451 | } | |
452 | ||
453 | spin_unlock_irqrestore(&chip->gpio_lock, flags); | |
454 | } | |
455 | ||
456 | /** | |
457 | * xgpio_set_irq_type - Write the specified signal of the GPIO device. | |
458 | * @irq_data: Per IRQ and chip data passed down to chip functions | |
459 | * @type: Interrupt type that is to be set for the gpio pin | |
460 | * | |
461 | * Return: | |
462 | * 0 if interrupt type is supported otherwise -EINVAL | |
463 | */ | |
464 | static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) | |
465 | { | |
466 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
467 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d | 468 | int bit = xgpio_to_bit(chip, irq_offset); |
a32c7cae SN |
469 | |
470 | /* | |
471 | * The Xilinx GPIO hardware provides a single interrupt status | |
472 | * indication for any state change in a given GPIO channel (bank). | |
473 | * Therefore, only rising edge or falling edge triggers are | |
474 | * supported. | |
475 | */ | |
476 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
477 | case IRQ_TYPE_EDGE_BOTH: | |
02b3f84d AS |
478 | __set_bit(bit, chip->rising_edge); |
479 | __set_bit(bit, chip->falling_edge); | |
a32c7cae SN |
480 | break; |
481 | case IRQ_TYPE_EDGE_RISING: | |
02b3f84d AS |
482 | __set_bit(bit, chip->rising_edge); |
483 | __clear_bit(bit, chip->falling_edge); | |
a32c7cae SN |
484 | break; |
485 | case IRQ_TYPE_EDGE_FALLING: | |
02b3f84d AS |
486 | __clear_bit(bit, chip->rising_edge); |
487 | __set_bit(bit, chip->falling_edge); | |
a32c7cae SN |
488 | break; |
489 | default: | |
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | irq_set_handler_locked(irq_data, handle_edge_irq); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | /** | |
498 | * xgpio_irqhandler - Gpio interrupt service routine | |
499 | * @desc: Pointer to interrupt description | |
500 | */ | |
501 | static void xgpio_irqhandler(struct irq_desc *desc) | |
502 | { | |
503 | struct xgpio_instance *chip = irq_desc_get_handler_data(desc); | |
02b3f84d | 504 | struct gpio_chip *gc = &chip->gc; |
a32c7cae | 505 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
02b3f84d AS |
506 | DECLARE_BITMAP(rising, 64); |
507 | DECLARE_BITMAP(falling, 64); | |
508 | DECLARE_BITMAP(all, 64); | |
509 | int irq_offset; | |
510 | u32 status; | |
511 | u32 bit; | |
a32c7cae | 512 | |
02b3f84d | 513 | status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
a32c7cae SN |
514 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); |
515 | ||
516 | chained_irq_enter(irqchip, desc); | |
02b3f84d | 517 | |
6453b953 | 518 | spin_lock(&chip->gpio_lock); |
02b3f84d AS |
519 | |
520 | xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); | |
521 | ||
522 | bitmap_complement(rising, chip->last_irq_read, 64); | |
523 | bitmap_and(rising, rising, all, 64); | |
524 | bitmap_and(rising, rising, chip->enable, 64); | |
525 | bitmap_and(rising, rising, chip->rising_edge, 64); | |
526 | ||
527 | bitmap_complement(falling, all, 64); | |
528 | bitmap_and(falling, falling, chip->last_irq_read, 64); | |
529 | bitmap_and(falling, falling, chip->enable, 64); | |
530 | bitmap_and(falling, falling, chip->falling_edge, 64); | |
531 | ||
532 | bitmap_copy(chip->last_irq_read, all, 64); | |
533 | bitmap_or(all, rising, falling, 64); | |
534 | ||
6453b953 | 535 | spin_unlock(&chip->gpio_lock); |
02b3f84d AS |
536 | |
537 | dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); | |
538 | ||
539 | for_each_set_bit(bit, all, 64) { | |
540 | irq_offset = xgpio_from_bit(chip, bit); | |
541 | generic_handle_irq(irq_find_mapping(gc->irq.domain, irq_offset)); | |
a32c7cae SN |
542 | } |
543 | ||
544 | chained_irq_exit(irqchip, desc); | |
545 | } | |
546 | ||
0bcb6069 JL |
547 | /** |
548 | * xgpio_of_probe - Probe method for the GPIO device. | |
749564ff | 549 | * @pdev: pointer to the platform device |
0bcb6069 | 550 | * |
4ae798fa RRD |
551 | * Return: |
552 | * It returns 0, if the driver is bound to the GPIO device, or | |
553 | * a negative value if there is an error. | |
0bcb6069 | 554 | */ |
749564ff | 555 | static int xgpio_probe(struct platform_device *pdev) |
0bcb6069 JL |
556 | { |
557 | struct xgpio_instance *chip; | |
0bcb6069 | 558 | int status = 0; |
749564ff | 559 | struct device_node *np = pdev->dev.of_node; |
a32c7cae SN |
560 | u32 is_dual = 0; |
561 | u32 cells = 2; | |
02b3f84d AS |
562 | u32 width[2]; |
563 | u32 state[2]; | |
564 | u32 dir[2]; | |
a32c7cae SN |
565 | struct gpio_irq_chip *girq; |
566 | u32 temp; | |
0bcb6069 | 567 | |
1d6902d3 RRD |
568 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
569 | if (!chip) | |
0bcb6069 | 570 | return -ENOMEM; |
0bcb6069 | 571 | |
1d6902d3 | 572 | platform_set_drvdata(pdev, chip); |
749564ff | 573 | |
02b3f84d AS |
574 | /* First, check if the device is dual-channel */ |
575 | of_property_read_u32(np, "xlnx,is-dual", &is_dual); | |
576 | ||
577 | /* Setup defaults */ | |
578 | memset32(width, 0, ARRAY_SIZE(width)); | |
579 | memset32(state, 0, ARRAY_SIZE(state)); | |
580 | memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); | |
581 | ||
0bcb6069 | 582 | /* Update GPIO state shadow register with default value */ |
02b3f84d AS |
583 | of_property_read_u32(np, "xlnx,dout-default", &state[0]); |
584 | of_property_read_u32(np, "xlnx,dout-default-2", &state[1]); | |
585 | ||
586 | bitmap_from_arr32(chip->state, state, 64); | |
0bcb6069 JL |
587 | |
588 | /* Update GPIO direction shadow register with default value */ | |
02b3f84d AS |
589 | of_property_read_u32(np, "xlnx,tri-default", &dir[0]); |
590 | of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]); | |
591 | ||
592 | bitmap_from_arr32(chip->dir, dir, 64); | |
6f8bf500 | 593 | |
a32c7cae SN |
594 | /* Update cells with gpio-cells value */ |
595 | if (of_property_read_u32(np, "#gpio-cells", &cells)) | |
596 | dev_dbg(&pdev->dev, "Missing gpio-cells property\n"); | |
597 | ||
598 | if (cells != 2) { | |
599 | dev_err(&pdev->dev, "#gpio-cells mismatch\n"); | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
1b4c5a6e GV |
603 | /* |
604 | * Check device node and parent device node for device width | |
605 | * and assume default width of 32 | |
606 | */ | |
02b3f84d AS |
607 | if (of_property_read_u32(np, "xlnx,gpio-width", &width[0])) |
608 | width[0] = 32; | |
1d6902d3 | 609 | |
02b3f84d | 610 | if (width[0] > 32) |
6e551bfa SN |
611 | return -EINVAL; |
612 | ||
02b3f84d AS |
613 | if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1])) |
614 | width[1] = 32; | |
1d6902d3 | 615 | |
02b3f84d AS |
616 | if (width[1] > 32) |
617 | return -EINVAL; | |
618 | ||
619 | /* Setup software pin mapping */ | |
620 | bitmap_set(chip->sw_map, 0, width[0] + width[1]); | |
621 | ||
622 | /* Setup hardware pin mapping */ | |
623 | bitmap_set(chip->hw_map, 0, width[0]); | |
624 | bitmap_set(chip->hw_map, 32, width[1]); | |
625 | ||
626 | spin_lock_init(&chip->gpio_lock); | |
1d6902d3 | 627 | |
1ebd0687 | 628 | chip->gc.base = -1; |
02b3f84d | 629 | chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); |
1ebd0687 RH |
630 | chip->gc.parent = &pdev->dev; |
631 | chip->gc.direction_input = xgpio_dir_in; | |
632 | chip->gc.direction_output = xgpio_dir_out; | |
a32c7cae | 633 | chip->gc.of_gpio_n_cells = cells; |
1ebd0687 RH |
634 | chip->gc.get = xgpio_get; |
635 | chip->gc.set = xgpio_set; | |
26b04774 SN |
636 | chip->gc.request = xgpio_request; |
637 | chip->gc.free = xgpio_free; | |
1ebd0687 RH |
638 | chip->gc.set_multiple = xgpio_set_multiple; |
639 | ||
640 | chip->gc.label = dev_name(&pdev->dev); | |
641 | ||
642 | chip->regs = devm_platform_ioremap_resource(pdev, 0); | |
643 | if (IS_ERR(chip->regs)) { | |
644 | dev_err(&pdev->dev, "failed to ioremap memory resource\n"); | |
645 | return PTR_ERR(chip->regs); | |
646 | } | |
0bcb6069 | 647 | |
65bbe531 | 648 | chip->clk = devm_clk_get_optional(&pdev->dev, NULL); |
45c5277f SN |
649 | if (IS_ERR(chip->clk)) |
650 | return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); | |
65bbe531 SN |
651 | |
652 | status = clk_prepare_enable(chip->clk); | |
653 | if (status < 0) { | |
654 | dev_err(&pdev->dev, "Failed to prepare clk\n"); | |
655 | return status; | |
656 | } | |
26b04774 SN |
657 | pm_runtime_get_noresume(&pdev->dev); |
658 | pm_runtime_set_active(&pdev->dev); | |
659 | pm_runtime_enable(&pdev->dev); | |
65bbe531 | 660 | |
1ebd0687 | 661 | xgpio_save_regs(chip); |
0bcb6069 | 662 | |
a32c7cae SN |
663 | chip->irq = platform_get_irq_optional(pdev, 0); |
664 | if (chip->irq <= 0) | |
665 | goto skip_irq; | |
666 | ||
667 | chip->irqchip.name = "gpio-xilinx"; | |
668 | chip->irqchip.irq_ack = xgpio_irq_ack; | |
669 | chip->irqchip.irq_mask = xgpio_irq_mask; | |
670 | chip->irqchip.irq_unmask = xgpio_irq_unmask; | |
671 | chip->irqchip.irq_set_type = xgpio_set_irq_type; | |
672 | ||
673 | /* Disable per-channel interrupts */ | |
674 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); | |
675 | /* Clear any existing per-channel interrupts */ | |
676 | temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); | |
677 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); | |
678 | /* Enable global interrupts */ | |
679 | xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); | |
680 | ||
681 | girq = &chip->gc.irq; | |
682 | girq->chip = &chip->irqchip; | |
683 | girq->parent_handler = xgpio_irqhandler; | |
684 | girq->num_parents = 1; | |
685 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
686 | sizeof(*girq->parents), | |
687 | GFP_KERNEL); | |
688 | if (!girq->parents) { | |
689 | status = -ENOMEM; | |
26b04774 | 690 | goto err_pm_put; |
a32c7cae SN |
691 | } |
692 | girq->parents[0] = chip->irq; | |
693 | girq->default_type = IRQ_TYPE_NONE; | |
694 | girq->handler = handle_bad_irq; | |
695 | ||
696 | skip_irq: | |
1ebd0687 | 697 | status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); |
0bcb6069 | 698 | if (status) { |
1ebd0687 | 699 | dev_err(&pdev->dev, "failed to add GPIO chip\n"); |
26b04774 | 700 | goto err_pm_put; |
0bcb6069 | 701 | } |
74600ee0 | 702 | |
26b04774 | 703 | pm_runtime_put(&pdev->dev); |
0bcb6069 | 704 | return 0; |
a32c7cae | 705 | |
26b04774 SN |
706 | err_pm_put: |
707 | pm_runtime_disable(&pdev->dev); | |
708 | pm_runtime_put_noidle(&pdev->dev); | |
a32c7cae SN |
709 | clk_disable_unprepare(chip->clk); |
710 | return status; | |
0bcb6069 JL |
711 | } |
712 | ||
9992bc95 | 713 | static const struct of_device_id xgpio_of_match[] = { |
0bcb6069 JL |
714 | { .compatible = "xlnx,xps-gpio-1.00.a", }, |
715 | { /* end of list */ }, | |
716 | }; | |
717 | ||
749564ff | 718 | MODULE_DEVICE_TABLE(of, xgpio_of_match); |
0bcb6069 | 719 | |
749564ff RRD |
720 | static struct platform_driver xgpio_plat_driver = { |
721 | .probe = xgpio_probe, | |
0230a41e | 722 | .remove = xgpio_remove, |
749564ff RRD |
723 | .driver = { |
724 | .name = "gpio-xilinx", | |
725 | .of_match_table = xgpio_of_match, | |
26b04774 | 726 | .pm = &xgpio_dev_pm_ops, |
749564ff RRD |
727 | }, |
728 | }; | |
0bcb6069 | 729 | |
749564ff RRD |
730 | static int __init xgpio_init(void) |
731 | { | |
732 | return platform_driver_register(&xgpio_plat_driver); | |
0bcb6069 JL |
733 | } |
734 | ||
0bcb6069 | 735 | subsys_initcall(xgpio_init); |
749564ff RRD |
736 | |
737 | static void __exit xgpio_exit(void) | |
738 | { | |
739 | platform_driver_unregister(&xgpio_plat_driver); | |
740 | } | |
741 | module_exit(xgpio_exit); | |
0bcb6069 JL |
742 | |
743 | MODULE_AUTHOR("Xilinx, Inc."); | |
744 | MODULE_DESCRIPTION("Xilinx GPIO driver"); | |
745 | MODULE_LICENSE("GPL"); |