Commit | Line | Data |
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6e75fc04 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0bcb6069 | 2 | /* |
74600ee0 | 3 | * Xilinx gpio driver for xps/axi_gpio IP. |
0bcb6069 | 4 | * |
74600ee0 | 5 | * Copyright 2008 - 2013 Xilinx, Inc. |
0bcb6069 JL |
6 | */ |
7 | ||
02b3f84d | 8 | #include <linux/bitmap.h> |
74600ee0 | 9 | #include <linux/bitops.h> |
65bbe531 | 10 | #include <linux/clk.h> |
0bcb6069 | 11 | #include <linux/errno.h> |
8c669fe6 SN |
12 | #include <linux/gpio/driver.h> |
13 | #include <linux/init.h> | |
a32c7cae | 14 | #include <linux/interrupt.h> |
8c669fe6 | 15 | #include <linux/io.h> |
a32c7cae | 16 | #include <linux/irq.h> |
bb207ef1 | 17 | #include <linux/module.h> |
e91d0f05 RH |
18 | #include <linux/of.h> |
19 | #include <linux/platform_device.h> | |
26b04774 | 20 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0bcb6069 JL |
22 | |
23 | /* Register Offset Definitions */ | |
24 | #define XGPIO_DATA_OFFSET (0x0) /* Data register */ | |
25 | #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ | |
26 | ||
043aa3db AS |
27 | #define XGPIO_CHANNEL0_OFFSET 0x0 |
28 | #define XGPIO_CHANNEL1_OFFSET 0x8 | |
74600ee0 | 29 | |
a32c7cae SN |
30 | #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ |
31 | #define XGPIO_GIER_IE BIT(31) | |
32 | #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ | |
33 | #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ | |
34 | ||
74600ee0 | 35 | /* Read/Write access to the GPIO registers */ |
c54c58ba | 36 | #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) |
cc090d61 MS |
37 | # define xgpio_readreg(offset) readl(offset) |
38 | # define xgpio_writereg(offset, val) writel(val, offset) | |
39 | #else | |
40 | # define xgpio_readreg(offset) __raw_readl(offset) | |
41 | # define xgpio_writereg(offset, val) __raw_writel(val, offset) | |
42 | #endif | |
74600ee0 MS |
43 | |
44 | /** | |
45 | * struct xgpio_instance - Stores information about GPIO device | |
1ebd0687 RH |
46 | * @gc: GPIO chip |
47 | * @regs: register block | |
02b3f84d AS |
48 | * @hw_map: GPIO pin mapping on hardware side |
49 | * @sw_map: GPIO pin mapping on software side | |
50 | * @state: GPIO write state shadow register | |
51 | * @last_irq_read: GPIO read state register from last interrupt | |
52 | * @dir: GPIO direction shadow register | |
4ae798fa | 53 | * @gpio_lock: Lock used for synchronization |
a32c7cae SN |
54 | * @irq: IRQ used by GPIO device |
55 | * @irqchip: IRQ chip | |
02b3f84d AS |
56 | * @enable: GPIO IRQ enable/disable bitfield |
57 | * @rising_edge: GPIO IRQ rising edge enable/disable bitfield | |
58 | * @falling_edge: GPIO IRQ falling edge enable/disable bitfield | |
65bbe531 | 59 | * @clk: clock resource for this driver |
74600ee0 | 60 | */ |
0bcb6069 | 61 | struct xgpio_instance { |
1ebd0687 RH |
62 | struct gpio_chip gc; |
63 | void __iomem *regs; | |
02b3f84d AS |
64 | DECLARE_BITMAP(hw_map, 64); |
65 | DECLARE_BITMAP(sw_map, 64); | |
66 | DECLARE_BITMAP(state, 64); | |
67 | DECLARE_BITMAP(last_irq_read, 64); | |
68 | DECLARE_BITMAP(dir, 64); | |
37ef3346 | 69 | spinlock_t gpio_lock; /* For serializing operations */ |
a32c7cae | 70 | int irq; |
02b3f84d AS |
71 | DECLARE_BITMAP(enable, 64); |
72 | DECLARE_BITMAP(rising_edge, 64); | |
73 | DECLARE_BITMAP(falling_edge, 64); | |
65bbe531 | 74 | struct clk *clk; |
749564ff RRD |
75 | }; |
76 | ||
02b3f84d | 77 | static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) |
1d6902d3 | 78 | { |
02b3f84d AS |
79 | return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); |
80 | } | |
1d6902d3 | 81 | |
02b3f84d AS |
82 | static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) |
83 | { | |
84 | return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); | |
1d6902d3 RRD |
85 | } |
86 | ||
02b3f84d | 87 | static inline u32 xgpio_get_value32(const unsigned long *map, int bit) |
1d6902d3 | 88 | { |
02b3f84d AS |
89 | const size_t index = BIT_WORD(bit); |
90 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); | |
1d6902d3 | 91 | |
02b3f84d AS |
92 | return (map[index] >> offset) & 0xFFFFFFFFul; |
93 | } | |
94 | ||
95 | static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) | |
96 | { | |
97 | const size_t index = BIT_WORD(bit); | |
98 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); | |
99 | ||
100 | map[index] &= ~(0xFFFFFFFFul << offset); | |
32c094a0 | 101 | map[index] |= (unsigned long)v << offset; |
1d6902d3 RRD |
102 | } |
103 | ||
043aa3db | 104 | static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) |
1d6902d3 | 105 | { |
043aa3db AS |
106 | switch (ch) { |
107 | case 0: | |
108 | return XGPIO_CHANNEL0_OFFSET; | |
109 | case 1: | |
110 | return XGPIO_CHANNEL1_OFFSET; | |
111 | default: | |
112 | return -EINVAL; | |
113 | } | |
1d6902d3 RRD |
114 | } |
115 | ||
02b3f84d | 116 | static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
1d6902d3 | 117 | { |
02b3f84d | 118 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); |
f2a2f2c9 | 119 | |
02b3f84d | 120 | xgpio_set_value32(a, bit, xgpio_readreg(addr)); |
043aa3db AS |
121 | } |
122 | ||
02b3f84d | 123 | static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
043aa3db | 124 | { |
02b3f84d | 125 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); |
f2a2f2c9 | 126 | |
02b3f84d | 127 | xgpio_writereg(addr, xgpio_get_value32(a, bit)); |
1d6902d3 RRD |
128 | } |
129 | ||
02b3f84d | 130 | static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) |
1d6902d3 | 131 | { |
02b3f84d | 132 | int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); |
1d6902d3 | 133 | |
02b3f84d AS |
134 | for (bit = 0; bit <= lastbit ; bit += 32) |
135 | xgpio_read_ch(chip, reg, bit, a); | |
136 | } | |
137 | ||
138 | static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) | |
139 | { | |
140 | int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); | |
1d6902d3 | 141 | |
02b3f84d AS |
142 | for (bit = 0; bit <= lastbit ; bit += 32) |
143 | xgpio_write_ch(chip, reg, bit, a); | |
1d6902d3 | 144 | } |
0bcb6069 JL |
145 | |
146 | /** | |
147 | * xgpio_get - Read the specified signal of the GPIO device. | |
148 | * @gc: Pointer to gpio_chip device structure. | |
149 | * @gpio: GPIO signal number. | |
150 | * | |
4ae798fa RRD |
151 | * This function reads the specified signal of the GPIO device. |
152 | * | |
153 | * Return: | |
154 | * 0 if direction of GPIO signals is set as input otherwise it | |
155 | * returns negative error value. | |
0bcb6069 JL |
156 | */ |
157 | static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) | |
158 | { | |
097d88e9 | 159 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d AS |
160 | int bit = xgpio_to_bit(chip, gpio); |
161 | DECLARE_BITMAP(state, 64); | |
0bcb6069 | 162 | |
02b3f84d | 163 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); |
1d6902d3 | 164 | |
02b3f84d | 165 | return test_bit(bit, state); |
0bcb6069 JL |
166 | } |
167 | ||
168 | /** | |
169 | * xgpio_set - Write the specified signal of the GPIO device. | |
170 | * @gc: Pointer to gpio_chip device structure. | |
171 | * @gpio: GPIO signal number. | |
172 | * @val: Value to be written to specified signal. | |
173 | * | |
174 | * This function writes the specified value in to the specified signal of the | |
175 | * GPIO device. | |
176 | */ | |
177 | static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
178 | { | |
179 | unsigned long flags; | |
097d88e9 | 180 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 181 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 182 | |
37ef3346 | 183 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
184 | |
185 | /* Write to GPIO signal and set its direction to output */ | |
02b3f84d | 186 | __assign_bit(bit, chip->state, val); |
74600ee0 | 187 | |
02b3f84d | 188 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); |
0bcb6069 | 189 | |
37ef3346 | 190 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
191 | } |
192 | ||
8e7c1b80 IR |
193 | /** |
194 | * xgpio_set_multiple - Write the specified signals of the GPIO device. | |
195 | * @gc: Pointer to gpio_chip device structure. | |
196 | * @mask: Mask of the GPIOS to modify. | |
197 | * @bits: Value to be wrote on each GPIO | |
198 | * | |
199 | * This function writes the specified values into the specified signals of the | |
200 | * GPIO devices. | |
201 | */ | |
202 | static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
203 | unsigned long *bits) | |
204 | { | |
02b3f84d AS |
205 | DECLARE_BITMAP(hw_mask, 64); |
206 | DECLARE_BITMAP(hw_bits, 64); | |
207 | DECLARE_BITMAP(state, 64); | |
8e7c1b80 | 208 | unsigned long flags; |
8e7c1b80 | 209 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d AS |
210 | |
211 | bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); | |
212 | bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); | |
8e7c1b80 | 213 | |
37ef3346 | 214 | spin_lock_irqsave(&chip->gpio_lock, flags); |
8e7c1b80 | 215 | |
02b3f84d | 216 | bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); |
8e7c1b80 | 217 | |
02b3f84d | 218 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); |
8e7c1b80 | 219 | |
02b3f84d | 220 | bitmap_copy(chip->state, state, 64); |
8e7c1b80 | 221 | |
37ef3346 | 222 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
8e7c1b80 IR |
223 | } |
224 | ||
0bcb6069 JL |
225 | /** |
226 | * xgpio_dir_in - Set the direction of the specified GPIO signal as input. | |
227 | * @gc: Pointer to gpio_chip device structure. | |
228 | * @gpio: GPIO signal number. | |
229 | * | |
4ae798fa RRD |
230 | * Return: |
231 | * 0 - if direction of GPIO signals is set as input | |
232 | * otherwise it returns negative error value. | |
0bcb6069 JL |
233 | */ |
234 | static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
235 | { | |
236 | unsigned long flags; | |
097d88e9 | 237 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 238 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 239 | |
37ef3346 | 240 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
241 | |
242 | /* Set the GPIO bit in shadow register and set direction as input */ | |
02b3f84d AS |
243 | __set_bit(bit, chip->dir); |
244 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); | |
0bcb6069 | 245 | |
37ef3346 | 246 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
247 | |
248 | return 0; | |
249 | } | |
250 | ||
251 | /** | |
252 | * xgpio_dir_out - Set the direction of the specified GPIO signal as output. | |
253 | * @gc: Pointer to gpio_chip device structure. | |
254 | * @gpio: GPIO signal number. | |
255 | * @val: Value to be written to specified signal. | |
256 | * | |
4ae798fa RRD |
257 | * This function sets the direction of specified GPIO signal as output. |
258 | * | |
259 | * Return: | |
260 | * If all GPIO signals of GPIO chip is configured as input then it returns | |
0bcb6069 JL |
261 | * error otherwise it returns 0. |
262 | */ | |
263 | static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
264 | { | |
265 | unsigned long flags; | |
097d88e9 | 266 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
02b3f84d | 267 | int bit = xgpio_to_bit(chip, gpio); |
0bcb6069 | 268 | |
37ef3346 | 269 | spin_lock_irqsave(&chip->gpio_lock, flags); |
0bcb6069 JL |
270 | |
271 | /* Write state of GPIO signal */ | |
02b3f84d AS |
272 | __assign_bit(bit, chip->state, val); |
273 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); | |
0bcb6069 JL |
274 | |
275 | /* Clear the GPIO bit in shadow register and set direction as output */ | |
02b3f84d AS |
276 | __clear_bit(bit, chip->dir); |
277 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); | |
0bcb6069 | 278 | |
37ef3346 | 279 | spin_unlock_irqrestore(&chip->gpio_lock, flags); |
0bcb6069 JL |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
284 | /** | |
285 | * xgpio_save_regs - Set initial values of GPIO pins | |
1ebd0687 | 286 | * @chip: Pointer to GPIO instance |
0bcb6069 | 287 | */ |
1ebd0687 | 288 | static void xgpio_save_regs(struct xgpio_instance *chip) |
0bcb6069 | 289 | { |
02b3f84d AS |
290 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); |
291 | xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); | |
0bcb6069 JL |
292 | } |
293 | ||
26b04774 SN |
294 | static int xgpio_request(struct gpio_chip *chip, unsigned int offset) |
295 | { | |
296 | int ret; | |
297 | ||
298 | ret = pm_runtime_get_sync(chip->parent); | |
299 | /* | |
300 | * If the device is already active pm_runtime_get() will return 1 on | |
301 | * success, but gpio_request still needs to return 0. | |
302 | */ | |
303 | return ret < 0 ? ret : 0; | |
304 | } | |
305 | ||
306 | static void xgpio_free(struct gpio_chip *chip, unsigned int offset) | |
307 | { | |
308 | pm_runtime_put(chip->parent); | |
309 | } | |
310 | ||
311 | static int __maybe_unused xgpio_suspend(struct device *dev) | |
312 | { | |
313 | struct xgpio_instance *gpio = dev_get_drvdata(dev); | |
314 | struct irq_data *data = irq_get_irq_data(gpio->irq); | |
315 | ||
316 | if (!data) { | |
be4dc321 SN |
317 | dev_dbg(dev, "IRQ not connected\n"); |
318 | return pm_runtime_force_suspend(dev); | |
26b04774 SN |
319 | } |
320 | ||
321 | if (!irqd_is_wakeup_set(data)) | |
322 | return pm_runtime_force_suspend(dev); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
0230a41e SN |
327 | /** |
328 | * xgpio_remove - Remove method for the GPIO device. | |
329 | * @pdev: pointer to the platform device | |
330 | * | |
331 | * This function remove gpiochips and frees all the allocated resources. | |
332 | * | |
333 | * Return: 0 always | |
334 | */ | |
335 | static int xgpio_remove(struct platform_device *pdev) | |
336 | { | |
337 | struct xgpio_instance *gpio = platform_get_drvdata(pdev); | |
338 | ||
26b04774 SN |
339 | pm_runtime_get_sync(&pdev->dev); |
340 | pm_runtime_put_noidle(&pdev->dev); | |
341 | pm_runtime_disable(&pdev->dev); | |
0230a41e SN |
342 | clk_disable_unprepare(gpio->clk); |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
a32c7cae SN |
347 | /** |
348 | * xgpio_irq_ack - Acknowledge a child GPIO interrupt. | |
349 | * @irq_data: per IRQ and chip data passed down to chip functions | |
350 | * This currently does nothing, but irq_ack is unconditionally called by | |
351 | * handle_edge_irq and therefore must be defined. | |
352 | */ | |
353 | static void xgpio_irq_ack(struct irq_data *irq_data) | |
354 | { | |
355 | } | |
356 | ||
26b04774 SN |
357 | static int __maybe_unused xgpio_resume(struct device *dev) |
358 | { | |
359 | struct xgpio_instance *gpio = dev_get_drvdata(dev); | |
360 | struct irq_data *data = irq_get_irq_data(gpio->irq); | |
361 | ||
362 | if (!data) { | |
be4dc321 SN |
363 | dev_dbg(dev, "IRQ not connected\n"); |
364 | return pm_runtime_force_resume(dev); | |
26b04774 SN |
365 | } |
366 | ||
367 | if (!irqd_is_wakeup_set(data)) | |
368 | return pm_runtime_force_resume(dev); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int __maybe_unused xgpio_runtime_suspend(struct device *dev) | |
374 | { | |
e24b9fc1 | 375 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
26b04774 SN |
376 | |
377 | clk_disable(gpio->clk); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int __maybe_unused xgpio_runtime_resume(struct device *dev) | |
383 | { | |
e24b9fc1 | 384 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
26b04774 SN |
385 | |
386 | return clk_enable(gpio->clk); | |
387 | } | |
388 | ||
389 | static const struct dev_pm_ops xgpio_dev_pm_ops = { | |
390 | SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) | |
391 | SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, | |
392 | xgpio_runtime_resume, NULL) | |
393 | }; | |
394 | ||
a32c7cae SN |
395 | /** |
396 | * xgpio_irq_mask - Write the specified signal of the GPIO device. | |
397 | * @irq_data: per IRQ and chip data passed down to chip functions | |
398 | */ | |
399 | static void xgpio_irq_mask(struct irq_data *irq_data) | |
400 | { | |
401 | unsigned long flags; | |
402 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
403 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d AS |
404 | int bit = xgpio_to_bit(chip, irq_offset); |
405 | u32 mask = BIT(bit / 32), temp; | |
a32c7cae SN |
406 | |
407 | spin_lock_irqsave(&chip->gpio_lock, flags); | |
408 | ||
02b3f84d | 409 | __clear_bit(bit, chip->enable); |
a32c7cae | 410 | |
02b3f84d | 411 | if (xgpio_get_value32(chip->enable, bit) == 0) { |
a32c7cae | 412 | /* Disable per channel interrupt */ |
02b3f84d AS |
413 | temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
414 | temp &= ~mask; | |
a32c7cae SN |
415 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); |
416 | } | |
417 | spin_unlock_irqrestore(&chip->gpio_lock, flags); | |
b4510f8f LW |
418 | |
419 | gpiochip_disable_irq(&chip->gc, irq_offset); | |
a32c7cae SN |
420 | } |
421 | ||
422 | /** | |
423 | * xgpio_irq_unmask - Write the specified signal of the GPIO device. | |
424 | * @irq_data: per IRQ and chip data passed down to chip functions | |
425 | */ | |
426 | static void xgpio_irq_unmask(struct irq_data *irq_data) | |
427 | { | |
428 | unsigned long flags; | |
429 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
430 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d AS |
431 | int bit = xgpio_to_bit(chip, irq_offset); |
432 | u32 old_enable = xgpio_get_value32(chip->enable, bit); | |
433 | u32 mask = BIT(bit / 32), val; | |
a32c7cae | 434 | |
b4510f8f LW |
435 | gpiochip_enable_irq(&chip->gc, irq_offset); |
436 | ||
a32c7cae SN |
437 | spin_lock_irqsave(&chip->gpio_lock, flags); |
438 | ||
02b3f84d | 439 | __set_bit(bit, chip->enable); |
a32c7cae | 440 | |
02b3f84d | 441 | if (old_enable == 0) { |
a32c7cae | 442 | /* Clear any existing per-channel interrupts */ |
02b3f84d AS |
443 | val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
444 | val &= mask; | |
445 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); | |
a32c7cae SN |
446 | |
447 | /* Update GPIO IRQ read data before enabling interrupt*/ | |
02b3f84d | 448 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); |
a32c7cae SN |
449 | |
450 | /* Enable per channel interrupt */ | |
451 | val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); | |
02b3f84d | 452 | val |= mask; |
a32c7cae SN |
453 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); |
454 | } | |
455 | ||
456 | spin_unlock_irqrestore(&chip->gpio_lock, flags); | |
457 | } | |
458 | ||
459 | /** | |
460 | * xgpio_set_irq_type - Write the specified signal of the GPIO device. | |
461 | * @irq_data: Per IRQ and chip data passed down to chip functions | |
462 | * @type: Interrupt type that is to be set for the gpio pin | |
463 | * | |
464 | * Return: | |
465 | * 0 if interrupt type is supported otherwise -EINVAL | |
466 | */ | |
467 | static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) | |
468 | { | |
469 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); | |
470 | int irq_offset = irqd_to_hwirq(irq_data); | |
02b3f84d | 471 | int bit = xgpio_to_bit(chip, irq_offset); |
a32c7cae SN |
472 | |
473 | /* | |
474 | * The Xilinx GPIO hardware provides a single interrupt status | |
475 | * indication for any state change in a given GPIO channel (bank). | |
476 | * Therefore, only rising edge or falling edge triggers are | |
477 | * supported. | |
478 | */ | |
479 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
480 | case IRQ_TYPE_EDGE_BOTH: | |
02b3f84d AS |
481 | __set_bit(bit, chip->rising_edge); |
482 | __set_bit(bit, chip->falling_edge); | |
a32c7cae SN |
483 | break; |
484 | case IRQ_TYPE_EDGE_RISING: | |
02b3f84d AS |
485 | __set_bit(bit, chip->rising_edge); |
486 | __clear_bit(bit, chip->falling_edge); | |
a32c7cae SN |
487 | break; |
488 | case IRQ_TYPE_EDGE_FALLING: | |
02b3f84d AS |
489 | __clear_bit(bit, chip->rising_edge); |
490 | __set_bit(bit, chip->falling_edge); | |
a32c7cae SN |
491 | break; |
492 | default: | |
493 | return -EINVAL; | |
494 | } | |
495 | ||
496 | irq_set_handler_locked(irq_data, handle_edge_irq); | |
497 | return 0; | |
498 | } | |
499 | ||
500 | /** | |
501 | * xgpio_irqhandler - Gpio interrupt service routine | |
502 | * @desc: Pointer to interrupt description | |
503 | */ | |
504 | static void xgpio_irqhandler(struct irq_desc *desc) | |
505 | { | |
506 | struct xgpio_instance *chip = irq_desc_get_handler_data(desc); | |
02b3f84d | 507 | struct gpio_chip *gc = &chip->gc; |
a32c7cae | 508 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
02b3f84d AS |
509 | DECLARE_BITMAP(rising, 64); |
510 | DECLARE_BITMAP(falling, 64); | |
511 | DECLARE_BITMAP(all, 64); | |
512 | int irq_offset; | |
513 | u32 status; | |
514 | u32 bit; | |
a32c7cae | 515 | |
02b3f84d | 516 | status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
a32c7cae SN |
517 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); |
518 | ||
519 | chained_irq_enter(irqchip, desc); | |
02b3f84d | 520 | |
6453b953 | 521 | spin_lock(&chip->gpio_lock); |
02b3f84d AS |
522 | |
523 | xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all); | |
524 | ||
525 | bitmap_complement(rising, chip->last_irq_read, 64); | |
526 | bitmap_and(rising, rising, all, 64); | |
527 | bitmap_and(rising, rising, chip->enable, 64); | |
528 | bitmap_and(rising, rising, chip->rising_edge, 64); | |
529 | ||
530 | bitmap_complement(falling, all, 64); | |
531 | bitmap_and(falling, falling, chip->last_irq_read, 64); | |
532 | bitmap_and(falling, falling, chip->enable, 64); | |
533 | bitmap_and(falling, falling, chip->falling_edge, 64); | |
534 | ||
535 | bitmap_copy(chip->last_irq_read, all, 64); | |
536 | bitmap_or(all, rising, falling, 64); | |
537 | ||
6453b953 | 538 | spin_unlock(&chip->gpio_lock); |
02b3f84d AS |
539 | |
540 | dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); | |
541 | ||
542 | for_each_set_bit(bit, all, 64) { | |
543 | irq_offset = xgpio_from_bit(chip, bit); | |
dbd1c54f | 544 | generic_handle_domain_irq(gc->irq.domain, irq_offset); |
a32c7cae SN |
545 | } |
546 | ||
547 | chained_irq_exit(irqchip, desc); | |
548 | } | |
549 | ||
b4510f8f LW |
550 | static const struct irq_chip xgpio_irq_chip = { |
551 | .name = "gpio-xilinx", | |
552 | .irq_ack = xgpio_irq_ack, | |
553 | .irq_mask = xgpio_irq_mask, | |
554 | .irq_unmask = xgpio_irq_unmask, | |
555 | .irq_set_type = xgpio_set_irq_type, | |
556 | .flags = IRQCHIP_IMMUTABLE, | |
557 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
558 | }; | |
559 | ||
0bcb6069 | 560 | /** |
a0579474 | 561 | * xgpio_probe - Probe method for the GPIO device. |
749564ff | 562 | * @pdev: pointer to the platform device |
0bcb6069 | 563 | * |
4ae798fa RRD |
564 | * Return: |
565 | * It returns 0, if the driver is bound to the GPIO device, or | |
566 | * a negative value if there is an error. | |
0bcb6069 | 567 | */ |
749564ff | 568 | static int xgpio_probe(struct platform_device *pdev) |
0bcb6069 JL |
569 | { |
570 | struct xgpio_instance *chip; | |
0bcb6069 | 571 | int status = 0; |
749564ff | 572 | struct device_node *np = pdev->dev.of_node; |
a32c7cae | 573 | u32 is_dual = 0; |
02b3f84d AS |
574 | u32 width[2]; |
575 | u32 state[2]; | |
576 | u32 dir[2]; | |
a32c7cae SN |
577 | struct gpio_irq_chip *girq; |
578 | u32 temp; | |
0bcb6069 | 579 | |
1d6902d3 RRD |
580 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
581 | if (!chip) | |
0bcb6069 | 582 | return -ENOMEM; |
0bcb6069 | 583 | |
1d6902d3 | 584 | platform_set_drvdata(pdev, chip); |
749564ff | 585 | |
02b3f84d AS |
586 | /* First, check if the device is dual-channel */ |
587 | of_property_read_u32(np, "xlnx,is-dual", &is_dual); | |
588 | ||
589 | /* Setup defaults */ | |
590 | memset32(width, 0, ARRAY_SIZE(width)); | |
591 | memset32(state, 0, ARRAY_SIZE(state)); | |
592 | memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); | |
593 | ||
0bcb6069 | 594 | /* Update GPIO state shadow register with default value */ |
02b3f84d AS |
595 | of_property_read_u32(np, "xlnx,dout-default", &state[0]); |
596 | of_property_read_u32(np, "xlnx,dout-default-2", &state[1]); | |
597 | ||
598 | bitmap_from_arr32(chip->state, state, 64); | |
0bcb6069 JL |
599 | |
600 | /* Update GPIO direction shadow register with default value */ | |
02b3f84d AS |
601 | of_property_read_u32(np, "xlnx,tri-default", &dir[0]); |
602 | of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]); | |
603 | ||
604 | bitmap_from_arr32(chip->dir, dir, 64); | |
6f8bf500 | 605 | |
1b4c5a6e GV |
606 | /* |
607 | * Check device node and parent device node for device width | |
608 | * and assume default width of 32 | |
609 | */ | |
02b3f84d AS |
610 | if (of_property_read_u32(np, "xlnx,gpio-width", &width[0])) |
611 | width[0] = 32; | |
1d6902d3 | 612 | |
02b3f84d | 613 | if (width[0] > 32) |
6e551bfa SN |
614 | return -EINVAL; |
615 | ||
02b3f84d AS |
616 | if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1])) |
617 | width[1] = 32; | |
1d6902d3 | 618 | |
02b3f84d AS |
619 | if (width[1] > 32) |
620 | return -EINVAL; | |
621 | ||
622 | /* Setup software pin mapping */ | |
623 | bitmap_set(chip->sw_map, 0, width[0] + width[1]); | |
624 | ||
625 | /* Setup hardware pin mapping */ | |
626 | bitmap_set(chip->hw_map, 0, width[0]); | |
627 | bitmap_set(chip->hw_map, 32, width[1]); | |
628 | ||
629 | spin_lock_init(&chip->gpio_lock); | |
1d6902d3 | 630 | |
1ebd0687 | 631 | chip->gc.base = -1; |
02b3f84d | 632 | chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); |
1ebd0687 RH |
633 | chip->gc.parent = &pdev->dev; |
634 | chip->gc.direction_input = xgpio_dir_in; | |
635 | chip->gc.direction_output = xgpio_dir_out; | |
636 | chip->gc.get = xgpio_get; | |
637 | chip->gc.set = xgpio_set; | |
26b04774 SN |
638 | chip->gc.request = xgpio_request; |
639 | chip->gc.free = xgpio_free; | |
1ebd0687 RH |
640 | chip->gc.set_multiple = xgpio_set_multiple; |
641 | ||
642 | chip->gc.label = dev_name(&pdev->dev); | |
643 | ||
644 | chip->regs = devm_platform_ioremap_resource(pdev, 0); | |
645 | if (IS_ERR(chip->regs)) { | |
646 | dev_err(&pdev->dev, "failed to ioremap memory resource\n"); | |
647 | return PTR_ERR(chip->regs); | |
648 | } | |
0bcb6069 | 649 | |
65bbe531 | 650 | chip->clk = devm_clk_get_optional(&pdev->dev, NULL); |
45c5277f SN |
651 | if (IS_ERR(chip->clk)) |
652 | return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); | |
65bbe531 SN |
653 | |
654 | status = clk_prepare_enable(chip->clk); | |
655 | if (status < 0) { | |
656 | dev_err(&pdev->dev, "Failed to prepare clk\n"); | |
657 | return status; | |
658 | } | |
26b04774 SN |
659 | pm_runtime_get_noresume(&pdev->dev); |
660 | pm_runtime_set_active(&pdev->dev); | |
661 | pm_runtime_enable(&pdev->dev); | |
65bbe531 | 662 | |
1ebd0687 | 663 | xgpio_save_regs(chip); |
0bcb6069 | 664 | |
a32c7cae SN |
665 | chip->irq = platform_get_irq_optional(pdev, 0); |
666 | if (chip->irq <= 0) | |
667 | goto skip_irq; | |
668 | ||
a32c7cae SN |
669 | /* Disable per-channel interrupts */ |
670 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); | |
671 | /* Clear any existing per-channel interrupts */ | |
672 | temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); | |
673 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); | |
674 | /* Enable global interrupts */ | |
675 | xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); | |
676 | ||
677 | girq = &chip->gc.irq; | |
b4510f8f | 678 | gpio_irq_chip_set_chip(girq, &xgpio_irq_chip); |
a32c7cae SN |
679 | girq->parent_handler = xgpio_irqhandler; |
680 | girq->num_parents = 1; | |
681 | girq->parents = devm_kcalloc(&pdev->dev, 1, | |
682 | sizeof(*girq->parents), | |
683 | GFP_KERNEL); | |
684 | if (!girq->parents) { | |
685 | status = -ENOMEM; | |
26b04774 | 686 | goto err_pm_put; |
a32c7cae SN |
687 | } |
688 | girq->parents[0] = chip->irq; | |
689 | girq->default_type = IRQ_TYPE_NONE; | |
690 | girq->handler = handle_bad_irq; | |
691 | ||
692 | skip_irq: | |
1ebd0687 | 693 | status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); |
0bcb6069 | 694 | if (status) { |
1ebd0687 | 695 | dev_err(&pdev->dev, "failed to add GPIO chip\n"); |
26b04774 | 696 | goto err_pm_put; |
0bcb6069 | 697 | } |
74600ee0 | 698 | |
26b04774 | 699 | pm_runtime_put(&pdev->dev); |
0bcb6069 | 700 | return 0; |
a32c7cae | 701 | |
26b04774 SN |
702 | err_pm_put: |
703 | pm_runtime_disable(&pdev->dev); | |
704 | pm_runtime_put_noidle(&pdev->dev); | |
a32c7cae SN |
705 | clk_disable_unprepare(chip->clk); |
706 | return status; | |
0bcb6069 JL |
707 | } |
708 | ||
9992bc95 | 709 | static const struct of_device_id xgpio_of_match[] = { |
0bcb6069 JL |
710 | { .compatible = "xlnx,xps-gpio-1.00.a", }, |
711 | { /* end of list */ }, | |
712 | }; | |
713 | ||
749564ff | 714 | MODULE_DEVICE_TABLE(of, xgpio_of_match); |
0bcb6069 | 715 | |
749564ff RRD |
716 | static struct platform_driver xgpio_plat_driver = { |
717 | .probe = xgpio_probe, | |
0230a41e | 718 | .remove = xgpio_remove, |
749564ff RRD |
719 | .driver = { |
720 | .name = "gpio-xilinx", | |
721 | .of_match_table = xgpio_of_match, | |
26b04774 | 722 | .pm = &xgpio_dev_pm_ops, |
749564ff RRD |
723 | }, |
724 | }; | |
0bcb6069 | 725 | |
749564ff RRD |
726 | static int __init xgpio_init(void) |
727 | { | |
728 | return platform_driver_register(&xgpio_plat_driver); | |
0bcb6069 JL |
729 | } |
730 | ||
0bcb6069 | 731 | subsys_initcall(xgpio_init); |
749564ff RRD |
732 | |
733 | static void __exit xgpio_exit(void) | |
734 | { | |
735 | platform_driver_unregister(&xgpio_plat_driver); | |
736 | } | |
737 | module_exit(xgpio_exit); | |
0bcb6069 JL |
738 | |
739 | MODULE_AUTHOR("Xilinx, Inc."); | |
740 | MODULE_DESCRIPTION("Xilinx GPIO driver"); | |
741 | MODULE_LICENSE("GPL"); |