[linux-2.6-block.git] / drivers / gpio / gpio-xgene.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AppliedMicro X-Gene SoC GPIO Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Author: Feng Kan <fkan@apm.com>.
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/types.h>
#include <linux/bitops.h>

#define GPIO_SET_DR_OFFSET	0x0C
#define GPIO_DATA_OFFSET	0x14
#define GPIO_BANK_STRIDE	0x0C

#define XGENE_GPIOS_PER_BANK	16
#define XGENE_MAX_GPIO_BANKS	3
#define XGENE_MAX_GPIOS		(XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)

#define GPIO_BIT_OFFSET(x)	(x % XGENE_GPIOS_PER_BANK)
#define GPIO_BANK_OFFSET(x)	((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)

struct xgene_gpio {
	struct gpio_chip	chip;
	void __iomem		*base;
	spinlock_t		lock;
	u32			set_dr_val[XGENE_MAX_GPIO_BANKS];
};

static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long bank_offset;
	u32 bit_offset;

	bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);
	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
}

static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long bank_offset;
	u32 setval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;

	setval = ioread32(chip->base + bank_offset);
	if (val)
		setval |= BIT(bit_offset);
	else
		setval &= ~BIT(bit_offset);
	iowrite32(setval, chip->base + bank_offset);
}

static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	__xgene_gpio_set(gc, offset, val);
	spin_unlock_irqrestore(&chip->lock, flags);
}

static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long bank_offset, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);

	if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags, bank_offset;
	u32 dirval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);

	spin_lock_irqsave(&chip->lock, flags);

	dirval = ioread32(chip->base + bank_offset);
	dirval |= BIT(bit_offset);
	iowrite32(dirval, chip->base + bank_offset);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int xgene_gpio_dir_out(struct gpio_chip *gc,
					unsigned int offset, int val)
{
	struct xgene_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags, bank_offset;
	u32 dirval, bit_offset;

	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	bit_offset = GPIO_BIT_OFFSET(offset);

	spin_lock_irqsave(&chip->lock, flags);

	dirval = ioread32(chip->base + bank_offset);
	dirval &= ~BIT(bit_offset);
	iowrite32(dirval, chip->base + bank_offset);
	__xgene_gpio_set(gc, offset, val);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static __maybe_unused int xgene_gpio_suspend(struct device *dev)
{
	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	unsigned long bank_offset;
	unsigned int bank;

	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
		gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
	}
	return 0;
}

static __maybe_unused int xgene_gpio_resume(struct device *dev)
{
	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	unsigned long bank_offset;
	unsigned int bank;

	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
		iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
	}
	return 0;
}

static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);

static int xgene_gpio_probe(struct platform_device *pdev)
{
	struct xgene_gpio *gpio;
	int err = 0;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio)
		return -ENOMEM;

	gpio->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(gpio->base))
		return PTR_ERR(gpio->base);

	gpio->chip.ngpio = XGENE_MAX_GPIOS;

	spin_lock_init(&gpio->lock);
	gpio->chip.parent = &pdev->dev;
	gpio->chip.get_direction = xgene_gpio_get_direction;
	gpio->chip.direction_input = xgene_gpio_dir_in;
	gpio->chip.direction_output = xgene_gpio_dir_out;
	gpio->chip.get = xgene_gpio_get;
	gpio->chip.set = xgene_gpio_set;
	gpio->chip.label = dev_name(&pdev->dev);
	gpio->chip.base = -1;

	platform_set_drvdata(pdev, gpio);

	err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
	if (err) {
		dev_err(&pdev->dev,
			"failed to register gpiochip.\n");
		return err;
	}

	dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
	return 0;
}

static const struct of_device_id xgene_gpio_of_match[] = {
	{ .compatible = "apm,xgene-gpio", },
	{},
};

#ifdef CONFIG_ACPI
static const struct acpi_device_id xgene_gpio_acpi_match[] = {
	{ "APMC0D14", 0 },
	{ },
};
#endif

static struct platform_driver xgene_gpio_driver = {
	.driver = {
		.name = "xgene-gpio",
		.of_match_table = xgene_gpio_of_match,
		.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
		.pm     = &xgene_gpio_pm,
	},
	.probe = xgene_gpio_probe,
};
builtin_platform_driver(xgene_gpio_driver);
Commit	Line	Data
caab277b	1	// SPDX-License-Identifier: GPL-2.0-only
29cbf458 FK	2	/*
	3	* AppliedMicro X-Gene SoC GPIO Driver
	4	*
	5	* Copyright (c) 2014, Applied Micro Circuits Corporation
	6	* Author: Feng Kan <fkan@apm.com>.
29cbf458 FK	7	*/
29cbf458 FK	8
0c60de3f	9	#include <linux/acpi.h>
29cbf458 FK	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/io.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/gpio/driver.h>
	16	#include <linux/types.h>
	17	#include <linux/bitops.h>
	18
	19	#define GPIO_SET_DR_OFFSET 0x0C
	20	#define GPIO_DATA_OFFSET 0x14
	21	#define GPIO_BANK_STRIDE 0x0C
	22
	23	#define XGENE_GPIOS_PER_BANK 16
	24	#define XGENE_MAX_GPIO_BANKS 3
	25	#define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
	26
	27	#define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK)
	28	#define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
	29
29cbf458 FK	30	struct xgene_gpio {
	31	struct gpio_chip chip;
	32	void __iomem *base;
	33	spinlock_t lock;
29cbf458	34	u32 set_dr_val[XGENE_MAX_GPIO_BANKS];
29cbf458 FK	35	};
29cbf458 FK	36
29cbf458 FK	37	static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
29cbf458 FK	38	{
ac9dc85e	39	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	40	unsigned long bank_offset;
	41	u32 bit_offset;
	42
	43	bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
	44	bit_offset = GPIO_BIT_OFFSET(offset);
	45	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
	46	}
	47
	48	static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	49	{
ac9dc85e	50	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	51	unsigned long bank_offset;
	52	u32 setval, bit_offset;
	53
	54	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	55	bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
	56
	57	setval = ioread32(chip->base + bank_offset);
	58	if (val)
	59	setval \|= BIT(bit_offset);
	60	else
	61	setval &= ~BIT(bit_offset);
	62	iowrite32(setval, chip->base + bank_offset);
	63	}
	64
	65	static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
	66	{
ac9dc85e	67	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	68	unsigned long flags;
	69
	70	spin_lock_irqsave(&chip->lock, flags);
	71	__xgene_gpio_set(gc, offset, val);
	72	spin_unlock_irqrestore(&chip->lock, flags);
	73	}
	74
3b711e07 LW	75	static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
	76	{
	77	struct xgene_gpio *chip = gpiochip_get_data(gc);
	78	unsigned long bank_offset, bit_offset;
	79
	80	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	81	bit_offset = GPIO_BIT_OFFSET(offset);
	82
e42615ec MV	83	if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
	84	return GPIO_LINE_DIRECTION_IN;
	85
	86	return GPIO_LINE_DIRECTION_OUT;
3b711e07 LW	87	}
3b711e07 LW	88
29cbf458 FK	89	static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
29cbf458 FK	90	{
ac9dc85e	91	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	92	unsigned long flags, bank_offset;
	93	u32 dirval, bit_offset;
	94
	95	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	96	bit_offset = GPIO_BIT_OFFSET(offset);
	97
	98	spin_lock_irqsave(&chip->lock, flags);
	99
	100	dirval = ioread32(chip->base + bank_offset);
	101	dirval \|= BIT(bit_offset);
	102	iowrite32(dirval, chip->base + bank_offset);
	103
	104	spin_unlock_irqrestore(&chip->lock, flags);
	105
	106	return 0;
	107	}
	108
	109	static int xgene_gpio_dir_out(struct gpio_chip *gc,
	110	unsigned int offset, int val)
	111	{
ac9dc85e	112	struct xgene_gpio *chip = gpiochip_get_data(gc);
29cbf458 FK	113	unsigned long flags, bank_offset;
	114	u32 dirval, bit_offset;
	115
	116	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
	117	bit_offset = GPIO_BIT_OFFSET(offset);
	118
	119	spin_lock_irqsave(&chip->lock, flags);
	120
	121	dirval = ioread32(chip->base + bank_offset);
	122	dirval &= ~BIT(bit_offset);
	123	iowrite32(dirval, chip->base + bank_offset);
	124	__xgene_gpio_set(gc, offset, val);
	125
	126	spin_unlock_irqrestore(&chip->lock, flags);
	127
	128	return 0;
	129	}
	130
b115bebc	131	static __maybe_unused int xgene_gpio_suspend(struct device *dev)
29cbf458 FK	132	{
	133	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	134	unsigned long bank_offset;
	135	unsigned int bank;
	136
	137	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
	138	bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
	139	gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
	140	}
	141	return 0;
	142	}
	143
b115bebc	144	static __maybe_unused int xgene_gpio_resume(struct device *dev)
29cbf458 FK	145	{
	146	struct xgene_gpio *gpio = dev_get_drvdata(dev);
	147	unsigned long bank_offset;
	148	unsigned int bank;
	149
	150	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
	151	bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
	152	iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
	153	}
	154	return 0;
	155	}
	156
	157	static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
29cbf458 FK	158
	159	static int xgene_gpio_probe(struct platform_device *pdev)
	160	{
29cbf458 FK	161	struct xgene_gpio *gpio;
	162	int err = 0;
	163
	164	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
cf62b4e4 BG	165	if (!gpio)
cf62b4e4 BG	166	return -ENOMEM;
29cbf458	167
f63516f4 BG	168	gpio->base = devm_platform_ioremap_resource(pdev, 0);
	169	if (IS_ERR(gpio->base))
	170	return PTR_ERR(gpio->base);
29cbf458 FK	171
	172	gpio->chip.ngpio = XGENE_MAX_GPIOS;
	173
1a19864e	174	spin_lock_init(&gpio->lock);
58383c78	175	gpio->chip.parent = &pdev->dev;
3b711e07	176	gpio->chip.get_direction = xgene_gpio_get_direction;
29cbf458 FK	177	gpio->chip.direction_input = xgene_gpio_dir_in;
	178	gpio->chip.direction_output = xgene_gpio_dir_out;
	179	gpio->chip.get = xgene_gpio_get;
	180	gpio->chip.set = xgene_gpio_set;
	181	gpio->chip.label = dev_name(&pdev->dev);
	182	gpio->chip.base = -1;
	183
	184	platform_set_drvdata(pdev, gpio);
	185
9d113c69	186	err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
29cbf458 FK	187	if (err) {
	188	dev_err(&pdev->dev,
	189	"failed to register gpiochip.\n");
cf62b4e4	190	return err;
29cbf458 FK	191	}
	192
	193	dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
	194	return 0;
29cbf458 FK	195	}
29cbf458 FK	196
29cbf458 FK	197	static const struct of_device_id xgene_gpio_of_match[] = {
	198	{ .compatible = "apm,xgene-gpio", },
	199	{},
	200	};
29cbf458	201
0c60de3f DD	202	#ifdef CONFIG_ACPI
	203	static const struct acpi_device_id xgene_gpio_acpi_match[] = {
	204	{ "APMC0D14", 0 },
	205	{ },
	206	};
	207	#endif
29cbf458 FK	208
	209	static struct platform_driver xgene_gpio_driver = {
	210	.driver = {
	211	.name = "xgene-gpio",
29cbf458	212	.of_match_table = xgene_gpio_of_match,
0c60de3f	213	.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
b115bebc	214	.pm = &xgene_gpio_pm,
29cbf458 FK	215	},
29cbf458 FK	216	.probe = xgene_gpio_probe,
29cbf458	217	};
b33d12d3	218	builtin_platform_driver(xgene_gpio_driver);