[linux-block.git] / drivers / gpio / gpio-xgene-sb.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * AppliedMicro X-Gene SoC GPIO-Standby Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Author:	Tin Huynh <tnhuynh@apm.com>.
 *		Y Vo <yvo@apm.com>.
 *		Quan Nguyen <qnguyen@apm.com>.
 */

#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/acpi.h>

#include "gpiolib.h"
#include "gpiolib-acpi.h"

/* Common property names */
#define XGENE_NIRQ_PROPERTY		"apm,nr-irqs"
#define XGENE_NGPIO_PROPERTY		"apm,nr-gpios"
#define XGENE_IRQ_START_PROPERTY	"apm,irq-start"

#define XGENE_DFLT_MAX_NGPIO		22
#define XGENE_DFLT_MAX_NIRQ		6
#define XGENE_DFLT_IRQ_START_PIN	8
#define GPIO_MASK(x)			(1U << ((x) % 32))

#define MPA_GPIO_INT_LVL		0x0290
#define MPA_GPIO_OE_ADDR		0x029c
#define MPA_GPIO_OUT_ADDR		0x02a0
#define MPA_GPIO_IN_ADDR 		0x02a4
#define MPA_GPIO_SEL_LO 		0x0294

#define GPIO_INT_LEVEL_H	0x000001
#define GPIO_INT_LEVEL_L	0x000000

/**
 * struct xgene_gpio_sb - GPIO-Standby private data structure.
 * @gc:				memory-mapped GPIO controllers.
 * @regs:			GPIO register base offset
 * @irq_domain:			GPIO interrupt domain
 * @irq_start:			GPIO pin that start support interrupt
 * @nirq:			Number of GPIO pins that supports interrupt
 * @parent_irq_base:		Start parent HWIRQ
 */
struct xgene_gpio_sb {
	struct gpio_chip	gc;
	void __iomem		*regs;
	struct irq_domain	*irq_domain;
	u16			irq_start;
	u16			nirq;
	u16			parent_irq_base;
};

#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)

static void xgene_gpio_set_bit(struct gpio_chip *gc,
				void __iomem *reg, u32 gpio, int val)
{
	u32 data;

	data = gc->read_reg(reg);
	if (val)
		data |= GPIO_MASK(gpio);
	else
		data &= ~GPIO_MASK(gpio);
	gc->write_reg(reg, data);
}

static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
	int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
	int lvl_type = GPIO_INT_LEVEL_H;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LEVEL_H;
		break;
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LEVEL_L;
		break;
	default:
		break;
	}

	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 1);
	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
			d->hwirq, lvl_type);

	/* Propagate IRQ type setting to parent */
	if (type & IRQ_TYPE_EDGE_BOTH)
		return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
	else
		return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
}

static struct irq_chip xgene_gpio_sb_irq_chip = {
	.name           = "sbgpio",
	.irq_eoi	= irq_chip_eoi_parent,
	.irq_mask       = irq_chip_mask_parent,
	.irq_unmask     = irq_chip_unmask_parent,
	.irq_set_type   = xgene_gpio_sb_irq_set_type,
};

static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
{
	struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
	struct irq_fwspec fwspec;

	if ((gpio < priv->irq_start) ||
			(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
		return -ENXIO;

	fwspec.fwnode = gc->parent->fwnode;
	fwspec.param_count = 2;
	fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
	return irq_create_fwspec_mapping(&fwspec);
}

static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
					 struct irq_data *irq_data,
					 bool reserve)
{
	struct xgene_gpio_sb *priv = d->host_data;
	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
	int ret;

	ret = gpiochip_lock_as_irq(&priv->gc, gpio);
	if (ret) {
		dev_err(priv->gc.parent,
		"Unable to configure XGene GPIO standby pin %d as IRQ\n",
				gpio);
		return ret;
	}

	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 1);
	return 0;
}

static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
		struct irq_data *irq_data)
{
	struct xgene_gpio_sb *priv = d->host_data;
	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);

	gpiochip_unlock_as_irq(&priv->gc, gpio);
	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 0);
}

static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
		struct irq_fwspec *fwspec,
		unsigned long *hwirq,
		unsigned int *type)
{
	struct xgene_gpio_sb *priv = d->host_data;

	if ((fwspec->param_count != 2) ||
		(fwspec->param[0] >= priv->nirq))
		return -EINVAL;
	*hwirq = fwspec->param[0];
	*type = fwspec->param[1];
	return 0;
}

static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
					unsigned int virq,
					unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	struct xgene_gpio_sb *priv = domain->host_data;
	irq_hw_number_t hwirq;
	unsigned int i;

	hwirq = fwspec->param[0];
	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
				&xgene_gpio_sb_irq_chip, priv);

	parent_fwspec.fwnode = domain->parent->fwnode;
	if (is_of_node(parent_fwspec.fwnode)) {
		parent_fwspec.param_count = 3;
		parent_fwspec.param[0] = 0;/* SPI */
		/* Skip SGIs and PPIs*/
		parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
		parent_fwspec.param[2] = fwspec->param[1];
	} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
		parent_fwspec.param_count = 2;
		parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
		parent_fwspec.param[1] = fwspec->param[1];
	} else
		return -EINVAL;

	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
			&parent_fwspec);
}

static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
	.translate      = xgene_gpio_sb_domain_translate,
	.alloc          = xgene_gpio_sb_domain_alloc,
	.free           = irq_domain_free_irqs_common,
	.activate	= xgene_gpio_sb_domain_activate,
	.deactivate	= xgene_gpio_sb_domain_deactivate,
};

static int xgene_gpio_sb_probe(struct platform_device *pdev)
{
	struct xgene_gpio_sb *priv;
	int ret;
	void __iomem *regs;
	struct irq_domain *parent_domain = NULL;
	u32 val32;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	priv->regs = regs;

	ret = platform_get_irq(pdev, 0);
	if (ret > 0) {
		priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
		parent_domain = irq_get_irq_data(ret)->domain;
	}
	if (!parent_domain) {
		dev_err(&pdev->dev, "unable to obtain parent domain\n");
		return -ENODEV;
	}

	ret = bgpio_init(&priv->gc, &pdev->dev, 4,
			regs + MPA_GPIO_IN_ADDR,
			regs + MPA_GPIO_OUT_ADDR, NULL,
			regs + MPA_GPIO_OE_ADDR, NULL, 0);
        if (ret)
                return ret;

	priv->gc.to_irq = xgene_gpio_sb_to_irq;

	/* Retrieve start irq pin, use default if property not found */
	priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
	if (!device_property_read_u32(&pdev->dev,
					XGENE_IRQ_START_PROPERTY, &val32))
		priv->irq_start = val32;

	/* Retrieve number irqs, use default if property not found */
	priv->nirq = XGENE_DFLT_MAX_NIRQ;
	if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
		priv->nirq = val32;

	/* Retrieve number gpio, use default if property not found */
	priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
	if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
		priv->gc.ngpio = val32;

	dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
			priv->gc.ngpio, priv->nirq, priv->irq_start);

	platform_set_drvdata(pdev, priv);

	priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
					0, priv->nirq, pdev->dev.fwnode,
					&xgene_gpio_sb_domain_ops, priv);
	if (!priv->irq_domain)
		return -ENODEV;

	priv->gc.irq.domain = priv->irq_domain;

	ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
	if (ret) {
		dev_err(&pdev->dev,
			"failed to register X-Gene GPIO Standby driver\n");
		irq_domain_remove(priv->irq_domain);
		return ret;
	}

	dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");

	/* Register interrupt handlers for GPIO signaled ACPI Events */
	acpi_gpiochip_request_interrupts(&priv->gc);

	return ret;
}

static int xgene_gpio_sb_remove(struct platform_device *pdev)
{
	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);

	acpi_gpiochip_free_interrupts(&priv->gc);

	irq_domain_remove(priv->irq_domain);

	return 0;
}

static const struct of_device_id xgene_gpio_sb_of_match[] = {
	{.compatible = "apm,xgene-gpio-sb", },
	{},
};
MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);

#ifdef CONFIG_ACPI
static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
	{"APMC0D15", 0},
	{},
};
MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
#endif

static struct platform_driver xgene_gpio_sb_driver = {
	.driver = {
		   .name = "xgene-gpio-sb",
		   .of_match_table = xgene_gpio_sb_of_match,
		   .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
		   },
	.probe = xgene_gpio_sb_probe,
	.remove = xgene_gpio_sb_remove,
};
module_platform_driver(xgene_gpio_sb_driver);

MODULE_AUTHOR("AppliedMicro");
MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
b2b35e10 V	2	/*
	3	* AppliedMicro X-Gene SoC GPIO-Standby Driver
	4	*
	5	* Copyright (c) 2014, Applied Micro Circuits Corporation
1013fc41 QN	6	* Author: Tin Huynh <tnhuynh@apm.com>.
	7	* Y Vo <yvo@apm.com>.
	8	* Quan Nguyen <qnguyen@apm.com>.
b2b35e10 V	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/io.h>
4d3a0500	13	#include <linux/of.h>
b2b35e10	14	#include <linux/platform_device.h>
b2b35e10	15	#include <linux/gpio/driver.h>
733cf014	16	#include <linux/acpi.h>
b2b35e10	17
733cf014	18	#include "gpiolib.h"
77cb907a	19	#include "gpiolib-acpi.h"
733cf014	20
1013fc41 QN	21	/* Common property names */
	22	#define XGENE_NIRQ_PROPERTY "apm,nr-irqs"
	23	#define XGENE_NGPIO_PROPERTY "apm,nr-gpios"
	24	#define XGENE_IRQ_START_PROPERTY "apm,irq-start"
b2b35e10	25
1013fc41 QN	26	#define XGENE_DFLT_MAX_NGPIO 22
	27	#define XGENE_DFLT_MAX_NIRQ 6
	28	#define XGENE_DFLT_IRQ_START_PIN 8
b2b35e10 V	29	#define GPIO_MASK(x) (1U << ((x) % 32))
	30
	31	#define MPA_GPIO_INT_LVL 0x0290
	32	#define MPA_GPIO_OE_ADDR 0x029c
	33	#define MPA_GPIO_OUT_ADDR 0x02a0
	34	#define MPA_GPIO_IN_ADDR 0x02a4
	35	#define MPA_GPIO_SEL_LO 0x0294
	36
1013fc41 QN	37	#define GPIO_INT_LEVEL_H 0x000001
	38	#define GPIO_INT_LEVEL_L 0x000000
	39
b2b35e10 V	40	/**
b2b35e10 V	41	* struct xgene_gpio_sb - GPIO-Standby private data structure.
0f4630f3	42	* @gc: memory-mapped GPIO controllers.
1013fc41 QN	43	* @regs: GPIO register base offset
	44	* @irq_domain: GPIO interrupt domain
	45	* @irq_start: GPIO pin that start support interrupt
	46	* @nirq: Number of GPIO pins that supports interrupt
	47	* @parent_irq_base: Start parent HWIRQ
b2b35e10 V	48	*/
b2b35e10 V	49	struct xgene_gpio_sb {
0f4630f3	50	struct gpio_chip gc;
1013fc41 QN	51	void __iomem *regs;
	52	struct irq_domain *irq_domain;
	53	u16 irq_start;
	54	u16 nirq;
	55	u16 parent_irq_base;
b2b35e10 V	56	};
b2b35e10 V	57
1013fc41 QN	58	#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
	59	#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
	60
	61	static void xgene_gpio_set_bit(struct gpio_chip *gc,
	62	void __iomem *reg, u32 gpio, int val)
b2b35e10 V	63	{
	64	u32 data;
	65
0f4630f3	66	data = gc->read_reg(reg);
b2b35e10 V	67	if (val)
	68	data \|= GPIO_MASK(gpio);
	69	else
	70	data &= ~GPIO_MASK(gpio);
0f4630f3	71	gc->write_reg(reg, data);
b2b35e10 V	72	}
b2b35e10 V	73
1013fc41 QN	74	static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
	75	{
	76	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
	77	int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
	78	int lvl_type = GPIO_INT_LEVEL_H;
	79
	80	switch (type & IRQ_TYPE_SENSE_MASK) {
	81	case IRQ_TYPE_EDGE_RISING:
	82	case IRQ_TYPE_LEVEL_HIGH:
	83	lvl_type = GPIO_INT_LEVEL_H;
	84	break;
	85	case IRQ_TYPE_EDGE_FALLING:
	86	case IRQ_TYPE_LEVEL_LOW:
	87	lvl_type = GPIO_INT_LEVEL_L;
	88	break;
	89	default:
	90	break;
	91	}
	92
	93	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	94	gpio * 2, 1);
	95	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
	96	d->hwirq, lvl_type);
	97
	98	/* Propagate IRQ type setting to parent */
	99	if (type & IRQ_TYPE_EDGE_BOTH)
	100	return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
	101	else
	102	return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
	103	}
	104
	105	static struct irq_chip xgene_gpio_sb_irq_chip = {
	106	.name = "sbgpio",
	107	.irq_eoi = irq_chip_eoi_parent,
	108	.irq_mask = irq_chip_mask_parent,
	109	.irq_unmask = irq_chip_unmask_parent,
	110	.irq_set_type = xgene_gpio_sb_irq_set_type,
	111	};
	112
	113	static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
b2b35e10	114	{
0f4630f3	115	struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
1013fc41 QN	116	struct irq_fwspec fwspec;
	117
	118	if ((gpio < priv->irq_start) \|\|
	119	(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
	120	return -ENXIO;
	121
aa5c2a88	122	fwspec.fwnode = gc->parent->fwnode;
1013fc41 QN	123	fwspec.param_count = 2;
1013fc41 QN	124	fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
7fc504b9	125	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
1013fc41 QN	126	return irq_create_fwspec_mapping(&fwspec);
	127	}
	128
72491643 TG	129	static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
72491643 TG	130	struct irq_data *irq_data,
702cb0a0	131	bool reserve)
1013fc41 QN	132	{
	133	struct xgene_gpio_sb *priv = d->host_data;
	134	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
6d7a2b8b	135	int ret;
1013fc41	136
6d7a2b8b AS	137	ret = gpiochip_lock_as_irq(&priv->gc, gpio);
6d7a2b8b AS	138	if (ret) {
1013fc41 QN	139	dev_err(priv->gc.parent,
	140	"Unable to configure XGene GPIO standby pin %d as IRQ\n",
	141	gpio);
6d7a2b8b	142	return ret;
1013fc41 QN	143	}
	144
	145	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	146	gpio * 2, 1);
72491643	147	return 0;
1013fc41 QN	148	}
	149
	150	static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
	151	struct irq_data *irq_data)
	152	{
	153	struct xgene_gpio_sb *priv = d->host_data;
	154	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
	155
	156	gpiochip_unlock_as_irq(&priv->gc, gpio);
	157	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	158	gpio * 2, 0);
	159	}
	160
	161	static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
	162	struct irq_fwspec *fwspec,
	163	unsigned long *hwirq,
	164	unsigned int *type)
	165	{
	166	struct xgene_gpio_sb *priv = d->host_data;
b2b35e10	167
1013fc41 QN	168	if ((fwspec->param_count != 2) \|\|
	169	(fwspec->param[0] >= priv->nirq))
	170	return -EINVAL;
	171	*hwirq = fwspec->param[0];
	172	*type = fwspec->param[1];
	173	return 0;
	174	}
	175
	176	static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
	177	unsigned int virq,
	178	unsigned int nr_irqs, void *data)
	179	{
	180	struct irq_fwspec *fwspec = data;
	181	struct irq_fwspec parent_fwspec;
	182	struct xgene_gpio_sb *priv = domain->host_data;
	183	irq_hw_number_t hwirq;
	184	unsigned int i;
	185
	186	hwirq = fwspec->param[0];
	187	for (i = 0; i < nr_irqs; i++)
	188	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	189	&xgene_gpio_sb_irq_chip, priv);
	190
	191	parent_fwspec.fwnode = domain->parent->fwnode;
	192	if (is_of_node(parent_fwspec.fwnode)) {
	193	parent_fwspec.param_count = 3;
	194	parent_fwspec.param[0] = 0;/* SPI */
	195	/* Skip SGIs and PPIs*/
	196	parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
	197	parent_fwspec.param[2] = fwspec->param[1];
	198	} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
	199	parent_fwspec.param_count = 2;
	200	parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
	201	parent_fwspec.param[1] = fwspec->param[1];
	202	} else
	203	return -EINVAL;
	204
	205	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
	206	&parent_fwspec);
	207	}
	208
1013fc41 QN	209	static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
	210	.translate = xgene_gpio_sb_domain_translate,
	211	.alloc = xgene_gpio_sb_domain_alloc,
c6cc75fe	212	.free = irq_domain_free_irqs_common,
1013fc41 QN	213	.activate = xgene_gpio_sb_domain_activate,
	214	.deactivate = xgene_gpio_sb_domain_deactivate,
	215	};
	216
b2b35e10 V	217	static int xgene_gpio_sb_probe(struct platform_device *pdev)
	218	{
	219	struct xgene_gpio_sb *priv;
67ebb742	220	int ret;
b2b35e10	221	void __iomem *regs;
1013fc41	222	struct irq_domain *parent_domain = NULL;
1013fc41	223	u32 val32;
b2b35e10 V	224
	225	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	226	if (!priv)
	227	return -ENOMEM;
	228
6ff49fba	229	regs = devm_platform_ioremap_resource(pdev, 0);
33c07b46	230	if (IS_ERR(regs))
b2b35e10 V	231	return PTR_ERR(regs);
b2b35e10 V	232
1013fc41 QN	233	priv->regs = regs;
	234
	235	ret = platform_get_irq(pdev, 0);
	236	if (ret > 0) {
	237	priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
	238	parent_domain = irq_get_irq_data(ret)->domain;
	239	}
	240	if (!parent_domain) {
	241	dev_err(&pdev->dev, "unable to obtain parent domain\n");
	242	return -ENODEV;
	243	}
	244
0f4630f3	245	ret = bgpio_init(&priv->gc, &pdev->dev, 4,
b2b35e10 V	246	regs + MPA_GPIO_IN_ADDR,
	247	regs + MPA_GPIO_OUT_ADDR, NULL,
	248	regs + MPA_GPIO_OE_ADDR, NULL, 0);
	249	if (ret)
	250	return ret;
	251
1013fc41	252	priv->gc.to_irq = xgene_gpio_sb_to_irq;
b2b35e10	253
1013fc41 QN	254	/* Retrieve start irq pin, use default if property not found */
	255	priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
	256	if (!device_property_read_u32(&pdev->dev,
	257	XGENE_IRQ_START_PROPERTY, &val32))
	258	priv->irq_start = val32;
b2b35e10	259
1013fc41 QN	260	/* Retrieve number irqs, use default if property not found */
	261	priv->nirq = XGENE_DFLT_MAX_NIRQ;
	262	if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
	263	priv->nirq = val32;
b2b35e10	264
1013fc41 QN	265	/* Retrieve number gpio, use default if property not found */
	266	priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
	267	if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
	268	priv->gc.ngpio = val32;
	269
	270	dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
	271	priv->gc.ngpio, priv->nirq, priv->irq_start);
b2b35e10 V	272
	273	platform_set_drvdata(pdev, priv);
	274
1013fc41	275	priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
aa5c2a88	276	0, priv->nirq, pdev->dev.fwnode,
1013fc41 QN	277	&xgene_gpio_sb_domain_ops, priv);
	278	if (!priv->irq_domain)
	279	return -ENODEV;
	280
f0fbe7bc	281	priv->gc.irq.domain = priv->irq_domain;
1013fc41	282
29862059	283	ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
1013fc41 QN	284	if (ret) {
	285	dev_err(&pdev->dev,
	286	"failed to register X-Gene GPIO Standby driver\n");
	287	irq_domain_remove(priv->irq_domain);
	288	return ret;
	289	}
	290
	291	dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
b2b35e10	292
d850c6f4 AS	293	/* Register interrupt handlers for GPIO signaled ACPI Events */
d850c6f4 AS	294	acpi_gpiochip_request_interrupts(&priv->gc);
733cf014	295
b2b35e10 V	296	return ret;
	297	}
	298
	299	static int xgene_gpio_sb_remove(struct platform_device *pdev)
	300	{
	301	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
	302
d850c6f4	303	acpi_gpiochip_free_interrupts(&priv->gc);
733cf014	304
1013fc41 QN	305	irq_domain_remove(priv->irq_domain);
1013fc41 QN	306
0f4630f3	307	return 0;
b2b35e10 V	308	}
	309
	310	static const struct of_device_id xgene_gpio_sb_of_match[] = {
	311	{.compatible = "apm,xgene-gpio-sb", },
	312	{},
	313	};
	314	MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
	315
733cf014 V	316	#ifdef CONFIG_ACPI
	317	static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
	318	{"APMC0D15", 0},
	319	{},
	320	};
	321	MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
	322	#endif
	323
b2b35e10 V	324	static struct platform_driver xgene_gpio_sb_driver = {
	325	.driver = {
	326	.name = "xgene-gpio-sb",
	327	.of_match_table = xgene_gpio_sb_of_match,
733cf014	328	.acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
b2b35e10 V	329	},
	330	.probe = xgene_gpio_sb_probe,
	331	.remove = xgene_gpio_sb_remove,
	332	};
	333	module_platform_driver(xgene_gpio_sb_driver);
	334
	335	MODULE_AUTHOR("AppliedMicro");
	336	MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
	337	MODULE_LICENSE("GPL");