Commit | Line | Data |
---|---|---|
b2b35e10 V |
1 | /* |
2 | * AppliedMicro X-Gene SoC GPIO-Standby Driver | |
3 | * | |
4 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
1013fc41 QN |
5 | * Author: Tin Huynh <tnhuynh@apm.com>. |
6 | * Y Vo <yvo@apm.com>. | |
7 | * Quan Nguyen <qnguyen@apm.com>. | |
b2b35e10 V |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/of_gpio.h> | |
b2b35e10 | 27 | #include <linux/gpio/driver.h> |
733cf014 | 28 | #include <linux/acpi.h> |
b2b35e10 | 29 | |
733cf014 V |
30 | #include "gpiolib.h" |
31 | ||
1013fc41 QN |
32 | /* Common property names */ |
33 | #define XGENE_NIRQ_PROPERTY "apm,nr-irqs" | |
34 | #define XGENE_NGPIO_PROPERTY "apm,nr-gpios" | |
35 | #define XGENE_IRQ_START_PROPERTY "apm,irq-start" | |
b2b35e10 | 36 | |
1013fc41 QN |
37 | #define XGENE_DFLT_MAX_NGPIO 22 |
38 | #define XGENE_DFLT_MAX_NIRQ 6 | |
39 | #define XGENE_DFLT_IRQ_START_PIN 8 | |
b2b35e10 V |
40 | #define GPIO_MASK(x) (1U << ((x) % 32)) |
41 | ||
42 | #define MPA_GPIO_INT_LVL 0x0290 | |
43 | #define MPA_GPIO_OE_ADDR 0x029c | |
44 | #define MPA_GPIO_OUT_ADDR 0x02a0 | |
45 | #define MPA_GPIO_IN_ADDR 0x02a4 | |
46 | #define MPA_GPIO_SEL_LO 0x0294 | |
47 | ||
1013fc41 QN |
48 | #define GPIO_INT_LEVEL_H 0x000001 |
49 | #define GPIO_INT_LEVEL_L 0x000000 | |
50 | ||
b2b35e10 V |
51 | /** |
52 | * struct xgene_gpio_sb - GPIO-Standby private data structure. | |
0f4630f3 | 53 | * @gc: memory-mapped GPIO controllers. |
1013fc41 QN |
54 | * @regs: GPIO register base offset |
55 | * @irq_domain: GPIO interrupt domain | |
56 | * @irq_start: GPIO pin that start support interrupt | |
57 | * @nirq: Number of GPIO pins that supports interrupt | |
58 | * @parent_irq_base: Start parent HWIRQ | |
b2b35e10 V |
59 | */ |
60 | struct xgene_gpio_sb { | |
0f4630f3 | 61 | struct gpio_chip gc; |
1013fc41 QN |
62 | void __iomem *regs; |
63 | struct irq_domain *irq_domain; | |
64 | u16 irq_start; | |
65 | u16 nirq; | |
66 | u16 parent_irq_base; | |
b2b35e10 V |
67 | }; |
68 | ||
1013fc41 QN |
69 | #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start) |
70 | #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start) | |
71 | ||
72 | static void xgene_gpio_set_bit(struct gpio_chip *gc, | |
73 | void __iomem *reg, u32 gpio, int val) | |
b2b35e10 V |
74 | { |
75 | u32 data; | |
76 | ||
0f4630f3 | 77 | data = gc->read_reg(reg); |
b2b35e10 V |
78 | if (val) |
79 | data |= GPIO_MASK(gpio); | |
80 | else | |
81 | data &= ~GPIO_MASK(gpio); | |
0f4630f3 | 82 | gc->write_reg(reg, data); |
b2b35e10 V |
83 | } |
84 | ||
1013fc41 QN |
85 | static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type) |
86 | { | |
87 | struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d); | |
88 | int gpio = HWIRQ_TO_GPIO(priv, d->hwirq); | |
89 | int lvl_type = GPIO_INT_LEVEL_H; | |
90 | ||
91 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
92 | case IRQ_TYPE_EDGE_RISING: | |
93 | case IRQ_TYPE_LEVEL_HIGH: | |
94 | lvl_type = GPIO_INT_LEVEL_H; | |
95 | break; | |
96 | case IRQ_TYPE_EDGE_FALLING: | |
97 | case IRQ_TYPE_LEVEL_LOW: | |
98 | lvl_type = GPIO_INT_LEVEL_L; | |
99 | break; | |
100 | default: | |
101 | break; | |
102 | } | |
103 | ||
104 | xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, | |
105 | gpio * 2, 1); | |
106 | xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL, | |
107 | d->hwirq, lvl_type); | |
108 | ||
109 | /* Propagate IRQ type setting to parent */ | |
110 | if (type & IRQ_TYPE_EDGE_BOTH) | |
111 | return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); | |
112 | else | |
113 | return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); | |
114 | } | |
115 | ||
116 | static struct irq_chip xgene_gpio_sb_irq_chip = { | |
117 | .name = "sbgpio", | |
118 | .irq_eoi = irq_chip_eoi_parent, | |
119 | .irq_mask = irq_chip_mask_parent, | |
120 | .irq_unmask = irq_chip_unmask_parent, | |
121 | .irq_set_type = xgene_gpio_sb_irq_set_type, | |
122 | }; | |
123 | ||
124 | static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio) | |
b2b35e10 | 125 | { |
0f4630f3 | 126 | struct xgene_gpio_sb *priv = gpiochip_get_data(gc); |
1013fc41 QN |
127 | struct irq_fwspec fwspec; |
128 | ||
129 | if ((gpio < priv->irq_start) || | |
130 | (gpio > HWIRQ_TO_GPIO(priv, priv->nirq))) | |
131 | return -ENXIO; | |
132 | ||
aa5c2a88 | 133 | fwspec.fwnode = gc->parent->fwnode; |
1013fc41 QN |
134 | fwspec.param_count = 2; |
135 | fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio); | |
136 | fwspec.param[1] = IRQ_TYPE_NONE; | |
137 | return irq_create_fwspec_mapping(&fwspec); | |
138 | } | |
139 | ||
72491643 TG |
140 | static int xgene_gpio_sb_domain_activate(struct irq_domain *d, |
141 | struct irq_data *irq_data, | |
142 | bool early) | |
1013fc41 QN |
143 | { |
144 | struct xgene_gpio_sb *priv = d->host_data; | |
145 | u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); | |
146 | ||
147 | if (gpiochip_lock_as_irq(&priv->gc, gpio)) { | |
148 | dev_err(priv->gc.parent, | |
149 | "Unable to configure XGene GPIO standby pin %d as IRQ\n", | |
150 | gpio); | |
72491643 | 151 | return -ENOSPC; |
1013fc41 QN |
152 | } |
153 | ||
154 | xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, | |
155 | gpio * 2, 1); | |
72491643 | 156 | return 0; |
1013fc41 QN |
157 | } |
158 | ||
159 | static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d, | |
160 | struct irq_data *irq_data) | |
161 | { | |
162 | struct xgene_gpio_sb *priv = d->host_data; | |
163 | u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); | |
164 | ||
165 | gpiochip_unlock_as_irq(&priv->gc, gpio); | |
166 | xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, | |
167 | gpio * 2, 0); | |
168 | } | |
169 | ||
170 | static int xgene_gpio_sb_domain_translate(struct irq_domain *d, | |
171 | struct irq_fwspec *fwspec, | |
172 | unsigned long *hwirq, | |
173 | unsigned int *type) | |
174 | { | |
175 | struct xgene_gpio_sb *priv = d->host_data; | |
b2b35e10 | 176 | |
1013fc41 QN |
177 | if ((fwspec->param_count != 2) || |
178 | (fwspec->param[0] >= priv->nirq)) | |
179 | return -EINVAL; | |
180 | *hwirq = fwspec->param[0]; | |
181 | *type = fwspec->param[1]; | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain, | |
186 | unsigned int virq, | |
187 | unsigned int nr_irqs, void *data) | |
188 | { | |
189 | struct irq_fwspec *fwspec = data; | |
190 | struct irq_fwspec parent_fwspec; | |
191 | struct xgene_gpio_sb *priv = domain->host_data; | |
192 | irq_hw_number_t hwirq; | |
193 | unsigned int i; | |
194 | ||
195 | hwirq = fwspec->param[0]; | |
196 | for (i = 0; i < nr_irqs; i++) | |
197 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, | |
198 | &xgene_gpio_sb_irq_chip, priv); | |
199 | ||
200 | parent_fwspec.fwnode = domain->parent->fwnode; | |
201 | if (is_of_node(parent_fwspec.fwnode)) { | |
202 | parent_fwspec.param_count = 3; | |
203 | parent_fwspec.param[0] = 0;/* SPI */ | |
204 | /* Skip SGIs and PPIs*/ | |
205 | parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32; | |
206 | parent_fwspec.param[2] = fwspec->param[1]; | |
207 | } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) { | |
208 | parent_fwspec.param_count = 2; | |
209 | parent_fwspec.param[0] = hwirq + priv->parent_irq_base; | |
210 | parent_fwspec.param[1] = fwspec->param[1]; | |
211 | } else | |
212 | return -EINVAL; | |
213 | ||
214 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, | |
215 | &parent_fwspec); | |
216 | } | |
217 | ||
1013fc41 QN |
218 | static const struct irq_domain_ops xgene_gpio_sb_domain_ops = { |
219 | .translate = xgene_gpio_sb_domain_translate, | |
220 | .alloc = xgene_gpio_sb_domain_alloc, | |
c6cc75fe | 221 | .free = irq_domain_free_irqs_common, |
1013fc41 QN |
222 | .activate = xgene_gpio_sb_domain_activate, |
223 | .deactivate = xgene_gpio_sb_domain_deactivate, | |
224 | }; | |
225 | ||
b2b35e10 V |
226 | static int xgene_gpio_sb_probe(struct platform_device *pdev) |
227 | { | |
228 | struct xgene_gpio_sb *priv; | |
67ebb742 | 229 | int ret; |
b2b35e10 V |
230 | struct resource *res; |
231 | void __iomem *regs; | |
1013fc41 | 232 | struct irq_domain *parent_domain = NULL; |
1013fc41 | 233 | u32 val32; |
b2b35e10 V |
234 | |
235 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
236 | if (!priv) | |
237 | return -ENOMEM; | |
238 | ||
239 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
240 | regs = devm_ioremap_resource(&pdev->dev, res); | |
33c07b46 | 241 | if (IS_ERR(regs)) |
b2b35e10 V |
242 | return PTR_ERR(regs); |
243 | ||
1013fc41 QN |
244 | priv->regs = regs; |
245 | ||
246 | ret = platform_get_irq(pdev, 0); | |
247 | if (ret > 0) { | |
248 | priv->parent_irq_base = irq_get_irq_data(ret)->hwirq; | |
249 | parent_domain = irq_get_irq_data(ret)->domain; | |
250 | } | |
251 | if (!parent_domain) { | |
252 | dev_err(&pdev->dev, "unable to obtain parent domain\n"); | |
253 | return -ENODEV; | |
254 | } | |
255 | ||
0f4630f3 | 256 | ret = bgpio_init(&priv->gc, &pdev->dev, 4, |
b2b35e10 V |
257 | regs + MPA_GPIO_IN_ADDR, |
258 | regs + MPA_GPIO_OUT_ADDR, NULL, | |
259 | regs + MPA_GPIO_OE_ADDR, NULL, 0); | |
260 | if (ret) | |
261 | return ret; | |
262 | ||
1013fc41 | 263 | priv->gc.to_irq = xgene_gpio_sb_to_irq; |
b2b35e10 | 264 | |
1013fc41 QN |
265 | /* Retrieve start irq pin, use default if property not found */ |
266 | priv->irq_start = XGENE_DFLT_IRQ_START_PIN; | |
267 | if (!device_property_read_u32(&pdev->dev, | |
268 | XGENE_IRQ_START_PROPERTY, &val32)) | |
269 | priv->irq_start = val32; | |
b2b35e10 | 270 | |
1013fc41 QN |
271 | /* Retrieve number irqs, use default if property not found */ |
272 | priv->nirq = XGENE_DFLT_MAX_NIRQ; | |
273 | if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32)) | |
274 | priv->nirq = val32; | |
b2b35e10 | 275 | |
1013fc41 QN |
276 | /* Retrieve number gpio, use default if property not found */ |
277 | priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO; | |
278 | if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32)) | |
279 | priv->gc.ngpio = val32; | |
280 | ||
281 | dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n", | |
282 | priv->gc.ngpio, priv->nirq, priv->irq_start); | |
b2b35e10 V |
283 | |
284 | platform_set_drvdata(pdev, priv); | |
285 | ||
1013fc41 | 286 | priv->irq_domain = irq_domain_create_hierarchy(parent_domain, |
aa5c2a88 | 287 | 0, priv->nirq, pdev->dev.fwnode, |
1013fc41 QN |
288 | &xgene_gpio_sb_domain_ops, priv); |
289 | if (!priv->irq_domain) | |
290 | return -ENODEV; | |
291 | ||
f0fbe7bc | 292 | priv->gc.irq.domain = priv->irq_domain; |
1013fc41 | 293 | |
29862059 | 294 | ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); |
1013fc41 QN |
295 | if (ret) { |
296 | dev_err(&pdev->dev, | |
297 | "failed to register X-Gene GPIO Standby driver\n"); | |
298 | irq_domain_remove(priv->irq_domain); | |
299 | return ret; | |
300 | } | |
301 | ||
302 | dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n"); | |
b2b35e10 | 303 | |
733cf014 V |
304 | if (priv->nirq > 0) { |
305 | /* Register interrupt handlers for gpio signaled acpi events */ | |
0f4630f3 | 306 | acpi_gpiochip_request_interrupts(&priv->gc); |
733cf014 V |
307 | } |
308 | ||
b2b35e10 V |
309 | return ret; |
310 | } | |
311 | ||
312 | static int xgene_gpio_sb_remove(struct platform_device *pdev) | |
313 | { | |
314 | struct xgene_gpio_sb *priv = platform_get_drvdata(pdev); | |
315 | ||
733cf014 | 316 | if (priv->nirq > 0) { |
0f4630f3 | 317 | acpi_gpiochip_free_interrupts(&priv->gc); |
733cf014 V |
318 | } |
319 | ||
1013fc41 QN |
320 | irq_domain_remove(priv->irq_domain); |
321 | ||
0f4630f3 | 322 | return 0; |
b2b35e10 V |
323 | } |
324 | ||
325 | static const struct of_device_id xgene_gpio_sb_of_match[] = { | |
326 | {.compatible = "apm,xgene-gpio-sb", }, | |
327 | {}, | |
328 | }; | |
329 | MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match); | |
330 | ||
733cf014 V |
331 | #ifdef CONFIG_ACPI |
332 | static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = { | |
333 | {"APMC0D15", 0}, | |
334 | {}, | |
335 | }; | |
336 | MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match); | |
337 | #endif | |
338 | ||
b2b35e10 V |
339 | static struct platform_driver xgene_gpio_sb_driver = { |
340 | .driver = { | |
341 | .name = "xgene-gpio-sb", | |
342 | .of_match_table = xgene_gpio_sb_of_match, | |
733cf014 | 343 | .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match), |
b2b35e10 V |
344 | }, |
345 | .probe = xgene_gpio_sb_probe, | |
346 | .remove = xgene_gpio_sb_remove, | |
347 | }; | |
348 | module_platform_driver(xgene_gpio_sb_driver); | |
349 | ||
350 | MODULE_AUTHOR("AppliedMicro"); | |
351 | MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver"); | |
352 | MODULE_LICENSE("GPL"); |