[linux-block.git] / drivers / gpio / gpio-ws16c48.c

/*
 * GPIO driver for the WinSystems WS16C48
 * Copyright (C) 2016 William Breathitt Gray
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define WS16C48_EXTENT 16
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)

static unsigned int base[MAX_NUM_WS16C48];
static unsigned int num_ws16c48;
module_param_array(base, uint, &num_ws16c48, 0);
MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");

static unsigned int irq[MAX_NUM_WS16C48];
module_param_array(irq, uint, NULL, 0);
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");

/**
 * struct ws16c48_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @io_state:	bit I/O state (whether bit is set to input or output)
 * @out_state:	output bits state
 * @lock:	synchronization lock to prevent I/O race conditions
 * @irq_mask:	I/O bits affected by interrupts
 * @flow_mask:	IRQ flow type mask for the respective I/O bits
 * @base:	base port address of the GPIO device
 * @irq:	Interrupt line number
 */
struct ws16c48_gpio {
	struct gpio_chip chip;
	unsigned char io_state[6];
	unsigned char out_state[6];
	spinlock_t lock;
	unsigned long irq_mask;
	unsigned long flow_mask;
	unsigned base;
	unsigned irq;
};

static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);

	return !!(ws16c48gpio->io_state[port] & mask);
}

static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] |= mask;
	ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] &= ~mask;
	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for input */
	if (!(ws16c48gpio->io_state[port] & mask)) {
		spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	port_state = inb(ws16c48gpio->base + port);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return !!(port_state & mask);
}

static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for output */
	if (ws16c48gpio->io_state[port] & mask) {
		spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return;
	}

	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	unsigned int i;
	const unsigned int gpio_reg_size = 8;
	unsigned int port;
	unsigned int iomask;
	unsigned int bitmask;
	unsigned long flags;

	/* set bits are evaluated a gpio register size at a time */
	for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
		/* no more set bits in this mask word; skip to the next word */
		if (!mask[BIT_WORD(i)]) {
			i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
			continue;
		}

		port = i / gpio_reg_size;

		/* mask out GPIO configured for input */
		iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
		bitmask = iomask & bits[BIT_WORD(i)];

		spin_lock_irqsave(&ws16c48gpio->lock, flags);

		/* update output state data and set device gpio register */
		ws16c48gpio->out_state[port] &= ~iomask;
		ws16c48gpio->out_state[port] |= bitmask;
		outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);

		spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

		/* prepare for next gpio register set */
		mask[BIT_WORD(i)] >>= gpio_reg_size;
		bits[BIT_WORD(i)] >>= gpio_reg_size;
	}
}

static void ws16c48_irq_ack(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	port_state = ws16c48gpio->irq_mask >> (8*port);

	outb(0x80, ws16c48gpio->base + 7);
	outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
	outb(port_state | mask, ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->irq_mask &= ~mask;

	outb(0x80, ws16c48gpio->base + 7);
	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->irq_mask |= mask;

	outb(0x80, ws16c48gpio->base + 7);
	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return -EINVAL;

	spin_lock_irqsave(&ws16c48gpio->lock, flags);

	switch (flow_type) {
	case IRQ_TYPE_NONE:
		break;
	case IRQ_TYPE_EDGE_RISING:
		ws16c48gpio->flow_mask |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		ws16c48gpio->flow_mask &= ~mask;
		break;
	default:
		spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	outb(0x40, ws16c48gpio->base + 7);
	outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
	outb(0xC0, ws16c48gpio->base + 7);

	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static struct irq_chip ws16c48_irqchip = {
	.name = "ws16c48",
	.irq_ack = ws16c48_irq_ack,
	.irq_mask = ws16c48_irq_mask,
	.irq_unmask = ws16c48_irq_unmask,
	.irq_set_type = ws16c48_irq_set_type
};

static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
{
	struct ws16c48_gpio *const ws16c48gpio = dev_id;
	struct gpio_chip *const chip = &ws16c48gpio->chip;
	unsigned long int_pending;
	unsigned long port;
	unsigned long int_id;
	unsigned long gpio;

	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	if (!int_pending)
		return IRQ_NONE;

	/* loop until all pending interrupts are handled */
	do {
		for_each_set_bit(port, &int_pending, 3) {
			int_id = inb(ws16c48gpio->base + 8 + port);
			for_each_set_bit(gpio, &int_id, 8)
				generic_handle_irq(irq_find_mapping(
					chip->irqdomain, gpio + 8*port));
		}

		int_pending = inb(ws16c48gpio->base + 6) & 0x7;
	} while (int_pending);

	return IRQ_HANDLED;
}

static int ws16c48_probe(struct device *dev, unsigned int id)
{
	struct ws16c48_gpio *ws16c48gpio;
	const char *const name = dev_name(dev);
	int err;

	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	if (!ws16c48gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + WS16C48_EXTENT);
		return -EBUSY;
	}

	ws16c48gpio->chip.label = name;
	ws16c48gpio->chip.parent = dev;
	ws16c48gpio->chip.owner = THIS_MODULE;
	ws16c48gpio->chip.base = -1;
	ws16c48gpio->chip.ngpio = 48;
	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	ws16c48gpio->chip.get = ws16c48_gpio_get;
	ws16c48gpio->chip.set = ws16c48_gpio_set;
	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
	ws16c48gpio->base = base[id];
	ws16c48gpio->irq = irq[id];

	spin_lock_init(&ws16c48gpio->lock);

	dev_set_drvdata(dev, ws16c48gpio);

	err = gpiochip_add_data(&ws16c48gpio->chip, ws16c48gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	/* Disable IRQ by default */
	outb(0x80, base[id] + 7);
	outb(0, base[id] + 8);
	outb(0, base[id] + 9);
	outb(0, base[id] + 10);
	outb(0xC0, base[id] + 7);

	err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
		handle_edge_irq, IRQ_TYPE_NONE);
	if (err) {
		dev_err(dev, "Could not add irqchip (%d)\n", err);
		goto err_gpiochip_remove;
	}

	err = request_irq(irq[id], ws16c48_irq_handler, IRQF_SHARED, name,
		ws16c48gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		goto err_gpiochip_remove;
	}

	return 0;

err_gpiochip_remove:
	gpiochip_remove(&ws16c48gpio->chip);
	return err;
}

static int ws16c48_remove(struct device *dev, unsigned int id)
{
	struct ws16c48_gpio *const ws16c48gpio = dev_get_drvdata(dev);

	free_irq(ws16c48gpio->irq, ws16c48gpio);
	gpiochip_remove(&ws16c48gpio->chip);

	return 0;
}

static struct isa_driver ws16c48_driver = {
	.probe = ws16c48_probe,
	.driver = {
		.name = "ws16c48"
	},
	.remove = ws16c48_remove
};

module_isa_driver(ws16c48_driver, num_ws16c48);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c26df9b WBG	1	/*
	2	* GPIO driver for the WinSystems WS16C48
	3	* Copyright (C) 2016 William Breathitt Gray
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License, version 2, as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* General Public License for more details.
	13	*/
	14	#include <linux/bitops.h>
	15	#include <linux/device.h>
	16	#include <linux/errno.h>
	17	#include <linux/gpio/driver.h>
	18	#include <linux/io.h>
	19	#include <linux/ioport.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irqdesc.h>
cc736607	22	#include <linux/isa.h>
9c26df9b WBG	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/moduleparam.h>
9c26df9b WBG	26	#include <linux/spinlock.h>
9c26df9b WBG	27
cc736607 WBG	28	#define WS16C48_EXTENT 16
	29	#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
	30
	31	static unsigned int base[MAX_NUM_WS16C48];
	32	static unsigned int num_ws16c48;
	33	module_param_array(base, uint, &num_ws16c48, 0);
	34	MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
	35
	36	static unsigned int irq[MAX_NUM_WS16C48];
	37	module_param_array(irq, uint, NULL, 0);
	38	MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
9c26df9b WBG	39
	40	/**
	41	* struct ws16c48_gpio - GPIO device private data structure
	42	* @chip: instance of the gpio_chip
	43	* @io_state: bit I/O state (whether bit is set to input or output)
	44	* @out_state: output bits state
	45	* @lock: synchronization lock to prevent I/O race conditions
	46	* @irq_mask: I/O bits affected by interrupts
	47	* @flow_mask: IRQ flow type mask for the respective I/O bits
	48	* @base: base port address of the GPIO device
9c26df9b WBG	49	* @irq: Interrupt line number
	50	*/
	51	struct ws16c48_gpio {
	52	struct gpio_chip chip;
	53	unsigned char io_state[6];
	54	unsigned char out_state[6];
	55	spinlock_t lock;
	56	unsigned long irq_mask;
	57	unsigned long flow_mask;
	58	unsigned base;
9c26df9b WBG	59	unsigned irq;
	60	};
	61
	62	static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	63	{
	64	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	65	const unsigned port = offset / 8;
	66	const unsigned mask = BIT(offset % 8);
	67
	68	return !!(ws16c48gpio->io_state[port] & mask);
	69	}
	70
	71	static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	72	{
	73	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	74	const unsigned port = offset / 8;
	75	const unsigned mask = BIT(offset % 8);
	76	unsigned long flags;
	77
	78	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	79
	80	ws16c48gpio->io_state[port] \|= mask;
	81	ws16c48gpio->out_state[port] &= ~mask;
	82	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	83
	84	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	85
	86	return 0;
	87	}
	88
	89	static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	90	unsigned offset, int value)
	91	{
	92	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	93	const unsigned port = offset / 8;
	94	const unsigned mask = BIT(offset % 8);
	95	unsigned long flags;
	96
	97	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	98
	99	ws16c48gpio->io_state[port] &= ~mask;
	100	if (value)
	101	ws16c48gpio->out_state[port] \|= mask;
	102	else
	103	ws16c48gpio->out_state[port] &= ~mask;
	104	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	105
	106	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	107
	108	return 0;
	109	}
	110
	111	static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
	112	{
	113	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	114	const unsigned port = offset / 8;
	115	const unsigned mask = BIT(offset % 8);
	116	unsigned long flags;
	117	unsigned port_state;
	118
	119	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	120
	121	/* ensure that GPIO is set for input */
	122	if (!(ws16c48gpio->io_state[port] & mask)) {
123	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
124	return -EINVAL;
125	}
126
127	port_state = inb(ws16c48gpio->base + port);
128
129	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
130
131	return !!(port_state & mask);
132	}
133
134	static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
135	{
136	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
137	const unsigned port = offset / 8;
138	const unsigned mask = BIT(offset % 8);
139	unsigned long flags;
140
141	spin_lock_irqsave(&ws16c48gpio->lock, flags);
142
143	/* ensure that GPIO is set for output */
144	if (ws16c48gpio->io_state[port] & mask) {
145	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
146	return;
147	}
148
149	if (value)
150	ws16c48gpio->out_state[port] \|= mask;
151	else
152	ws16c48gpio->out_state[port] &= ~mask;
153	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
154
155	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
156	}
157
99c8ac95 WBG	158	static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	159	unsigned long mask, unsigned long bits)
	160	{
	161	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	162	unsigned int i;
	163	const unsigned int gpio_reg_size = 8;
	164	unsigned int port;
	165	unsigned int iomask;
	166	unsigned int bitmask;
	167	unsigned long flags;
	168
	169	/* set bits are evaluated a gpio register size at a time */
	170	for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
	171	/* no more set bits in this mask word; skip to the next word */
	172	if (!mask[BIT_WORD(i)]) {
	173	i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
	174	continue;
	175	}
	176
	177	port = i / gpio_reg_size;
	178
	179	/* mask out GPIO configured for input */
	180	iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
	181	bitmask = iomask & bits[BIT_WORD(i)];
	182
	183	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	184
	185	/* update output state data and set device gpio register */
	186	ws16c48gpio->out_state[port] &= ~iomask;
	187	ws16c48gpio->out_state[port] \|= bitmask;
	188	outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
	189
	190	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	191
	192	/* prepare for next gpio register set */
	193	mask[BIT_WORD(i)] >>= gpio_reg_size;
	194	bits[BIT_WORD(i)] >>= gpio_reg_size;
	195	}
	196	}
	197
9c26df9b WBG	198	static void ws16c48_irq_ack(struct irq_data *data)
	199	{
	200	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	201	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	202	const unsigned long offset = irqd_to_hwirq(data);
	203	const unsigned port = offset / 8;
	204	const unsigned mask = BIT(offset % 8);
	205	unsigned long flags;
	206	unsigned port_state;
	207
	208	/* only the first 3 ports support interrupts */
	209	if (port > 2)
	210	return;
	211
	212	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	213
	214	port_state = ws16c48gpio->irq_mask >> (8*port);
	215
	216	outb(0x80, ws16c48gpio->base + 7);
	217	outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
	218	outb(port_state \| mask, ws16c48gpio->base + 8 + port);
	219	outb(0xC0, ws16c48gpio->base + 7);
	220
	221	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	222	}
	223
	224	static void ws16c48_irq_mask(struct irq_data *data)
	225	{
	226	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	227	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	228	const unsigned long offset = irqd_to_hwirq(data);
	229	const unsigned long mask = BIT(offset);
	230	const unsigned port = offset / 8;
	231	unsigned long flags;
	232
	233	/* only the first 3 ports support interrupts */
	234	if (port > 2)
	235	return;
	236
	237	spin_lock_irqsave(&ws16c48gpio->lock, flags);
	238
	239	ws16c48gpio->irq_mask &= ~mask;
	240
	241	outb(0x80, ws16c48gpio->base + 7);
	242	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
	243	outb(0xC0, ws16c48gpio->base + 7);
	244
	245	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	246	}
	247
	248	static void ws16c48_irq_unmask(struct irq_data *data)
	249	{
	250	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	251	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	252	const unsigned long offset = irqd_to_hwirq(data);
	253	const unsigned long mask = BIT(offset);
	254	const unsigned port = offset / 8;
	255	unsigned long flags;
	256
	257	/* only the first 3 ports support interrupts */
	258	if (port > 2)
	259	return;
	260
	261	spin_lock_irqsave(&ws16c48gpio->lock, flags);
262
263	ws16c48gpio->irq_mask \|= mask;
264
265	outb(0x80, ws16c48gpio->base + 7);
266	outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
267	outb(0xC0, ws16c48gpio->base + 7);
268
269	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
270	}
271
272	static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
273	{
274	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
275	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
276	const unsigned long offset = irqd_to_hwirq(data);
277	const unsigned long mask = BIT(offset);
278	const unsigned port = offset / 8;
279	unsigned long flags;
280
281	/* only the first 3 ports support interrupts */
282	if (port > 2)
283	return -EINVAL;
284
285	spin_lock_irqsave(&ws16c48gpio->lock, flags);
286
287	switch (flow_type) {
288	case IRQ_TYPE_NONE:
289	break;
290	case IRQ_TYPE_EDGE_RISING:
291	ws16c48gpio->flow_mask \|= mask;
292	break;
293	case IRQ_TYPE_EDGE_FALLING:
294	ws16c48gpio->flow_mask &= ~mask;
295	break;
296	default:
297	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
298	return -EINVAL;
299	}
300
301	outb(0x40, ws16c48gpio->base + 7);
302	outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
303	outb(0xC0, ws16c48gpio->base + 7);
304
305	spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
306
307	return 0;
308	}
309
310	static struct irq_chip ws16c48_irqchip = {
311	.name = "ws16c48",
312	.irq_ack = ws16c48_irq_ack,
313	.irq_mask = ws16c48_irq_mask,
314	.irq_unmask = ws16c48_irq_unmask,
315	.irq_set_type = ws16c48_irq_set_type
316	};
317
318	static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
319	{
320	struct ws16c48_gpio *const ws16c48gpio = dev_id;
321	struct gpio_chip *const chip = &ws16c48gpio->chip;
322	unsigned long int_pending;
323	unsigned long port;
324	unsigned long int_id;
325	unsigned long gpio;
326
327	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
328	if (!int_pending)
329	return IRQ_NONE;
330
331	/* loop until all pending interrupts are handled */
332	do {
333	for_each_set_bit(port, &int_pending, 3) {
334	int_id = inb(ws16c48gpio->base + 8 + port);
335	for_each_set_bit(gpio, &int_id, 8)
336	generic_handle_irq(irq_find_mapping(
337	chip->irqdomain, gpio + 8*port));
338	}
339
340	int_pending = inb(ws16c48gpio->base + 6) & 0x7;
341	} while (int_pending);
342
343	return IRQ_HANDLED;
344	}
345
cc736607	346	static int ws16c48_probe(struct device *dev, unsigned int id)
9c26df9b	347	{
9c26df9b	348	struct ws16c48_gpio *ws16c48gpio;
9c26df9b WBG	349	const char *const name = dev_name(dev);
9c26df9b WBG	350	int err;
9c26df9b WBG	351
	352	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	353	if (!ws16c48gpio)
	354	return -ENOMEM;
	355
cc736607	356	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
148ad68b	357	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
cc736607	358	base[id], base[id] + WS16C48_EXTENT);
148ad68b	359	return -EBUSY;
9c26df9b WBG	360	}
	361
	362	ws16c48gpio->chip.label = name;
	363	ws16c48gpio->chip.parent = dev;
	364	ws16c48gpio->chip.owner = THIS_MODULE;
	365	ws16c48gpio->chip.base = -1;
	366	ws16c48gpio->chip.ngpio = 48;
	367	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	368	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	369	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	370	ws16c48gpio->chip.get = ws16c48_gpio_get;
	371	ws16c48gpio->chip.set = ws16c48_gpio_set;
99c8ac95	372	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
cc736607 WBG	373	ws16c48gpio->base = base[id];
cc736607 WBG	374	ws16c48gpio->irq = irq[id];
9c26df9b WBG	375
	376	spin_lock_init(&ws16c48gpio->lock);
	377
	378	dev_set_drvdata(dev, ws16c48gpio);
	379
	380	err = gpiochip_add_data(&ws16c48gpio->chip, ws16c48gpio);
	381	if (err) {
	382	dev_err(dev, "GPIO registering failed (%d)\n", err);
148ad68b	383	return err;
9c26df9b WBG	384	}
	385
	386	/* Disable IRQ by default */
cc736607 WBG	387	outb(0x80, base[id] + 7);
	388	outb(0, base[id] + 8);
	389	outb(0, base[id] + 9);
	390	outb(0, base[id] + 10);
	391	outb(0xC0, base[id] + 7);
9c26df9b WBG	392
	393	err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
	394	handle_edge_irq, IRQ_TYPE_NONE);
	395	if (err) {
	396	dev_err(dev, "Could not add irqchip (%d)\n", err);
148ad68b	397	goto err_gpiochip_remove;
9c26df9b WBG	398	}
9c26df9b WBG	399
cc736607	400	err = request_irq(irq[id], ws16c48_irq_handler, IRQF_SHARED, name,
9c26df9b WBG	401	ws16c48gpio);
	402	if (err) {
	403	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
148ad68b	404	goto err_gpiochip_remove;
9c26df9b WBG	405	}
	406
	407	return 0;
	408
148ad68b	409	err_gpiochip_remove:
9c26df9b	410	gpiochip_remove(&ws16c48gpio->chip);
9c26df9b WBG	411	return err;
	412	}
	413
cc736607	414	static int ws16c48_remove(struct device *dev, unsigned int id)
9c26df9b	415	{
cc736607	416	struct ws16c48_gpio *const ws16c48gpio = dev_get_drvdata(dev);
9c26df9b WBG	417
	418	free_irq(ws16c48gpio->irq, ws16c48gpio);
	419	gpiochip_remove(&ws16c48gpio->chip);
9c26df9b WBG	420
	421	return 0;
	422	}
	423
cc736607 WBG	424	static struct isa_driver ws16c48_driver = {
cc736607 WBG	425	.probe = ws16c48_probe,
9c26df9b WBG	426	.driver = {
	427	.name = "ws16c48"
	428	},
	429	.remove = ws16c48_remove
	430	};
	431
cc736607	432	module_isa_driver(ws16c48_driver, num_ws16c48);
9c26df9b WBG	433
	434	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	435	MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
22aeddb5	436	MODULE_LICENSE("GPL v2");