[linux-block.git] / drivers / gpio / gpio-ws16c48.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO driver for the WinSystems WS16C48
 * Copyright (C) 2016 William Breathitt Gray
 */
#include <linux/bitmap.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqdesc.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#define WS16C48_EXTENT 10
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)

static unsigned int base[MAX_NUM_WS16C48];
static unsigned int num_ws16c48;
module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");

static unsigned int irq[MAX_NUM_WS16C48];
static unsigned int num_irq;
module_param_hw_array(irq, uint, irq, &num_irq, 0);
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");

/**
 * struct ws16c48_reg - device register structure
 * @port:		Port 0 through 5 I/O
 * @int_pending:	Interrupt Pending
 * @page_lock:		Register page (Bits 7-6) and I/O port lock (Bits 5-0)
 * @pol_enab_int_id:	Interrupt polarity, enable, and ID
 */
struct ws16c48_reg {
	u8 port[6];
	u8 int_pending;
	u8 page_lock;
	u8 pol_enab_int_id[3];
};

/**
 * struct ws16c48_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @io_state:	bit I/O state (whether bit is set to input or output)
 * @out_state:	output bits state
 * @lock:	synchronization lock to prevent I/O race conditions
 * @irq_mask:	I/O bits affected by interrupts
 * @flow_mask:	IRQ flow type mask for the respective I/O bits
 * @reg:	I/O address offset for the device registers
 */
struct ws16c48_gpio {
	struct gpio_chip chip;
	unsigned char io_state[6];
	unsigned char out_state[6];
	raw_spinlock_t lock;
	unsigned long irq_mask;
	unsigned long flow_mask;
	struct ws16c48_reg __iomem *reg;
};

static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);

	if (ws16c48gpio->io_state[port] & mask)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] |= mask;
	ws16c48gpio->out_state[port] &= ~mask;
	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->io_state[port] &= ~mask;
	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for input */
	if (!(ws16c48gpio->io_state[port] & mask)) {
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	port_state = ioread8(ws16c48gpio->reg->port + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return !!(port_state & mask);
}

static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	unsigned long offset;
	unsigned long gpio_mask;
	size_t index;
	u8 __iomem *port_addr;
	unsigned long port_state;

	/* clear bits array to a clean slate */
	bitmap_zero(bits, chip->ngpio);

	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
		index = offset / 8;
		port_addr = ws16c48gpio->reg->port + index;
		port_state = ioread8(port_addr) & gpio_mask;

		bitmap_set_value8(bits, port_state, offset);
	}

	return 0;
}

static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	/* ensure that GPIO is set for output */
	if (ws16c48gpio->io_state[port] & mask) {
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return;
	}

	if (value)
		ws16c48gpio->out_state[port] |= mask;
	else
		ws16c48gpio->out_state[port] &= ~mask;
	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	unsigned long offset;
	unsigned long gpio_mask;
	size_t index;
	u8 __iomem *port_addr;
	unsigned long bitmask;
	unsigned long flags;

	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
		index = offset / 8;
		port_addr = ws16c48gpio->reg->port + index;

		/* mask out GPIO configured for input */
		gpio_mask &= ~ws16c48gpio->io_state[index];
		bitmask = bitmap_get_value8(bits, offset) & gpio_mask;

		raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

		/* update output state data and set device gpio register */
		ws16c48gpio->out_state[index] &= ~gpio_mask;
		ws16c48gpio->out_state[index] |= bitmask;
		iowrite8(ws16c48gpio->out_state[index], port_addr);

		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
	}
}

static void ws16c48_irq_ack(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned port = offset / 8;
	const unsigned mask = BIT(offset % 8);
	unsigned long flags;
	unsigned port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	port_state = ws16c48gpio->irq_mask >> (8*port);

	/* Select Register Page 2; Unlock all I/O ports */
	iowrite8(0x80, &ws16c48gpio->reg->page_lock);

	/* Clear pending interrupt */
	iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
	iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);

	/* Select Register Page 3; Unlock all I/O ports */
	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;
	unsigned long port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	ws16c48gpio->irq_mask &= ~mask;
	gpiochip_disable_irq(chip, offset);
	port_state = ws16c48gpio->irq_mask >> (8 * port);

	/* Select Register Page 2; Unlock all I/O ports */
	iowrite8(0x80, &ws16c48gpio->reg->page_lock);

	/* Disable interrupt */
	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);

	/* Select Register Page 3; Unlock all I/O ports */
	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static void ws16c48_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;
	unsigned long port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	gpiochip_enable_irq(chip, offset);
	ws16c48gpio->irq_mask |= mask;
	port_state = ws16c48gpio->irq_mask >> (8 * port);

	/* Select Register Page 2; Unlock all I/O ports */
	iowrite8(0x80, &ws16c48gpio->reg->page_lock);

	/* Enable interrupt */
	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);

	/* Select Register Page 3; Unlock all I/O ports */
	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
}

static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	const unsigned long offset = irqd_to_hwirq(data);
	const unsigned long mask = BIT(offset);
	const unsigned port = offset / 8;
	unsigned long flags;
	unsigned long port_state;

	/* only the first 3 ports support interrupts */
	if (port > 2)
		return -EINVAL;

	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);

	switch (flow_type) {
	case IRQ_TYPE_NONE:
		break;
	case IRQ_TYPE_EDGE_RISING:
		ws16c48gpio->flow_mask |= mask;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		ws16c48gpio->flow_mask &= ~mask;
		break;
	default:
		raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
		return -EINVAL;
	}

	port_state = ws16c48gpio->flow_mask >> (8 * port);

	/* Select Register Page 1; Unlock all I/O ports */
	iowrite8(0x40, &ws16c48gpio->reg->page_lock);

	/* Set interrupt polarity */
	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);

	/* Select Register Page 3; Unlock all I/O ports */
	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);

	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);

	return 0;
}

static const struct irq_chip ws16c48_irqchip = {
	.name = "ws16c48",
	.irq_ack = ws16c48_irq_ack,
	.irq_mask = ws16c48_irq_mask,
	.irq_unmask = ws16c48_irq_unmask,
	.irq_set_type = ws16c48_irq_set_type,
	.flags = IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
{
	struct ws16c48_gpio *const ws16c48gpio = dev_id;
	struct gpio_chip *const chip = &ws16c48gpio->chip;
	struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
	unsigned long int_pending;
	unsigned long port;
	unsigned long int_id;
	unsigned long gpio;

	int_pending = ioread8(&reg->int_pending) & 0x7;
	if (!int_pending)
		return IRQ_NONE;

	/* loop until all pending interrupts are handled */
	do {
		for_each_set_bit(port, &int_pending, 3) {
			int_id = ioread8(reg->pol_enab_int_id + port);
			for_each_set_bit(gpio, &int_id, 8)
				generic_handle_domain_irq(chip->irq.domain,
							  gpio + 8*port);
		}

		int_pending = ioread8(&reg->int_pending) & 0x7;
	} while (int_pending);

	return IRQ_HANDLED;
}

#define WS16C48_NGPIO 48
static const char *ws16c48_names[WS16C48_NGPIO] = {
	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
};

static int ws16c48_irq_init_hw(struct gpio_chip *gc)
{
	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);

	/* Select Register Page 2; Unlock all I/O ports */
	iowrite8(0x80, &ws16c48gpio->reg->page_lock);

	/* Disable interrupts for all lines */
	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);

	/* Select Register Page 3; Unlock all I/O ports */
	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);

	return 0;
}

static int ws16c48_probe(struct device *dev, unsigned int id)
{
	struct ws16c48_gpio *ws16c48gpio;
	const char *const name = dev_name(dev);
	struct gpio_irq_chip *girq;
	int err;

	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	if (!ws16c48gpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + WS16C48_EXTENT);
		return -EBUSY;
	}

	ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
	if (!ws16c48gpio->reg)
		return -ENOMEM;

	ws16c48gpio->chip.label = name;
	ws16c48gpio->chip.parent = dev;
	ws16c48gpio->chip.owner = THIS_MODULE;
	ws16c48gpio->chip.base = -1;
	ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
	ws16c48gpio->chip.names = ws16c48_names;
	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	ws16c48gpio->chip.get = ws16c48_gpio_get;
	ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
	ws16c48gpio->chip.set = ws16c48_gpio_set;
	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;

	girq = &ws16c48gpio->chip.irq;
	gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;
	girq->init_hw = ws16c48_irq_init_hw;

	raw_spin_lock_init(&ws16c48gpio->lock);

	err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
		name, ws16c48gpio);
	if (err) {
		dev_err(dev, "IRQ handler registering failed (%d)\n", err);
		return err;
	}

	return 0;
}

static struct isa_driver ws16c48_driver = {
	.probe = ws16c48_probe,
	.driver = {
		.name = "ws16c48"
	},
};

module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
9c26df9b WBG	2	/*
	3	* GPIO driver for the WinSystems WS16C48
	4	* Copyright (C) 2016 William Breathitt Gray
9c26df9b	5	*/
a8ff510d	6	#include <linux/bitmap.h>
9c26df9b WBG	7	#include <linux/device.h>
	8	#include <linux/errno.h>
	9	#include <linux/gpio/driver.h>
	10	#include <linux/io.h>
	11	#include <linux/ioport.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/irqdesc.h>
cc736607	14	#include <linux/isa.h>
9c26df9b WBG	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
9c26df9b	18	#include <linux/spinlock.h>
2c05a0f2	19	#include <linux/types.h>
9c26df9b	20
2c05a0f2	21	#define WS16C48_EXTENT 10
cc736607 WBG	22	#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
	23
	24	static unsigned int base[MAX_NUM_WS16C48];
	25	static unsigned int num_ws16c48;
d759f906	26	module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
cc736607 WBG	27	MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
	28
	29	static unsigned int irq[MAX_NUM_WS16C48];
c95671a3 WBG	30	static unsigned int num_irq;
c95671a3 WBG	31	module_param_hw_array(irq, uint, irq, &num_irq, 0);
cc736607	32	MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
9c26df9b	33
2c05a0f2 WBG	34	/**
	35	* struct ws16c48_reg - device register structure
	36	* @port: Port 0 through 5 I/O
	37	* @int_pending: Interrupt Pending
	38	* @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
	39	* @pol_enab_int_id: Interrupt polarity, enable, and ID
	40	*/
	41	struct ws16c48_reg {
	42	u8 port[6];
	43	u8 int_pending;
	44	u8 page_lock;
	45	u8 pol_enab_int_id[3];
	46	};
	47
9c26df9b WBG	48	/**
	49	* struct ws16c48_gpio - GPIO device private data structure
	50	* @chip: instance of the gpio_chip
	51	* @io_state: bit I/O state (whether bit is set to input or output)
	52	* @out_state: output bits state
	53	* @lock: synchronization lock to prevent I/O race conditions
	54	* @irq_mask: I/O bits affected by interrupts
	55	* @flow_mask: IRQ flow type mask for the respective I/O bits
2c05a0f2	56	* @reg: I/O address offset for the device registers
9c26df9b WBG	57	*/
	58	struct ws16c48_gpio {
	59	struct gpio_chip chip;
	60	unsigned char io_state[6];
	61	unsigned char out_state[6];
a0a584f0	62	raw_spinlock_t lock;
9c26df9b WBG	63	unsigned long irq_mask;
9c26df9b WBG	64	unsigned long flow_mask;
2c05a0f2	65	struct ws16c48_reg __iomem *reg;
9c26df9b WBG	66	};
	67
	68	static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
	69	{
	70	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	71	const unsigned port = offset / 8;
	72	const unsigned mask = BIT(offset % 8);
	73
e42615ec MV	74	if (ws16c48gpio->io_state[port] & mask)
	75	return GPIO_LINE_DIRECTION_IN;
	76
	77	return GPIO_LINE_DIRECTION_OUT;
9c26df9b WBG	78	}
	79
	80	static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	81	{
	82	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	83	const unsigned port = offset / 8;
	84	const unsigned mask = BIT(offset % 8);
	85	unsigned long flags;
	86
a0a584f0	87	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	88
	89	ws16c48gpio->io_state[port] \|= mask;
	90	ws16c48gpio->out_state[port] &= ~mask;
2c05a0f2	91	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
9c26df9b	92
a0a584f0	93	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	94
	95	return 0;
	96	}
	97
	98	static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
	99	unsigned offset, int value)
	100	{
	101	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	102	const unsigned port = offset / 8;
	103	const unsigned mask = BIT(offset % 8);
	104	unsigned long flags;
	105
a0a584f0	106	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	107
	108	ws16c48gpio->io_state[port] &= ~mask;
	109	if (value)
	110	ws16c48gpio->out_state[port] \|= mask;
	111	else
	112	ws16c48gpio->out_state[port] &= ~mask;
2c05a0f2	113	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
9c26df9b	114
a0a584f0	115	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	116
	117	return 0;
	118	}
	119
	120	static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
	121	{
	122	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	123	const unsigned port = offset / 8;
	124	const unsigned mask = BIT(offset % 8);
	125	unsigned long flags;
	126	unsigned port_state;
	127
a0a584f0	128	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	129
	130	/* ensure that GPIO is set for input */
	131	if (!(ws16c48gpio->io_state[port] & mask)) {
a0a584f0	132	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	133	return -EINVAL;
	134	}
	135
2c05a0f2	136	port_state = ioread8(ws16c48gpio->reg->port + port);
9c26df9b	137
a0a584f0	138	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	139
	140	return !!(port_state & mask);
	141	}
	142
a8ff510d WBG	143	static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
	144	unsigned long mask, unsigned long bits)
	145	{
	146	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
acebb82f WBG	147	unsigned long offset;
acebb82f WBG	148	unsigned long gpio_mask;
2c05a0f2 WBG	149	size_t index;
2c05a0f2 WBG	150	u8 __iomem *port_addr;
a8ff510d WBG	151	unsigned long port_state;
	152
	153	/* clear bits array to a clean slate */
	154	bitmap_zero(bits, chip->ngpio);
	155
acebb82f	156	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
2c05a0f2 WBG	157	index = offset / 8;
2c05a0f2 WBG	158	port_addr = ws16c48gpio->reg->port + index;
5561a2b0	159	port_state = ioread8(port_addr) & gpio_mask;
a8ff510d	160
acebb82f	161	bitmap_set_value8(bits, port_state, offset);
a8ff510d WBG	162	}
	163
	164	return 0;
	165	}
	166
9c26df9b WBG	167	static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	168	{
	169	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	170	const unsigned port = offset / 8;
	171	const unsigned mask = BIT(offset % 8);
	172	unsigned long flags;
	173
a0a584f0	174	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	175
	176	/* ensure that GPIO is set for output */
	177	if (ws16c48gpio->io_state[port] & mask) {
a0a584f0	178	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	179	return;
	180	}
	181
	182	if (value)
	183	ws16c48gpio->out_state[port] \|= mask;
	184	else
	185	ws16c48gpio->out_state[port] &= ~mask;
2c05a0f2	186	iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
9c26df9b	187
a0a584f0	188	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	189	}
9c26df9b WBG	190
99c8ac95 WBG	191	static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
	192	unsigned long mask, unsigned long bits)
	193	{
	194	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
acebb82f WBG	195	unsigned long offset;
	196	unsigned long gpio_mask;
	197	size_t index;
2c05a0f2	198	u8 __iomem *port_addr;
acebb82f	199	unsigned long bitmask;
99c8ac95 WBG	200	unsigned long flags;
99c8ac95 WBG	201
acebb82f WBG	202	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
acebb82f WBG	203	index = offset / 8;
2c05a0f2	204	port_addr = ws16c48gpio->reg->port + index;
99c8ac95 WBG	205
99c8ac95 WBG	206	/* mask out GPIO configured for input */
acebb82f WBG	207	gpio_mask &= ~ws16c48gpio->io_state[index];
acebb82f WBG	208	bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
99c8ac95	209
a0a584f0	210	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
99c8ac95 WBG	211
99c8ac95 WBG	212	/* update output state data and set device gpio register */
acebb82f WBG	213	ws16c48gpio->out_state[index] &= ~gpio_mask;
acebb82f WBG	214	ws16c48gpio->out_state[index] \|= bitmask;
5561a2b0	215	iowrite8(ws16c48gpio->out_state[index], port_addr);
99c8ac95	216
a0a584f0	217	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
99c8ac95 WBG	218	}
	219	}
	220
9c26df9b WBG	221	static void ws16c48_irq_ack(struct irq_data *data)
	222	{
	223	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	224	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	225	const unsigned long offset = irqd_to_hwirq(data);
	226	const unsigned port = offset / 8;
	227	const unsigned mask = BIT(offset % 8);
	228	unsigned long flags;
	229	unsigned port_state;
	230
	231	/* only the first 3 ports support interrupts */
	232	if (port > 2)
	233	return;
	234
a0a584f0	235	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	236
	237	port_state = ws16c48gpio->irq_mask >> (8*port);
	238
2c05a0f2 WBG	239	/* Select Register Page 2; Unlock all I/O ports */
	240	iowrite8(0x80, &ws16c48gpio->reg->page_lock);
	241
	242	/* Clear pending interrupt */
	243	iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
	244	iowrite8(port_state \| mask, ws16c48gpio->reg->pol_enab_int_id + port);
	245
	246	/* Select Register Page 3; Unlock all I/O ports */
	247	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
9c26df9b	248
a0a584f0	249	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	250	}
	251
	252	static void ws16c48_irq_mask(struct irq_data *data)
	253	{
	254	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	255	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	256	const unsigned long offset = irqd_to_hwirq(data);
	257	const unsigned long mask = BIT(offset);
	258	const unsigned port = offset / 8;
	259	unsigned long flags;
2c05a0f2	260	unsigned long port_state;
9c26df9b WBG	261
	262	/* only the first 3 ports support interrupts */
	263	if (port > 2)
	264	return;
	265
a0a584f0	266	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	267
9c26df9b WBG	268	ws16c48gpio->irq_mask &= ~mask;
68903817	269	gpiochip_disable_irq(chip, offset);
2c05a0f2 WBG	270	port_state = ws16c48gpio->irq_mask >> (8 * port);
	271
	272	/* Select Register Page 2; Unlock all I/O ports */
	273	iowrite8(0x80, &ws16c48gpio->reg->page_lock);
9c26df9b	274
2c05a0f2 WBG	275	/* Disable interrupt */
	276	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
	277
	278	/* Select Register Page 3; Unlock all I/O ports */
	279	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
9c26df9b	280
a0a584f0	281	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	282	}
	283
	284	static void ws16c48_irq_unmask(struct irq_data *data)
	285	{
	286	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	287	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	288	const unsigned long offset = irqd_to_hwirq(data);
	289	const unsigned long mask = BIT(offset);
	290	const unsigned port = offset / 8;
	291	unsigned long flags;
2c05a0f2	292	unsigned long port_state;
9c26df9b WBG	293
	294	/* only the first 3 ports support interrupts */
	295	if (port > 2)
	296	return;
	297
a0a584f0	298	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b	299
68903817	300	gpiochip_enable_irq(chip, offset);
9c26df9b	301	ws16c48gpio->irq_mask \|= mask;
2c05a0f2 WBG	302	port_state = ws16c48gpio->irq_mask >> (8 * port);
	303
	304	/* Select Register Page 2; Unlock all I/O ports */
	305	iowrite8(0x80, &ws16c48gpio->reg->page_lock);
9c26df9b	306
2c05a0f2 WBG	307	/* Enable interrupt */
	308	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
	309
	310	/* Select Register Page 3; Unlock all I/O ports */
	311	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
9c26df9b	312
a0a584f0	313	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	314	}
	315
	316	static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
	317	{
	318	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	319	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
	320	const unsigned long offset = irqd_to_hwirq(data);
	321	const unsigned long mask = BIT(offset);
	322	const unsigned port = offset / 8;
	323	unsigned long flags;
2c05a0f2	324	unsigned long port_state;
9c26df9b WBG	325
	326	/* only the first 3 ports support interrupts */
	327	if (port > 2)
	328	return -EINVAL;
	329
a0a584f0	330	raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
9c26df9b WBG	331
	332	switch (flow_type) {
	333	case IRQ_TYPE_NONE:
	334	break;
	335	case IRQ_TYPE_EDGE_RISING:
	336	ws16c48gpio->flow_mask \|= mask;
	337	break;
	338	case IRQ_TYPE_EDGE_FALLING:
	339	ws16c48gpio->flow_mask &= ~mask;
	340	break;
	341	default:
a0a584f0	342	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	343	return -EINVAL;
	344	}
	345
2c05a0f2 WBG	346	port_state = ws16c48gpio->flow_mask >> (8 * port);
	347
	348	/* Select Register Page 1; Unlock all I/O ports */
	349	iowrite8(0x40, &ws16c48gpio->reg->page_lock);
	350
	351	/* Set interrupt polarity */
	352	iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
	353
	354	/* Select Register Page 3; Unlock all I/O ports */
	355	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
9c26df9b	356
a0a584f0	357	raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
9c26df9b WBG	358
	359	return 0;
	360	}
	361
68903817	362	static const struct irq_chip ws16c48_irqchip = {
9c26df9b WBG	363	.name = "ws16c48",
	364	.irq_ack = ws16c48_irq_ack,
	365	.irq_mask = ws16c48_irq_mask,
	366	.irq_unmask = ws16c48_irq_unmask,
68903817 WBG	367	.irq_set_type = ws16c48_irq_set_type,
	368	.flags = IRQCHIP_IMMUTABLE,
	369	GPIOCHIP_IRQ_RESOURCE_HELPERS,
9c26df9b WBG	370	};
	371
	372	static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
	373	{
	374	struct ws16c48_gpio *const ws16c48gpio = dev_id;
	375	struct gpio_chip *const chip = &ws16c48gpio->chip;
2c05a0f2	376	struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
9c26df9b WBG	377	unsigned long int_pending;
	378	unsigned long port;
	379	unsigned long int_id;
	380	unsigned long gpio;
	381
2c05a0f2	382	int_pending = ioread8(&reg->int_pending) & 0x7;
9c26df9b WBG	383	if (!int_pending)
	384	return IRQ_NONE;
	385
	386	/* loop until all pending interrupts are handled */
	387	do {
	388	for_each_set_bit(port, &int_pending, 3) {
2c05a0f2	389	int_id = ioread8(reg->pol_enab_int_id + port);
9c26df9b	390	for_each_set_bit(gpio, &int_id, 8)
dbd1c54f MZ	391	generic_handle_domain_irq(chip->irq.domain,
dbd1c54f MZ	392	gpio + 8*port);
9c26df9b WBG	393	}
9c26df9b WBG	394
2c05a0f2	395	int_pending = ioread8(&reg->int_pending) & 0x7;
9c26df9b WBG	396	} while (int_pending);
	397
	398	return IRQ_HANDLED;
	399	}
	400
5238f60f WBG	401	#define WS16C48_NGPIO 48
	402	static const char *ws16c48_names[WS16C48_NGPIO] = {
	403	"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
	404	"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
	405	"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
	406	"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
	407	"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
	408	"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
	409	"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
	410	"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
	411	"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
	412	"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
	413	"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
	414	"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
	415	};
	416
fceb7ab3 LW	417	static int ws16c48_irq_init_hw(struct gpio_chip *gc)
	418	{
	419	struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
	420
2c05a0f2 WBG	421	/* Select Register Page 2; Unlock all I/O ports */
	422	iowrite8(0x80, &ws16c48gpio->reg->page_lock);
	423
	424	/* Disable interrupts for all lines */
	425	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
	426	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
	427	iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
	428
	429	/* Select Register Page 3; Unlock all I/O ports */
	430	iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
fceb7ab3 LW	431
	432	return 0;
	433	}
	434
cc736607	435	static int ws16c48_probe(struct device *dev, unsigned int id)
9c26df9b	436	{
9c26df9b	437	struct ws16c48_gpio *ws16c48gpio;
9c26df9b	438	const char *const name = dev_name(dev);
fceb7ab3	439	struct gpio_irq_chip *girq;
9c26df9b	440	int err;
9c26df9b WBG	441
	442	ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
	443	if (!ws16c48gpio)
	444	return -ENOMEM;
	445
cc736607	446	if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
148ad68b	447	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
cc736607	448	base[id], base[id] + WS16C48_EXTENT);
148ad68b	449	return -EBUSY;
9c26df9b WBG	450	}
9c26df9b WBG	451
2c05a0f2 WBG	452	ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
2c05a0f2 WBG	453	if (!ws16c48gpio->reg)
5561a2b0 WBG	454	return -ENOMEM;
5561a2b0 WBG	455
9c26df9b WBG	456	ws16c48gpio->chip.label = name;
	457	ws16c48gpio->chip.parent = dev;
	458	ws16c48gpio->chip.owner = THIS_MODULE;
	459	ws16c48gpio->chip.base = -1;
5238f60f WBG	460	ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
5238f60f WBG	461	ws16c48gpio->chip.names = ws16c48_names;
9c26df9b WBG	462	ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
	463	ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
	464	ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
	465	ws16c48gpio->chip.get = ws16c48_gpio_get;
a8ff510d	466	ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
9c26df9b	467	ws16c48gpio->chip.set = ws16c48_gpio_set;
99c8ac95	468	ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
9c26df9b	469
fceb7ab3	470	girq = &ws16c48gpio->chip.irq;
68903817	471	gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
fceb7ab3 LW	472	/* This will let us handle the parent IRQ in the driver */
	473	girq->parent_handler = NULL;
	474	girq->num_parents = 0;
	475	girq->parents = NULL;
	476	girq->default_type = IRQ_TYPE_NONE;
	477	girq->handler = handle_edge_irq;
	478	girq->init_hw = ws16c48_irq_init_hw;
	479
a0a584f0	480	raw_spin_lock_init(&ws16c48gpio->lock);
9c26df9b	481
b4cad1bc	482	err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
9c26df9b WBG	483	if (err) {
9c26df9b WBG	484	dev_err(dev, "GPIO registering failed (%d)\n", err);
148ad68b	485	return err;
9c26df9b WBG	486	}
9c26df9b WBG	487
b4cad1bc WBG	488	err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
b4cad1bc WBG	489	name, ws16c48gpio);
9c26df9b WBG	490	if (err) {
9c26df9b WBG	491	dev_err(dev, "IRQ handler registering failed (%d)\n", err);
b4cad1bc	492	return err;
9c26df9b WBG	493	}
9c26df9b WBG	494
9c26df9b WBG	495	return 0;
	496	}
	497
cc736607 WBG	498	static struct isa_driver ws16c48_driver = {
cc736607 WBG	499	.probe = ws16c48_probe,
9c26df9b WBG	500	.driver = {
	501	.name = "ws16c48"
	502	},
9c26df9b WBG	503	};
9c26df9b WBG	504
c95671a3	505	module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
9c26df9b WBG	506
	507	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	508	MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
22aeddb5	509	MODULE_LICENSE("GPL v2");