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0ba19cfc BG |
1 | /* |
2 | * Intel Whiskey Cove PMIC GPIO Driver | |
3 | * | |
4 | * This driver is written based on gpio-crystalcove.c | |
5 | * | |
6 | * Copyright (C) 2016 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License version | |
10 | * 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/bitops.h> | |
39d80072 | 19 | #include <linux/module.h> |
0ba19cfc BG |
20 | #include <linux/interrupt.h> |
21 | #include <linux/gpio/driver.h> | |
22 | #include <linux/mfd/intel_soc_pmic.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
25 | #include <linux/seq_file.h> | |
26 | ||
27 | /* | |
28 | * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: | |
29 | * Bank 0: Pin 0 - 6 | |
30 | * Bank 1: Pin 7 - 10 | |
31 | * Bank 2: Pin 11 -12 | |
32 | * Each pin has one output control register and one input control register. | |
33 | */ | |
34 | #define BANK0_NR_PINS 7 | |
35 | #define BANK1_NR_PINS 4 | |
36 | #define BANK2_NR_PINS 2 | |
37 | #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) | |
38 | #define WCOVE_VGPIO_NUM 94 | |
39 | /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ | |
40 | #define GPIO_OUT_CTRL_BASE 0x4e44 | |
41 | /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ | |
42 | #define GPIO_IN_CTRL_BASE 0x4e51 | |
43 | ||
44 | /* | |
45 | * GPIO interrupts are organized in two groups: | |
46 | * Group 0: Bank 0 pins (Pin 0 - 6) | |
47 | * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) | |
48 | * Each group has two registers (one bit per pin): status and mask. | |
49 | */ | |
50 | #define GROUP0_NR_IRQS 7 | |
51 | #define GROUP1_NR_IRQS 6 | |
52 | #define IRQ_MASK_BASE 0x4e19 | |
53 | #define IRQ_STATUS_BASE 0x4e0b | |
54 | #define UPDATE_IRQ_TYPE BIT(0) | |
55 | #define UPDATE_IRQ_MASK BIT(1) | |
56 | ||
57 | #define CTLI_INTCNT_DIS (0 << 1) | |
58 | #define CTLI_INTCNT_NE (1 << 1) | |
59 | #define CTLI_INTCNT_PE (2 << 1) | |
60 | #define CTLI_INTCNT_BE (3 << 1) | |
61 | ||
62 | #define CTLO_DIR_IN (0 << 5) | |
63 | #define CTLO_DIR_OUT (1 << 5) | |
64 | ||
65 | #define CTLO_DRV_MASK (1 << 4) | |
66 | #define CTLO_DRV_OD (0 << 4) | |
67 | #define CTLO_DRV_CMOS (1 << 4) | |
68 | ||
69 | #define CTLO_DRV_REN (1 << 3) | |
70 | ||
71 | #define CTLO_RVAL_2KDOWN (0 << 1) | |
72 | #define CTLO_RVAL_2KUP (1 << 1) | |
73 | #define CTLO_RVAL_50KDOWN (2 << 1) | |
74 | #define CTLO_RVAL_50KUP (3 << 1) | |
75 | ||
76 | #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) | |
77 | #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) | |
78 | ||
79 | enum ctrl_register { | |
80 | CTRL_IN, | |
81 | CTRL_OUT, | |
82 | }; | |
83 | ||
84 | /* | |
85 | * struct wcove_gpio - Whiskey Cove GPIO controller | |
86 | * @buslock: for bus lock/sync and unlock. | |
87 | * @chip: the abstract gpio_chip structure. | |
88 | * @dev: the gpio device | |
89 | * @regmap: the regmap from the parent device. | |
90 | * @regmap_irq_chip: the regmap of the gpio irq chip. | |
91 | * @update: pending IRQ setting update, to be written to the chip upon unlock. | |
92 | * @intcnt: the Interrupt Detect value to be written. | |
93 | * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. | |
94 | */ | |
95 | struct wcove_gpio { | |
96 | struct mutex buslock; | |
97 | struct gpio_chip chip; | |
98 | struct device *dev; | |
99 | struct regmap *regmap; | |
100 | struct regmap_irq_chip_data *regmap_irq_chip; | |
101 | int update; | |
102 | int intcnt; | |
103 | bool set_irq_mask; | |
104 | }; | |
105 | ||
106 | static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type) | |
107 | { | |
108 | unsigned int reg; | |
109 | int bank; | |
110 | ||
111 | if (gpio < BANK0_NR_PINS) | |
112 | bank = 0; | |
113 | else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS) | |
114 | bank = 1; | |
115 | else | |
116 | bank = 2; | |
117 | ||
118 | if (reg_type == CTRL_IN) | |
119 | reg = GPIO_IN_CTRL_BASE + bank; | |
120 | else | |
121 | reg = GPIO_OUT_CTRL_BASE + bank; | |
122 | ||
123 | return reg; | |
124 | } | |
125 | ||
126 | static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) | |
127 | { | |
128 | unsigned int reg, mask; | |
129 | ||
130 | if (gpio < GROUP0_NR_IRQS) { | |
131 | reg = IRQ_MASK_BASE; | |
132 | mask = BIT(gpio % GROUP0_NR_IRQS); | |
133 | } else { | |
134 | reg = IRQ_MASK_BASE + 1; | |
135 | mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); | |
136 | } | |
137 | ||
138 | if (wg->set_irq_mask) | |
139 | regmap_update_bits(wg->regmap, reg, mask, mask); | |
140 | else | |
141 | regmap_update_bits(wg->regmap, reg, mask, 0); | |
142 | } | |
143 | ||
144 | static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) | |
145 | { | |
146 | unsigned int reg = to_reg(gpio, CTRL_IN); | |
147 | ||
148 | regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); | |
149 | } | |
150 | ||
151 | static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) | |
152 | { | |
153 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
154 | ||
155 | return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT), | |
156 | CTLO_INPUT_SET); | |
157 | } | |
158 | ||
159 | static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, | |
160 | int value) | |
161 | { | |
162 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
163 | ||
164 | return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT), | |
165 | CTLO_OUTPUT_SET | value); | |
166 | } | |
167 | ||
7d9e59ce BG |
168 | static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) |
169 | { | |
170 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
171 | unsigned int val; | |
172 | int ret; | |
173 | ||
174 | ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &val); | |
175 | if (ret) | |
176 | return ret; | |
177 | ||
178 | return !(val & CTLO_DIR_OUT); | |
179 | } | |
180 | ||
0ba19cfc BG |
181 | static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) |
182 | { | |
183 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
184 | unsigned int val; | |
185 | int ret; | |
186 | ||
187 | ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val); | |
188 | if (ret) | |
189 | return ret; | |
190 | ||
191 | return val & 0x1; | |
192 | } | |
193 | ||
194 | static void wcove_gpio_set(struct gpio_chip *chip, | |
195 | unsigned int gpio, int value) | |
196 | { | |
197 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
198 | ||
199 | if (value) | |
200 | regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1); | |
201 | else | |
202 | regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0); | |
203 | } | |
204 | ||
205 | static int wcove_gpio_set_single_ended(struct gpio_chip *chip, | |
206 | unsigned int gpio, | |
207 | enum single_ended_mode mode) | |
208 | { | |
209 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
210 | ||
211 | switch (mode) { | |
212 | case LINE_MODE_OPEN_DRAIN: | |
213 | return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), | |
214 | CTLO_DRV_MASK, CTLO_DRV_OD); | |
215 | case LINE_MODE_PUSH_PULL: | |
216 | return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), | |
217 | CTLO_DRV_MASK, CTLO_DRV_CMOS); | |
218 | default: | |
219 | break; | |
220 | } | |
221 | ||
222 | return -ENOTSUPP; | |
223 | } | |
224 | ||
225 | static int wcove_irq_type(struct irq_data *data, unsigned int type) | |
226 | { | |
227 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
228 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
229 | ||
230 | switch (type) { | |
231 | case IRQ_TYPE_NONE: | |
232 | wg->intcnt = CTLI_INTCNT_DIS; | |
233 | break; | |
234 | case IRQ_TYPE_EDGE_BOTH: | |
235 | wg->intcnt = CTLI_INTCNT_BE; | |
236 | break; | |
237 | case IRQ_TYPE_EDGE_RISING: | |
238 | wg->intcnt = CTLI_INTCNT_PE; | |
239 | break; | |
240 | case IRQ_TYPE_EDGE_FALLING: | |
241 | wg->intcnt = CTLI_INTCNT_NE; | |
242 | break; | |
243 | default: | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | wg->update |= UPDATE_IRQ_TYPE; | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static void wcove_bus_lock(struct irq_data *data) | |
253 | { | |
254 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
255 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
256 | ||
257 | mutex_lock(&wg->buslock); | |
258 | } | |
259 | ||
260 | static void wcove_bus_sync_unlock(struct irq_data *data) | |
261 | { | |
262 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
263 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
264 | int gpio = data->hwirq; | |
265 | ||
266 | if (wg->update & UPDATE_IRQ_TYPE) | |
267 | wcove_update_irq_ctrl(wg, gpio); | |
268 | if (wg->update & UPDATE_IRQ_MASK) | |
269 | wcove_update_irq_mask(wg, gpio); | |
270 | wg->update = 0; | |
271 | ||
272 | mutex_unlock(&wg->buslock); | |
273 | } | |
274 | ||
275 | static void wcove_irq_unmask(struct irq_data *data) | |
276 | { | |
277 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
278 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
279 | ||
280 | wg->set_irq_mask = false; | |
281 | wg->update |= UPDATE_IRQ_MASK; | |
282 | } | |
283 | ||
284 | static void wcove_irq_mask(struct irq_data *data) | |
285 | { | |
286 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
287 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
288 | ||
289 | wg->set_irq_mask = true; | |
290 | wg->update |= UPDATE_IRQ_MASK; | |
291 | } | |
292 | ||
293 | static struct irq_chip wcove_irqchip = { | |
294 | .name = "Whiskey Cove", | |
295 | .irq_mask = wcove_irq_mask, | |
296 | .irq_unmask = wcove_irq_unmask, | |
297 | .irq_set_type = wcove_irq_type, | |
298 | .irq_bus_lock = wcove_bus_lock, | |
299 | .irq_bus_sync_unlock = wcove_bus_sync_unlock, | |
300 | }; | |
301 | ||
302 | static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) | |
303 | { | |
304 | struct wcove_gpio *wg = (struct wcove_gpio *)data; | |
305 | unsigned int pending, virq, gpio, mask, offset; | |
306 | u8 p[2]; | |
307 | ||
308 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
309 | dev_err(wg->dev, "Failed to read irq status register\n"); | |
310 | return IRQ_NONE; | |
311 | } | |
312 | ||
313 | pending = p[0] | (p[1] << 8); | |
314 | if (!pending) | |
315 | return IRQ_NONE; | |
316 | ||
317 | /* Iterate until no interrupt is pending */ | |
318 | while (pending) { | |
319 | /* One iteration is for all pending bits */ | |
320 | for_each_set_bit(gpio, (const unsigned long *)&pending, | |
321 | GROUP0_NR_IRQS) { | |
322 | offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0; | |
323 | mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : | |
324 | BIT(gpio); | |
325 | virq = irq_find_mapping(wg->chip.irqdomain, gpio); | |
326 | handle_nested_irq(virq); | |
327 | regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, | |
328 | mask, mask); | |
329 | } | |
330 | ||
331 | /* Next iteration */ | |
332 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
333 | dev_err(wg->dev, "Failed to read irq status\n"); | |
334 | break; | |
335 | } | |
336 | ||
337 | pending = p[0] | (p[1] << 8); | |
338 | } | |
339 | ||
340 | return IRQ_HANDLED; | |
341 | } | |
342 | ||
343 | static void wcove_gpio_dbg_show(struct seq_file *s, | |
344 | struct gpio_chip *chip) | |
345 | { | |
346 | unsigned int ctlo, ctli, irq_mask, irq_status; | |
347 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
348 | int gpio, offset, group, ret = 0; | |
349 | ||
350 | for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { | |
351 | group = gpio < GROUP0_NR_IRQS ? 0 : 1; | |
352 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); | |
353 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); | |
354 | ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, | |
355 | &irq_mask); | |
356 | ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, | |
357 | &irq_status); | |
358 | if (ret) { | |
359 | pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); | |
360 | break; | |
361 | } | |
362 | ||
363 | offset = gpio % 8; | |
364 | seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", | |
365 | gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", | |
366 | ctli & 0x1 ? "hi" : "lo", | |
367 | ctli & CTLI_INTCNT_NE ? "fall" : " ", | |
368 | ctli & CTLI_INTCNT_PE ? "rise" : " ", | |
369 | ctlo, | |
370 | irq_mask & BIT(offset) ? "mask " : "unmask", | |
371 | irq_status & BIT(offset) ? "pending" : " "); | |
372 | } | |
373 | } | |
374 | ||
375 | static int wcove_gpio_probe(struct platform_device *pdev) | |
376 | { | |
377 | struct intel_soc_pmic *pmic; | |
378 | struct wcove_gpio *wg; | |
379 | int virq, ret, irq; | |
380 | struct device *dev; | |
381 | ||
382 | /* | |
383 | * This gpio platform device is created by a mfd device (see | |
384 | * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information | |
385 | * shared by all sub-devices created by the mfd device, the regmap | |
386 | * pointer for instance, is stored as driver data of the mfd device | |
387 | * driver. | |
388 | */ | |
389 | pmic = dev_get_drvdata(pdev->dev.parent); | |
390 | if (!pmic) | |
391 | return -ENODEV; | |
392 | ||
393 | irq = platform_get_irq(pdev, 0); | |
394 | if (irq < 0) | |
395 | return irq; | |
396 | ||
397 | dev = &pdev->dev; | |
398 | ||
399 | wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); | |
400 | if (!wg) | |
401 | return -ENOMEM; | |
402 | ||
403 | wg->regmap_irq_chip = pmic->irq_chip_data_level2; | |
404 | ||
405 | platform_set_drvdata(pdev, wg); | |
406 | ||
407 | mutex_init(&wg->buslock); | |
408 | wg->chip.label = KBUILD_MODNAME; | |
409 | wg->chip.direction_input = wcove_gpio_dir_in; | |
410 | wg->chip.direction_output = wcove_gpio_dir_out; | |
7d9e59ce | 411 | wg->chip.get_direction = wcove_gpio_get_direction; |
0ba19cfc BG |
412 | wg->chip.get = wcove_gpio_get; |
413 | wg->chip.set = wcove_gpio_set; | |
414 | wg->chip.set_single_ended = wcove_gpio_set_single_ended, | |
415 | wg->chip.base = -1; | |
416 | wg->chip.ngpio = WCOVE_VGPIO_NUM; | |
417 | wg->chip.can_sleep = true; | |
418 | wg->chip.parent = pdev->dev.parent; | |
419 | wg->chip.dbg_show = wcove_gpio_dbg_show; | |
420 | wg->dev = dev; | |
421 | wg->regmap = pmic->regmap; | |
422 | ||
423 | ret = devm_gpiochip_add_data(dev, &wg->chip, wg); | |
424 | if (ret) { | |
425 | dev_err(dev, "Failed to add gpiochip: %d\n", ret); | |
426 | return ret; | |
427 | } | |
428 | ||
d245b3f9 LW |
429 | ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0, |
430 | handle_simple_irq, IRQ_TYPE_NONE); | |
0ba19cfc BG |
431 | if (ret) { |
432 | dev_err(dev, "Failed to add irqchip: %d\n", ret); | |
433 | return ret; | |
434 | } | |
435 | ||
436 | virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); | |
437 | if (virq < 0) { | |
438 | dev_err(dev, "Failed to get virq by irq %d\n", irq); | |
439 | return virq; | |
440 | } | |
441 | ||
442 | ret = devm_request_threaded_irq(dev, virq, NULL, | |
443 | wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg); | |
444 | if (ret) { | |
445 | dev_err(dev, "Failed to request irq %d\n", virq); | |
446 | return ret; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /* | |
453 | * Whiskey Cove PMIC itself is a analog device(but with digital control | |
454 | * interface) providing power management support for other devices in | |
455 | * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. | |
456 | */ | |
457 | static struct platform_driver wcove_gpio_driver = { | |
458 | .driver = { | |
459 | .name = "bxt_wcove_gpio", | |
460 | }, | |
461 | .probe = wcove_gpio_probe, | |
462 | }; | |
463 | ||
464 | module_platform_driver(wcove_gpio_driver); | |
465 | ||
466 | MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); | |
467 | MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); | |
468 | MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); | |
469 | MODULE_LICENSE("GPL v2"); | |
470 | MODULE_ALIAS("platform:bxt_wcove_gpio"); |