[linux-2.6-block.git] / drivers / gpio / gpio-wcove.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Whiskey Cove PMIC GPIO Driver
 *
 * This driver is written based on gpio-crystalcove.c
 *
 * Copyright (C) 2016 Intel Corporation. All rights reserved.
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>

/*
 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
 * Bank 0: Pin  0 - 6
 * Bank 1: Pin  7 - 10
 * Bank 2: Pin 11 - 12
 * Each pin has one output control register and one input control register.
 */
#define BANK0_NR_PINS		7
#define BANK1_NR_PINS		4
#define BANK2_NR_PINS		2
#define WCOVE_GPIO_NUM		(BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
#define WCOVE_VGPIO_NUM		94
/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
#define GPIO_OUT_CTRL_BASE	0x4e44
/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
#define GPIO_IN_CTRL_BASE	0x4e51

/*
 * GPIO interrupts are organized in two groups:
 * Group 0: Bank 0 pins (Pin 0 - 6)
 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
 * Each group has two registers (one bit per pin): status and mask.
 */
#define GROUP0_NR_IRQS		7
#define GROUP1_NR_IRQS		6
#define IRQ_MASK_BASE		0x4e19
#define IRQ_STATUS_BASE		0x4e0b
#define GPIO_IRQ0_MASK		GENMASK(6, 0)
#define GPIO_IRQ1_MASK		GENMASK(5, 0)
#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define CTLI_INTCNT_DIS		(0 << 1)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0 << 5)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_MASK		(1 << 4)
#define CTLO_DRV_OD		(0 << 4)
#define CTLO_DRV_CMOS		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDOWN	(0 << 1)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDOWN	(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET		(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET		(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/*
 * struct wcove_gpio - Whiskey Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @dev: the gpio device
 * @regmap: the regmap from the parent device.
 * @regmap_irq_chip: the regmap of the gpio irq chip.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct wcove_gpio {
	struct mutex buslock;
	struct gpio_chip chip;
	struct device *dev;
	struct regmap *regmap;
	struct regmap_irq_chip_data *regmap_irq_chip;
	int update;
	int intcnt;
	bool set_irq_mask;
};

static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
	unsigned int reg;

	if (gpio >= WCOVE_GPIO_NUM)
		return -EOPNOTSUPP;

	if (reg_type == CTRL_IN)
		reg = GPIO_IN_CTRL_BASE + gpio;
	else
		reg = GPIO_OUT_CTRL_BASE + gpio;

	return reg;
}

static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
{
	unsigned int reg, mask;

	if (gpio < GROUP0_NR_IRQS) {
		reg = IRQ_MASK_BASE;
		mask = BIT(gpio % GROUP0_NR_IRQS);
	} else {
		reg = IRQ_MASK_BASE + 1;
		mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
	}

	if (wg->set_irq_mask)
		regmap_update_bits(wg->regmap, reg, mask, mask);
	else
		regmap_update_bits(wg->regmap, reg, mask, 0);
}

static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return;

	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
}

static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
}

static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
				    int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
}

static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	return !(val & CTLO_DIR_OUT);
}

static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return 0;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return;

	if (value)
		regmap_update_bits(wg->regmap, reg, 1, 1);
	else
		regmap_update_bits(wg->regmap, reg, 1, 0);
}

static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
				 unsigned long config)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	switch (pinconf_to_config_param(config)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_OD);
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_CMOS);
	default:
		break;
	}

	return -ENOTSUPP;
}

static int wcove_irq_type(struct irq_data *data, unsigned int type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		wg->intcnt = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		wg->intcnt = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wg->intcnt = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wg->intcnt = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	wg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void wcove_bus_lock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	mutex_lock(&wg->buslock);
}

static void wcove_bus_sync_unlock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio = data->hwirq;

	if (wg->update & UPDATE_IRQ_TYPE)
		wcove_update_irq_ctrl(wg, gpio);
	if (wg->update & UPDATE_IRQ_MASK)
		wcove_update_irq_mask(wg, gpio);
	wg->update = 0;

	mutex_unlock(&wg->buslock);
}

static void wcove_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return;

	wg->set_irq_mask = false;
	wg->update |= UPDATE_IRQ_MASK;
}

static void wcove_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return;

	wg->set_irq_mask = true;
	wg->update |= UPDATE_IRQ_MASK;
}

static struct irq_chip wcove_irqchip = {
	.name			= "Whiskey Cove",
	.irq_mask		= wcove_irq_mask,
	.irq_unmask		= wcove_irq_unmask,
	.irq_set_type		= wcove_irq_type,
	.irq_bus_lock		= wcove_bus_lock,
	.irq_bus_sync_unlock	= wcove_bus_sync_unlock,
};

static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
{
	struct wcove_gpio *wg = (struct wcove_gpio *)data;
	unsigned int pending, virq, gpio, mask, offset;
	u8 p[2];

	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
		dev_err(wg->dev, "Failed to read irq status register\n");
		return IRQ_NONE;
	}

	pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	if (!pending)
		return IRQ_NONE;

	/* Iterate until no interrupt is pending */
	while (pending) {
		/* One iteration is for all pending bits */
		for_each_set_bit(gpio, (const unsigned long *)&pending,
						 WCOVE_GPIO_NUM) {
			offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
			mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
								BIT(gpio);
			virq = irq_find_mapping(wg->chip.irq.domain, gpio);
			handle_nested_irq(virq);
			regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
								mask, mask);
		}

		/* Next iteration */
		if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
			dev_err(wg->dev, "Failed to read irq status\n");
			break;
		}

		pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	}

	return IRQ_HANDLED;
}

static void wcove_gpio_dbg_show(struct seq_file *s,
				      struct gpio_chip *chip)
{
	unsigned int ctlo, ctli, irq_mask, irq_status;
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio, offset, group, ret = 0;

	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
		group = gpio < GROUP0_NR_IRQS ? 0 : 1;
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
							&irq_mask);
		ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
							&irq_status);
		if (ret) {
			pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
			break;
		}

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   irq_mask & BIT(offset) ? "mask  " : "unmask",
			   irq_status & BIT(offset) ? "pending" : "       ");
	}
}

static int wcove_gpio_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic;
	struct wcove_gpio *wg;
	int virq, ret, irq;
	struct device *dev;

	/*
	 * This gpio platform device is created by a mfd device (see
	 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	 * shared by all sub-devices created by the mfd device, the regmap
	 * pointer for instance, is stored as driver data of the mfd device
	 * driver.
	 */
	pmic = dev_get_drvdata(pdev->dev.parent);
	if (!pmic)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	dev = &pdev->dev;

	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	if (!wg)
		return -ENOMEM;

	wg->regmap_irq_chip = pmic->irq_chip_data;

	platform_set_drvdata(pdev, wg);

	mutex_init(&wg->buslock);
	wg->chip.label = KBUILD_MODNAME;
	wg->chip.direction_input = wcove_gpio_dir_in;
	wg->chip.direction_output = wcove_gpio_dir_out;
	wg->chip.get_direction = wcove_gpio_get_direction;
	wg->chip.get = wcove_gpio_get;
	wg->chip.set = wcove_gpio_set;
	wg->chip.set_config = wcove_gpio_set_config,
	wg->chip.base = -1;
	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	wg->chip.can_sleep = true;
	wg->chip.parent = pdev->dev.parent;
	wg->chip.dbg_show = wcove_gpio_dbg_show;
	wg->dev = dev;
	wg->regmap = pmic->regmap;

	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	if (ret) {
		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
		return ret;
	}

	ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
					  handle_simple_irq, IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "Failed to add irqchip: %d\n", ret);
		return ret;
	}

	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	if (virq < 0) {
		dev_err(dev, "Failed to get virq by irq %d\n", irq);
		return virq;
	}

	ret = devm_request_threaded_irq(dev, virq, NULL,
		wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	if (ret) {
		dev_err(dev, "Failed to request irq %d\n", virq);
		return ret;
	}

	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);

	/* Enable GPIO0 interrupts */
	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
				 0x00);
	if (ret)
		return ret;

	/* Enable GPIO1 interrupts */
	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
				 0x00);
	if (ret)
		return ret;

	return 0;
}

/*
 * Whiskey Cove PMIC itself is a analog device(but with digital control
 * interface) providing power management support for other devices in
 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 */
static struct platform_driver wcove_gpio_driver = {
	.driver = {
		.name = "bxt_wcove_gpio",
	},
	.probe = wcove_gpio_probe,
};

module_platform_driver(wcove_gpio_driver);

MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:bxt_wcove_gpio");
Commit	Line	Data
fd30b72e	1	// SPDX-License-Identifier: GPL-2.0
0ba19cfc BG	2	/*
	3	* Intel Whiskey Cove PMIC GPIO Driver
	4	*
	5	* This driver is written based on gpio-crystalcove.c
	6	*
	7	* Copyright (C) 2016 Intel Corporation. All rights reserved.
0ba19cfc BG	8	*/
	9
	10	#include <linux/bitops.h>
0ba19cfc	11	#include <linux/gpio/driver.h>
39684807	12	#include <linux/interrupt.h>
0ba19cfc	13	#include <linux/mfd/intel_soc_pmic.h>
39684807	14	#include <linux/module.h>
0ba19cfc BG	15	#include <linux/platform_device.h>
	16	#include <linux/regmap.h>
	17	#include <linux/seq_file.h>
	18
	19	/*
	20	* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
cb19c7f3 AS	21	* Bank 0: Pin 0 - 6
	22	* Bank 1: Pin 7 - 10
	23	* Bank 2: Pin 11 - 12
0ba19cfc BG	24	* Each pin has one output control register and one input control register.
	25	*/
	26	#define BANK0_NR_PINS 7
	27	#define BANK1_NR_PINS 4
	28	#define BANK2_NR_PINS 2
	29	#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
	30	#define WCOVE_VGPIO_NUM 94
	31	/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
	32	#define GPIO_OUT_CTRL_BASE 0x4e44
	33	/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
	34	#define GPIO_IN_CTRL_BASE 0x4e51
	35
	36	/*
	37	* GPIO interrupts are organized in two groups:
	38	* Group 0: Bank 0 pins (Pin 0 - 6)
	39	* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
	40	* Each group has two registers (one bit per pin): status and mask.
	41	*/
	42	#define GROUP0_NR_IRQS 7
	43	#define GROUP1_NR_IRQS 6
	44	#define IRQ_MASK_BASE 0x4e19
	45	#define IRQ_STATUS_BASE 0x4e0b
881ebd22 KS	46	#define GPIO_IRQ0_MASK GENMASK(6, 0)
881ebd22 KS	47	#define GPIO_IRQ1_MASK GENMASK(5, 0)
0ba19cfc BG	48	#define UPDATE_IRQ_TYPE BIT(0)
	49	#define UPDATE_IRQ_MASK BIT(1)
	50
	51	#define CTLI_INTCNT_DIS (0 << 1)
	52	#define CTLI_INTCNT_NE (1 << 1)
	53	#define CTLI_INTCNT_PE (2 << 1)
	54	#define CTLI_INTCNT_BE (3 << 1)
	55
	56	#define CTLO_DIR_IN (0 << 5)
	57	#define CTLO_DIR_OUT (1 << 5)
	58
	59	#define CTLO_DRV_MASK (1 << 4)
	60	#define CTLO_DRV_OD (0 << 4)
	61	#define CTLO_DRV_CMOS (1 << 4)
	62
	63	#define CTLO_DRV_REN (1 << 3)
	64
	65	#define CTLO_RVAL_2KDOWN (0 << 1)
	66	#define CTLO_RVAL_2KUP (1 << 1)
	67	#define CTLO_RVAL_50KDOWN (2 << 1)
	68	#define CTLO_RVAL_50KUP (3 << 1)
	69
cb19c7f3 AS	70	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
cb19c7f3 AS	71	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
0ba19cfc BG	72
	73	enum ctrl_register {
	74	CTRL_IN,
	75	CTRL_OUT,
	76	};
	77
	78	/*
	79	* struct wcove_gpio - Whiskey Cove GPIO controller
	80	* @buslock: for bus lock/sync and unlock.
	81	* @chip: the abstract gpio_chip structure.
	82	* @dev: the gpio device
	83	* @regmap: the regmap from the parent device.
	84	* @regmap_irq_chip: the regmap of the gpio irq chip.
	85	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	86	* @intcnt: the Interrupt Detect value to be written.
	87	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	88	*/
	89	struct wcove_gpio {
	90	struct mutex buslock;
	91	struct gpio_chip chip;
	92	struct device *dev;
	93	struct regmap *regmap;
	94	struct regmap_irq_chip_data *regmap_irq_chip;
	95	int update;
	96	int intcnt;
	97	bool set_irq_mask;
	98	};
	99
282db906	100	static inline int to_reg(int gpio, enum ctrl_register reg_type)
0ba19cfc BG	101	{
0ba19cfc BG	102	unsigned int reg;
0ba19cfc	103
3a02dc97 KS	104	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	105	return -EOPNOTSUPP;
0ba19cfc BG	106
0ba19cfc BG	107	if (reg_type == CTRL_IN)
3a02dc97	108	reg = GPIO_IN_CTRL_BASE + gpio;
0ba19cfc	109	else
3a02dc97	110	reg = GPIO_OUT_CTRL_BASE + gpio;
0ba19cfc BG	111
	112	return reg;
	113	}
	114
	115	static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
	116	{
	117	unsigned int reg, mask;
	118
	119	if (gpio < GROUP0_NR_IRQS) {
	120	reg = IRQ_MASK_BASE;
	121	mask = BIT(gpio % GROUP0_NR_IRQS);
	122	} else {
	123	reg = IRQ_MASK_BASE + 1;
	124	mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
	125	}
	126
	127	if (wg->set_irq_mask)
	128	regmap_update_bits(wg->regmap, reg, mask, mask);
	129	else
	130	regmap_update_bits(wg->regmap, reg, mask, 0);
	131	}
	132
	133	static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
	134	{
3a02dc97 KS	135	int reg = to_reg(gpio, CTRL_IN);
	136
	137	if (reg < 0)
	138	return;
0ba19cfc BG	139
	140	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
	141	}
	142
	143	static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
	144	{
	145	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	146	int reg = to_reg(gpio, CTRL_OUT);
	147
	148	if (reg < 0)
	149	return 0;
0ba19cfc	150
3a02dc97	151	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
0ba19cfc BG	152	}
	153
	154	static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
	155	int value)
	156	{
	157	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97	158	int reg = to_reg(gpio, CTRL_OUT);
0ba19cfc	159
3a02dc97 KS	160	if (reg < 0)
	161	return 0;
	162
	163	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET \| value);
0ba19cfc BG	164	}
0ba19cfc BG	165
7d9e59ce BG	166	static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
	167	{
	168	struct wcove_gpio *wg = gpiochip_get_data(chip);
	169	unsigned int val;
3a02dc97 KS	170	int ret, reg = to_reg(gpio, CTRL_OUT);
	171
	172	if (reg < 0)
	173	return 0;
7d9e59ce	174
3a02dc97	175	ret = regmap_read(wg->regmap, reg, &val);
7d9e59ce BG	176	if (ret)
	177	return ret;
	178
	179	return !(val & CTLO_DIR_OUT);
	180	}
	181
0ba19cfc BG	182	static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
	183	{
	184	struct wcove_gpio *wg = gpiochip_get_data(chip);
	185	unsigned int val;
3a02dc97 KS	186	int ret, reg = to_reg(gpio, CTRL_IN);
	187
	188	if (reg < 0)
	189	return 0;
0ba19cfc	190
3a02dc97	191	ret = regmap_read(wg->regmap, reg, &val);
0ba19cfc BG	192	if (ret)
	193	return ret;
	194
	195	return val & 0x1;
	196	}
	197
cb19c7f3	198	static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
0ba19cfc BG	199	{
0ba19cfc BG	200	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	201	int reg = to_reg(gpio, CTRL_OUT);
	202
	203	if (reg < 0)
	204	return;
0ba19cfc BG	205
0ba19cfc BG	206	if (value)
3a02dc97	207	regmap_update_bits(wg->regmap, reg, 1, 1);
0ba19cfc	208	else
3a02dc97	209	regmap_update_bits(wg->regmap, reg, 1, 0);
0ba19cfc BG	210	}
0ba19cfc BG	211
2956b5d9 MW	212	static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
2956b5d9 MW	213	unsigned long config)
0ba19cfc BG	214	{
0ba19cfc BG	215	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	216	int reg = to_reg(gpio, CTRL_OUT);
	217
	218	if (reg < 0)
	219	return 0;
0ba19cfc	220
2956b5d9 MW	221	switch (pinconf_to_config_param(config)) {
2956b5d9 MW	222	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
3a02dc97 KS	223	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	224	CTLO_DRV_OD);
2956b5d9	225	case PIN_CONFIG_DRIVE_PUSH_PULL:
3a02dc97 KS	226	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	227	CTLO_DRV_CMOS);
0ba19cfc BG	228	default:
	229	break;
	230	}
	231
	232	return -ENOTSUPP;
	233	}
	234
	235	static int wcove_irq_type(struct irq_data *data, unsigned int type)
	236	{
	237	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	238	struct wcove_gpio *wg = gpiochip_get_data(chip);
	239
3a02dc97 KS	240	if (data->hwirq >= WCOVE_GPIO_NUM)
	241	return 0;
	242
0ba19cfc BG	243	switch (type) {
	244	case IRQ_TYPE_NONE:
	245	wg->intcnt = CTLI_INTCNT_DIS;
	246	break;
	247	case IRQ_TYPE_EDGE_BOTH:
	248	wg->intcnt = CTLI_INTCNT_BE;
	249	break;
	250	case IRQ_TYPE_EDGE_RISING:
	251	wg->intcnt = CTLI_INTCNT_PE;
	252	break;
	253	case IRQ_TYPE_EDGE_FALLING:
	254	wg->intcnt = CTLI_INTCNT_NE;
	255	break;
	256	default:
	257	return -EINVAL;
	258	}
	259
	260	wg->update \|= UPDATE_IRQ_TYPE;
	261
	262	return 0;
	263	}
	264
	265	static void wcove_bus_lock(struct irq_data *data)
	266	{
	267	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	268	struct wcove_gpio *wg = gpiochip_get_data(chip);
	269
	270	mutex_lock(&wg->buslock);
	271	}
	272
	273	static void wcove_bus_sync_unlock(struct irq_data *data)
	274	{
	275	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	276	struct wcove_gpio *wg = gpiochip_get_data(chip);
	277	int gpio = data->hwirq;
	278
	279	if (wg->update & UPDATE_IRQ_TYPE)
	280	wcove_update_irq_ctrl(wg, gpio);
	281	if (wg->update & UPDATE_IRQ_MASK)
	282	wcove_update_irq_mask(wg, gpio);
	283	wg->update = 0;
	284
	285	mutex_unlock(&wg->buslock);
	286	}
	287
	288	static void wcove_irq_unmask(struct irq_data *data)
	289	{
	290	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	291	struct wcove_gpio *wg = gpiochip_get_data(chip);
	292
3a02dc97 KS	293	if (data->hwirq >= WCOVE_GPIO_NUM)
	294	return;
	295
0ba19cfc BG	296	wg->set_irq_mask = false;
	297	wg->update \|= UPDATE_IRQ_MASK;
	298	}
	299
	300	static void wcove_irq_mask(struct irq_data *data)
	301	{
	302	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	303	struct wcove_gpio *wg = gpiochip_get_data(chip);
	304
3a02dc97 KS	305	if (data->hwirq >= WCOVE_GPIO_NUM)
	306	return;
	307
0ba19cfc BG	308	wg->set_irq_mask = true;
	309	wg->update \|= UPDATE_IRQ_MASK;
	310	}
	311
	312	static struct irq_chip wcove_irqchip = {
	313	.name = "Whiskey Cove",
	314	.irq_mask = wcove_irq_mask,
	315	.irq_unmask = wcove_irq_unmask,
	316	.irq_set_type = wcove_irq_type,
	317	.irq_bus_lock = wcove_bus_lock,
	318	.irq_bus_sync_unlock = wcove_bus_sync_unlock,
	319	};
	320
	321	static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
	322	{
	323	struct wcove_gpio wg = (struct wcove_gpio )data;
	324	unsigned int pending, virq, gpio, mask, offset;
	325	u8 p[2];
	326
	327	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	328	dev_err(wg->dev, "Failed to read irq status register\n");
	329	return IRQ_NONE;
	330	}
	331
881ebd22	332	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	333	if (!pending)
	334	return IRQ_NONE;
	335
	336	/* Iterate until no interrupt is pending */
	337	while (pending) {
	338	/* One iteration is for all pending bits */
	339	for_each_set_bit(gpio, (const unsigned long *)&pending,
7c2d176f	340	WCOVE_GPIO_NUM) {
0ba19cfc BG	341	offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
	342	mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
	343	BIT(gpio);
f0fbe7bc	344	virq = irq_find_mapping(wg->chip.irq.domain, gpio);
0ba19cfc BG	345	handle_nested_irq(virq);
	346	regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
	347	mask, mask);
	348	}
	349
	350	/* Next iteration */
	351	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	352	dev_err(wg->dev, "Failed to read irq status\n");
	353	break;
	354	}
	355
881ebd22	356	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	357	}
	358
	359	return IRQ_HANDLED;
	360	}
	361
	362	static void wcove_gpio_dbg_show(struct seq_file *s,
	363	struct gpio_chip *chip)
	364	{
	365	unsigned int ctlo, ctli, irq_mask, irq_status;
	366	struct wcove_gpio *wg = gpiochip_get_data(chip);
	367	int gpio, offset, group, ret = 0;
	368
	369	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
	370	group = gpio < GROUP0_NR_IRQS ? 0 : 1;
	371	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
	372	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
	373	ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
	374	&irq_mask);
	375	ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
	376	&irq_status);
	377	if (ret) {
	378	pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
	379	break;
	380	}
	381
	382	offset = gpio % 8;
	383	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
	384	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	385	ctli & 0x1 ? "hi" : "lo",
	386	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	387	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	388	ctlo,
	389	irq_mask & BIT(offset) ? "mask " : "unmask",
	390	irq_status & BIT(offset) ? "pending" : " ");
	391	}
	392	}
	393
	394	static int wcove_gpio_probe(struct platform_device *pdev)
	395	{
	396	struct intel_soc_pmic *pmic;
	397	struct wcove_gpio *wg;
	398	int virq, ret, irq;
	399	struct device *dev;
	400
	401	/*
	402	* This gpio platform device is created by a mfd device (see
	403	* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	404	* shared by all sub-devices created by the mfd device, the regmap
	405	* pointer for instance, is stored as driver data of the mfd device
	406	* driver.
	407	*/
	408	pmic = dev_get_drvdata(pdev->dev.parent);
	409	if (!pmic)
	410	return -ENODEV;
	411
	412	irq = platform_get_irq(pdev, 0);
	413	if (irq < 0)
	414	return irq;
	415
	416	dev = &pdev->dev;
	417
	418	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	419	if (!wg)
	420	return -ENOMEM;
421
a1d28c59	422	wg->regmap_irq_chip = pmic->irq_chip_data;
0ba19cfc BG	423
	424	platform_set_drvdata(pdev, wg);
	425
	426	mutex_init(&wg->buslock);
	427	wg->chip.label = KBUILD_MODNAME;
	428	wg->chip.direction_input = wcove_gpio_dir_in;
	429	wg->chip.direction_output = wcove_gpio_dir_out;
7d9e59ce	430	wg->chip.get_direction = wcove_gpio_get_direction;
0ba19cfc BG	431	wg->chip.get = wcove_gpio_get;
0ba19cfc BG	432	wg->chip.set = wcove_gpio_set;
2956b5d9	433	wg->chip.set_config = wcove_gpio_set_config,
0ba19cfc BG	434	wg->chip.base = -1;
	435	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	436	wg->chip.can_sleep = true;
	437	wg->chip.parent = pdev->dev.parent;
	438	wg->chip.dbg_show = wcove_gpio_dbg_show;
	439	wg->dev = dev;
	440	wg->regmap = pmic->regmap;
	441
	442	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	443	if (ret) {
	444	dev_err(dev, "Failed to add gpiochip: %d\n", ret);
	445	return ret;
	446	}
	447
d245b3f9 LW	448	ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
d245b3f9 LW	449	handle_simple_irq, IRQ_TYPE_NONE);
0ba19cfc BG	450	if (ret) {
	451	dev_err(dev, "Failed to add irqchip: %d\n", ret);
	452	return ret;
	453	}
	454
	455	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	456	if (virq < 0) {
	457	dev_err(dev, "Failed to get virq by irq %d\n", irq);
	458	return virq;
	459	}
	460
	461	ret = devm_request_threaded_irq(dev, virq, NULL,
	462	wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	463	if (ret) {
	464	dev_err(dev, "Failed to request irq %d\n", virq);
	465	return ret;
	466	}
	467
35ca3f61 LW	468	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
35ca3f61 LW	469
a1d28c59 KS	470	/* Enable GPIO0 interrupts */
	471	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
	472	0x00);
	473	if (ret)
	474	return ret;
	475
	476	/* Enable GPIO1 interrupts */
	477	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
	478	0x00);
	479	if (ret)
	480	return ret;
	481
0ba19cfc BG	482	return 0;
	483	}
	484
	485	/*
	486	* Whiskey Cove PMIC itself is a analog device(but with digital control
	487	* interface) providing power management support for other devices in
	488	* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
	489	*/
	490	static struct platform_driver wcove_gpio_driver = {
	491	.driver = {
	492	.name = "bxt_wcove_gpio",
	493	},
	494	.probe = wcove_gpio_probe,
	495	};
	496
	497	module_platform_driver(wcove_gpio_driver);
	498
	499	MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
	500	MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
	501	MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
	502	MODULE_LICENSE("GPL v2");
	503	MODULE_ALIAS("platform:bxt_wcove_gpio");