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fd30b72e | 1 | // SPDX-License-Identifier: GPL-2.0 |
0ba19cfc BG |
2 | /* |
3 | * Intel Whiskey Cove PMIC GPIO Driver | |
4 | * | |
5 | * This driver is written based on gpio-crystalcove.c | |
6 | * | |
7 | * Copyright (C) 2016 Intel Corporation. All rights reserved. | |
0ba19cfc BG |
8 | */ |
9 | ||
10 | #include <linux/bitops.h> | |
0ba19cfc | 11 | #include <linux/gpio/driver.h> |
39684807 | 12 | #include <linux/interrupt.h> |
0ba19cfc | 13 | #include <linux/mfd/intel_soc_pmic.h> |
39684807 | 14 | #include <linux/module.h> |
0ba19cfc BG |
15 | #include <linux/platform_device.h> |
16 | #include <linux/regmap.h> | |
17 | #include <linux/seq_file.h> | |
18 | ||
19 | /* | |
20 | * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: | |
cb19c7f3 AS |
21 | * Bank 0: Pin 0 - 6 |
22 | * Bank 1: Pin 7 - 10 | |
23 | * Bank 2: Pin 11 - 12 | |
0ba19cfc BG |
24 | * Each pin has one output control register and one input control register. |
25 | */ | |
26 | #define BANK0_NR_PINS 7 | |
27 | #define BANK1_NR_PINS 4 | |
28 | #define BANK2_NR_PINS 2 | |
29 | #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) | |
30 | #define WCOVE_VGPIO_NUM 94 | |
31 | /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ | |
32 | #define GPIO_OUT_CTRL_BASE 0x4e44 | |
33 | /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ | |
34 | #define GPIO_IN_CTRL_BASE 0x4e51 | |
35 | ||
36 | /* | |
37 | * GPIO interrupts are organized in two groups: | |
38 | * Group 0: Bank 0 pins (Pin 0 - 6) | |
39 | * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) | |
40 | * Each group has two registers (one bit per pin): status and mask. | |
41 | */ | |
42 | #define GROUP0_NR_IRQS 7 | |
43 | #define GROUP1_NR_IRQS 6 | |
44 | #define IRQ_MASK_BASE 0x4e19 | |
45 | #define IRQ_STATUS_BASE 0x4e0b | |
881ebd22 KS |
46 | #define GPIO_IRQ0_MASK GENMASK(6, 0) |
47 | #define GPIO_IRQ1_MASK GENMASK(5, 0) | |
0ba19cfc BG |
48 | #define UPDATE_IRQ_TYPE BIT(0) |
49 | #define UPDATE_IRQ_MASK BIT(1) | |
50 | ||
51 | #define CTLI_INTCNT_DIS (0 << 1) | |
52 | #define CTLI_INTCNT_NE (1 << 1) | |
53 | #define CTLI_INTCNT_PE (2 << 1) | |
54 | #define CTLI_INTCNT_BE (3 << 1) | |
55 | ||
56 | #define CTLO_DIR_IN (0 << 5) | |
57 | #define CTLO_DIR_OUT (1 << 5) | |
58 | ||
59 | #define CTLO_DRV_MASK (1 << 4) | |
60 | #define CTLO_DRV_OD (0 << 4) | |
61 | #define CTLO_DRV_CMOS (1 << 4) | |
62 | ||
63 | #define CTLO_DRV_REN (1 << 3) | |
64 | ||
65 | #define CTLO_RVAL_2KDOWN (0 << 1) | |
66 | #define CTLO_RVAL_2KUP (1 << 1) | |
67 | #define CTLO_RVAL_50KDOWN (2 << 1) | |
68 | #define CTLO_RVAL_50KUP (3 << 1) | |
69 | ||
cb19c7f3 AS |
70 | #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) |
71 | #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) | |
0ba19cfc BG |
72 | |
73 | enum ctrl_register { | |
74 | CTRL_IN, | |
75 | CTRL_OUT, | |
5a2a46ae AS |
76 | IRQ_STATUS, |
77 | IRQ_MASK, | |
0ba19cfc BG |
78 | }; |
79 | ||
80 | /* | |
81 | * struct wcove_gpio - Whiskey Cove GPIO controller | |
82 | * @buslock: for bus lock/sync and unlock. | |
83 | * @chip: the abstract gpio_chip structure. | |
84 | * @dev: the gpio device | |
85 | * @regmap: the regmap from the parent device. | |
86 | * @regmap_irq_chip: the regmap of the gpio irq chip. | |
87 | * @update: pending IRQ setting update, to be written to the chip upon unlock. | |
88 | * @intcnt: the Interrupt Detect value to be written. | |
89 | * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. | |
90 | */ | |
91 | struct wcove_gpio { | |
92 | struct mutex buslock; | |
93 | struct gpio_chip chip; | |
94 | struct device *dev; | |
95 | struct regmap *regmap; | |
96 | struct regmap_irq_chip_data *regmap_irq_chip; | |
97 | int update; | |
98 | int intcnt; | |
99 | bool set_irq_mask; | |
100 | }; | |
101 | ||
5d993664 | 102 | static inline int to_reg(int gpio, enum ctrl_register type) |
0ba19cfc | 103 | { |
5d993664 | 104 | unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE; |
0ba19cfc | 105 | |
3a02dc97 KS |
106 | if (gpio >= WCOVE_GPIO_NUM) |
107 | return -EOPNOTSUPP; | |
0ba19cfc | 108 | |
5d993664 | 109 | return reg + gpio; |
0ba19cfc BG |
110 | } |
111 | ||
5a2a46ae | 112 | static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask) |
0ba19cfc | 113 | { |
5a2a46ae | 114 | unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE; |
0ba19cfc BG |
115 | |
116 | if (gpio < GROUP0_NR_IRQS) { | |
5a2a46ae AS |
117 | reg += 0; |
118 | *mask = BIT(gpio); | |
0ba19cfc | 119 | } else { |
5a2a46ae AS |
120 | reg += 1; |
121 | *mask = BIT(gpio - GROUP0_NR_IRQS); | |
0ba19cfc BG |
122 | } |
123 | ||
5a2a46ae AS |
124 | return reg; |
125 | } | |
126 | ||
f3019092 | 127 | static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio) |
5a2a46ae AS |
128 | { |
129 | unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask); | |
130 | ||
0ba19cfc | 131 | if (wg->set_irq_mask) |
9fe5fcd6 | 132 | regmap_set_bits(wg->regmap, reg, mask); |
0ba19cfc | 133 | else |
9fe5fcd6 | 134 | regmap_clear_bits(wg->regmap, reg, mask); |
0ba19cfc BG |
135 | } |
136 | ||
f3019092 | 137 | static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio) |
0ba19cfc | 138 | { |
3a02dc97 KS |
139 | int reg = to_reg(gpio, CTRL_IN); |
140 | ||
0ba19cfc BG |
141 | regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); |
142 | } | |
143 | ||
144 | static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) | |
145 | { | |
146 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
3a02dc97 KS |
147 | int reg = to_reg(gpio, CTRL_OUT); |
148 | ||
149 | if (reg < 0) | |
150 | return 0; | |
0ba19cfc | 151 | |
3a02dc97 | 152 | return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); |
0ba19cfc BG |
153 | } |
154 | ||
155 | static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, | |
156 | int value) | |
157 | { | |
158 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
3a02dc97 | 159 | int reg = to_reg(gpio, CTRL_OUT); |
0ba19cfc | 160 | |
3a02dc97 KS |
161 | if (reg < 0) |
162 | return 0; | |
163 | ||
164 | return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); | |
0ba19cfc BG |
165 | } |
166 | ||
7d9e59ce BG |
167 | static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) |
168 | { | |
169 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
170 | unsigned int val; | |
3a02dc97 KS |
171 | int ret, reg = to_reg(gpio, CTRL_OUT); |
172 | ||
173 | if (reg < 0) | |
e42615ec | 174 | return GPIO_LINE_DIRECTION_OUT; |
7d9e59ce | 175 | |
3a02dc97 | 176 | ret = regmap_read(wg->regmap, reg, &val); |
7d9e59ce BG |
177 | if (ret) |
178 | return ret; | |
179 | ||
e42615ec MV |
180 | if (val & CTLO_DIR_OUT) |
181 | return GPIO_LINE_DIRECTION_OUT; | |
182 | ||
183 | return GPIO_LINE_DIRECTION_IN; | |
7d9e59ce BG |
184 | } |
185 | ||
0ba19cfc BG |
186 | static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) |
187 | { | |
188 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
189 | unsigned int val; | |
3a02dc97 KS |
190 | int ret, reg = to_reg(gpio, CTRL_IN); |
191 | ||
192 | if (reg < 0) | |
193 | return 0; | |
0ba19cfc | 194 | |
3a02dc97 | 195 | ret = regmap_read(wg->regmap, reg, &val); |
0ba19cfc BG |
196 | if (ret) |
197 | return ret; | |
198 | ||
199 | return val & 0x1; | |
200 | } | |
201 | ||
cb19c7f3 | 202 | static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) |
0ba19cfc BG |
203 | { |
204 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
3a02dc97 KS |
205 | int reg = to_reg(gpio, CTRL_OUT); |
206 | ||
207 | if (reg < 0) | |
208 | return; | |
0ba19cfc BG |
209 | |
210 | if (value) | |
9fe5fcd6 | 211 | regmap_set_bits(wg->regmap, reg, 1); |
0ba19cfc | 212 | else |
9fe5fcd6 | 213 | regmap_clear_bits(wg->regmap, reg, 1); |
0ba19cfc BG |
214 | } |
215 | ||
2956b5d9 MW |
216 | static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, |
217 | unsigned long config) | |
0ba19cfc BG |
218 | { |
219 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
3a02dc97 KS |
220 | int reg = to_reg(gpio, CTRL_OUT); |
221 | ||
222 | if (reg < 0) | |
223 | return 0; | |
0ba19cfc | 224 | |
2956b5d9 MW |
225 | switch (pinconf_to_config_param(config)) { |
226 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
3a02dc97 KS |
227 | return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, |
228 | CTLO_DRV_OD); | |
2956b5d9 | 229 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
3a02dc97 KS |
230 | return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, |
231 | CTLO_DRV_CMOS); | |
0ba19cfc BG |
232 | default: |
233 | break; | |
234 | } | |
235 | ||
236 | return -ENOTSUPP; | |
237 | } | |
238 | ||
239 | static int wcove_irq_type(struct irq_data *data, unsigned int type) | |
240 | { | |
241 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
242 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
f3019092 | 243 | irq_hw_number_t gpio = irqd_to_hwirq(data); |
0ba19cfc | 244 | |
f3019092 | 245 | if (gpio >= WCOVE_GPIO_NUM) |
3a02dc97 KS |
246 | return 0; |
247 | ||
0ba19cfc BG |
248 | switch (type) { |
249 | case IRQ_TYPE_NONE: | |
250 | wg->intcnt = CTLI_INTCNT_DIS; | |
251 | break; | |
252 | case IRQ_TYPE_EDGE_BOTH: | |
253 | wg->intcnt = CTLI_INTCNT_BE; | |
254 | break; | |
255 | case IRQ_TYPE_EDGE_RISING: | |
256 | wg->intcnt = CTLI_INTCNT_PE; | |
257 | break; | |
258 | case IRQ_TYPE_EDGE_FALLING: | |
259 | wg->intcnt = CTLI_INTCNT_NE; | |
260 | break; | |
261 | default: | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
265 | wg->update |= UPDATE_IRQ_TYPE; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void wcove_bus_lock(struct irq_data *data) | |
271 | { | |
272 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
273 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
274 | ||
275 | mutex_lock(&wg->buslock); | |
276 | } | |
277 | ||
278 | static void wcove_bus_sync_unlock(struct irq_data *data) | |
279 | { | |
280 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
281 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
f3019092 | 282 | irq_hw_number_t gpio = irqd_to_hwirq(data); |
0ba19cfc BG |
283 | |
284 | if (wg->update & UPDATE_IRQ_TYPE) | |
285 | wcove_update_irq_ctrl(wg, gpio); | |
286 | if (wg->update & UPDATE_IRQ_MASK) | |
287 | wcove_update_irq_mask(wg, gpio); | |
288 | wg->update = 0; | |
289 | ||
290 | mutex_unlock(&wg->buslock); | |
291 | } | |
292 | ||
293 | static void wcove_irq_unmask(struct irq_data *data) | |
294 | { | |
295 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
296 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
f3019092 | 297 | irq_hw_number_t gpio = irqd_to_hwirq(data); |
0ba19cfc | 298 | |
f3019092 | 299 | if (gpio >= WCOVE_GPIO_NUM) |
3a02dc97 KS |
300 | return; |
301 | ||
0ba19cfc BG |
302 | wg->set_irq_mask = false; |
303 | wg->update |= UPDATE_IRQ_MASK; | |
304 | } | |
305 | ||
306 | static void wcove_irq_mask(struct irq_data *data) | |
307 | { | |
308 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
309 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
f3019092 | 310 | irq_hw_number_t gpio = irqd_to_hwirq(data); |
0ba19cfc | 311 | |
f3019092 | 312 | if (gpio >= WCOVE_GPIO_NUM) |
3a02dc97 KS |
313 | return; |
314 | ||
0ba19cfc BG |
315 | wg->set_irq_mask = true; |
316 | wg->update |= UPDATE_IRQ_MASK; | |
317 | } | |
318 | ||
319 | static struct irq_chip wcove_irqchip = { | |
320 | .name = "Whiskey Cove", | |
321 | .irq_mask = wcove_irq_mask, | |
322 | .irq_unmask = wcove_irq_unmask, | |
323 | .irq_set_type = wcove_irq_type, | |
324 | .irq_bus_lock = wcove_bus_lock, | |
325 | .irq_bus_sync_unlock = wcove_bus_sync_unlock, | |
326 | }; | |
327 | ||
328 | static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) | |
329 | { | |
330 | struct wcove_gpio *wg = (struct wcove_gpio *)data; | |
5a2a46ae | 331 | unsigned int virq, gpio; |
2edba74c | 332 | unsigned long pending; |
0ba19cfc BG |
333 | u8 p[2]; |
334 | ||
335 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
336 | dev_err(wg->dev, "Failed to read irq status register\n"); | |
337 | return IRQ_NONE; | |
338 | } | |
339 | ||
881ebd22 | 340 | pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); |
0ba19cfc BG |
341 | if (!pending) |
342 | return IRQ_NONE; | |
343 | ||
344 | /* Iterate until no interrupt is pending */ | |
345 | while (pending) { | |
346 | /* One iteration is for all pending bits */ | |
2edba74c | 347 | for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) { |
5a2a46ae AS |
348 | unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask); |
349 | ||
f0fbe7bc | 350 | virq = irq_find_mapping(wg->chip.irq.domain, gpio); |
0ba19cfc | 351 | handle_nested_irq(virq); |
5a2a46ae | 352 | regmap_set_bits(wg->regmap, reg, mask); |
0ba19cfc BG |
353 | } |
354 | ||
355 | /* Next iteration */ | |
356 | if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { | |
357 | dev_err(wg->dev, "Failed to read irq status\n"); | |
358 | break; | |
359 | } | |
360 | ||
881ebd22 | 361 | pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); |
0ba19cfc BG |
362 | } |
363 | ||
364 | return IRQ_HANDLED; | |
365 | } | |
366 | ||
367 | static void wcove_gpio_dbg_show(struct seq_file *s, | |
368 | struct gpio_chip *chip) | |
369 | { | |
370 | unsigned int ctlo, ctli, irq_mask, irq_status; | |
371 | struct wcove_gpio *wg = gpiochip_get_data(chip); | |
5a2a46ae | 372 | int gpio, mask, ret = 0; |
0ba19cfc BG |
373 | |
374 | for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { | |
0ba19cfc BG |
375 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); |
376 | ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); | |
5a2a46ae AS |
377 | ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask); |
378 | ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status); | |
0ba19cfc BG |
379 | if (ret) { |
380 | pr_err("Failed to read registers: ctrl out/in or irq status/mask\n"); | |
381 | break; | |
382 | } | |
383 | ||
0ba19cfc BG |
384 | seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", |
385 | gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", | |
386 | ctli & 0x1 ? "hi" : "lo", | |
387 | ctli & CTLI_INTCNT_NE ? "fall" : " ", | |
388 | ctli & CTLI_INTCNT_PE ? "rise" : " ", | |
389 | ctlo, | |
5a2a46ae AS |
390 | irq_mask & mask ? "mask " : "unmask", |
391 | irq_status & mask ? "pending" : " "); | |
0ba19cfc BG |
392 | } |
393 | } | |
394 | ||
395 | static int wcove_gpio_probe(struct platform_device *pdev) | |
396 | { | |
397 | struct intel_soc_pmic *pmic; | |
398 | struct wcove_gpio *wg; | |
399 | int virq, ret, irq; | |
400 | struct device *dev; | |
22f61d4e | 401 | struct gpio_irq_chip *girq; |
0ba19cfc BG |
402 | |
403 | /* | |
404 | * This gpio platform device is created by a mfd device (see | |
405 | * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information | |
406 | * shared by all sub-devices created by the mfd device, the regmap | |
407 | * pointer for instance, is stored as driver data of the mfd device | |
408 | * driver. | |
409 | */ | |
410 | pmic = dev_get_drvdata(pdev->dev.parent); | |
411 | if (!pmic) | |
412 | return -ENODEV; | |
413 | ||
414 | irq = platform_get_irq(pdev, 0); | |
415 | if (irq < 0) | |
416 | return irq; | |
417 | ||
418 | dev = &pdev->dev; | |
419 | ||
420 | wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); | |
421 | if (!wg) | |
422 | return -ENOMEM; | |
423 | ||
a1d28c59 | 424 | wg->regmap_irq_chip = pmic->irq_chip_data; |
0ba19cfc BG |
425 | |
426 | platform_set_drvdata(pdev, wg); | |
427 | ||
428 | mutex_init(&wg->buslock); | |
429 | wg->chip.label = KBUILD_MODNAME; | |
430 | wg->chip.direction_input = wcove_gpio_dir_in; | |
431 | wg->chip.direction_output = wcove_gpio_dir_out; | |
7d9e59ce | 432 | wg->chip.get_direction = wcove_gpio_get_direction; |
0ba19cfc BG |
433 | wg->chip.get = wcove_gpio_get; |
434 | wg->chip.set = wcove_gpio_set; | |
481a4209 | 435 | wg->chip.set_config = wcove_gpio_set_config; |
0ba19cfc BG |
436 | wg->chip.base = -1; |
437 | wg->chip.ngpio = WCOVE_VGPIO_NUM; | |
438 | wg->chip.can_sleep = true; | |
439 | wg->chip.parent = pdev->dev.parent; | |
440 | wg->chip.dbg_show = wcove_gpio_dbg_show; | |
441 | wg->dev = dev; | |
442 | wg->regmap = pmic->regmap; | |
443 | ||
0ba19cfc BG |
444 | virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); |
445 | if (virq < 0) { | |
446 | dev_err(dev, "Failed to get virq by irq %d\n", irq); | |
447 | return virq; | |
448 | } | |
449 | ||
22f61d4e LW |
450 | girq = &wg->chip.irq; |
451 | girq->chip = &wcove_irqchip; | |
452 | /* This will let us handle the parent IRQ in the driver */ | |
453 | girq->parent_handler = NULL; | |
454 | girq->num_parents = 0; | |
455 | girq->parents = NULL; | |
456 | girq->default_type = IRQ_TYPE_NONE; | |
457 | girq->handler = handle_simple_irq; | |
458 | girq->threaded = true; | |
459 | ||
22cc4220 AS |
460 | ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler, |
461 | IRQF_ONESHOT, pdev->name, wg); | |
462 | if (ret) { | |
463 | dev_err(dev, "Failed to request irq %d\n", virq); | |
464 | return ret; | |
465 | } | |
466 | ||
22f61d4e LW |
467 | ret = devm_gpiochip_add_data(dev, &wg->chip, wg); |
468 | if (ret) { | |
469 | dev_err(dev, "Failed to add gpiochip: %d\n", ret); | |
470 | return ret; | |
471 | } | |
35ca3f61 | 472 | |
a1d28c59 | 473 | /* Enable GPIO0 interrupts */ |
9fe5fcd6 | 474 | ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK); |
a1d28c59 KS |
475 | if (ret) |
476 | return ret; | |
477 | ||
478 | /* Enable GPIO1 interrupts */ | |
9fe5fcd6 | 479 | ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK); |
a1d28c59 KS |
480 | if (ret) |
481 | return ret; | |
482 | ||
0ba19cfc BG |
483 | return 0; |
484 | } | |
485 | ||
486 | /* | |
487 | * Whiskey Cove PMIC itself is a analog device(but with digital control | |
488 | * interface) providing power management support for other devices in | |
489 | * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. | |
490 | */ | |
491 | static struct platform_driver wcove_gpio_driver = { | |
492 | .driver = { | |
493 | .name = "bxt_wcove_gpio", | |
494 | }, | |
495 | .probe = wcove_gpio_probe, | |
496 | }; | |
497 | ||
498 | module_platform_driver(wcove_gpio_driver); | |
499 | ||
500 | MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); | |
501 | MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); | |
502 | MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); | |
503 | MODULE_LICENSE("GPL v2"); | |
504 | MODULE_ALIAS("platform:bxt_wcove_gpio"); |