[linux-2.6-block.git] / drivers / gpio / gpio-wcove.c

/*
 * Intel Whiskey Cove PMIC GPIO Driver
 *
 * This driver is written based on gpio-crystalcove.c
 *
 * Copyright (C) 2016 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>

/*
 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
 * Bank 0: Pin 0 - 6
 * Bank 1: Pin 7 - 10
 * Bank 2: Pin 11 -12
 * Each pin has one output control register and one input control register.
 */
#define BANK0_NR_PINS		7
#define BANK1_NR_PINS		4
#define BANK2_NR_PINS		2
#define WCOVE_GPIO_NUM		(BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
#define WCOVE_VGPIO_NUM		94
/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
#define GPIO_OUT_CTRL_BASE	0x4e44
/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
#define GPIO_IN_CTRL_BASE	0x4e51

/*
 * GPIO interrupts are organized in two groups:
 * Group 0: Bank 0 pins (Pin 0 - 6)
 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
 * Each group has two registers (one bit per pin): status and mask.
 */
#define GROUP0_NR_IRQS		7
#define GROUP1_NR_IRQS		6
#define IRQ_MASK_BASE		0x4e19
#define IRQ_STATUS_BASE		0x4e0b
#define GPIO_IRQ0_MASK		GENMASK(6, 0)
#define GPIO_IRQ1_MASK		GENMASK(5, 0)
#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define CTLI_INTCNT_DIS		(0 << 1)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0 << 5)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_MASK		(1 << 4)
#define CTLO_DRV_OD		(0 << 4)
#define CTLO_DRV_CMOS		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDOWN	(0 << 1)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDOWN	(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/*
 * struct wcove_gpio - Whiskey Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @dev: the gpio device
 * @regmap: the regmap from the parent device.
 * @regmap_irq_chip: the regmap of the gpio irq chip.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct wcove_gpio {
	struct mutex buslock;
	struct gpio_chip chip;
	struct device *dev;
	struct regmap *regmap;
	struct regmap_irq_chip_data *regmap_irq_chip;
	int update;
	int intcnt;
	bool set_irq_mask;
};

static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
{
	unsigned int reg;

	if (gpio >= WCOVE_GPIO_NUM)
		return -EOPNOTSUPP;

	if (reg_type == CTRL_IN)
		reg = GPIO_IN_CTRL_BASE + gpio;
	else
		reg = GPIO_OUT_CTRL_BASE + gpio;

	return reg;
}

static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
{
	unsigned int reg, mask;

	if (gpio < GROUP0_NR_IRQS) {
		reg = IRQ_MASK_BASE;
		mask = BIT(gpio % GROUP0_NR_IRQS);
	} else {
		reg = IRQ_MASK_BASE + 1;
		mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
	}

	if (wg->set_irq_mask)
		regmap_update_bits(wg->regmap, reg, mask, mask);
	else
		regmap_update_bits(wg->regmap, reg, mask, 0);
}

static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return;

	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
}

static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
}

static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
				    int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
}

static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	return !(val & CTLO_DIR_OUT);
}

static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return 0;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void wcove_gpio_set(struct gpio_chip *chip,
				 unsigned int gpio, int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return;

	if (value)
		regmap_update_bits(wg->regmap, reg, 1, 1);
	else
		regmap_update_bits(wg->regmap, reg, 1, 0);
}

static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
				 unsigned long config)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	switch (pinconf_to_config_param(config)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_OD);
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_CMOS);
	default:
		break;
	}

	return -ENOTSUPP;
}

static int wcove_irq_type(struct irq_data *data, unsigned int type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		wg->intcnt = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		wg->intcnt = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wg->intcnt = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wg->intcnt = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	wg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void wcove_bus_lock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	mutex_lock(&wg->buslock);
}

static void wcove_bus_sync_unlock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio = data->hwirq;

	if (wg->update & UPDATE_IRQ_TYPE)
		wcove_update_irq_ctrl(wg, gpio);
	if (wg->update & UPDATE_IRQ_MASK)
		wcove_update_irq_mask(wg, gpio);
	wg->update = 0;

	mutex_unlock(&wg->buslock);
}

static void wcove_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return;

	wg->set_irq_mask = false;
	wg->update |= UPDATE_IRQ_MASK;
}

static void wcove_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	if (data->hwirq >= WCOVE_GPIO_NUM)
		return;

	wg->set_irq_mask = true;
	wg->update |= UPDATE_IRQ_MASK;
}

static struct irq_chip wcove_irqchip = {
	.name			= "Whiskey Cove",
	.irq_mask		= wcove_irq_mask,
	.irq_unmask		= wcove_irq_unmask,
	.irq_set_type		= wcove_irq_type,
	.irq_bus_lock		= wcove_bus_lock,
	.irq_bus_sync_unlock	= wcove_bus_sync_unlock,
};

static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
{
	struct wcove_gpio *wg = (struct wcove_gpio *)data;
	unsigned int pending, virq, gpio, mask, offset;
	u8 p[2];

	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
		dev_err(wg->dev, "Failed to read irq status register\n");
		return IRQ_NONE;
	}

	pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	if (!pending)
		return IRQ_NONE;

	/* Iterate until no interrupt is pending */
	while (pending) {
		/* One iteration is for all pending bits */
		for_each_set_bit(gpio, (const unsigned long *)&pending,
						 WCOVE_GPIO_NUM) {
			offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
			mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
								BIT(gpio);
			virq = irq_find_mapping(wg->chip.irq.domain, gpio);
			handle_nested_irq(virq);
			regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
								mask, mask);
		}

		/* Next iteration */
		if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
			dev_err(wg->dev, "Failed to read irq status\n");
			break;
		}

		pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	}

	return IRQ_HANDLED;
}

static void wcove_gpio_dbg_show(struct seq_file *s,
				      struct gpio_chip *chip)
{
	unsigned int ctlo, ctli, irq_mask, irq_status;
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio, offset, group, ret = 0;

	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
		group = gpio < GROUP0_NR_IRQS ? 0 : 1;
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
							&irq_mask);
		ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
							&irq_status);
		if (ret) {
			pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
			break;
		}

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   irq_mask & BIT(offset) ? "mask  " : "unmask",
			   irq_status & BIT(offset) ? "pending" : "       ");
	}
}

static int wcove_gpio_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic;
	struct wcove_gpio *wg;
	int virq, ret, irq;
	struct device *dev;

	/*
	 * This gpio platform device is created by a mfd device (see
	 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	 * shared by all sub-devices created by the mfd device, the regmap
	 * pointer for instance, is stored as driver data of the mfd device
	 * driver.
	 */
	pmic = dev_get_drvdata(pdev->dev.parent);
	if (!pmic)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	dev = &pdev->dev;

	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	if (!wg)
		return -ENOMEM;

	wg->regmap_irq_chip = pmic->irq_chip_data;

	platform_set_drvdata(pdev, wg);

	mutex_init(&wg->buslock);
	wg->chip.label = KBUILD_MODNAME;
	wg->chip.direction_input = wcove_gpio_dir_in;
	wg->chip.direction_output = wcove_gpio_dir_out;
	wg->chip.get_direction = wcove_gpio_get_direction;
	wg->chip.get = wcove_gpio_get;
	wg->chip.set = wcove_gpio_set;
	wg->chip.set_config = wcove_gpio_set_config,
	wg->chip.base = -1;
	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	wg->chip.can_sleep = true;
	wg->chip.parent = pdev->dev.parent;
	wg->chip.dbg_show = wcove_gpio_dbg_show;
	wg->dev = dev;
	wg->regmap = pmic->regmap;

	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	if (ret) {
		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
		return ret;
	}

	ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
					  handle_simple_irq, IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "Failed to add irqchip: %d\n", ret);
		return ret;
	}

	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	if (virq < 0) {
		dev_err(dev, "Failed to get virq by irq %d\n", irq);
		return virq;
	}

	ret = devm_request_threaded_irq(dev, virq, NULL,
		wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	if (ret) {
		dev_err(dev, "Failed to request irq %d\n", virq);
		return ret;
	}

	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);

	/* Enable GPIO0 interrupts */
	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
				 0x00);
	if (ret)
		return ret;

	/* Enable GPIO1 interrupts */
	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
				 0x00);
	if (ret)
		return ret;

	return 0;
}

/*
 * Whiskey Cove PMIC itself is a analog device(but with digital control
 * interface) providing power management support for other devices in
 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 */
static struct platform_driver wcove_gpio_driver = {
	.driver = {
		.name = "bxt_wcove_gpio",
	},
	.probe = wcove_gpio_probe,
};

module_platform_driver(wcove_gpio_driver);

MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:bxt_wcove_gpio");
Commit	Line	Data
0ba19cfc BG	1	/*
	2	* Intel Whiskey Cove PMIC GPIO Driver
	3	*
	4	* This driver is written based on gpio-crystalcove.c
	5	*
	6	* Copyright (C) 2016 Intel Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License version
	10	* 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/bitops.h>
39d80072	19	#include <linux/module.h>
0ba19cfc BG	20	#include <linux/interrupt.h>
	21	#include <linux/gpio/driver.h>
	22	#include <linux/mfd/intel_soc_pmic.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/regmap.h>
	25	#include <linux/seq_file.h>
	26
	27	/*
	28	* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
	29	* Bank 0: Pin 0 - 6
	30	* Bank 1: Pin 7 - 10
	31	* Bank 2: Pin 11 -12
	32	* Each pin has one output control register and one input control register.
	33	*/
	34	#define BANK0_NR_PINS 7
	35	#define BANK1_NR_PINS 4
	36	#define BANK2_NR_PINS 2
	37	#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
	38	#define WCOVE_VGPIO_NUM 94
	39	/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
	40	#define GPIO_OUT_CTRL_BASE 0x4e44
	41	/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
	42	#define GPIO_IN_CTRL_BASE 0x4e51
	43
	44	/*
	45	* GPIO interrupts are organized in two groups:
	46	* Group 0: Bank 0 pins (Pin 0 - 6)
	47	* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
	48	* Each group has two registers (one bit per pin): status and mask.
	49	*/
	50	#define GROUP0_NR_IRQS 7
	51	#define GROUP1_NR_IRQS 6
	52	#define IRQ_MASK_BASE 0x4e19
	53	#define IRQ_STATUS_BASE 0x4e0b
881ebd22 KS	54	#define GPIO_IRQ0_MASK GENMASK(6, 0)
881ebd22 KS	55	#define GPIO_IRQ1_MASK GENMASK(5, 0)
0ba19cfc BG	56	#define UPDATE_IRQ_TYPE BIT(0)
	57	#define UPDATE_IRQ_MASK BIT(1)
	58
	59	#define CTLI_INTCNT_DIS (0 << 1)
	60	#define CTLI_INTCNT_NE (1 << 1)
	61	#define CTLI_INTCNT_PE (2 << 1)
	62	#define CTLI_INTCNT_BE (3 << 1)
	63
	64	#define CTLO_DIR_IN (0 << 5)
	65	#define CTLO_DIR_OUT (1 << 5)
	66
	67	#define CTLO_DRV_MASK (1 << 4)
	68	#define CTLO_DRV_OD (0 << 4)
	69	#define CTLO_DRV_CMOS (1 << 4)
	70
	71	#define CTLO_DRV_REN (1 << 3)
	72
	73	#define CTLO_RVAL_2KDOWN (0 << 1)
	74	#define CTLO_RVAL_2KUP (1 << 1)
	75	#define CTLO_RVAL_50KDOWN (2 << 1)
	76	#define CTLO_RVAL_50KUP (3 << 1)
	77
	78	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
	79	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
	80
	81	enum ctrl_register {
	82	CTRL_IN,
	83	CTRL_OUT,
	84	};
	85
	86	/*
	87	* struct wcove_gpio - Whiskey Cove GPIO controller
	88	* @buslock: for bus lock/sync and unlock.
	89	* @chip: the abstract gpio_chip structure.
	90	* @dev: the gpio device
	91	* @regmap: the regmap from the parent device.
	92	* @regmap_irq_chip: the regmap of the gpio irq chip.
	93	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	94	* @intcnt: the Interrupt Detect value to be written.
	95	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	96	*/
	97	struct wcove_gpio {
	98	struct mutex buslock;
	99	struct gpio_chip chip;
	100	struct device *dev;
	101	struct regmap *regmap;
	102	struct regmap_irq_chip_data *regmap_irq_chip;
	103	int update;
	104	int intcnt;
	105	bool set_irq_mask;
	106	};
	107
	108	static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
	109	{
	110	unsigned int reg;
0ba19cfc	111
3a02dc97 KS	112	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	113	return -EOPNOTSUPP;
0ba19cfc BG	114
0ba19cfc BG	115	if (reg_type == CTRL_IN)
3a02dc97	116	reg = GPIO_IN_CTRL_BASE + gpio;
0ba19cfc	117	else
3a02dc97	118	reg = GPIO_OUT_CTRL_BASE + gpio;
0ba19cfc BG	119
	120	return reg;
	121	}
	122
	123	static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
	124	{
	125	unsigned int reg, mask;
	126
	127	if (gpio < GROUP0_NR_IRQS) {
	128	reg = IRQ_MASK_BASE;
	129	mask = BIT(gpio % GROUP0_NR_IRQS);
	130	} else {
	131	reg = IRQ_MASK_BASE + 1;
	132	mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
	133	}
	134
	135	if (wg->set_irq_mask)
	136	regmap_update_bits(wg->regmap, reg, mask, mask);
	137	else
	138	regmap_update_bits(wg->regmap, reg, mask, 0);
	139	}
	140
	141	static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
	142	{
3a02dc97 KS	143	int reg = to_reg(gpio, CTRL_IN);
	144
	145	if (reg < 0)
	146	return;
0ba19cfc BG	147
	148	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
	149	}
	150
	151	static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
	152	{
	153	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	154	int reg = to_reg(gpio, CTRL_OUT);
	155
	156	if (reg < 0)
	157	return 0;
0ba19cfc	158
3a02dc97	159	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
0ba19cfc BG	160	}
	161
	162	static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
	163	int value)
	164	{
	165	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97	166	int reg = to_reg(gpio, CTRL_OUT);
0ba19cfc	167
3a02dc97 KS	168	if (reg < 0)
	169	return 0;
	170
	171	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET \| value);
0ba19cfc BG	172	}
0ba19cfc BG	173
7d9e59ce BG	174	static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
	175	{
	176	struct wcove_gpio *wg = gpiochip_get_data(chip);
	177	unsigned int val;
3a02dc97 KS	178	int ret, reg = to_reg(gpio, CTRL_OUT);
	179
	180	if (reg < 0)
	181	return 0;
7d9e59ce	182
3a02dc97	183	ret = regmap_read(wg->regmap, reg, &val);
7d9e59ce BG	184	if (ret)
	185	return ret;
	186
	187	return !(val & CTLO_DIR_OUT);
	188	}
	189
0ba19cfc BG	190	static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
	191	{
	192	struct wcove_gpio *wg = gpiochip_get_data(chip);
	193	unsigned int val;
3a02dc97 KS	194	int ret, reg = to_reg(gpio, CTRL_IN);
	195
	196	if (reg < 0)
	197	return 0;
0ba19cfc	198
3a02dc97	199	ret = regmap_read(wg->regmap, reg, &val);
0ba19cfc BG	200	if (ret)
	201	return ret;
	202
	203	return val & 0x1;
	204	}
	205
	206	static void wcove_gpio_set(struct gpio_chip *chip,
	207	unsigned int gpio, int value)
	208	{
	209	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	210	int reg = to_reg(gpio, CTRL_OUT);
	211
	212	if (reg < 0)
	213	return;
0ba19cfc BG	214
0ba19cfc BG	215	if (value)
3a02dc97	216	regmap_update_bits(wg->regmap, reg, 1, 1);
0ba19cfc	217	else
3a02dc97	218	regmap_update_bits(wg->regmap, reg, 1, 0);
0ba19cfc BG	219	}
0ba19cfc BG	220
2956b5d9 MW	221	static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
2956b5d9 MW	222	unsigned long config)
0ba19cfc BG	223	{
0ba19cfc BG	224	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	225	int reg = to_reg(gpio, CTRL_OUT);
	226
	227	if (reg < 0)
	228	return 0;
0ba19cfc	229
2956b5d9 MW	230	switch (pinconf_to_config_param(config)) {
2956b5d9 MW	231	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
3a02dc97 KS	232	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	233	CTLO_DRV_OD);
2956b5d9	234	case PIN_CONFIG_DRIVE_PUSH_PULL:
3a02dc97 KS	235	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	236	CTLO_DRV_CMOS);
0ba19cfc BG	237	default:
	238	break;
	239	}
	240
	241	return -ENOTSUPP;
	242	}
	243
	244	static int wcove_irq_type(struct irq_data *data, unsigned int type)
	245	{
	246	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	247	struct wcove_gpio *wg = gpiochip_get_data(chip);
	248
3a02dc97 KS	249	if (data->hwirq >= WCOVE_GPIO_NUM)
	250	return 0;
	251
0ba19cfc BG	252	switch (type) {
	253	case IRQ_TYPE_NONE:
	254	wg->intcnt = CTLI_INTCNT_DIS;
	255	break;
	256	case IRQ_TYPE_EDGE_BOTH:
	257	wg->intcnt = CTLI_INTCNT_BE;
	258	break;
	259	case IRQ_TYPE_EDGE_RISING:
	260	wg->intcnt = CTLI_INTCNT_PE;
	261	break;
	262	case IRQ_TYPE_EDGE_FALLING:
	263	wg->intcnt = CTLI_INTCNT_NE;
	264	break;
	265	default:
	266	return -EINVAL;
	267	}
	268
	269	wg->update \|= UPDATE_IRQ_TYPE;
	270
	271	return 0;
	272	}
	273
	274	static void wcove_bus_lock(struct irq_data *data)
	275	{
	276	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	277	struct wcove_gpio *wg = gpiochip_get_data(chip);
	278
	279	mutex_lock(&wg->buslock);
	280	}
	281
	282	static void wcove_bus_sync_unlock(struct irq_data *data)
	283	{
	284	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	285	struct wcove_gpio *wg = gpiochip_get_data(chip);
	286	int gpio = data->hwirq;
	287
	288	if (wg->update & UPDATE_IRQ_TYPE)
	289	wcove_update_irq_ctrl(wg, gpio);
	290	if (wg->update & UPDATE_IRQ_MASK)
	291	wcove_update_irq_mask(wg, gpio);
	292	wg->update = 0;
	293
	294	mutex_unlock(&wg->buslock);
	295	}
	296
	297	static void wcove_irq_unmask(struct irq_data *data)
	298	{
	299	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	300	struct wcove_gpio *wg = gpiochip_get_data(chip);
	301
3a02dc97 KS	302	if (data->hwirq >= WCOVE_GPIO_NUM)
	303	return;
	304
0ba19cfc BG	305	wg->set_irq_mask = false;
	306	wg->update \|= UPDATE_IRQ_MASK;
	307	}
	308
	309	static void wcove_irq_mask(struct irq_data *data)
	310	{
	311	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	312	struct wcove_gpio *wg = gpiochip_get_data(chip);
	313
3a02dc97 KS	314	if (data->hwirq >= WCOVE_GPIO_NUM)
	315	return;
	316
0ba19cfc BG	317	wg->set_irq_mask = true;
	318	wg->update \|= UPDATE_IRQ_MASK;
	319	}
	320
	321	static struct irq_chip wcove_irqchip = {
	322	.name = "Whiskey Cove",
	323	.irq_mask = wcove_irq_mask,
	324	.irq_unmask = wcove_irq_unmask,
	325	.irq_set_type = wcove_irq_type,
	326	.irq_bus_lock = wcove_bus_lock,
	327	.irq_bus_sync_unlock = wcove_bus_sync_unlock,
	328	};
	329
	330	static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
	331	{
	332	struct wcove_gpio wg = (struct wcove_gpio )data;
	333	unsigned int pending, virq, gpio, mask, offset;
	334	u8 p[2];
	335
	336	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	337	dev_err(wg->dev, "Failed to read irq status register\n");
	338	return IRQ_NONE;
	339	}
	340
881ebd22	341	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	342	if (!pending)
	343	return IRQ_NONE;
	344
	345	/* Iterate until no interrupt is pending */
	346	while (pending) {
	347	/* One iteration is for all pending bits */
	348	for_each_set_bit(gpio, (const unsigned long *)&pending,
7c2d176f	349	WCOVE_GPIO_NUM) {
0ba19cfc BG	350	offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
	351	mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
	352	BIT(gpio);
f0fbe7bc	353	virq = irq_find_mapping(wg->chip.irq.domain, gpio);
0ba19cfc BG	354	handle_nested_irq(virq);
	355	regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
	356	mask, mask);
	357	}
	358
	359	/* Next iteration */
	360	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	361	dev_err(wg->dev, "Failed to read irq status\n");
	362	break;
	363	}
	364
881ebd22	365	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	366	}
	367
	368	return IRQ_HANDLED;
	369	}
	370
	371	static void wcove_gpio_dbg_show(struct seq_file *s,
	372	struct gpio_chip *chip)
	373	{
	374	unsigned int ctlo, ctli, irq_mask, irq_status;
	375	struct wcove_gpio *wg = gpiochip_get_data(chip);
	376	int gpio, offset, group, ret = 0;
	377
	378	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
	379	group = gpio < GROUP0_NR_IRQS ? 0 : 1;
	380	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
	381	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
	382	ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
	383	&irq_mask);
	384	ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
	385	&irq_status);
	386	if (ret) {
	387	pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
	388	break;
	389	}
	390
	391	offset = gpio % 8;
	392	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
	393	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	394	ctli & 0x1 ? "hi" : "lo",
	395	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	396	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	397	ctlo,
	398	irq_mask & BIT(offset) ? "mask " : "unmask",
	399	irq_status & BIT(offset) ? "pending" : " ");
	400	}
	401	}
	402
	403	static int wcove_gpio_probe(struct platform_device *pdev)
	404	{
	405	struct intel_soc_pmic *pmic;
	406	struct wcove_gpio *wg;
	407	int virq, ret, irq;
	408	struct device *dev;
	409
	410	/*
	411	* This gpio platform device is created by a mfd device (see
	412	* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	413	* shared by all sub-devices created by the mfd device, the regmap
	414	* pointer for instance, is stored as driver data of the mfd device
	415	* driver.
	416	*/
	417	pmic = dev_get_drvdata(pdev->dev.parent);
	418	if (!pmic)
	419	return -ENODEV;
	420
	421	irq = platform_get_irq(pdev, 0);
	422	if (irq < 0)
	423	return irq;
	424
	425	dev = &pdev->dev;
	426
	427	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	428	if (!wg)
	429	return -ENOMEM;
430
a1d28c59	431	wg->regmap_irq_chip = pmic->irq_chip_data;
0ba19cfc BG	432
	433	platform_set_drvdata(pdev, wg);
	434
	435	mutex_init(&wg->buslock);
	436	wg->chip.label = KBUILD_MODNAME;
	437	wg->chip.direction_input = wcove_gpio_dir_in;
	438	wg->chip.direction_output = wcove_gpio_dir_out;
7d9e59ce	439	wg->chip.get_direction = wcove_gpio_get_direction;
0ba19cfc BG	440	wg->chip.get = wcove_gpio_get;
0ba19cfc BG	441	wg->chip.set = wcove_gpio_set;
2956b5d9	442	wg->chip.set_config = wcove_gpio_set_config,
0ba19cfc BG	443	wg->chip.base = -1;
	444	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	445	wg->chip.can_sleep = true;
	446	wg->chip.parent = pdev->dev.parent;
	447	wg->chip.dbg_show = wcove_gpio_dbg_show;
	448	wg->dev = dev;
	449	wg->regmap = pmic->regmap;
	450
	451	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	452	if (ret) {
	453	dev_err(dev, "Failed to add gpiochip: %d\n", ret);
	454	return ret;
	455	}
	456
d245b3f9 LW	457	ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
d245b3f9 LW	458	handle_simple_irq, IRQ_TYPE_NONE);
0ba19cfc BG	459	if (ret) {
	460	dev_err(dev, "Failed to add irqchip: %d\n", ret);
	461	return ret;
	462	}
	463
	464	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	465	if (virq < 0) {
	466	dev_err(dev, "Failed to get virq by irq %d\n", irq);
	467	return virq;
	468	}
	469
	470	ret = devm_request_threaded_irq(dev, virq, NULL,
	471	wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
	472	if (ret) {
	473	dev_err(dev, "Failed to request irq %d\n", virq);
	474	return ret;
	475	}
	476
35ca3f61 LW	477	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
35ca3f61 LW	478
a1d28c59 KS	479	/* Enable GPIO0 interrupts */
	480	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
	481	0x00);
	482	if (ret)
	483	return ret;
	484
	485	/* Enable GPIO1 interrupts */
	486	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
	487	0x00);
	488	if (ret)
	489	return ret;
	490
0ba19cfc BG	491	return 0;
	492	}
	493
	494	/*
	495	* Whiskey Cove PMIC itself is a analog device(but with digital control
	496	* interface) providing power management support for other devices in
	497	* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
	498	*/
	499	static struct platform_driver wcove_gpio_driver = {
	500	.driver = {
	501	.name = "bxt_wcove_gpio",
	502	},
	503	.probe = wcove_gpio_probe,
	504	};
	505
	506	module_platform_driver(wcove_gpio_driver);
	507
	508	MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
	509	MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
	510	MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
	511	MODULE_LICENSE("GPL v2");
	512	MODULE_ALIAS("platform:bxt_wcove_gpio");