[linux-2.6-block.git] / drivers / gpio / gpio-wcove.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Whiskey Cove PMIC GPIO Driver
 *
 * This driver is written based on gpio-crystalcove.c
 *
 * Copyright (C) 2016 Intel Corporation. All rights reserved.
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>

/*
 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
 * Bank 0: Pin  0 - 6
 * Bank 1: Pin  7 - 10
 * Bank 2: Pin 11 - 12
 * Each pin has one output control register and one input control register.
 */
#define BANK0_NR_PINS		7
#define BANK1_NR_PINS		4
#define BANK2_NR_PINS		2
#define WCOVE_GPIO_NUM		(BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
#define WCOVE_VGPIO_NUM		94
/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
#define GPIO_OUT_CTRL_BASE	0x4e44
/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
#define GPIO_IN_CTRL_BASE	0x4e51

/*
 * GPIO interrupts are organized in two groups:
 * Group 0: Bank 0 pins (Pin 0 - 6)
 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
 * Each group has two registers (one bit per pin): status and mask.
 */
#define GROUP0_NR_IRQS		7
#define GROUP1_NR_IRQS		6
#define IRQ_MASK_BASE		0x4e19
#define IRQ_STATUS_BASE		0x4e0b
#define GPIO_IRQ0_MASK		GENMASK(6, 0)
#define GPIO_IRQ1_MASK		GENMASK(5, 0)
#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define CTLI_INTCNT_DIS		(0 << 1)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0 << 5)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_MASK		(1 << 4)
#define CTLO_DRV_OD		(0 << 4)
#define CTLO_DRV_CMOS		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDOWN	(0 << 1)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDOWN	(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET		(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET		(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
	IRQ_STATUS,
	IRQ_MASK,
};

/*
 * struct wcove_gpio - Whiskey Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @dev: the gpio device
 * @regmap: the regmap from the parent device.
 * @regmap_irq_chip: the regmap of the gpio irq chip.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct wcove_gpio {
	struct mutex buslock;
	struct gpio_chip chip;
	struct device *dev;
	struct regmap *regmap;
	struct regmap_irq_chip_data *regmap_irq_chip;
	int update;
	int intcnt;
	bool set_irq_mask;
};

static inline int to_reg(int gpio, enum ctrl_register type)
{
	unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE;

	if (gpio >= WCOVE_GPIO_NUM)
		return -EOPNOTSUPP;

	return reg + gpio;
}

static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
{
	unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;

	if (gpio < GROUP0_NR_IRQS) {
		reg += 0;
		*mask = BIT(gpio);
	} else {
		reg += 1;
		*mask = BIT(gpio - GROUP0_NR_IRQS);
	}

	return reg;
}

static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
{
	unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);

	if (wg->set_irq_mask)
		regmap_set_bits(wg->regmap, reg, mask);
	else
		regmap_clear_bits(wg->regmap, reg, mask);
}

static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
}

static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
}

static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
				    int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
}

static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return GPIO_LINE_DIRECTION_OUT;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	if (val & CTLO_DIR_OUT)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return 0;

	ret = regmap_read(wg->regmap, reg, &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return;

	if (value)
		regmap_set_bits(wg->regmap, reg, 1);
	else
		regmap_clear_bits(wg->regmap, reg, 1);
}

static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
				 unsigned long config)
{
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	switch (pinconf_to_config_param(config)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_OD);
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
					  CTLO_DRV_CMOS);
	default:
		break;
	}

	return -ENOTSUPP;
}

static int wcove_irq_type(struct irq_data *data, unsigned int type)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	irq_hw_number_t gpio = irqd_to_hwirq(data);

	if (gpio >= WCOVE_GPIO_NUM)
		return 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		wg->intcnt = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		wg->intcnt = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wg->intcnt = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wg->intcnt = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	wg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void wcove_bus_lock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);

	mutex_lock(&wg->buslock);
}

static void wcove_bus_sync_unlock(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	irq_hw_number_t gpio = irqd_to_hwirq(data);

	if (wg->update & UPDATE_IRQ_TYPE)
		wcove_update_irq_ctrl(wg, gpio);
	if (wg->update & UPDATE_IRQ_MASK)
		wcove_update_irq_mask(wg, gpio);
	wg->update = 0;

	mutex_unlock(&wg->buslock);
}

static void wcove_irq_unmask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	irq_hw_number_t gpio = irqd_to_hwirq(data);

	if (gpio >= WCOVE_GPIO_NUM)
		return;

	gpiochip_enable_irq(chip, gpio);

	wg->set_irq_mask = false;
	wg->update |= UPDATE_IRQ_MASK;
}

static void wcove_irq_mask(struct irq_data *data)
{
	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	irq_hw_number_t gpio = irqd_to_hwirq(data);

	if (gpio >= WCOVE_GPIO_NUM)
		return;

	wg->set_irq_mask = true;
	wg->update |= UPDATE_IRQ_MASK;

	gpiochip_disable_irq(chip, gpio);
}

static const struct irq_chip wcove_irqchip = {
	.name			= "Whiskey Cove",
	.irq_mask		= wcove_irq_mask,
	.irq_unmask		= wcove_irq_unmask,
	.irq_set_type		= wcove_irq_type,
	.irq_bus_lock		= wcove_bus_lock,
	.irq_bus_sync_unlock	= wcove_bus_sync_unlock,
	.flags			= IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
{
	struct wcove_gpio *wg = (struct wcove_gpio *)data;
	unsigned int virq, gpio;
	unsigned long pending;
	u8 p[2];

	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
		dev_err(wg->dev, "Failed to read irq status register\n");
		return IRQ_NONE;
	}

	pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	if (!pending)
		return IRQ_NONE;

	/* Iterate until no interrupt is pending */
	while (pending) {
		/* One iteration is for all pending bits */
		for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
			unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);

			virq = irq_find_mapping(wg->chip.irq.domain, gpio);
			handle_nested_irq(virq);
			regmap_set_bits(wg->regmap, reg, mask);
		}

		/* Next iteration */
		if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
			dev_err(wg->dev, "Failed to read irq status\n");
			break;
		}

		pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
	}

	return IRQ_HANDLED;
}

static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	unsigned int ctlo, ctli, irq_mask, irq_status;
	struct wcove_gpio *wg = gpiochip_get_data(chip);
	int gpio, mask, ret = 0;

	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		if (ret) {
			dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
			break;
		}

		ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
		ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
		if (ret) {
			dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
			break;
		}

		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   irq_mask & mask ? "mask  " : "unmask",
			   irq_status & mask ? "pending" : "       ");
	}
}

static int wcove_gpio_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic;
	struct wcove_gpio *wg;
	int virq, ret, irq;
	struct device *dev;
	struct gpio_irq_chip *girq;

	/*
	 * This gpio platform device is created by a mfd device (see
	 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	 * shared by all sub-devices created by the mfd device, the regmap
	 * pointer for instance, is stored as driver data of the mfd device
	 * driver.
	 */
	pmic = dev_get_drvdata(pdev->dev.parent);
	if (!pmic)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	dev = &pdev->dev;

	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	if (!wg)
		return -ENOMEM;

	wg->regmap_irq_chip = pmic->irq_chip_data;

	platform_set_drvdata(pdev, wg);

	mutex_init(&wg->buslock);
	wg->chip.label = KBUILD_MODNAME;
	wg->chip.direction_input = wcove_gpio_dir_in;
	wg->chip.direction_output = wcove_gpio_dir_out;
	wg->chip.get_direction = wcove_gpio_get_direction;
	wg->chip.get = wcove_gpio_get;
	wg->chip.set = wcove_gpio_set;
	wg->chip.set_config = wcove_gpio_set_config;
	wg->chip.base = -1;
	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	wg->chip.can_sleep = true;
	wg->chip.parent = pdev->dev.parent;
	wg->chip.dbg_show = wcove_gpio_dbg_show;
	wg->dev = dev;
	wg->regmap = pmic->regmap;

	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	if (virq < 0) {
		dev_err(dev, "Failed to get virq by irq %d\n", irq);
		return virq;
	}

	girq = &wg->chip.irq;
	gpio_irq_chip_set_chip(girq, &wcove_irqchip);
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_simple_irq;
	girq->threaded = true;

	ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
					IRQF_ONESHOT, pdev->name, wg);
	if (ret) {
		dev_err(dev, "Failed to request irq %d\n", virq);
		return ret;
	}

	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	if (ret) {
		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
		return ret;
	}

	/* Enable GPIO0 interrupts */
	ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
	if (ret)
		return ret;

	/* Enable GPIO1 interrupts */
	ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
	if (ret)
		return ret;

	return 0;
}

/*
 * Whiskey Cove PMIC itself is a analog device(but with digital control
 * interface) providing power management support for other devices in
 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 */
static struct platform_driver wcove_gpio_driver = {
	.driver = {
		.name = "bxt_wcove_gpio",
	},
	.probe = wcove_gpio_probe,
};

module_platform_driver(wcove_gpio_driver);

MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:bxt_wcove_gpio");
Commit	Line	Data
fd30b72e	1	// SPDX-License-Identifier: GPL-2.0
0ba19cfc BG	2	/*
	3	* Intel Whiskey Cove PMIC GPIO Driver
	4	*
	5	* This driver is written based on gpio-crystalcove.c
	6	*
	7	* Copyright (C) 2016 Intel Corporation. All rights reserved.
0ba19cfc BG	8	*/
	9
	10	#include <linux/bitops.h>
0ba19cfc	11	#include <linux/gpio/driver.h>
39684807	12	#include <linux/interrupt.h>
0ba19cfc	13	#include <linux/mfd/intel_soc_pmic.h>
39684807	14	#include <linux/module.h>
0ba19cfc BG	15	#include <linux/platform_device.h>
	16	#include <linux/regmap.h>
	17	#include <linux/seq_file.h>
	18
	19	/*
	20	* Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
cb19c7f3 AS	21	* Bank 0: Pin 0 - 6
	22	* Bank 1: Pin 7 - 10
	23	* Bank 2: Pin 11 - 12
0ba19cfc BG	24	* Each pin has one output control register and one input control register.
	25	*/
	26	#define BANK0_NR_PINS 7
	27	#define BANK1_NR_PINS 4
	28	#define BANK2_NR_PINS 2
	29	#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
	30	#define WCOVE_VGPIO_NUM 94
	31	/* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
	32	#define GPIO_OUT_CTRL_BASE 0x4e44
	33	/* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
	34	#define GPIO_IN_CTRL_BASE 0x4e51
	35
	36	/*
	37	* GPIO interrupts are organized in two groups:
	38	* Group 0: Bank 0 pins (Pin 0 - 6)
	39	* Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
	40	* Each group has two registers (one bit per pin): status and mask.
	41	*/
	42	#define GROUP0_NR_IRQS 7
	43	#define GROUP1_NR_IRQS 6
	44	#define IRQ_MASK_BASE 0x4e19
	45	#define IRQ_STATUS_BASE 0x4e0b
881ebd22 KS	46	#define GPIO_IRQ0_MASK GENMASK(6, 0)
881ebd22 KS	47	#define GPIO_IRQ1_MASK GENMASK(5, 0)
0ba19cfc BG	48	#define UPDATE_IRQ_TYPE BIT(0)
	49	#define UPDATE_IRQ_MASK BIT(1)
	50
	51	#define CTLI_INTCNT_DIS (0 << 1)
	52	#define CTLI_INTCNT_NE (1 << 1)
	53	#define CTLI_INTCNT_PE (2 << 1)
	54	#define CTLI_INTCNT_BE (3 << 1)
	55
	56	#define CTLO_DIR_IN (0 << 5)
	57	#define CTLO_DIR_OUT (1 << 5)
	58
	59	#define CTLO_DRV_MASK (1 << 4)
	60	#define CTLO_DRV_OD (0 << 4)
	61	#define CTLO_DRV_CMOS (1 << 4)
	62
	63	#define CTLO_DRV_REN (1 << 3)
	64
	65	#define CTLO_RVAL_2KDOWN (0 << 1)
	66	#define CTLO_RVAL_2KUP (1 << 1)
	67	#define CTLO_RVAL_50KDOWN (2 << 1)
	68	#define CTLO_RVAL_50KUP (3 << 1)
	69
cb19c7f3 AS	70	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
cb19c7f3 AS	71	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
0ba19cfc BG	72
	73	enum ctrl_register {
	74	CTRL_IN,
	75	CTRL_OUT,
5a2a46ae AS	76	IRQ_STATUS,
5a2a46ae AS	77	IRQ_MASK,
0ba19cfc BG	78	};
	79
	80	/*
	81	* struct wcove_gpio - Whiskey Cove GPIO controller
	82	* @buslock: for bus lock/sync and unlock.
	83	* @chip: the abstract gpio_chip structure.
	84	* @dev: the gpio device
	85	* @regmap: the regmap from the parent device.
	86	* @regmap_irq_chip: the regmap of the gpio irq chip.
	87	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	88	* @intcnt: the Interrupt Detect value to be written.
	89	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	90	*/
	91	struct wcove_gpio {
	92	struct mutex buslock;
	93	struct gpio_chip chip;
	94	struct device *dev;
	95	struct regmap *regmap;
	96	struct regmap_irq_chip_data *regmap_irq_chip;
	97	int update;
	98	int intcnt;
	99	bool set_irq_mask;
	100	};
	101
5d993664	102	static inline int to_reg(int gpio, enum ctrl_register type)
0ba19cfc	103	{
5d993664	104	unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE;
0ba19cfc	105
3a02dc97 KS	106	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	107	return -EOPNOTSUPP;
0ba19cfc	108
5d993664	109	return reg + gpio;
0ba19cfc BG	110	}
0ba19cfc BG	111
5a2a46ae	112	static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask)
0ba19cfc	113	{
5a2a46ae	114	unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE;
0ba19cfc BG	115
0ba19cfc BG	116	if (gpio < GROUP0_NR_IRQS) {
5a2a46ae AS	117	reg += 0;
5a2a46ae AS	118	*mask = BIT(gpio);
0ba19cfc	119	} else {
5a2a46ae AS	120	reg += 1;
5a2a46ae AS	121	*mask = BIT(gpio - GROUP0_NR_IRQS);
0ba19cfc BG	122	}
0ba19cfc BG	123
5a2a46ae AS	124	return reg;
	125	}
	126
f3019092	127	static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
5a2a46ae AS	128	{
	129	unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask);
	130
0ba19cfc	131	if (wg->set_irq_mask)
9fe5fcd6	132	regmap_set_bits(wg->regmap, reg, mask);
0ba19cfc	133	else
9fe5fcd6	134	regmap_clear_bits(wg->regmap, reg, mask);
0ba19cfc BG	135	}
0ba19cfc BG	136
f3019092	137	static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
0ba19cfc	138	{
3a02dc97 KS	139	int reg = to_reg(gpio, CTRL_IN);
3a02dc97 KS	140
0ba19cfc BG	141	regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
	142	}
	143
	144	static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
	145	{
	146	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	147	int reg = to_reg(gpio, CTRL_OUT);
	148
	149	if (reg < 0)
	150	return 0;
0ba19cfc	151
3a02dc97	152	return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
0ba19cfc BG	153	}
	154
	155	static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
	156	int value)
	157	{
	158	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97	159	int reg = to_reg(gpio, CTRL_OUT);
0ba19cfc	160
3a02dc97 KS	161	if (reg < 0)
	162	return 0;
	163
	164	return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET \| value);
0ba19cfc BG	165	}
0ba19cfc BG	166
7d9e59ce BG	167	static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
	168	{
	169	struct wcove_gpio *wg = gpiochip_get_data(chip);
	170	unsigned int val;
3a02dc97 KS	171	int ret, reg = to_reg(gpio, CTRL_OUT);
	172
	173	if (reg < 0)
e42615ec	174	return GPIO_LINE_DIRECTION_OUT;
7d9e59ce	175
3a02dc97	176	ret = regmap_read(wg->regmap, reg, &val);
7d9e59ce BG	177	if (ret)
	178	return ret;
	179
e42615ec MV	180	if (val & CTLO_DIR_OUT)
	181	return GPIO_LINE_DIRECTION_OUT;
	182
	183	return GPIO_LINE_DIRECTION_IN;
7d9e59ce BG	184	}
7d9e59ce BG	185
0ba19cfc BG	186	static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
	187	{
	188	struct wcove_gpio *wg = gpiochip_get_data(chip);
	189	unsigned int val;
3a02dc97 KS	190	int ret, reg = to_reg(gpio, CTRL_IN);
	191
	192	if (reg < 0)
	193	return 0;
0ba19cfc	194
3a02dc97	195	ret = regmap_read(wg->regmap, reg, &val);
0ba19cfc BG	196	if (ret)
	197	return ret;
	198
	199	return val & 0x1;
	200	}
	201
cb19c7f3	202	static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
0ba19cfc BG	203	{
0ba19cfc BG	204	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	205	int reg = to_reg(gpio, CTRL_OUT);
	206
	207	if (reg < 0)
	208	return;
0ba19cfc BG	209
0ba19cfc BG	210	if (value)
9fe5fcd6	211	regmap_set_bits(wg->regmap, reg, 1);
0ba19cfc	212	else
9fe5fcd6	213	regmap_clear_bits(wg->regmap, reg, 1);
0ba19cfc BG	214	}
0ba19cfc BG	215
2956b5d9 MW	216	static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio,
2956b5d9 MW	217	unsigned long config)
0ba19cfc BG	218	{
0ba19cfc BG	219	struct wcove_gpio *wg = gpiochip_get_data(chip);
3a02dc97 KS	220	int reg = to_reg(gpio, CTRL_OUT);
	221
	222	if (reg < 0)
	223	return 0;
0ba19cfc	224
2956b5d9 MW	225	switch (pinconf_to_config_param(config)) {
2956b5d9 MW	226	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
3a02dc97 KS	227	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	228	CTLO_DRV_OD);
2956b5d9	229	case PIN_CONFIG_DRIVE_PUSH_PULL:
3a02dc97 KS	230	return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
3a02dc97 KS	231	CTLO_DRV_CMOS);
0ba19cfc BG	232	default:
	233	break;
	234	}
	235
	236	return -ENOTSUPP;
	237	}
	238
	239	static int wcove_irq_type(struct irq_data *data, unsigned int type)
	240	{
	241	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	242	struct wcove_gpio *wg = gpiochip_get_data(chip);
f3019092	243	irq_hw_number_t gpio = irqd_to_hwirq(data);
0ba19cfc	244
f3019092	245	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	246	return 0;
3a02dc97 KS	247
0ba19cfc BG	248	switch (type) {
	249	case IRQ_TYPE_NONE:
	250	wg->intcnt = CTLI_INTCNT_DIS;
	251	break;
	252	case IRQ_TYPE_EDGE_BOTH:
	253	wg->intcnt = CTLI_INTCNT_BE;
	254	break;
	255	case IRQ_TYPE_EDGE_RISING:
	256	wg->intcnt = CTLI_INTCNT_PE;
	257	break;
	258	case IRQ_TYPE_EDGE_FALLING:
	259	wg->intcnt = CTLI_INTCNT_NE;
	260	break;
	261	default:
	262	return -EINVAL;
	263	}
	264
	265	wg->update \|= UPDATE_IRQ_TYPE;
	266
	267	return 0;
	268	}
	269
	270	static void wcove_bus_lock(struct irq_data *data)
	271	{
	272	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	273	struct wcove_gpio *wg = gpiochip_get_data(chip);
	274
	275	mutex_lock(&wg->buslock);
	276	}
	277
	278	static void wcove_bus_sync_unlock(struct irq_data *data)
	279	{
	280	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	281	struct wcove_gpio *wg = gpiochip_get_data(chip);
f3019092	282	irq_hw_number_t gpio = irqd_to_hwirq(data);
0ba19cfc BG	283
	284	if (wg->update & UPDATE_IRQ_TYPE)
	285	wcove_update_irq_ctrl(wg, gpio);
	286	if (wg->update & UPDATE_IRQ_MASK)
	287	wcove_update_irq_mask(wg, gpio);
	288	wg->update = 0;
	289
	290	mutex_unlock(&wg->buslock);
	291	}
	292
	293	static void wcove_irq_unmask(struct irq_data *data)
	294	{
	295	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	296	struct wcove_gpio *wg = gpiochip_get_data(chip);
f3019092	297	irq_hw_number_t gpio = irqd_to_hwirq(data);
0ba19cfc	298
f3019092	299	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	300	return;
3a02dc97 KS	301
41a18c49 AS	302	gpiochip_enable_irq(chip, gpio);
41a18c49 AS	303
0ba19cfc BG	304	wg->set_irq_mask = false;
	305	wg->update \|= UPDATE_IRQ_MASK;
	306	}
	307
	308	static void wcove_irq_mask(struct irq_data *data)
	309	{
	310	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
	311	struct wcove_gpio *wg = gpiochip_get_data(chip);
f3019092	312	irq_hw_number_t gpio = irqd_to_hwirq(data);
0ba19cfc	313
f3019092	314	if (gpio >= WCOVE_GPIO_NUM)
3a02dc97 KS	315	return;
3a02dc97 KS	316
0ba19cfc BG	317	wg->set_irq_mask = true;
0ba19cfc BG	318	wg->update \|= UPDATE_IRQ_MASK;
41a18c49 AS	319
41a18c49 AS	320	gpiochip_disable_irq(chip, gpio);
0ba19cfc BG	321	}
0ba19cfc BG	322
41a18c49	323	static const struct irq_chip wcove_irqchip = {
0ba19cfc BG	324	.name = "Whiskey Cove",
	325	.irq_mask = wcove_irq_mask,
	326	.irq_unmask = wcove_irq_unmask,
	327	.irq_set_type = wcove_irq_type,
	328	.irq_bus_lock = wcove_bus_lock,
	329	.irq_bus_sync_unlock = wcove_bus_sync_unlock,
41a18c49 AS	330	.flags = IRQCHIP_IMMUTABLE,
41a18c49 AS	331	GPIOCHIP_IRQ_RESOURCE_HELPERS,
0ba19cfc BG	332	};
	333
	334	static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
	335	{
	336	struct wcove_gpio wg = (struct wcove_gpio )data;
5a2a46ae	337	unsigned int virq, gpio;
2edba74c	338	unsigned long pending;
0ba19cfc BG	339	u8 p[2];
	340
	341	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	342	dev_err(wg->dev, "Failed to read irq status register\n");
	343	return IRQ_NONE;
	344	}
	345
881ebd22	346	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	347	if (!pending)
	348	return IRQ_NONE;
	349
	350	/* Iterate until no interrupt is pending */
	351	while (pending) {
	352	/* One iteration is for all pending bits */
2edba74c	353	for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) {
5a2a46ae AS	354	unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask);
5a2a46ae AS	355
f0fbe7bc	356	virq = irq_find_mapping(wg->chip.irq.domain, gpio);
0ba19cfc	357	handle_nested_irq(virq);
5a2a46ae	358	regmap_set_bits(wg->regmap, reg, mask);
0ba19cfc BG	359	}
	360
	361	/* Next iteration */
	362	if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
	363	dev_err(wg->dev, "Failed to read irq status\n");
	364	break;
	365	}
	366
881ebd22	367	pending = (p[0] & GPIO_IRQ0_MASK) \| ((p[1] & GPIO_IRQ1_MASK) << 7);
0ba19cfc BG	368	}
	369
	370	return IRQ_HANDLED;
	371	}
	372
2b71b66a	373	static void wcove_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
0ba19cfc BG	374	{
	375	unsigned int ctlo, ctli, irq_mask, irq_status;
	376	struct wcove_gpio *wg = gpiochip_get_data(chip);
5a2a46ae	377	int gpio, mask, ret = 0;
0ba19cfc BG	378
0ba19cfc BG	379	for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
0ba19cfc BG	380	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
0ba19cfc BG	381	ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
2b71b66a AS	382	if (ret) {
	383	dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
	384	break;
	385	}
	386
5a2a46ae AS	387	ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
5a2a46ae AS	388	ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
0ba19cfc	389	if (ret) {
2b71b66a	390	dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
0ba19cfc BG	391	break;
	392	}
	393
0ba19cfc BG	394	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
	395	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	396	ctli & 0x1 ? "hi" : "lo",
	397	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	398	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	399	ctlo,
5a2a46ae AS	400	irq_mask & mask ? "mask " : "unmask",
5a2a46ae AS	401	irq_status & mask ? "pending" : " ");
0ba19cfc BG	402	}
	403	}
	404
	405	static int wcove_gpio_probe(struct platform_device *pdev)
	406	{
	407	struct intel_soc_pmic *pmic;
	408	struct wcove_gpio *wg;
	409	int virq, ret, irq;
	410	struct device *dev;
22f61d4e	411	struct gpio_irq_chip *girq;
0ba19cfc BG	412
	413	/*
	414	* This gpio platform device is created by a mfd device (see
	415	* drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
	416	* shared by all sub-devices created by the mfd device, the regmap
	417	* pointer for instance, is stored as driver data of the mfd device
	418	* driver.
	419	*/
	420	pmic = dev_get_drvdata(pdev->dev.parent);
	421	if (!pmic)
	422	return -ENODEV;
	423
	424	irq = platform_get_irq(pdev, 0);
	425	if (irq < 0)
	426	return irq;
	427
	428	dev = &pdev->dev;
	429
	430	wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
	431	if (!wg)
	432	return -ENOMEM;
	433
a1d28c59	434	wg->regmap_irq_chip = pmic->irq_chip_data;
0ba19cfc BG	435
	436	platform_set_drvdata(pdev, wg);
	437
	438	mutex_init(&wg->buslock);
	439	wg->chip.label = KBUILD_MODNAME;
	440	wg->chip.direction_input = wcove_gpio_dir_in;
	441	wg->chip.direction_output = wcove_gpio_dir_out;
7d9e59ce	442	wg->chip.get_direction = wcove_gpio_get_direction;
0ba19cfc BG	443	wg->chip.get = wcove_gpio_get;
0ba19cfc BG	444	wg->chip.set = wcove_gpio_set;
481a4209	445	wg->chip.set_config = wcove_gpio_set_config;
0ba19cfc BG	446	wg->chip.base = -1;
	447	wg->chip.ngpio = WCOVE_VGPIO_NUM;
	448	wg->chip.can_sleep = true;
	449	wg->chip.parent = pdev->dev.parent;
	450	wg->chip.dbg_show = wcove_gpio_dbg_show;
	451	wg->dev = dev;
	452	wg->regmap = pmic->regmap;
	453
0ba19cfc BG	454	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
	455	if (virq < 0) {
	456	dev_err(dev, "Failed to get virq by irq %d\n", irq);
	457	return virq;
	458	}
	459
22f61d4e	460	girq = &wg->chip.irq;
41a18c49	461	gpio_irq_chip_set_chip(girq, &wcove_irqchip);
22f61d4e LW	462	/* This will let us handle the parent IRQ in the driver */
	463	girq->parent_handler = NULL;
	464	girq->num_parents = 0;
	465	girq->parents = NULL;
	466	girq->default_type = IRQ_TYPE_NONE;
	467	girq->handler = handle_simple_irq;
	468	girq->threaded = true;
	469
22cc4220 AS	470	ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
	471	IRQF_ONESHOT, pdev->name, wg);
	472	if (ret) {
	473	dev_err(dev, "Failed to request irq %d\n", virq);
	474	return ret;
	475	}
	476
22f61d4e LW	477	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
	478	if (ret) {
	479	dev_err(dev, "Failed to add gpiochip: %d\n", ret);
	480	return ret;
	481	}
35ca3f61	482
a1d28c59	483	/* Enable GPIO0 interrupts */
9fe5fcd6	484	ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
a1d28c59 KS	485	if (ret)
	486	return ret;
	487
	488	/* Enable GPIO1 interrupts */
9fe5fcd6	489	ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);
a1d28c59 KS	490	if (ret)
	491	return ret;
	492
0ba19cfc BG	493	return 0;
	494	}
	495
	496	/*
	497	* Whiskey Cove PMIC itself is a analog device(but with digital control
	498	* interface) providing power management support for other devices in
	499	* the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
	500	*/
	501	static struct platform_driver wcove_gpio_driver = {
	502	.driver = {
	503	.name = "bxt_wcove_gpio",
	504	},
	505	.probe = wcove_gpio_probe,
	506	};
	507
	508	module_platform_driver(wcove_gpio_driver);
	509
	510	MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
	511	MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
	512	MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
	513	MODULE_LICENSE("GPL v2");
	514	MODULE_ALIAS("platform:bxt_wcove_gpio");