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2ad74f40 NI |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Toshiba Visconti GPIO Support | |
4 | * | |
5 | * (C) Copyright 2020 Toshiba Electronic Devices & Storage Corporation | |
6 | * (C) Copyright 2020 TOSHIBA CORPORATION | |
7 | * | |
8 | * Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> | |
9 | */ | |
10 | ||
11 | #include <linux/gpio/driver.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/platform_device.h> | |
5cf3e019 | 18 | #include <linux/seq_file.h> |
2ad74f40 NI |
19 | #include <linux/bitops.h> |
20 | ||
21 | /* register offset */ | |
22 | #define GPIO_DIR 0x00 | |
23 | #define GPIO_IDATA 0x08 | |
24 | #define GPIO_ODATA 0x10 | |
25 | #define GPIO_OSET 0x18 | |
26 | #define GPIO_OCLR 0x20 | |
27 | #define GPIO_INTMODE 0x30 | |
28 | ||
29 | #define BASE_HW_IRQ 24 | |
30 | ||
31 | struct visconti_gpio { | |
32 | void __iomem *base; | |
33 | spinlock_t lock; /* protect gpio register */ | |
34 | struct gpio_chip gpio_chip; | |
5cf3e019 | 35 | struct device *dev; |
2ad74f40 NI |
36 | }; |
37 | ||
38 | static int visconti_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
39 | { | |
40 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
41 | struct visconti_gpio *priv = gpiochip_get_data(gc); | |
42 | u32 offset = irqd_to_hwirq(d); | |
43 | u32 bit = BIT(offset); | |
44 | u32 intc_type = IRQ_TYPE_EDGE_RISING; | |
45 | u32 intmode, odata; | |
46 | int ret = 0; | |
47 | unsigned long flags; | |
48 | ||
49 | spin_lock_irqsave(&priv->lock, flags); | |
50 | ||
51 | odata = readl(priv->base + GPIO_ODATA); | |
52 | intmode = readl(priv->base + GPIO_INTMODE); | |
53 | ||
54 | switch (type) { | |
55 | case IRQ_TYPE_EDGE_RISING: | |
56 | odata &= ~bit; | |
57 | intmode &= ~bit; | |
58 | break; | |
59 | case IRQ_TYPE_EDGE_FALLING: | |
60 | odata |= bit; | |
61 | intmode &= ~bit; | |
62 | break; | |
63 | case IRQ_TYPE_EDGE_BOTH: | |
64 | intmode |= bit; | |
65 | break; | |
66 | case IRQ_TYPE_LEVEL_HIGH: | |
67 | intc_type = IRQ_TYPE_LEVEL_HIGH; | |
68 | odata &= ~bit; | |
69 | intmode &= ~bit; | |
70 | break; | |
71 | case IRQ_TYPE_LEVEL_LOW: | |
72 | intc_type = IRQ_TYPE_LEVEL_HIGH; | |
73 | odata |= bit; | |
74 | intmode &= ~bit; | |
75 | break; | |
76 | default: | |
77 | ret = -EINVAL; | |
78 | goto err; | |
79 | } | |
80 | ||
81 | writel(odata, priv->base + GPIO_ODATA); | |
82 | writel(intmode, priv->base + GPIO_INTMODE); | |
83 | irq_set_irq_type(offset, intc_type); | |
84 | ||
85 | ret = irq_chip_set_type_parent(d, type); | |
86 | err: | |
87 | spin_unlock_irqrestore(&priv->lock, flags); | |
88 | return ret; | |
89 | } | |
90 | ||
91 | static int visconti_gpio_child_to_parent_hwirq(struct gpio_chip *gc, | |
92 | unsigned int child, | |
93 | unsigned int child_type, | |
94 | unsigned int *parent, | |
95 | unsigned int *parent_type) | |
96 | { | |
97 | /* Interrupts 0..15 mapped to interrupts 24..39 on the GIC */ | |
98 | if (child < 16) { | |
99 | /* All these interrupts are level high in the CPU */ | |
100 | *parent_type = IRQ_TYPE_LEVEL_HIGH; | |
101 | *parent = child + BASE_HW_IRQ; | |
102 | return 0; | |
103 | } | |
104 | return -EINVAL; | |
105 | } | |
106 | ||
91a29af4 MZ |
107 | static int visconti_gpio_populate_parent_fwspec(struct gpio_chip *chip, |
108 | union gpio_irq_fwspec *gfwspec, | |
109 | unsigned int parent_hwirq, | |
110 | unsigned int parent_type) | |
2ad74f40 | 111 | { |
91a29af4 | 112 | struct irq_fwspec *fwspec = &gfwspec->fwspec; |
2ad74f40 NI |
113 | |
114 | fwspec->fwnode = chip->irq.parent_domain->fwnode; | |
115 | fwspec->param_count = 3; | |
116 | fwspec->param[0] = 0; | |
117 | fwspec->param[1] = parent_hwirq; | |
118 | fwspec->param[2] = parent_type; | |
119 | ||
91a29af4 | 120 | return 0; |
2ad74f40 NI |
121 | } |
122 | ||
5cf3e019 LW |
123 | static void visconti_gpio_mask_irq(struct irq_data *d) |
124 | { | |
125 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
126 | ||
127 | irq_chip_mask_parent(d); | |
128 | gpiochip_disable_irq(gc, irqd_to_hwirq(d)); | |
129 | } | |
130 | ||
131 | static void visconti_gpio_unmask_irq(struct irq_data *d) | |
132 | { | |
133 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
134 | ||
135 | gpiochip_enable_irq(gc, irqd_to_hwirq(d)); | |
136 | irq_chip_unmask_parent(d); | |
137 | } | |
138 | ||
139 | static void visconti_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) | |
140 | { | |
141 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
142 | struct visconti_gpio *priv = gpiochip_get_data(gc); | |
143 | ||
144 | seq_printf(p, dev_name(priv->dev)); | |
145 | } | |
146 | ||
147 | static const struct irq_chip visconti_gpio_irq_chip = { | |
148 | .irq_mask = visconti_gpio_mask_irq, | |
149 | .irq_unmask = visconti_gpio_unmask_irq, | |
150 | .irq_eoi = irq_chip_eoi_parent, | |
151 | .irq_set_type = visconti_gpio_irq_set_type, | |
152 | .irq_print_chip = visconti_gpio_irq_print_chip, | |
153 | .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND | | |
154 | IRQCHIP_IMMUTABLE, | |
155 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
156 | }; | |
157 | ||
2ad74f40 NI |
158 | static int visconti_gpio_probe(struct platform_device *pdev) |
159 | { | |
160 | struct device *dev = &pdev->dev; | |
161 | struct visconti_gpio *priv; | |
2ad74f40 NI |
162 | struct gpio_irq_chip *girq; |
163 | struct irq_domain *parent; | |
164 | struct device_node *irq_parent; | |
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165 | int ret; |
166 | ||
167 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
168 | if (!priv) | |
169 | return -ENOMEM; | |
170 | ||
171 | spin_lock_init(&priv->lock); | |
5cf3e019 | 172 | priv->dev = dev; |
2ad74f40 NI |
173 | |
174 | priv->base = devm_platform_ioremap_resource(pdev, 0); | |
175 | if (IS_ERR(priv->base)) | |
176 | return PTR_ERR(priv->base); | |
177 | ||
178 | irq_parent = of_irq_find_parent(dev->of_node); | |
179 | if (!irq_parent) { | |
180 | dev_err(dev, "No IRQ parent node\n"); | |
181 | return -ENODEV; | |
182 | } | |
183 | ||
184 | parent = irq_find_host(irq_parent); | |
171865da | 185 | of_node_put(irq_parent); |
2ad74f40 NI |
186 | if (!parent) { |
187 | dev_err(dev, "No IRQ parent domain\n"); | |
188 | return -ENODEV; | |
189 | } | |
190 | ||
2ad74f40 NI |
191 | ret = bgpio_init(&priv->gpio_chip, dev, 4, |
192 | priv->base + GPIO_IDATA, | |
193 | priv->base + GPIO_OSET, | |
194 | priv->base + GPIO_OCLR, | |
195 | priv->base + GPIO_DIR, | |
196 | NULL, | |
197 | 0); | |
198 | if (ret) { | |
199 | dev_err(dev, "unable to init generic GPIO\n"); | |
200 | return ret; | |
201 | } | |
202 | ||
2ad74f40 | 203 | girq = &priv->gpio_chip.irq; |
5cf3e019 | 204 | gpio_irq_chip_set_chip(girq, &visconti_gpio_irq_chip); |
171865da | 205 | girq->fwnode = of_node_to_fwnode(dev->of_node); |
2ad74f40 NI |
206 | girq->parent_domain = parent; |
207 | girq->child_to_parent_hwirq = visconti_gpio_child_to_parent_hwirq; | |
208 | girq->populate_parent_alloc_arg = visconti_gpio_populate_parent_fwspec; | |
209 | girq->default_type = IRQ_TYPE_NONE; | |
210 | girq->handler = handle_level_irq; | |
211 | ||
ec5aa31b | 212 | return devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); |
2ad74f40 NI |
213 | } |
214 | ||
215 | static const struct of_device_id visconti_gpio_of_match[] = { | |
216 | { .compatible = "toshiba,gpio-tmpv7708", }, | |
217 | { /* end of table */ } | |
218 | }; | |
219 | MODULE_DEVICE_TABLE(of, visconti_gpio_of_match); | |
220 | ||
221 | static struct platform_driver visconti_gpio_driver = { | |
222 | .probe = visconti_gpio_probe, | |
223 | .driver = { | |
224 | .name = "visconti_gpio", | |
b39cf819 | 225 | .of_match_table = visconti_gpio_of_match, |
2ad74f40 NI |
226 | } |
227 | }; | |
228 | module_platform_driver(visconti_gpio_driver); | |
229 | ||
230 | MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>"); | |
231 | MODULE_DESCRIPTION("Toshiba Visconti GPIO Driver"); | |
232 | MODULE_LICENSE("GPL v2"); |