[linux-2.6-block.git] / drivers / gpio / gpio-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <stefan@agner.ch>.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>

#define VF610_GPIO_PER_PORT		32

struct fsl_gpio_soc_data {
	/* SoCs has a Port Data Direction Register (PDDR) */
	bool have_paddr;
	bool have_dual_base;
};

struct vf610_gpio_port {
	struct gpio_chip gc;
	void __iomem *base;
	void __iomem *gpio_base;
	const struct fsl_gpio_soc_data *sdata;
	u8 irqc[VF610_GPIO_PER_PORT];
	struct clk *clk_port;
	struct clk *clk_gpio;
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10
#define GPIO_PDDR		0x14

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

#define IMX8ULP_GPIO_BASE_OFF	0x40
#define IMX8ULP_BASE_OFF	0x80

static const struct fsl_gpio_soc_data vf610_data = {
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx_data = {
	.have_paddr = true,
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx8ulp_data = {
	.have_paddr = true,
};

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio",	.data = &vf610_data },
	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
	{ .compatible = "fsl,imx8ulp-gpio",	.data = &imx8ulp_data, },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = BIT(gpio);
	unsigned long offset = GPIO_PDIR;

	if (port->sdata->have_paddr) {
		mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		if (mask)
			offset = GPIO_PDOR;
	}

	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
}

static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = BIT(gpio);
	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;

	vf610_gpio_writel(mask, port->gpio_base + offset);
}

static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	u32 mask = BIT(gpio);
	u32 val;

	if (port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val &= ~mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_input(chip, gpio);
}

static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
				       int value)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	u32 mask = BIT(gpio);
	u32 val;

	vf610_gpio_set(chip, gpio, value);

	if (port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val |= mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_output(chip, gpio);
}

static int vf610_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = BIT(gpio);

	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);

	if (mask)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_domain_irq(port->gc.irq.domain, pin);
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	vf610_gpio_writel(0, pcr_base);
	gpiochip_disable_irq(gc, gpio_num);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	gpiochip_enable_irq(gc, gpio_num);
	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static const struct irq_chip vf610_irqchip = {
	.name = "gpio-vf610",
	.irq_ack = vf610_gpio_irq_ack,
	.irq_mask = vf610_gpio_irq_mask,
	.irq_unmask = vf610_gpio_irq_unmask,
	.irq_set_type = vf610_gpio_irq_set_type,
	.irq_set_wake = vf610_gpio_irq_set_wake,
	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
			| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void vf610_gpio_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct vf610_gpio_port *port;
	struct gpio_chip *gc;
	struct gpio_irq_chip *girq;
	int i;
	int ret;
	bool dual_base;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->sdata = of_device_get_match_data(dev);

	dual_base = port->sdata->have_dual_base;

	/*
	 * Handle legacy compatible combinations which used two reg values
	 * for the i.MX8ULP and i.MX93.
	 */
	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	    (device_is_compatible(dev, "fsl,imx93-gpio") ||
	    (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
		dual_base = true;

	if (dual_base) {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
		if (IS_ERR(port->gpio_base))
			return PTR_ERR(port->gpio_base);
	} else {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
		port->base = port->base + IMX8ULP_BASE_OFF;
	}

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	port->clk_port = devm_clk_get(dev, "port");
	ret = PTR_ERR_OR_ZERO(port->clk_port);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_port);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_port);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return ret;
	}

	port->clk_gpio = devm_clk_get(dev, "gpio");
	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_gpio);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_gpio);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		return ret;
	}

	gc = &port->gc;
	gc->parent = dev;
	gc->label = dev_name(dev);
	gc->ngpio = VF610_GPIO_PER_PORT;
	gc->base = -1;

	gc->request = gpiochip_generic_request;
	gc->free = gpiochip_generic_free;
	gc->direction_input = vf610_gpio_direction_input;
	gc->get = vf610_gpio_get;
	gc->direction_output = vf610_gpio_direction_output;
	gc->set = vf610_gpio_set;
	/*
	 * only IP has Port Data Direction Register(PDDR) can
	 * support get direction
	 */
	if (port->sdata->have_paddr)
		gc->get_direction = vf610_gpio_get_direction;

	/* Mask all GPIO interrupts */
	for (i = 0; i < gc->ngpio; i++)
		vf610_gpio_writel(0, port->base + PORT_PCR(i));

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	girq = &gc->irq;
	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
	girq->parent_handler = vf610_gpio_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1,
				     sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = port->irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;

	return devm_gpiochip_add_data(dev, gc, port);
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

builtin_platform_driver(vf610_gpio_driver);
Commit	Line	Data
36e2add1	1	// SPDX-License-Identifier: GPL-2.0+
7f2691a1	2	/*
adaaf63e	3	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	4	*
	5	* Copyright (c) 2014 Toradex AG.
	6	*
	7	* Author: Stefan Agner <stefan@agner.ch>.
7f2691a1	8	*/
7f2691a1	9	#include <linux/bitops.h>
91393622	10	#include <linux/clk.h>
7f2691a1	11	#include <linux/err.h>
45e8296c	12	#include <linux/gpio/driver.h>
7f2691a1 SA	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
7f2691a1 SA	18	#include <linux/platform_device.h>
7f2691a1 SA	19	#include <linux/of.h>
7f2691a1	20	#include <linux/of_irq.h>
8af3a0b2	21	#include <linux/pinctrl/consumer.h>
7f2691a1 SA	22
	23	#define VF610_GPIO_PER_PORT 32
	24
659d8a62 DA	25	struct fsl_gpio_soc_data {
	26	/* SoCs has a Port Data Direction Register (PDDR) */
	27	bool have_paddr;
76bc907b	28	bool have_dual_base;
659d8a62 DA	29	};
659d8a62 DA	30
7f2691a1 SA	31	struct vf610_gpio_port {
	32	struct gpio_chip gc;
	33	void __iomem *base;
	34	void __iomem *gpio_base;
659d8a62	35	const struct fsl_gpio_soc_data *sdata;
7f2691a1	36	u8 irqc[VF610_GPIO_PER_PORT];
91393622 D	37	struct clk *clk_port;
91393622 D	38	struct clk *clk_gpio;
7f2691a1 SA	39	int irq;
	40	};
	41
	42	#define GPIO_PDOR 0x00
	43	#define GPIO_PSOR 0x04
	44	#define GPIO_PCOR 0x08
	45	#define GPIO_PTOR 0x0c
	46	#define GPIO_PDIR 0x10
659d8a62	47	#define GPIO_PDDR 0x14
7f2691a1 SA	48
	49	#define PORT_PCR(n) ((n) * 0x4)
	50	#define PORT_PCR_IRQC_OFFSET 16
	51
	52	#define PORT_ISFR 0xa0
	53	#define PORT_DFER 0xc0
	54	#define PORT_DFCR 0xc4
	55	#define PORT_DFWR 0xc8
	56
	57	#define PORT_INT_OFF 0x0
	58	#define PORT_INT_LOGIC_ZERO 0x8
	59	#define PORT_INT_RISING_EDGE 0x9
	60	#define PORT_INT_FALLING_EDGE 0xa
	61	#define PORT_INT_EITHER_EDGE 0xb
	62	#define PORT_INT_LOGIC_ONE 0xc
	63
76bc907b PF	64	#define IMX8ULP_GPIO_BASE_OFF 0x40
	65	#define IMX8ULP_BASE_OFF 0x80
	66
	67	static const struct fsl_gpio_soc_data vf610_data = {
	68	.have_dual_base = true,
	69	};
	70
659d8a62 DA	71	static const struct fsl_gpio_soc_data imx_data = {
659d8a62 DA	72	.have_paddr = true,
76bc907b PF	73	.have_dual_base = true,
	74	};
	75
	76	static const struct fsl_gpio_soc_data imx8ulp_data = {
	77	.have_paddr = true,
659d8a62 DA	78	};
659d8a62 DA	79
7f2691a1	80	static const struct of_device_id vf610_gpio_dt_ids[] = {
76bc907b	81	{ .compatible = "fsl,vf610-gpio", .data = &vf610_data },
659d8a62	82	{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
76bc907b	83	{ .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
7f2691a1 SA	84	{ /* sentinel */ }
	85	};
	86
	87	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	88	{
	89	writel_relaxed(val, reg);
	90	}
	91
	92	static inline u32 vf610_gpio_readl(void __iomem *reg)
	93	{
	94	return readl_relaxed(reg);
	95	}
	96
7f2691a1 SA	97	static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
7f2691a1 SA	98	{
65389b49	99	struct vf610_gpio_port *port = gpiochip_get_data(gc);
3e7ebf27	100	u32 mask = BIT(gpio);
4a8909d0	101	unsigned long offset = GPIO_PDIR;
659d8a62	102
b57587f1	103	if (port->sdata->have_paddr) {
659d8a62	104	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
4a8909d0 AS	105	if (mask)
4a8909d0 AS	106	offset = GPIO_PDOR;
659d8a62	107	}
4a8909d0 AS	108
4a8909d0 AS	109	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
7f2691a1 SA	110	}
	111
	112	static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	113	{
65389b49	114	struct vf610_gpio_port *port = gpiochip_get_data(gc);
3e7ebf27	115	u32 mask = BIT(gpio);
a262555b	116	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
7f2691a1	117
a262555b	118	vf610_gpio_writel(mask, port->gpio_base + offset);
7f2691a1 SA	119	}
7f2691a1 SA	120
3e7ebf27	121	static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
7f2691a1	122	{
659d8a62	123	struct vf610_gpio_port *port = gpiochip_get_data(chip);
3e7ebf27	124	u32 mask = BIT(gpio);
659d8a62 DA	125	u32 val;
659d8a62 DA	126
b57587f1	127	if (port->sdata->have_paddr) {
659d8a62 DA	128	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	129	val &= ~mask;
	130	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	131	}
	132
315c46f9	133	return pinctrl_gpio_direction_input(chip, gpio);
7f2691a1 SA	134	}
7f2691a1 SA	135
3e7ebf27	136	static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
7f2691a1 SA	137	int value)
7f2691a1 SA	138	{
659d8a62	139	struct vf610_gpio_port *port = gpiochip_get_data(chip);
3e7ebf27	140	u32 mask = BIT(gpio);
9bf3ac46	141	u32 val;
659d8a62	142
fc363413 HC	143	vf610_gpio_set(chip, gpio, value);
fc363413 HC	144
b57587f1	145	if (port->sdata->have_paddr) {
9bf3ac46 HC	146	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	147	val \|= mask;
	148	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	149	}
659d8a62	150
b679d6c0	151	return pinctrl_gpio_direction_output(chip, gpio);
7f2691a1 SA	152	}
7f2691a1 SA	153
26b95b7b HC	154	static int vf610_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
	155	{
	156	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	157	u32 mask = BIT(gpio);
	158
	159	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	160
	161	if (mask)
	162	return GPIO_LINE_DIRECTION_OUT;
	163
	164	return GPIO_LINE_DIRECTION_IN;
	165	}
	166
bd0b9ac4	167	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	168	{
2f930643	169	struct vf610_gpio_port *port =
65389b49	170	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	171	struct irq_chip *chip = irq_desc_get_chip(desc);
	172	int pin;
	173	unsigned long irq_isfr;
	174
	175	chained_irq_enter(chip, desc);
	176
	177	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	178
	179	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	180	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	181
dbd1c54f	182	generic_handle_domain_irq(port->gc.irq.domain, pin);
7f2691a1 SA	183	}
	184
	185	chained_irq_exit(chip, desc);
	186	}
	187
	188	static void vf610_gpio_irq_ack(struct irq_data *d)
	189	{
2f930643	190	struct vf610_gpio_port *port =
65389b49	191	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	192	int gpio = d->hwirq;
	193
	194	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	195	}
	196
	197	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	198	{
2f930643	199	struct vf610_gpio_port *port =
65389b49	200	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	201	u8 irqc;
	202
	203	switch (type) {
	204	case IRQ_TYPE_EDGE_RISING:
	205	irqc = PORT_INT_RISING_EDGE;
	206	break;
	207	case IRQ_TYPE_EDGE_FALLING:
	208	irqc = PORT_INT_FALLING_EDGE;
	209	break;
	210	case IRQ_TYPE_EDGE_BOTH:
	211	irqc = PORT_INT_EITHER_EDGE;
	212	break;
	213	case IRQ_TYPE_LEVEL_LOW:
	214	irqc = PORT_INT_LOGIC_ZERO;
	215	break;
	216	case IRQ_TYPE_LEVEL_HIGH:
	217	irqc = PORT_INT_LOGIC_ONE;
	218	break;
	219	default:
	220	return -EINVAL;
	221	}
	222
	223	port->irqc[d->hwirq] = irqc;
	224
fd968115	225	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	226	irq_set_handler_locked(d, handle_level_irq);
fd968115	227	else
a7147db0	228	irq_set_handler_locked(d, handle_edge_irq);
fd968115	229
7f2691a1 SA	230	return 0;
	231	}
	232
	233	static void vf610_gpio_irq_mask(struct irq_data *d)
	234	{
e6ef4f8e AS	235	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	236	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	237	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	238	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1 SA	239
7f2691a1 SA	240	vf610_gpio_writel(0, pcr_base);
e6ef4f8e	241	gpiochip_disable_irq(gc, gpio_num);
7f2691a1 SA	242	}
	243
	244	static void vf610_gpio_irq_unmask(struct irq_data *d)
	245	{
e6ef4f8e AS	246	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	247	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	248	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	249	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1	250
e6ef4f8e AS	251	gpiochip_enable_irq(gc, gpio_num);
e6ef4f8e AS	252	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
7f2691a1 SA	253	pcr_base);
	254	}
	255
	256	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	257	{
2f930643	258	struct vf610_gpio_port *port =
65389b49	259	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	260
	261	if (enable)
	262	enable_irq_wake(port->irq);
	263	else
	264	disable_irq_wake(port->irq);
	265
	266	return 0;
	267	}
	268
e6ef4f8e AS	269	static const struct irq_chip vf610_irqchip = {
	270	.name = "gpio-vf610",
	271	.irq_ack = vf610_gpio_irq_ack,
	272	.irq_mask = vf610_gpio_irq_mask,
	273	.irq_unmask = vf610_gpio_irq_unmask,
	274	.irq_set_type = vf610_gpio_irq_set_type,
	275	.irq_set_wake = vf610_gpio_irq_set_wake,
43023261 HC	276	.flags = IRQCHIP_IMMUTABLE \| IRQCHIP_MASK_ON_SUSPEND
43023261 HC	277	\| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
e6ef4f8e AS	278	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	279	};
	280
db9ed63c AS	281	static void vf610_gpio_disable_clk(void *data)
	282	{
	283	clk_disable_unprepare(data);
	284	}
7f2691a1 SA	285
	286	static int vf610_gpio_probe(struct platform_device *pdev)
	287	{
	288	struct device *dev = &pdev->dev;
7f2691a1	289	struct vf610_gpio_port *port;
7f2691a1	290	struct gpio_chip *gc;
e599256a	291	struct gpio_irq_chip *girq;
7ae710f9	292	int i;
7f2691a1	293	int ret;
76bc907b	294	bool dual_base;
7f2691a1	295
2e35bb6c	296	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
7f2691a1 SA	297	if (!port)
	298	return -ENOMEM;
	299
23e577eb	300	port->sdata = of_device_get_match_data(dev);
7f2691a1	301
76bc907b PF	302	dual_base = port->sdata->have_dual_base;
76bc907b PF	303
8a58cd57 PF	304	/*
	305	* Handle legacy compatible combinations which used two reg values
	306	* for the i.MX8ULP and i.MX93.
	307	*/
76bc907b PF	308	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	309	(device_is_compatible(dev, "fsl,imx93-gpio") \|\|
	310	(device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
	311	dual_base = true;
	312
	313	if (dual_base) {
	314	port->base = devm_platform_ioremap_resource(pdev, 0);
	315	if (IS_ERR(port->base))
	316	return PTR_ERR(port->base);
	317
	318	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
	319	if (IS_ERR(port->gpio_base))
	320	return PTR_ERR(port->gpio_base);
	321	} else {
	322	port->base = devm_platform_ioremap_resource(pdev, 0);
	323	if (IS_ERR(port->base))
	324	return PTR_ERR(port->base);
	325
	326	port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
	327	port->base = port->base + IMX8ULP_BASE_OFF;
	328	}
7f2691a1 SA	329
	330	port->irq = platform_get_irq(pdev, 0);
	331	if (port->irq < 0)
	332	return port->irq;
	333
2e35bb6c	334	port->clk_port = devm_clk_get(dev, "port");
663ba742 AS	335	ret = PTR_ERR_OR_ZERO(port->clk_port);
663ba742 AS	336	if (!ret) {
91393622 D	337	ret = clk_prepare_enable(port->clk_port);
	338	if (ret)
	339	return ret;
db9ed63c AS	340	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	341	port->clk_port);
	342	if (ret)
	343	return ret;
663ba742	344	} else if (ret == -EPROBE_DEFER) {
91393622 D	345	/*
	346	* Percolate deferrals, for anything else,
	347	* just live without the clocking.
	348	*/
663ba742	349	return ret;
91393622 D	350	}
91393622 D	351
2e35bb6c	352	port->clk_gpio = devm_clk_get(dev, "gpio");
663ba742 AS	353	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
663ba742 AS	354	if (!ret) {
91393622	355	ret = clk_prepare_enable(port->clk_gpio);
db9ed63c	356	if (ret)
91393622	357	return ret;
fc57949c AS	358	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	359	port->clk_gpio);
	360	if (ret)
91393622	361	return ret;
663ba742 AS	362	} else if (ret == -EPROBE_DEFER) {
663ba742 AS	363	return ret;
91393622 D	364	}
91393622 D	365
7f2691a1	366	gc = &port->gc;
58383c78	367	gc->parent = dev;
6f8ecb7f	368	gc->label = dev_name(dev);
d32efe37	369	gc->ngpio = VF610_GPIO_PER_PORT;
bb5ad5ef	370	gc->base = -1;
7f2691a1	371
203f0daa JG	372	gc->request = gpiochip_generic_request;
203f0daa JG	373	gc->free = gpiochip_generic_free;
d32efe37 AL	374	gc->direction_input = vf610_gpio_direction_input;
	375	gc->get = vf610_gpio_get;
	376	gc->direction_output = vf610_gpio_direction_output;
	377	gc->set = vf610_gpio_set;
26b95b7b HC	378	/*
	379	* only IP has Port Data Direction Register(PDDR) can
	380	* support get direction
	381	*/
	382	if (port->sdata->have_paddr)
	383	gc->get_direction = vf610_gpio_get_direction;
7f2691a1	384
7ae710f9 AL	385	/* Mask all GPIO interrupts */
	386	for (i = 0; i < gc->ngpio; i++)
	387	vf610_gpio_writel(0, port->base + PORT_PCR(i));
	388
7f2691a1 SA	389	/* Clear the interrupt status register for all GPIO's */
	390	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	391
e599256a	392	girq = &gc->irq;
e6ef4f8e	393	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
e599256a LW	394	girq->parent_handler = vf610_gpio_irq_handler;
	395	girq->num_parents = 1;
	396	girq->parents = devm_kcalloc(&pdev->dev, 1,
	397	sizeof(*girq->parents),
	398	GFP_KERNEL);
	399	if (!girq->parents)
	400	return -ENOMEM;
	401	girq->parents[0] = port->irq;
	402	girq->default_type = IRQ_TYPE_NONE;
	403	girq->handler = handle_edge_irq;
7f2691a1	404
e599256a	405	return devm_gpiochip_add_data(dev, gc, port);
7f2691a1 SA	406	}
	407
	408	static struct platform_driver vf610_gpio_driver = {
	409	.driver = {
	410	.name = "gpio-vf610",
7f2691a1 SA	411	.of_match_table = vf610_gpio_dt_ids,
	412	},
	413	.probe = vf610_gpio_probe,
	414	};
	415
df950da1	416	builtin_platform_driver(vf610_gpio_driver);