[linux-2.6-block.git] / drivers / gpio / gpio-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <stefan@agner.ch>.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/property.h>

#define VF610_GPIO_PER_PORT		32

struct fsl_gpio_soc_data {
	/* SoCs has a Port Data Direction Register (PDDR) */
	bool have_paddr;
	bool have_dual_base;
};

struct vf610_gpio_port {
	struct gpio_chip gc;
	void __iomem *base;
	void __iomem *gpio_base;
	const struct fsl_gpio_soc_data *sdata;
	u8 irqc[VF610_GPIO_PER_PORT];
	struct clk *clk_port;
	struct clk *clk_gpio;
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10
#define GPIO_PDDR		0x14

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

#define IMX8ULP_GPIO_BASE_OFF	0x40
#define IMX8ULP_BASE_OFF	0x80

static const struct fsl_gpio_soc_data vf610_data = {
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx_data = {
	.have_paddr = true,
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx8ulp_data = {
	.have_paddr = true,
};

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio",	.data = &vf610_data },
	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
	{ .compatible = "fsl,imx8ulp-gpio",	.data = &imx8ulp_data, },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_domain_irq(port->gc.irq.domain, pin);
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	vf610_gpio_writel(0, pcr_base);
	gpiochip_disable_irq(gc, gpio_num);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	gpiochip_enable_irq(gc, gpio_num);
	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static const struct irq_chip vf610_irqchip = {
	.name = "gpio-vf610",
	.irq_ack = vf610_gpio_irq_ack,
	.irq_mask = vf610_gpio_irq_mask,
	.irq_unmask = vf610_gpio_irq_unmask,
	.irq_set_type = vf610_gpio_irq_set_type,
	.irq_set_wake = vf610_gpio_irq_set_wake,
	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
			| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void vf610_gpio_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct vf610_gpio_port *port;
	struct gpio_chip *gc;
	struct gpio_irq_chip *girq;
	unsigned long flags;
	int i;
	int ret;
	bool dual_base;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->sdata = device_get_match_data(dev);

	dual_base = port->sdata->have_dual_base;

	/*
	 * Handle legacy compatible combinations which used two reg values
	 * for the i.MX8ULP and i.MX93.
	 */
	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	    (device_is_compatible(dev, "fsl,imx93-gpio") ||
	    (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
		dual_base = true;

	if (dual_base) {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
		if (IS_ERR(port->gpio_base))
			return PTR_ERR(port->gpio_base);
	} else {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
		port->base = port->base + IMX8ULP_BASE_OFF;
	}

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	port->clk_port = devm_clk_get(dev, "port");
	ret = PTR_ERR_OR_ZERO(port->clk_port);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_port);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_port);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return ret;
	}

	port->clk_gpio = devm_clk_get(dev, "gpio");
	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_gpio);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_gpio);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		return ret;
	}

	gc = &port->gc;
	flags = BGPIOF_PINCTRL_BACKEND;
	/*
	 * We only read the output register for current value on output
	 * lines if the direction register is available so we can switch
	 * direction.
	 */
	if (port->sdata->have_paddr)
		flags |= BGPIOF_READ_OUTPUT_REG_SET;
	ret = bgpio_init(gc, dev, 4,
			 port->gpio_base + GPIO_PDIR,
			 port->gpio_base + GPIO_PDOR,
			 NULL,
			 port->sdata->have_paddr ? port->gpio_base + GPIO_PDDR : NULL,
			 NULL,
			 flags);
	if (ret)
		return dev_err_probe(dev, ret, "unable to init generic GPIO\n");
	gc->label = dev_name(dev);
	gc->base = -1;

	/* Mask all GPIO interrupts */
	for (i = 0; i < gc->ngpio; i++)
		vf610_gpio_writel(0, port->base + PORT_PCR(i));

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	girq = &gc->irq;
	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
	girq->parent_handler = vf610_gpio_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1,
				     sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = port->irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;

	return devm_gpiochip_add_data(dev, gc, port);
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

module_platform_driver(vf610_gpio_driver);
MODULE_DESCRIPTION("VF610 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
36e2add1	1	// SPDX-License-Identifier: GPL-2.0+
7f2691a1	2	/*
adaaf63e	3	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	4	*
	5	* Copyright (c) 2014 Toradex AG.
	6	*
	7	* Author: Stefan Agner <stefan@agner.ch>.
7f2691a1	8	*/
7f2691a1	9	#include <linux/bitops.h>
91393622	10	#include <linux/clk.h>
7f2691a1	11	#include <linux/err.h>
45e8296c	12	#include <linux/gpio/driver.h>
7f2691a1 SA	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
8af3a0b2	18	#include <linux/pinctrl/consumer.h>
1b35c124 BG	19	#include <linux/platform_device.h>
1b35c124 BG	20	#include <linux/property.h>
7f2691a1 SA	21
	22	#define VF610_GPIO_PER_PORT 32
	23
659d8a62 DA	24	struct fsl_gpio_soc_data {
	25	/* SoCs has a Port Data Direction Register (PDDR) */
	26	bool have_paddr;
76bc907b	27	bool have_dual_base;
659d8a62 DA	28	};
659d8a62 DA	29
7f2691a1 SA	30	struct vf610_gpio_port {
	31	struct gpio_chip gc;
	32	void __iomem *base;
	33	void __iomem *gpio_base;
659d8a62	34	const struct fsl_gpio_soc_data *sdata;
7f2691a1	35	u8 irqc[VF610_GPIO_PER_PORT];
91393622 D	36	struct clk *clk_port;
91393622 D	37	struct clk *clk_gpio;
7f2691a1 SA	38	int irq;
	39	};
	40
	41	#define GPIO_PDOR 0x00
	42	#define GPIO_PSOR 0x04
	43	#define GPIO_PCOR 0x08
	44	#define GPIO_PTOR 0x0c
	45	#define GPIO_PDIR 0x10
659d8a62	46	#define GPIO_PDDR 0x14
7f2691a1 SA	47
	48	#define PORT_PCR(n) ((n) * 0x4)
	49	#define PORT_PCR_IRQC_OFFSET 16
	50
	51	#define PORT_ISFR 0xa0
	52	#define PORT_DFER 0xc0
	53	#define PORT_DFCR 0xc4
	54	#define PORT_DFWR 0xc8
	55
	56	#define PORT_INT_OFF 0x0
	57	#define PORT_INT_LOGIC_ZERO 0x8
	58	#define PORT_INT_RISING_EDGE 0x9
	59	#define PORT_INT_FALLING_EDGE 0xa
	60	#define PORT_INT_EITHER_EDGE 0xb
	61	#define PORT_INT_LOGIC_ONE 0xc
	62
76bc907b PF	63	#define IMX8ULP_GPIO_BASE_OFF 0x40
	64	#define IMX8ULP_BASE_OFF 0x80
	65
	66	static const struct fsl_gpio_soc_data vf610_data = {
	67	.have_dual_base = true,
	68	};
	69
659d8a62 DA	70	static const struct fsl_gpio_soc_data imx_data = {
659d8a62 DA	71	.have_paddr = true,
76bc907b PF	72	.have_dual_base = true,
	73	};
	74
	75	static const struct fsl_gpio_soc_data imx8ulp_data = {
	76	.have_paddr = true,
659d8a62 DA	77	};
659d8a62 DA	78
7f2691a1	79	static const struct of_device_id vf610_gpio_dt_ids[] = {
76bc907b	80	{ .compatible = "fsl,vf610-gpio", .data = &vf610_data },
659d8a62	81	{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
76bc907b	82	{ .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
7f2691a1 SA	83	{ /* sentinel */ }
	84	};
	85
	86	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	87	{
	88	writel_relaxed(val, reg);
	89	}
	90
	91	static inline u32 vf610_gpio_readl(void __iomem *reg)
	92	{
	93	return readl_relaxed(reg);
	94	}
	95
bd0b9ac4	96	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	97	{
2f930643	98	struct vf610_gpio_port *port =
65389b49	99	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	100	struct irq_chip *chip = irq_desc_get_chip(desc);
	101	int pin;
	102	unsigned long irq_isfr;
	103
	104	chained_irq_enter(chip, desc);
	105
	106	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	107
	108	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	109	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	110
dbd1c54f	111	generic_handle_domain_irq(port->gc.irq.domain, pin);
7f2691a1 SA	112	}
	113
	114	chained_irq_exit(chip, desc);
	115	}
	116
	117	static void vf610_gpio_irq_ack(struct irq_data *d)
	118	{
2f930643	119	struct vf610_gpio_port *port =
65389b49	120	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	121	int gpio = d->hwirq;
	122
	123	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	124	}
	125
	126	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	127	{
2f930643	128	struct vf610_gpio_port *port =
65389b49	129	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	130	u8 irqc;
	131
	132	switch (type) {
	133	case IRQ_TYPE_EDGE_RISING:
	134	irqc = PORT_INT_RISING_EDGE;
	135	break;
	136	case IRQ_TYPE_EDGE_FALLING:
	137	irqc = PORT_INT_FALLING_EDGE;
	138	break;
	139	case IRQ_TYPE_EDGE_BOTH:
	140	irqc = PORT_INT_EITHER_EDGE;
	141	break;
	142	case IRQ_TYPE_LEVEL_LOW:
	143	irqc = PORT_INT_LOGIC_ZERO;
	144	break;
	145	case IRQ_TYPE_LEVEL_HIGH:
	146	irqc = PORT_INT_LOGIC_ONE;
	147	break;
	148	default:
	149	return -EINVAL;
	150	}
	151
	152	port->irqc[d->hwirq] = irqc;
	153
fd968115	154	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	155	irq_set_handler_locked(d, handle_level_irq);
fd968115	156	else
a7147db0	157	irq_set_handler_locked(d, handle_edge_irq);
fd968115	158
7f2691a1 SA	159	return 0;
	160	}
	161
	162	static void vf610_gpio_irq_mask(struct irq_data *d)
	163	{
e6ef4f8e AS	164	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	165	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	166	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	167	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1 SA	168
7f2691a1 SA	169	vf610_gpio_writel(0, pcr_base);
e6ef4f8e	170	gpiochip_disable_irq(gc, gpio_num);
7f2691a1 SA	171	}
	172
	173	static void vf610_gpio_irq_unmask(struct irq_data *d)
	174	{
e6ef4f8e AS	175	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	176	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	177	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	178	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1	179
e6ef4f8e AS	180	gpiochip_enable_irq(gc, gpio_num);
e6ef4f8e AS	181	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
7f2691a1 SA	182	pcr_base);
	183	}
	184
	185	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	186	{
2f930643	187	struct vf610_gpio_port *port =
65389b49	188	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	189
	190	if (enable)
	191	enable_irq_wake(port->irq);
	192	else
	193	disable_irq_wake(port->irq);
	194
	195	return 0;
	196	}
	197
e6ef4f8e AS	198	static const struct irq_chip vf610_irqchip = {
	199	.name = "gpio-vf610",
	200	.irq_ack = vf610_gpio_irq_ack,
	201	.irq_mask = vf610_gpio_irq_mask,
	202	.irq_unmask = vf610_gpio_irq_unmask,
	203	.irq_set_type = vf610_gpio_irq_set_type,
	204	.irq_set_wake = vf610_gpio_irq_set_wake,
43023261 HC	205	.flags = IRQCHIP_IMMUTABLE \| IRQCHIP_MASK_ON_SUSPEND
43023261 HC	206	\| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
e6ef4f8e AS	207	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	208	};
	209
db9ed63c AS	210	static void vf610_gpio_disable_clk(void *data)
	211	{
	212	clk_disable_unprepare(data);
	213	}
7f2691a1 SA	214
	215	static int vf610_gpio_probe(struct platform_device *pdev)
	216	{
	217	struct device *dev = &pdev->dev;
7f2691a1	218	struct vf610_gpio_port *port;
7f2691a1	219	struct gpio_chip *gc;
e599256a	220	struct gpio_irq_chip *girq;
da5dd31e	221	unsigned long flags;
7ae710f9	222	int i;
7f2691a1	223	int ret;
76bc907b	224	bool dual_base;
7f2691a1	225
2e35bb6c	226	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
7f2691a1 SA	227	if (!port)
	228	return -ENOMEM;
	229
1b35c124	230	port->sdata = device_get_match_data(dev);
7f2691a1	231
76bc907b PF	232	dual_base = port->sdata->have_dual_base;
76bc907b PF	233
8a58cd57 PF	234	/*
	235	* Handle legacy compatible combinations which used two reg values
	236	* for the i.MX8ULP and i.MX93.
	237	*/
76bc907b PF	238	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	239	(device_is_compatible(dev, "fsl,imx93-gpio") \|\|
	240	(device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
	241	dual_base = true;
	242
	243	if (dual_base) {
	244	port->base = devm_platform_ioremap_resource(pdev, 0);
	245	if (IS_ERR(port->base))
	246	return PTR_ERR(port->base);
	247
	248	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
	249	if (IS_ERR(port->gpio_base))
	250	return PTR_ERR(port->gpio_base);
	251	} else {
	252	port->base = devm_platform_ioremap_resource(pdev, 0);
	253	if (IS_ERR(port->base))
	254	return PTR_ERR(port->base);
	255
	256	port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
	257	port->base = port->base + IMX8ULP_BASE_OFF;
	258	}
7f2691a1 SA	259
	260	port->irq = platform_get_irq(pdev, 0);
	261	if (port->irq < 0)
	262	return port->irq;
	263
2e35bb6c	264	port->clk_port = devm_clk_get(dev, "port");
663ba742 AS	265	ret = PTR_ERR_OR_ZERO(port->clk_port);
663ba742 AS	266	if (!ret) {
91393622 D	267	ret = clk_prepare_enable(port->clk_port);
	268	if (ret)
	269	return ret;
db9ed63c AS	270	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	271	port->clk_port);
	272	if (ret)
	273	return ret;
663ba742	274	} else if (ret == -EPROBE_DEFER) {
91393622 D	275	/*
	276	* Percolate deferrals, for anything else,
	277	* just live without the clocking.
	278	*/
663ba742	279	return ret;
91393622 D	280	}
91393622 D	281
2e35bb6c	282	port->clk_gpio = devm_clk_get(dev, "gpio");
663ba742 AS	283	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
663ba742 AS	284	if (!ret) {
91393622	285	ret = clk_prepare_enable(port->clk_gpio);
db9ed63c	286	if (ret)
91393622	287	return ret;
fc57949c AS	288	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	289	port->clk_gpio);
	290	if (ret)
91393622	291	return ret;
663ba742 AS	292	} else if (ret == -EPROBE_DEFER) {
663ba742 AS	293	return ret;
91393622 D	294	}
91393622 D	295
7f2691a1	296	gc = &port->gc;
da5dd31e	297	flags = BGPIOF_PINCTRL_BACKEND;
26b95b7b	298	/*
da5dd31e LW	299	* We only read the output register for current value on output
	300	* lines if the direction register is available so we can switch
	301	* direction.
26b95b7b HC	302	*/
26b95b7b HC	303	if (port->sdata->have_paddr)
da5dd31e LW	304	flags \|= BGPIOF_READ_OUTPUT_REG_SET;
	305	ret = bgpio_init(gc, dev, 4,
	306	port->gpio_base + GPIO_PDIR,
	307	port->gpio_base + GPIO_PDOR,
	308	NULL,
	309	port->sdata->have_paddr ? port->gpio_base + GPIO_PDDR : NULL,
	310	NULL,
	311	flags);
	312	if (ret)
	313	return dev_err_probe(dev, ret, "unable to init generic GPIO\n");
	314	gc->label = dev_name(dev);
	315	gc->base = -1;
7f2691a1	316
7ae710f9 AL	317	/* Mask all GPIO interrupts */
	318	for (i = 0; i < gc->ngpio; i++)
	319	vf610_gpio_writel(0, port->base + PORT_PCR(i));
	320
7f2691a1 SA	321	/* Clear the interrupt status register for all GPIO's */
	322	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	323
e599256a	324	girq = &gc->irq;
e6ef4f8e	325	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
e599256a LW	326	girq->parent_handler = vf610_gpio_irq_handler;
	327	girq->num_parents = 1;
	328	girq->parents = devm_kcalloc(&pdev->dev, 1,
	329	sizeof(*girq->parents),
	330	GFP_KERNEL);
	331	if (!girq->parents)
	332	return -ENOMEM;
	333	girq->parents[0] = port->irq;
	334	girq->default_type = IRQ_TYPE_NONE;
	335	girq->handler = handle_edge_irq;
7f2691a1	336
e599256a	337	return devm_gpiochip_add_data(dev, gc, port);
7f2691a1 SA	338	}
	339
	340	static struct platform_driver vf610_gpio_driver = {
	341	.driver = {
	342	.name = "gpio-vf610",
7f2691a1 SA	343	.of_match_table = vf610_gpio_dt_ids,
	344	},
	345	.probe = vf610_gpio_probe,
	346	};
	347
73dc041f JY	348	module_platform_driver(vf610_gpio_driver);
	349	MODULE_DESCRIPTION("VF610 GPIO driver");
	350	MODULE_LICENSE("GPL");