[linux-block.git] / drivers / gpio / gpio-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <stefan@agner.ch>.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>

#define VF610_GPIO_PER_PORT		32

struct fsl_gpio_soc_data {
	/* SoCs has a Port Data Direction Register (PDDR) */
	bool have_paddr;
	bool have_dual_base;
};

struct vf610_gpio_port {
	struct gpio_chip gc;
	void __iomem *base;
	void __iomem *gpio_base;
	const struct fsl_gpio_soc_data *sdata;
	u8 irqc[VF610_GPIO_PER_PORT];
	struct clk *clk_port;
	struct clk *clk_gpio;
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10
#define GPIO_PDDR		0x14

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

#define IMX8ULP_GPIO_BASE_OFF	0x40
#define IMX8ULP_BASE_OFF	0x80

static const struct fsl_gpio_soc_data vf610_data = {
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx_data = {
	.have_paddr = true,
	.have_dual_base = true,
};

static const struct fsl_gpio_soc_data imx8ulp_data = {
	.have_paddr = true,
};

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio",	.data = &vf610_data },
	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
	{ .compatible = "fsl,imx8ulp-gpio",	.data = &imx8ulp_data, },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = GPIO_PDIR;

	if (port->sdata->have_paddr) {
		mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		if (mask)
			offset = GPIO_PDOR;
	}

	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
}

static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;

	vf610_gpio_writel(mask, port->gpio_base + offset);
}

static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);
	u32 val;

	if (port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val &= ~mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_input(chip, gpio);
}

static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
				       int value)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);
	u32 val;

	vf610_gpio_set(chip, gpio, value);

	if (port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val |= mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_output(chip, gpio);
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_domain_irq(port->gc.irq.domain, pin);
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	vf610_gpio_writel(0, pcr_base);
	gpiochip_disable_irq(gc, gpio_num);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	gpiochip_enable_irq(gc, gpio_num);
	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static const struct irq_chip vf610_irqchip = {
	.name = "gpio-vf610",
	.irq_ack = vf610_gpio_irq_ack,
	.irq_mask = vf610_gpio_irq_mask,
	.irq_unmask = vf610_gpio_irq_unmask,
	.irq_set_type = vf610_gpio_irq_set_type,
	.irq_set_wake = vf610_gpio_irq_set_wake,
	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
			| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void vf610_gpio_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct vf610_gpio_port *port;
	struct gpio_chip *gc;
	struct gpio_irq_chip *girq;
	int i;
	int ret;
	bool dual_base;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->sdata = of_device_get_match_data(dev);

	dual_base = port->sdata->have_dual_base;

	/*
	 * Handle legacy compatible combinations which used two reg values
	 * for the i.MX8ULP and i.MX93.
	 */
	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	    (device_is_compatible(dev, "fsl,imx93-gpio") ||
	    (device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
		dual_base = true;

	if (dual_base) {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
		if (IS_ERR(port->gpio_base))
			return PTR_ERR(port->gpio_base);
	} else {
		port->base = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(port->base))
			return PTR_ERR(port->base);

		port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
		port->base = port->base + IMX8ULP_BASE_OFF;
	}

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	port->clk_port = devm_clk_get(dev, "port");
	ret = PTR_ERR_OR_ZERO(port->clk_port);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_port);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_port);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return ret;
	}

	port->clk_gpio = devm_clk_get(dev, "gpio");
	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_gpio);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_gpio);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		return ret;
	}

	gc = &port->gc;
	gc->parent = dev;
	gc->label = dev_name(dev);
	gc->ngpio = VF610_GPIO_PER_PORT;
	gc->base = -1;

	gc->request = gpiochip_generic_request;
	gc->free = gpiochip_generic_free;
	gc->direction_input = vf610_gpio_direction_input;
	gc->get = vf610_gpio_get;
	gc->direction_output = vf610_gpio_direction_output;
	gc->set = vf610_gpio_set;

	/* Mask all GPIO interrupts */
	for (i = 0; i < gc->ngpio; i++)
		vf610_gpio_writel(0, port->base + PORT_PCR(i));

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	girq = &gc->irq;
	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
	girq->parent_handler = vf610_gpio_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1,
				     sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = port->irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;

	return devm_gpiochip_add_data(dev, gc, port);
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

builtin_platform_driver(vf610_gpio_driver);
Commit	Line	Data
36e2add1	1	// SPDX-License-Identifier: GPL-2.0+
7f2691a1	2	/*
adaaf63e	3	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	4	*
	5	* Copyright (c) 2014 Toradex AG.
	6	*
	7	* Author: Stefan Agner <stefan@agner.ch>.
7f2691a1	8	*/
7f2691a1	9	#include <linux/bitops.h>
91393622	10	#include <linux/clk.h>
7f2691a1	11	#include <linux/err.h>
45e8296c	12	#include <linux/gpio/driver.h>
7f2691a1 SA	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
7f2691a1 SA	18	#include <linux/platform_device.h>
7f2691a1 SA	19	#include <linux/of.h>
7f2691a1	20	#include <linux/of_irq.h>
8af3a0b2	21	#include <linux/pinctrl/consumer.h>
7f2691a1 SA	22
	23	#define VF610_GPIO_PER_PORT 32
	24
659d8a62 DA	25	struct fsl_gpio_soc_data {
	26	/* SoCs has a Port Data Direction Register (PDDR) */
	27	bool have_paddr;
76bc907b	28	bool have_dual_base;
659d8a62 DA	29	};
659d8a62 DA	30
7f2691a1 SA	31	struct vf610_gpio_port {
	32	struct gpio_chip gc;
	33	void __iomem *base;
	34	void __iomem *gpio_base;
659d8a62	35	const struct fsl_gpio_soc_data *sdata;
7f2691a1	36	u8 irqc[VF610_GPIO_PER_PORT];
91393622 D	37	struct clk *clk_port;
91393622 D	38	struct clk *clk_gpio;
7f2691a1 SA	39	int irq;
	40	};
	41
	42	#define GPIO_PDOR 0x00
	43	#define GPIO_PSOR 0x04
	44	#define GPIO_PCOR 0x08
	45	#define GPIO_PTOR 0x0c
	46	#define GPIO_PDIR 0x10
659d8a62	47	#define GPIO_PDDR 0x14
7f2691a1 SA	48
	49	#define PORT_PCR(n) ((n) * 0x4)
	50	#define PORT_PCR_IRQC_OFFSET 16
	51
	52	#define PORT_ISFR 0xa0
	53	#define PORT_DFER 0xc0
	54	#define PORT_DFCR 0xc4
	55	#define PORT_DFWR 0xc8
	56
	57	#define PORT_INT_OFF 0x0
	58	#define PORT_INT_LOGIC_ZERO 0x8
	59	#define PORT_INT_RISING_EDGE 0x9
	60	#define PORT_INT_FALLING_EDGE 0xa
	61	#define PORT_INT_EITHER_EDGE 0xb
	62	#define PORT_INT_LOGIC_ONE 0xc
	63
76bc907b PF	64	#define IMX8ULP_GPIO_BASE_OFF 0x40
	65	#define IMX8ULP_BASE_OFF 0x80
	66
	67	static const struct fsl_gpio_soc_data vf610_data = {
	68	.have_dual_base = true,
	69	};
	70
659d8a62 DA	71	static const struct fsl_gpio_soc_data imx_data = {
659d8a62 DA	72	.have_paddr = true,
76bc907b PF	73	.have_dual_base = true,
	74	};
	75
	76	static const struct fsl_gpio_soc_data imx8ulp_data = {
	77	.have_paddr = true,
659d8a62 DA	78	};
659d8a62 DA	79
7f2691a1	80	static const struct of_device_id vf610_gpio_dt_ids[] = {
76bc907b	81	{ .compatible = "fsl,vf610-gpio", .data = &vf610_data },
659d8a62	82	{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
76bc907b	83	{ .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
7f2691a1 SA	84	{ /* sentinel */ }
	85	};
	86
	87	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	88	{
	89	writel_relaxed(val, reg);
	90	}
	91
	92	static inline u32 vf610_gpio_readl(void __iomem *reg)
	93	{
	94	return readl_relaxed(reg);
	95	}
	96
7f2691a1 SA	97	static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
7f2691a1 SA	98	{
65389b49	99	struct vf610_gpio_port *port = gpiochip_get_data(gc);
659d8a62	100	unsigned long mask = BIT(gpio);
4a8909d0	101	unsigned long offset = GPIO_PDIR;
659d8a62	102
b57587f1	103	if (port->sdata->have_paddr) {
659d8a62	104	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
4a8909d0 AS	105	if (mask)
4a8909d0 AS	106	offset = GPIO_PDOR;
659d8a62	107	}
4a8909d0 AS	108
4a8909d0 AS	109	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
7f2691a1 SA	110	}
	111
	112	static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	113	{
65389b49	114	struct vf610_gpio_port *port = gpiochip_get_data(gc);
7f2691a1	115	unsigned long mask = BIT(gpio);
a262555b	116	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
7f2691a1	117
a262555b	118	vf610_gpio_writel(mask, port->gpio_base + offset);
7f2691a1 SA	119	}
	120
	121	static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	122	{
659d8a62 DA	123	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	124	unsigned long mask = BIT(gpio);
	125	u32 val;
	126
b57587f1	127	if (port->sdata->have_paddr) {
659d8a62 DA	128	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	129	val &= ~mask;
	130	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	131	}
	132
315c46f9	133	return pinctrl_gpio_direction_input(chip, gpio);
7f2691a1 SA	134	}
	135
	136	static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	137	int value)
	138	{
659d8a62 DA	139	struct vf610_gpio_port *port = gpiochip_get_data(chip);
659d8a62 DA	140	unsigned long mask = BIT(gpio);
9bf3ac46	141	u32 val;
659d8a62	142
fc363413 HC	143	vf610_gpio_set(chip, gpio, value);
fc363413 HC	144
b57587f1	145	if (port->sdata->have_paddr) {
9bf3ac46 HC	146	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	147	val \|= mask;
	148	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	149	}
659d8a62	150
b679d6c0	151	return pinctrl_gpio_direction_output(chip, gpio);
7f2691a1 SA	152	}
7f2691a1 SA	153
bd0b9ac4	154	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	155	{
2f930643	156	struct vf610_gpio_port *port =
65389b49	157	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	158	struct irq_chip *chip = irq_desc_get_chip(desc);
	159	int pin;
	160	unsigned long irq_isfr;
	161
	162	chained_irq_enter(chip, desc);
	163
	164	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	165
	166	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	167	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	168
dbd1c54f	169	generic_handle_domain_irq(port->gc.irq.domain, pin);
7f2691a1 SA	170	}
	171
	172	chained_irq_exit(chip, desc);
	173	}
	174
	175	static void vf610_gpio_irq_ack(struct irq_data *d)
	176	{
2f930643	177	struct vf610_gpio_port *port =
65389b49	178	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	179	int gpio = d->hwirq;
	180
	181	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	182	}
	183
	184	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	185	{
2f930643	186	struct vf610_gpio_port *port =
65389b49	187	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	188	u8 irqc;
	189
	190	switch (type) {
	191	case IRQ_TYPE_EDGE_RISING:
	192	irqc = PORT_INT_RISING_EDGE;
	193	break;
	194	case IRQ_TYPE_EDGE_FALLING:
	195	irqc = PORT_INT_FALLING_EDGE;
	196	break;
	197	case IRQ_TYPE_EDGE_BOTH:
	198	irqc = PORT_INT_EITHER_EDGE;
	199	break;
	200	case IRQ_TYPE_LEVEL_LOW:
	201	irqc = PORT_INT_LOGIC_ZERO;
	202	break;
	203	case IRQ_TYPE_LEVEL_HIGH:
	204	irqc = PORT_INT_LOGIC_ONE;
	205	break;
	206	default:
	207	return -EINVAL;
	208	}
	209
	210	port->irqc[d->hwirq] = irqc;
	211
fd968115	212	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	213	irq_set_handler_locked(d, handle_level_irq);
fd968115	214	else
a7147db0	215	irq_set_handler_locked(d, handle_edge_irq);
fd968115	216
7f2691a1 SA	217	return 0;
	218	}
	219
	220	static void vf610_gpio_irq_mask(struct irq_data *d)
	221	{
e6ef4f8e AS	222	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	223	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	224	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	225	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1 SA	226
7f2691a1 SA	227	vf610_gpio_writel(0, pcr_base);
e6ef4f8e	228	gpiochip_disable_irq(gc, gpio_num);
7f2691a1 SA	229	}
	230
	231	static void vf610_gpio_irq_unmask(struct irq_data *d)
	232	{
e6ef4f8e AS	233	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	234	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	235	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	236	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1	237
e6ef4f8e AS	238	gpiochip_enable_irq(gc, gpio_num);
e6ef4f8e AS	239	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
7f2691a1 SA	240	pcr_base);
	241	}
	242
	243	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	244	{
2f930643	245	struct vf610_gpio_port *port =
65389b49	246	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	247
	248	if (enable)
	249	enable_irq_wake(port->irq);
	250	else
	251	disable_irq_wake(port->irq);
	252
	253	return 0;
	254	}
	255
e6ef4f8e AS	256	static const struct irq_chip vf610_irqchip = {
	257	.name = "gpio-vf610",
	258	.irq_ack = vf610_gpio_irq_ack,
	259	.irq_mask = vf610_gpio_irq_mask,
	260	.irq_unmask = vf610_gpio_irq_unmask,
	261	.irq_set_type = vf610_gpio_irq_set_type,
	262	.irq_set_wake = vf610_gpio_irq_set_wake,
43023261 HC	263	.flags = IRQCHIP_IMMUTABLE \| IRQCHIP_MASK_ON_SUSPEND
43023261 HC	264	\| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
e6ef4f8e AS	265	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	266	};
	267
db9ed63c AS	268	static void vf610_gpio_disable_clk(void *data)
	269	{
	270	clk_disable_unprepare(data);
	271	}
7f2691a1 SA	272
	273	static int vf610_gpio_probe(struct platform_device *pdev)
	274	{
	275	struct device *dev = &pdev->dev;
7f2691a1	276	struct vf610_gpio_port *port;
7f2691a1	277	struct gpio_chip *gc;
e599256a	278	struct gpio_irq_chip *girq;
7ae710f9	279	int i;
7f2691a1	280	int ret;
76bc907b	281	bool dual_base;
7f2691a1	282
2e35bb6c	283	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
7f2691a1 SA	284	if (!port)
	285	return -ENOMEM;
	286
23e577eb	287	port->sdata = of_device_get_match_data(dev);
7f2691a1	288
76bc907b PF	289	dual_base = port->sdata->have_dual_base;
76bc907b PF	290
8a58cd57 PF	291	/*
	292	* Handle legacy compatible combinations which used two reg values
	293	* for the i.MX8ULP and i.MX93.
	294	*/
76bc907b PF	295	if (device_is_compatible(dev, "fsl,imx7ulp-gpio") &&
	296	(device_is_compatible(dev, "fsl,imx93-gpio") \|\|
	297	(device_is_compatible(dev, "fsl,imx8ulp-gpio"))))
	298	dual_base = true;
	299
	300	if (dual_base) {
	301	port->base = devm_platform_ioremap_resource(pdev, 0);
	302	if (IS_ERR(port->base))
	303	return PTR_ERR(port->base);
	304
	305	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
	306	if (IS_ERR(port->gpio_base))
	307	return PTR_ERR(port->gpio_base);
	308	} else {
	309	port->base = devm_platform_ioremap_resource(pdev, 0);
	310	if (IS_ERR(port->base))
	311	return PTR_ERR(port->base);
	312
	313	port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF;
	314	port->base = port->base + IMX8ULP_BASE_OFF;
	315	}
7f2691a1 SA	316
	317	port->irq = platform_get_irq(pdev, 0);
	318	if (port->irq < 0)
	319	return port->irq;
	320
2e35bb6c	321	port->clk_port = devm_clk_get(dev, "port");
663ba742 AS	322	ret = PTR_ERR_OR_ZERO(port->clk_port);
663ba742 AS	323	if (!ret) {
91393622 D	324	ret = clk_prepare_enable(port->clk_port);
	325	if (ret)
	326	return ret;
db9ed63c AS	327	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	328	port->clk_port);
	329	if (ret)
	330	return ret;
663ba742	331	} else if (ret == -EPROBE_DEFER) {
91393622 D	332	/*
	333	* Percolate deferrals, for anything else,
	334	* just live without the clocking.
	335	*/
663ba742	336	return ret;
91393622 D	337	}
91393622 D	338
2e35bb6c	339	port->clk_gpio = devm_clk_get(dev, "gpio");
663ba742 AS	340	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
663ba742 AS	341	if (!ret) {
91393622	342	ret = clk_prepare_enable(port->clk_gpio);
db9ed63c	343	if (ret)
91393622	344	return ret;
fc57949c AS	345	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	346	port->clk_gpio);
	347	if (ret)
91393622	348	return ret;
663ba742 AS	349	} else if (ret == -EPROBE_DEFER) {
663ba742 AS	350	return ret;
91393622 D	351	}
91393622 D	352
7f2691a1	353	gc = &port->gc;
58383c78	354	gc->parent = dev;
6f8ecb7f	355	gc->label = dev_name(dev);
d32efe37	356	gc->ngpio = VF610_GPIO_PER_PORT;
bb5ad5ef	357	gc->base = -1;
7f2691a1	358
203f0daa JG	359	gc->request = gpiochip_generic_request;
203f0daa JG	360	gc->free = gpiochip_generic_free;
d32efe37 AL	361	gc->direction_input = vf610_gpio_direction_input;
	362	gc->get = vf610_gpio_get;
	363	gc->direction_output = vf610_gpio_direction_output;
	364	gc->set = vf610_gpio_set;
7f2691a1	365
7ae710f9 AL	366	/* Mask all GPIO interrupts */
	367	for (i = 0; i < gc->ngpio; i++)
	368	vf610_gpio_writel(0, port->base + PORT_PCR(i));
	369
7f2691a1 SA	370	/* Clear the interrupt status register for all GPIO's */
	371	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	372
e599256a	373	girq = &gc->irq;
e6ef4f8e	374	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
e599256a LW	375	girq->parent_handler = vf610_gpio_irq_handler;
	376	girq->num_parents = 1;
	377	girq->parents = devm_kcalloc(&pdev->dev, 1,
	378	sizeof(*girq->parents),
	379	GFP_KERNEL);
	380	if (!girq->parents)
	381	return -ENOMEM;
	382	girq->parents[0] = port->irq;
	383	girq->default_type = IRQ_TYPE_NONE;
	384	girq->handler = handle_edge_irq;
7f2691a1	385
e599256a	386	return devm_gpiochip_add_data(dev, gc, port);
7f2691a1 SA	387	}
	388
	389	static struct platform_driver vf610_gpio_driver = {
	390	.driver = {
	391	.name = "gpio-vf610",
7f2691a1 SA	392	.of_match_table = vf610_gpio_dt_ids,
	393	},
	394	.probe = vf610_gpio_probe,
	395	};
	396
df950da1	397	builtin_platform_driver(vf610_gpio_driver);