[linux-2.6-block.git] / drivers / gpio / gpio-uniphier.c

// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <dt-bindings/gpio/uniphier-gpio.h>

#define UNIPHIER_GPIO_BANK_MASK		\
				GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)

#define UNIPHIER_GPIO_IRQ_MAX_NUM	24

#define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
#define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
#define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */
#define UNIPHIER_GPIO_IRQ_MODE		0x94	/* irq mode (1: both edge) */
#define UNIPHIER_GPIO_IRQ_FLT_EN	0x98	/* noise filter enable */
#define UNIPHIER_GPIO_IRQ_FLT_CYC	0x9c	/* noise filter clock cycle */

struct uniphier_gpio_priv {
	struct gpio_chip chip;
	struct irq_chip irq_chip;
	struct irq_domain *domain;
	void __iomem *regs;
	spinlock_t lock;
	u32 saved_vals[0];
};

static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
{
	unsigned int reg;

	reg = (bank + 1) * 8;

	/*
	 * Unfortunately, the GPIO port registers are not contiguous because
	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
	 */
	if (reg >= UNIPHIER_GPIO_IRQ_EN)
		reg += 0x10;

	return reg;
}

static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
					    unsigned int *bank, u32 *mask)
{
	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
}

static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
				     unsigned int reg, u32 mask, u32 val)
{
	unsigned long flags;
	u32 tmp;

	spin_lock_irqsave(&priv->lock, flags);
	tmp = readl(priv->regs + reg);
	tmp &= ~mask;
	tmp |= mask & val;
	writel(tmp, priv->regs + reg);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
				     unsigned int reg, u32 mask, u32 val)
{
	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);

	if (!mask)
		return;

	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
				 mask, val);
}

static void uniphier_gpio_offset_write(struct gpio_chip *chip,
				       unsigned int offset, unsigned int reg,
				       int val)
{
	unsigned int bank;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
}

static int uniphier_gpio_offset_read(struct gpio_chip *chip,
				     unsigned int offset, unsigned int reg)
{
	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int bank, reg_offset;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

	return !!(readl(priv->regs + reg_offset) & mask);
}

static int uniphier_gpio_get_direction(struct gpio_chip *chip,
				       unsigned int offset)
{
	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);
}

static int uniphier_gpio_direction_input(struct gpio_chip *chip,
					 unsigned int offset)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);

	return 0;
}

static int uniphier_gpio_direction_output(struct gpio_chip *chip,
					  unsigned int offset, int val)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);

	return 0;
}

static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
}

static void uniphier_gpio_set(struct gpio_chip *chip,
			      unsigned int offset, int val)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
}

static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
				       unsigned long *mask, unsigned long *bits)
{
	unsigned int bank, shift, bank_mask, bank_bits;
	int i;

	for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {
		bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
		shift = i % BITS_PER_LONG;
		bank_mask = (mask[BIT_WORD(i)] >> shift) &
						UNIPHIER_GPIO_BANK_MASK;
		bank_bits = bits[BIT_WORD(i)] >> shift;

		uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
					 bank_mask, bank_bits);
	}
}

static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
	struct irq_fwspec fwspec;

	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
		return -ENXIO;

	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
	fwspec.param_count = 2;
	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
	/*
	 * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
	 * temporarily. Anyway, ->irq_set_type() will override it later.
	 */
	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;

	return irq_create_fwspec_mapping(&fwspec);
}

static void uniphier_gpio_irq_mask(struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);

	return irq_chip_mask_parent(data);
}

static void uniphier_gpio_irq_unmask(struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);

	return irq_chip_unmask_parent(data);
}

static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);
	u32 val = 0;

	if (type == IRQ_TYPE_EDGE_BOTH) {
		val = mask;
		type = IRQ_TYPE_EDGE_FALLING;
	}

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
	/* To enable both edge detection, the noise filter must be enabled. */
	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);

	return irq_chip_set_type_parent(data, type);
}

static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
					      unsigned int hwirq)
{
	struct device_node *np = priv->chip.parent->of_node;
	const __be32 *range;
	u32 base, parent_base, size;
	int len;

	range = of_get_property(np, "socionext,interrupt-ranges", &len);
	if (!range)
		return -EINVAL;

	len /= sizeof(*range);

	for (; len >= 3; len -= 3) {
		base = be32_to_cpu(*range++);
		parent_base = be32_to_cpu(*range++);
		size = be32_to_cpu(*range++);

		if (base <= hwirq && hwirq < base + size)
			return hwirq - base + parent_base;
	}

	return -ENOENT;
}

static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
					      struct irq_fwspec *fwspec,
					      unsigned long *out_hwirq,
					      unsigned int *out_type)
{
	if (WARN_ON(fwspec->param_count < 2))
		return -EINVAL;

	*out_hwirq = fwspec->param[0];
	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;

	return 0;
}

static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
					  unsigned int virq,
					  unsigned int nr_irqs, void *arg)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	unsigned int type;
	int ret;

	if (WARN_ON(nr_irqs != 1))
		return -EINVAL;

	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
	if (ret)
		return ret;

	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
	if (ret < 0)
		return ret;

	/* parent is UniPhier AIDET */
	parent_fwspec.fwnode = domain->parent->fwnode;
	parent_fwspec.param_count = 2;
	parent_fwspec.param[0] = ret;
	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
						IRQ_TYPE_EDGE_FALLING : type;

	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
					    &priv->irq_chip, priv);
	if (ret)
		return ret;

	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
}

static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
					     struct irq_data *data, bool early)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct gpio_chip *chip = &priv->chip;

	return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
}

static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
						struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct gpio_chip *chip = &priv->chip;

	gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
}

static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
	.alloc = uniphier_gpio_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
	.activate = uniphier_gpio_irq_domain_activate,
	.deactivate = uniphier_gpio_irq_domain_deactivate,
	.translate = uniphier_gpio_irq_domain_translate,
};

static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
{
	/*
	 * Due to the hardware design, the noise filter must be enabled to
	 * detect both edge interrupts.  This filter is intended to remove the
	 * noise from the irq lines.  It does not work for GPIO input, so GPIO
	 * debounce is not supported.  Unfortunately, the filter period is
	 * shared among all irq lines.  Just choose a sensible period here.
	 */
	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
}

static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
{
	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
}

static int uniphier_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *parent_np;
	struct irq_domain *parent_domain;
	struct uniphier_gpio_priv *priv;
	struct gpio_chip *chip;
	struct irq_chip *irq_chip;
	unsigned int nregs;
	u32 ngpios;
	int ret;

	parent_np = of_irq_find_parent(dev->of_node);
	if (!parent_np)
		return -ENXIO;

	parent_domain = irq_find_host(parent_np);
	of_node_put(parent_np);
	if (!parent_domain)
		return -EPROBE_DEFER;

	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
	if (ret)
		return ret;

	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
			    GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->regs))
		return PTR_ERR(priv->regs);

	spin_lock_init(&priv->lock);

	chip = &priv->chip;
	chip->label = dev_name(dev);
	chip->parent = dev;
	chip->request = gpiochip_generic_request;
	chip->free = gpiochip_generic_free;
	chip->get_direction = uniphier_gpio_get_direction;
	chip->direction_input = uniphier_gpio_direction_input;
	chip->direction_output = uniphier_gpio_direction_output;
	chip->get = uniphier_gpio_get;
	chip->set = uniphier_gpio_set;
	chip->set_multiple = uniphier_gpio_set_multiple;
	chip->to_irq = uniphier_gpio_to_irq;
	chip->base = -1;
	chip->ngpio = ngpios;

	irq_chip = &priv->irq_chip;
	irq_chip->name = dev_name(dev);
	irq_chip->irq_mask = uniphier_gpio_irq_mask;
	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
	irq_chip->irq_eoi = irq_chip_eoi_parent;
	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;

	uniphier_gpio_hw_init(priv);

	ret = devm_gpiochip_add_data(dev, chip, priv);
	if (ret)
		return ret;

	priv->domain = irq_domain_create_hierarchy(
					parent_domain, 0,
					UNIPHIER_GPIO_IRQ_MAX_NUM,
					of_node_to_fwnode(dev->of_node),
					&uniphier_gpio_irq_domain_ops, priv);
	if (!priv->domain)
		return -ENOMEM;

	platform_set_drvdata(pdev, priv);

	return 0;
}

static int uniphier_gpio_remove(struct platform_device *pdev)
{
	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);

	irq_domain_remove(priv->domain);

	return 0;
}

static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
	u32 *val = priv->saved_vals;
	unsigned int reg;
	int i;

	for (i = 0; i < nbanks; i++) {
		reg = uniphier_gpio_bank_to_reg(i);

		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
	}

	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);

	return 0;
}

static int __maybe_unused uniphier_gpio_resume(struct device *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
	const u32 *val = priv->saved_vals;
	unsigned int reg;
	int i;

	for (i = 0; i < nbanks; i++) {
		reg = uniphier_gpio_bank_to_reg(i);

		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
	}

	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);

	uniphier_gpio_hw_init(priv);

	return 0;
}

static const struct dev_pm_ops uniphier_gpio_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
				     uniphier_gpio_resume)
};

static const struct of_device_id uniphier_gpio_match[] = {
	{ .compatible = "socionext,uniphier-gpio" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_gpio_match);

static struct platform_driver uniphier_gpio_driver = {
	.probe = uniphier_gpio_probe,
	.remove = uniphier_gpio_remove,
	.driver = {
		.name = "uniphier-gpio",
		.of_match_table = uniphier_gpio_match,
		.pm = &uniphier_gpio_pm_ops,
	},
};
module_platform_driver(uniphier_gpio_driver);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
b00b7980 MY	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Copyright (C) 2017 Socionext Inc.
	4	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
dbe776c2	5
ee8edbf8	6	#include <linux/bits.h>
dbe776c2 MY	7	#include <linux/gpio/driver.h>
	8	#include <linux/irq.h>
	9	#include <linux/irqdomain.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_device.h>
	13	#include <linux/of_irq.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/spinlock.h>
	16	#include <dt-bindings/gpio/uniphier-gpio.h>
	17
	18	#define UNIPHIER_GPIO_BANK_MASK \
	19	GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)
	20
	21	#define UNIPHIER_GPIO_IRQ_MAX_NUM 24
	22
	23	#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
	24	#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
	25	#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
	26	#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */
	27	#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */
	28	#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */
	29
	30	struct uniphier_gpio_priv {
	31	struct gpio_chip chip;
	32	struct irq_chip irq_chip;
	33	struct irq_domain *domain;
	34	void __iomem *regs;
	35	spinlock_t lock;
	36	u32 saved_vals[0];
	37	};
	38
	39	static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
	40	{
	41	unsigned int reg;
	42
	43	reg = (bank + 1) * 8;
	44
	45	/*
	46	* Unfortunately, the GPIO port registers are not contiguous because
	47	* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
	48	*/
	49	if (reg >= UNIPHIER_GPIO_IRQ_EN)
	50	reg += 0x10;
	51
	52	return reg;
	53	}
	54
	55	static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
	56	unsigned int bank, u32 mask)
	57	{
	58	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	59	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
	60	}
	61
	62	static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
	63	unsigned int reg, u32 mask, u32 val)
	64	{
	65	unsigned long flags;
	66	u32 tmp;
	67
	68	spin_lock_irqsave(&priv->lock, flags);
	69	tmp = readl(priv->regs + reg);
	70	tmp &= ~mask;
71	tmp \|= mask & val;
72	writel(tmp, priv->regs + reg);
73	spin_unlock_irqrestore(&priv->lock, flags);
74	}
75
76	static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
77	unsigned int reg, u32 mask, u32 val)
78	{
79	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
80
81	if (!mask)
82	return;
83
84	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
85	mask, val);
86	}
87
88	static void uniphier_gpio_offset_write(struct gpio_chip *chip,
89	unsigned int offset, unsigned int reg,
90	int val)
91	{
92	unsigned int bank;
93	u32 mask;
94
95	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
96
97	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
98	}
99
100	static int uniphier_gpio_offset_read(struct gpio_chip *chip,
101	unsigned int offset, unsigned int reg)
102	{
103	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
104	unsigned int bank, reg_offset;
105	u32 mask;
106
107	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
108	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
109
110	return !!(readl(priv->regs + reg_offset) & mask);
111	}
112
113	static int uniphier_gpio_get_direction(struct gpio_chip *chip,
114	unsigned int offset)
115	{
116	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);
117	}
118
119	static int uniphier_gpio_direction_input(struct gpio_chip *chip,
120	unsigned int offset)
121	{
122	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
123
124	return 0;
125	}
126
127	static int uniphier_gpio_direction_output(struct gpio_chip *chip,
128	unsigned int offset, int val)
129	{
130	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
131	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
132
133	return 0;
134	}
135
136	static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
137	{
138	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
139	}
140
141	static void uniphier_gpio_set(struct gpio_chip *chip,
142	unsigned int offset, int val)
143	{
144	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
145	}
146
147	static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
148	unsigned long mask, unsigned long bits)
149	{
150	unsigned int bank, shift, bank_mask, bank_bits;
151	int i;
152
153	for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {
154	bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
155	shift = i % BITS_PER_LONG;
156	bank_mask = (mask[BIT_WORD(i)] >> shift) &
157	UNIPHIER_GPIO_BANK_MASK;
158	bank_bits = bits[BIT_WORD(i)] >> shift;
159
160	uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
161	bank_mask, bank_bits);
162	}
163	}
164
165	static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
166	{
167	struct irq_fwspec fwspec;
168
169	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
170	return -ENXIO;
171
172	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
173	fwspec.param_count = 2;
174	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
bbfbf04c MY	175	/*
	176	* IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
	177	* temporarily. Anyway, ->irq_set_type() will override it later.
	178	*/
	179	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
dbe776c2 MY	180
	181	return irq_create_fwspec_mapping(&fwspec);
	182	}
	183
	184	static void uniphier_gpio_irq_mask(struct irq_data *data)
	185	{
	186	struct uniphier_gpio_priv *priv = data->chip_data;
	187	u32 mask = BIT(data->hwirq);
	188
	189	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
	190
	191	return irq_chip_mask_parent(data);
	192	}
	193
	194	static void uniphier_gpio_irq_unmask(struct irq_data *data)
	195	{
	196	struct uniphier_gpio_priv *priv = data->chip_data;
	197	u32 mask = BIT(data->hwirq);
	198
	199	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
	200
	201	return irq_chip_unmask_parent(data);
	202	}
	203
	204	static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
	205	{
	206	struct uniphier_gpio_priv *priv = data->chip_data;
	207	u32 mask = BIT(data->hwirq);
	208	u32 val = 0;
	209
	210	if (type == IRQ_TYPE_EDGE_BOTH) {
	211	val = mask;
	212	type = IRQ_TYPE_EDGE_FALLING;
	213	}
	214
	215	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
	216	/* To enable both edge detection, the noise filter must be enabled. */
	217	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
	218
	219	return irq_chip_set_type_parent(data, type);
	220	}
	221
	222	static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
	223	unsigned int hwirq)
	224	{
	225	struct device_node *np = priv->chip.parent->of_node;
	226	const __be32 *range;
	227	u32 base, parent_base, size;
	228	int len;
	229
	230	range = of_get_property(np, "socionext,interrupt-ranges", &len);
	231	if (!range)
	232	return -EINVAL;
	233
	234	len /= sizeof(*range);
	235
	236	for (; len >= 3; len -= 3) {
	237	base = be32_to_cpu(*range++);
	238	parent_base = be32_to_cpu(*range++);
	239	size = be32_to_cpu(*range++);
	240
	241	if (base <= hwirq && hwirq < base + size)
	242	return hwirq - base + parent_base;
	243	}
244
245	return -ENOENT;
246	}
247
248	static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
249	struct irq_fwspec *fwspec,
250	unsigned long *out_hwirq,
251	unsigned int *out_type)
252	{
253	if (WARN_ON(fwspec->param_count < 2))
254	return -EINVAL;
255
256	*out_hwirq = fwspec->param[0];
257	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
258
259	return 0;
260	}
261
262	static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
263	unsigned int virq,
264	unsigned int nr_irqs, void *arg)
265	{
266	struct uniphier_gpio_priv *priv = domain->host_data;
267	struct irq_fwspec parent_fwspec;
268	irq_hw_number_t hwirq;
269	unsigned int type;
270	int ret;
271
272	if (WARN_ON(nr_irqs != 1))
273	return -EINVAL;
274
275	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
276	if (ret)
277	return ret;
278
279	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
280	if (ret < 0)
281	return ret;
282
283	/* parent is UniPhier AIDET */
284	parent_fwspec.fwnode = domain->parent->fwnode;
285	parent_fwspec.param_count = 2;
286	parent_fwspec.param[0] = ret;
287	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
288	IRQ_TYPE_EDGE_FALLING : type;
289
290	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
291	&priv->irq_chip, priv);
292	if (ret)
293	return ret;
294
295	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
296	}
297
6aa2f944 LT	298	static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
6aa2f944 LT	299	struct irq_data *data, bool early)
dbe776c2 MY	300	{
	301	struct uniphier_gpio_priv *priv = domain->host_data;
	302	struct gpio_chip *chip = &priv->chip;
	303
d124339d	304	return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
dbe776c2 MY	305	}
	306
	307	static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
	308	struct irq_data *data)
	309	{
	310	struct uniphier_gpio_priv *priv = domain->host_data;
	311	struct gpio_chip *chip = &priv->chip;
	312
	313	gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
	314	}
	315
	316	static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
	317	.alloc = uniphier_gpio_irq_domain_alloc,
	318	.free = irq_domain_free_irqs_common,
	319	.activate = uniphier_gpio_irq_domain_activate,
	320	.deactivate = uniphier_gpio_irq_domain_deactivate,
	321	.translate = uniphier_gpio_irq_domain_translate,
	322	};
	323
	324	static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
	325	{
	326	/*
	327	* Due to the hardware design, the noise filter must be enabled to
	328	* detect both edge interrupts. This filter is intended to remove the
	329	* noise from the irq lines. It does not work for GPIO input, so GPIO
	330	* debounce is not supported. Unfortunately, the filter period is
	331	* shared among all irq lines. Just choose a sensible period here.
	332	*/
	333	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
	334	}
	335
	336	static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
	337	{
	338	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
	339	}
	340
	341	static int uniphier_gpio_probe(struct platform_device *pdev)
	342	{
	343	struct device *dev = &pdev->dev;
	344	struct device_node *parent_np;
	345	struct irq_domain *parent_domain;
	346	struct uniphier_gpio_priv *priv;
	347	struct gpio_chip *chip;
	348	struct irq_chip *irq_chip;
dbe776c2 MY	349	unsigned int nregs;
	350	u32 ngpios;
	351	int ret;
	352
	353	parent_np = of_irq_find_parent(dev->of_node);
	354	if (!parent_np)
	355	return -ENXIO;
	356
	357	parent_domain = irq_find_host(parent_np);
	358	of_node_put(parent_np);
	359	if (!parent_domain)
	360	return -EPROBE_DEFER;
	361
	362	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
	363	if (ret)
	364	return ret;
	365
	366	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
0ed2dd03	367	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
dbe776c2 MY	368	GFP_KERNEL);
	369	if (!priv)
	370	return -ENOMEM;
	371
83fa76b6	372	priv->regs = devm_platform_ioremap_resource(pdev, 0);
dbe776c2 MY	373	if (IS_ERR(priv->regs))
	374	return PTR_ERR(priv->regs);
	375
	376	spin_lock_init(&priv->lock);
	377
	378	chip = &priv->chip;
	379	chip->label = dev_name(dev);
	380	chip->parent = dev;
	381	chip->request = gpiochip_generic_request;
	382	chip->free = gpiochip_generic_free;
	383	chip->get_direction = uniphier_gpio_get_direction;
	384	chip->direction_input = uniphier_gpio_direction_input;
	385	chip->direction_output = uniphier_gpio_direction_output;
	386	chip->get = uniphier_gpio_get;
	387	chip->set = uniphier_gpio_set;
	388	chip->set_multiple = uniphier_gpio_set_multiple;
	389	chip->to_irq = uniphier_gpio_to_irq;
	390	chip->base = -1;
	391	chip->ngpio = ngpios;
	392
	393	irq_chip = &priv->irq_chip;
	394	irq_chip->name = dev_name(dev);
	395	irq_chip->irq_mask = uniphier_gpio_irq_mask;
	396	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
	397	irq_chip->irq_eoi = irq_chip_eoi_parent;
	398	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
	399	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
	400
	401	uniphier_gpio_hw_init(priv);
	402
	403	ret = devm_gpiochip_add_data(dev, chip, priv);
	404	if (ret)
	405	return ret;
	406
	407	priv->domain = irq_domain_create_hierarchy(
	408	parent_domain, 0,
	409	UNIPHIER_GPIO_IRQ_MAX_NUM,
	410	of_node_to_fwnode(dev->of_node),
	411	&uniphier_gpio_irq_domain_ops, priv);
	412	if (!priv->domain)
	413	return -ENOMEM;
	414
	415	platform_set_drvdata(pdev, priv);
	416
	417	return 0;
	418	}
	419
	420	static int uniphier_gpio_remove(struct platform_device *pdev)
	421	{
	422	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
	423
	424	irq_domain_remove(priv->domain);
	425
	426	return 0;
	427	}
	428
	429	static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
	430	{
	431	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
	432	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
	433	u32 *val = priv->saved_vals;
	434	unsigned int reg;
	435	int i;
	436
437	for (i = 0; i < nbanks; i++) {
438	reg = uniphier_gpio_bank_to_reg(i);
439
440	*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
441	*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
442	}
443
444	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
445	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
446	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
447
448	return 0;
449	}
450
451	static int __maybe_unused uniphier_gpio_resume(struct device *dev)
452	{
453	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
454	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
455	const u32 *val = priv->saved_vals;
456	unsigned int reg;
457	int i;
458
459	for (i = 0; i < nbanks; i++) {
460	reg = uniphier_gpio_bank_to_reg(i);
461
462	writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
463	writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
464	}
465
466	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
467	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
468	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
469
470	uniphier_gpio_hw_init(priv);
471
472	return 0;
473	}
474
475	static const struct dev_pm_ops uniphier_gpio_pm_ops = {
476	SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
477	uniphier_gpio_resume)
478	};
479
480	static const struct of_device_id uniphier_gpio_match[] = {
481	{ .compatible = "socionext,uniphier-gpio" },
482	{ /* sentinel */ }
483	};
484	MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
485
486	static struct platform_driver uniphier_gpio_driver = {
487	.probe = uniphier_gpio_probe,
488	.remove = uniphier_gpio_remove,
489	.driver = {
490	.name = "uniphier-gpio",
491	.of_match_table = uniphier_gpio_match,
492	.pm = &uniphier_gpio_pm_ops,
493	},
494	};
495	module_platform_driver(uniphier_gpio_driver);
496
497	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
498	MODULE_DESCRIPTION("UniPhier GPIO driver");
13f9d59c	499	MODULE_LICENSE("GPL v2");