[linux-2.6-block.git] / drivers / gpio / gpio-uniphier.c

/*
 * Copyright (C) 2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <dt-bindings/gpio/uniphier-gpio.h>

#define UNIPHIER_GPIO_BANK_MASK		\
				GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)

#define UNIPHIER_GPIO_IRQ_MAX_NUM	24

#define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
#define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
#define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */
#define UNIPHIER_GPIO_IRQ_MODE		0x94	/* irq mode (1: both edge) */
#define UNIPHIER_GPIO_IRQ_FLT_EN	0x98	/* noise filter enable */
#define UNIPHIER_GPIO_IRQ_FLT_CYC	0x9c	/* noise filter clock cycle */

struct uniphier_gpio_priv {
	struct gpio_chip chip;
	struct irq_chip irq_chip;
	struct irq_domain *domain;
	void __iomem *regs;
	spinlock_t lock;
	u32 saved_vals[0];
};

static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
{
	unsigned int reg;

	reg = (bank + 1) * 8;

	/*
	 * Unfortunately, the GPIO port registers are not contiguous because
	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
	 */
	if (reg >= UNIPHIER_GPIO_IRQ_EN)
		reg += 0x10;

	return reg;
}

static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
					    unsigned int *bank, u32 *mask)
{
	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
}

static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
				     unsigned int reg, u32 mask, u32 val)
{
	unsigned long flags;
	u32 tmp;

	spin_lock_irqsave(&priv->lock, flags);
	tmp = readl(priv->regs + reg);
	tmp &= ~mask;
	tmp |= mask & val;
	writel(tmp, priv->regs + reg);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
				     unsigned int reg, u32 mask, u32 val)
{
	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);

	if (!mask)
		return;

	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
				 mask, val);
}

static void uniphier_gpio_offset_write(struct gpio_chip *chip,
				       unsigned int offset, unsigned int reg,
				       int val)
{
	unsigned int bank;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
}

static int uniphier_gpio_offset_read(struct gpio_chip *chip,
				     unsigned int offset, unsigned int reg)
{
	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int bank, reg_offset;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

	return !!(readl(priv->regs + reg_offset) & mask);
}

static int uniphier_gpio_get_direction(struct gpio_chip *chip,
				       unsigned int offset)
{
	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);
}

static int uniphier_gpio_direction_input(struct gpio_chip *chip,
					 unsigned int offset)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);

	return 0;
}

static int uniphier_gpio_direction_output(struct gpio_chip *chip,
					  unsigned int offset, int val)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);

	return 0;
}

static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
}

static void uniphier_gpio_set(struct gpio_chip *chip,
			      unsigned int offset, int val)
{
	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
}

static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
				       unsigned long *mask, unsigned long *bits)
{
	unsigned int bank, shift, bank_mask, bank_bits;
	int i;

	for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {
		bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
		shift = i % BITS_PER_LONG;
		bank_mask = (mask[BIT_WORD(i)] >> shift) &
						UNIPHIER_GPIO_BANK_MASK;
		bank_bits = bits[BIT_WORD(i)] >> shift;

		uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
					 bank_mask, bank_bits);
	}
}

static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
	struct irq_fwspec fwspec;

	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
		return -ENXIO;

	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
	fwspec.param_count = 2;
	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
	/*
	 * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
	 * temporarily. Anyway, ->irq_set_type() will override it later.
	 */
	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;

	return irq_create_fwspec_mapping(&fwspec);
}

static void uniphier_gpio_irq_mask(struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);

	return irq_chip_mask_parent(data);
}

static void uniphier_gpio_irq_unmask(struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);

	return irq_chip_unmask_parent(data);
}

static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct uniphier_gpio_priv *priv = data->chip_data;
	u32 mask = BIT(data->hwirq);
	u32 val = 0;

	if (type == IRQ_TYPE_EDGE_BOTH) {
		val = mask;
		type = IRQ_TYPE_EDGE_FALLING;
	}

	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
	/* To enable both edge detection, the noise filter must be enabled. */
	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);

	return irq_chip_set_type_parent(data, type);
}

static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
					      unsigned int hwirq)
{
	struct device_node *np = priv->chip.parent->of_node;
	const __be32 *range;
	u32 base, parent_base, size;
	int len;

	range = of_get_property(np, "socionext,interrupt-ranges", &len);
	if (!range)
		return -EINVAL;

	len /= sizeof(*range);

	for (; len >= 3; len -= 3) {
		base = be32_to_cpu(*range++);
		parent_base = be32_to_cpu(*range++);
		size = be32_to_cpu(*range++);

		if (base <= hwirq && hwirq < base + size)
			return hwirq - base + parent_base;
	}

	return -ENOENT;
}

static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
					      struct irq_fwspec *fwspec,
					      unsigned long *out_hwirq,
					      unsigned int *out_type)
{
	if (WARN_ON(fwspec->param_count < 2))
		return -EINVAL;

	*out_hwirq = fwspec->param[0];
	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;

	return 0;
}

static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
					  unsigned int virq,
					  unsigned int nr_irqs, void *arg)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	unsigned int type;
	int ret;

	if (WARN_ON(nr_irqs != 1))
		return -EINVAL;

	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
	if (ret)
		return ret;

	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
	if (ret < 0)
		return ret;

	/* parent is UniPhier AIDET */
	parent_fwspec.fwnode = domain->parent->fwnode;
	parent_fwspec.param_count = 2;
	parent_fwspec.param[0] = ret;
	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
						IRQ_TYPE_EDGE_FALLING : type;

	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
					    &priv->irq_chip, priv);
	if (ret)
		return ret;

	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
}

static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
					     struct irq_data *data, bool early)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct gpio_chip *chip = &priv->chip;

	return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
}

static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
						struct irq_data *data)
{
	struct uniphier_gpio_priv *priv = domain->host_data;
	struct gpio_chip *chip = &priv->chip;

	gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
}

static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
	.alloc = uniphier_gpio_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
	.activate = uniphier_gpio_irq_domain_activate,
	.deactivate = uniphier_gpio_irq_domain_deactivate,
	.translate = uniphier_gpio_irq_domain_translate,
};

static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
{
	/*
	 * Due to the hardware design, the noise filter must be enabled to
	 * detect both edge interrupts.  This filter is intended to remove the
	 * noise from the irq lines.  It does not work for GPIO input, so GPIO
	 * debounce is not supported.  Unfortunately, the filter period is
	 * shared among all irq lines.  Just choose a sensible period here.
	 */
	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
}

static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
{
	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
}

static int uniphier_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *parent_np;
	struct irq_domain *parent_domain;
	struct uniphier_gpio_priv *priv;
	struct gpio_chip *chip;
	struct irq_chip *irq_chip;
	struct resource *regs;
	unsigned int nregs;
	u32 ngpios;
	int ret;

	parent_np = of_irq_find_parent(dev->of_node);
	if (!parent_np)
		return -ENXIO;

	parent_domain = irq_find_host(parent_np);
	of_node_put(parent_np);
	if (!parent_domain)
		return -EPROBE_DEFER;

	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
	if (ret)
		return ret;

	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
			    GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->regs = devm_ioremap_resource(dev, regs);
	if (IS_ERR(priv->regs))
		return PTR_ERR(priv->regs);

	spin_lock_init(&priv->lock);

	chip = &priv->chip;
	chip->label = dev_name(dev);
	chip->parent = dev;
	chip->request = gpiochip_generic_request;
	chip->free = gpiochip_generic_free;
	chip->get_direction = uniphier_gpio_get_direction;
	chip->direction_input = uniphier_gpio_direction_input;
	chip->direction_output = uniphier_gpio_direction_output;
	chip->get = uniphier_gpio_get;
	chip->set = uniphier_gpio_set;
	chip->set_multiple = uniphier_gpio_set_multiple;
	chip->to_irq = uniphier_gpio_to_irq;
	chip->base = -1;
	chip->ngpio = ngpios;

	irq_chip = &priv->irq_chip;
	irq_chip->name = dev_name(dev);
	irq_chip->irq_mask = uniphier_gpio_irq_mask;
	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
	irq_chip->irq_eoi = irq_chip_eoi_parent;
	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;

	uniphier_gpio_hw_init(priv);

	ret = devm_gpiochip_add_data(dev, chip, priv);
	if (ret)
		return ret;

	priv->domain = irq_domain_create_hierarchy(
					parent_domain, 0,
					UNIPHIER_GPIO_IRQ_MAX_NUM,
					of_node_to_fwnode(dev->of_node),
					&uniphier_gpio_irq_domain_ops, priv);
	if (!priv->domain)
		return -ENOMEM;

	platform_set_drvdata(pdev, priv);

	return 0;
}

static int uniphier_gpio_remove(struct platform_device *pdev)
{
	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);

	irq_domain_remove(priv->domain);

	return 0;
}

static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
	u32 *val = priv->saved_vals;
	unsigned int reg;
	int i;

	for (i = 0; i < nbanks; i++) {
		reg = uniphier_gpio_bank_to_reg(i);

		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
		*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
	}

	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);

	return 0;
}

static int __maybe_unused uniphier_gpio_resume(struct device *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
	const u32 *val = priv->saved_vals;
	unsigned int reg;
	int i;

	for (i = 0; i < nbanks; i++) {
		reg = uniphier_gpio_bank_to_reg(i);

		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
		writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
	}

	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);

	uniphier_gpio_hw_init(priv);

	return 0;
}

static const struct dev_pm_ops uniphier_gpio_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
				     uniphier_gpio_resume)
};

static const struct of_device_id uniphier_gpio_match[] = {
	{ .compatible = "socionext,uniphier-gpio" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_gpio_match);

static struct platform_driver uniphier_gpio_driver = {
	.probe = uniphier_gpio_probe,
	.remove = uniphier_gpio_remove,
	.driver = {
		.name = "uniphier-gpio",
		.of_match_table = uniphier_gpio_match,
		.pm = &uniphier_gpio_pm_ops,
	},
};
module_platform_driver(uniphier_gpio_driver);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
dbe776c2 MY	1	/*
	2	* Copyright (C) 2017 Socionext Inc.
	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
ee8edbf8	15	#include <linux/bits.h>
dbe776c2 MY	16	#include <linux/gpio/driver.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqdomain.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/of_device.h>
	22	#include <linux/of_irq.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/spinlock.h>
	25	#include <dt-bindings/gpio/uniphier-gpio.h>
	26
	27	#define UNIPHIER_GPIO_BANK_MASK \
	28	GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0)
	29
	30	#define UNIPHIER_GPIO_IRQ_MAX_NUM 24
	31
	32	#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
	33	#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
	34	#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
	35	#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */
	36	#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */
	37	#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */
	38
	39	struct uniphier_gpio_priv {
	40	struct gpio_chip chip;
	41	struct irq_chip irq_chip;
	42	struct irq_domain *domain;
	43	void __iomem *regs;
	44	spinlock_t lock;
	45	u32 saved_vals[0];
	46	};
	47
	48	static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
	49	{
	50	unsigned int reg;
	51
	52	reg = (bank + 1) * 8;
	53
	54	/*
	55	* Unfortunately, the GPIO port registers are not contiguous because
	56	* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
	57	*/
	58	if (reg >= UNIPHIER_GPIO_IRQ_EN)
	59	reg += 0x10;
	60
	61	return reg;
	62	}
	63
	64	static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
	65	unsigned int bank, u32 mask)
	66	{
	67	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	68	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
	69	}
	70
	71	static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
	72	unsigned int reg, u32 mask, u32 val)
	73	{
	74	unsigned long flags;
	75	u32 tmp;
	76
	77	spin_lock_irqsave(&priv->lock, flags);
	78	tmp = readl(priv->regs + reg);
	79	tmp &= ~mask;
80	tmp \|= mask & val;
81	writel(tmp, priv->regs + reg);
82	spin_unlock_irqrestore(&priv->lock, flags);
83	}
84
85	static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank,
86	unsigned int reg, u32 mask, u32 val)
87	{
88	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
89
90	if (!mask)
91	return;
92
93	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
94	mask, val);
95	}
96
97	static void uniphier_gpio_offset_write(struct gpio_chip *chip,
98	unsigned int offset, unsigned int reg,
99	int val)
100	{
101	unsigned int bank;
102	u32 mask;
103
104	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
105
106	uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
107	}
108
109	static int uniphier_gpio_offset_read(struct gpio_chip *chip,
110	unsigned int offset, unsigned int reg)
111	{
112	struct uniphier_gpio_priv *priv = gpiochip_get_data(chip);
113	unsigned int bank, reg_offset;
114	u32 mask;
115
116	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
117	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
118
119	return !!(readl(priv->regs + reg_offset) & mask);
120	}
121
122	static int uniphier_gpio_get_direction(struct gpio_chip *chip,
123	unsigned int offset)
124	{
125	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR);
126	}
127
128	static int uniphier_gpio_direction_input(struct gpio_chip *chip,
129	unsigned int offset)
130	{
131	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1);
132
133	return 0;
134	}
135
136	static int uniphier_gpio_direction_output(struct gpio_chip *chip,
137	unsigned int offset, int val)
138	{
139	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
140	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0);
141
142	return 0;
143	}
144
145	static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset)
146	{
147	return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA);
148	}
149
150	static void uniphier_gpio_set(struct gpio_chip *chip,
151	unsigned int offset, int val)
152	{
153	uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
154	}
155
156	static void uniphier_gpio_set_multiple(struct gpio_chip *chip,
157	unsigned long mask, unsigned long bits)
158	{
159	unsigned int bank, shift, bank_mask, bank_bits;
160	int i;
161
162	for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) {
163	bank = i / UNIPHIER_GPIO_LINES_PER_BANK;
164	shift = i % BITS_PER_LONG;
165	bank_mask = (mask[BIT_WORD(i)] >> shift) &
166	UNIPHIER_GPIO_BANK_MASK;
167	bank_bits = bits[BIT_WORD(i)] >> shift;
168
169	uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA,
170	bank_mask, bank_bits);
171	}
172	}
173
174	static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
175	{
176	struct irq_fwspec fwspec;
177
178	if (offset < UNIPHIER_GPIO_IRQ_OFFSET)
179	return -ENXIO;
180
181	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
182	fwspec.param_count = 2;
183	fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET;
bbfbf04c MY	184	/*
	185	* IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH
	186	* temporarily. Anyway, ->irq_set_type() will override it later.
	187	*/
	188	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
dbe776c2 MY	189
	190	return irq_create_fwspec_mapping(&fwspec);
	191	}
	192
	193	static void uniphier_gpio_irq_mask(struct irq_data *data)
	194	{
	195	struct uniphier_gpio_priv *priv = data->chip_data;
	196	u32 mask = BIT(data->hwirq);
	197
	198	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0);
	199
	200	return irq_chip_mask_parent(data);
	201	}
	202
	203	static void uniphier_gpio_irq_unmask(struct irq_data *data)
	204	{
	205	struct uniphier_gpio_priv *priv = data->chip_data;
	206	u32 mask = BIT(data->hwirq);
	207
	208	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask);
	209
	210	return irq_chip_unmask_parent(data);
	211	}
	212
	213	static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type)
	214	{
	215	struct uniphier_gpio_priv *priv = data->chip_data;
	216	u32 mask = BIT(data->hwirq);
	217	u32 val = 0;
	218
	219	if (type == IRQ_TYPE_EDGE_BOTH) {
	220	val = mask;
	221	type = IRQ_TYPE_EDGE_FALLING;
	222	}
	223
	224	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
	225	/* To enable both edge detection, the noise filter must be enabled. */
	226	uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
	227
	228	return irq_chip_set_type_parent(data, type);
	229	}
	230
	231	static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv,
	232	unsigned int hwirq)
	233	{
	234	struct device_node *np = priv->chip.parent->of_node;
	235	const __be32 *range;
	236	u32 base, parent_base, size;
	237	int len;
	238
	239	range = of_get_property(np, "socionext,interrupt-ranges", &len);
	240	if (!range)
	241	return -EINVAL;
	242
	243	len /= sizeof(*range);
	244
	245	for (; len >= 3; len -= 3) {
	246	base = be32_to_cpu(*range++);
	247	parent_base = be32_to_cpu(*range++);
	248	size = be32_to_cpu(*range++);
	249
	250	if (base <= hwirq && hwirq < base + size)
	251	return hwirq - base + parent_base;
	252	}
253
254	return -ENOENT;
255	}
256
257	static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain,
258	struct irq_fwspec *fwspec,
259	unsigned long *out_hwirq,
260	unsigned int *out_type)
261	{
262	if (WARN_ON(fwspec->param_count < 2))
263	return -EINVAL;
264
265	*out_hwirq = fwspec->param[0];
266	*out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
267
268	return 0;
269	}
270
271	static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain,
272	unsigned int virq,
273	unsigned int nr_irqs, void *arg)
274	{
275	struct uniphier_gpio_priv *priv = domain->host_data;
276	struct irq_fwspec parent_fwspec;
277	irq_hw_number_t hwirq;
278	unsigned int type;
279	int ret;
280
281	if (WARN_ON(nr_irqs != 1))
282	return -EINVAL;
283
284	ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
285	if (ret)
286	return ret;
287
288	ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
289	if (ret < 0)
290	return ret;
291
292	/* parent is UniPhier AIDET */
293	parent_fwspec.fwnode = domain->parent->fwnode;
294	parent_fwspec.param_count = 2;
295	parent_fwspec.param[0] = ret;
296	parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ?
297	IRQ_TYPE_EDGE_FALLING : type;
298
299	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
300	&priv->irq_chip, priv);
301	if (ret)
302	return ret;
303
304	return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
305	}
306
6aa2f944 LT	307	static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain,
6aa2f944 LT	308	struct irq_data *data, bool early)
dbe776c2 MY	309	{
	310	struct uniphier_gpio_priv *priv = domain->host_data;
	311	struct gpio_chip *chip = &priv->chip;
	312
d124339d	313	return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
dbe776c2 MY	314	}
	315
	316	static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain,
	317	struct irq_data *data)
	318	{
	319	struct uniphier_gpio_priv *priv = domain->host_data;
	320	struct gpio_chip *chip = &priv->chip;
	321
	322	gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET);
	323	}
	324
	325	static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = {
	326	.alloc = uniphier_gpio_irq_domain_alloc,
	327	.free = irq_domain_free_irqs_common,
	328	.activate = uniphier_gpio_irq_domain_activate,
	329	.deactivate = uniphier_gpio_irq_domain_deactivate,
	330	.translate = uniphier_gpio_irq_domain_translate,
	331	};
	332
	333	static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv)
	334	{
	335	/*
	336	* Due to the hardware design, the noise filter must be enabled to
	337	* detect both edge interrupts. This filter is intended to remove the
	338	* noise from the irq lines. It does not work for GPIO input, so GPIO
	339	* debounce is not supported. Unfortunately, the filter period is
	340	* shared among all irq lines. Just choose a sensible period here.
	341	*/
	342	writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
	343	}
	344
	345	static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio)
	346	{
	347	return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK);
	348	}
	349
	350	static int uniphier_gpio_probe(struct platform_device *pdev)
	351	{
	352	struct device *dev = &pdev->dev;
	353	struct device_node *parent_np;
	354	struct irq_domain *parent_domain;
	355	struct uniphier_gpio_priv *priv;
	356	struct gpio_chip *chip;
	357	struct irq_chip *irq_chip;
	358	struct resource *regs;
	359	unsigned int nregs;
	360	u32 ngpios;
	361	int ret;
	362
	363	parent_np = of_irq_find_parent(dev->of_node);
	364	if (!parent_np)
	365	return -ENXIO;
	366
	367	parent_domain = irq_find_host(parent_np);
	368	of_node_put(parent_np);
	369	if (!parent_domain)
	370	return -EPROBE_DEFER;
	371
	372	ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
	373	if (ret)
	374	return ret;
	375
	376	nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3;
0ed2dd03	377	priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs),
dbe776c2 MY	378	GFP_KERNEL);
	379	if (!priv)
	380	return -ENOMEM;
	381
	382	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	383	priv->regs = devm_ioremap_resource(dev, regs);
	384	if (IS_ERR(priv->regs))
	385	return PTR_ERR(priv->regs);
	386
	387	spin_lock_init(&priv->lock);
	388
	389	chip = &priv->chip;
	390	chip->label = dev_name(dev);
	391	chip->parent = dev;
	392	chip->request = gpiochip_generic_request;
	393	chip->free = gpiochip_generic_free;
	394	chip->get_direction = uniphier_gpio_get_direction;
	395	chip->direction_input = uniphier_gpio_direction_input;
	396	chip->direction_output = uniphier_gpio_direction_output;
	397	chip->get = uniphier_gpio_get;
	398	chip->set = uniphier_gpio_set;
	399	chip->set_multiple = uniphier_gpio_set_multiple;
	400	chip->to_irq = uniphier_gpio_to_irq;
	401	chip->base = -1;
	402	chip->ngpio = ngpios;
	403
	404	irq_chip = &priv->irq_chip;
	405	irq_chip->name = dev_name(dev);
	406	irq_chip->irq_mask = uniphier_gpio_irq_mask;
	407	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
	408	irq_chip->irq_eoi = irq_chip_eoi_parent;
	409	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
	410	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
	411
	412	uniphier_gpio_hw_init(priv);
	413
	414	ret = devm_gpiochip_add_data(dev, chip, priv);
	415	if (ret)
	416	return ret;
	417
	418	priv->domain = irq_domain_create_hierarchy(
	419	parent_domain, 0,
	420	UNIPHIER_GPIO_IRQ_MAX_NUM,
	421	of_node_to_fwnode(dev->of_node),
	422	&uniphier_gpio_irq_domain_ops, priv);
	423	if (!priv->domain)
	424	return -ENOMEM;
	425
	426	platform_set_drvdata(pdev, priv);
	427
	428	return 0;
	429	}
	430
	431	static int uniphier_gpio_remove(struct platform_device *pdev)
	432	{
	433	struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev);
	434
	435	irq_domain_remove(priv->domain);
	436
	437	return 0;
	438	}
	439
	440	static int __maybe_unused uniphier_gpio_suspend(struct device *dev)
	441	{
442	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
443	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
444	u32 *val = priv->saved_vals;
445	unsigned int reg;
446	int i;
447
448	for (i = 0; i < nbanks; i++) {
449	reg = uniphier_gpio_bank_to_reg(i);
450
451	*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
452	*val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
453	}
454
455	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
456	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
457	*val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
458
459	return 0;
460	}
461
462	static int __maybe_unused uniphier_gpio_resume(struct device *dev)
463	{
464	struct uniphier_gpio_priv *priv = dev_get_drvdata(dev);
465	unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio);
466	const u32 *val = priv->saved_vals;
467	unsigned int reg;
468	int i;
469
470	for (i = 0; i < nbanks; i++) {
471	reg = uniphier_gpio_bank_to_reg(i);
472
473	writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
474	writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
475	}
476
477	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
478	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
479	writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
480
481	uniphier_gpio_hw_init(priv);
482
483	return 0;
484	}
485
486	static const struct dev_pm_ops uniphier_gpio_pm_ops = {
487	SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend,
488	uniphier_gpio_resume)
489	};
490
491	static const struct of_device_id uniphier_gpio_match[] = {
492	{ .compatible = "socionext,uniphier-gpio" },
493	{ /* sentinel */ }
494	};
495	MODULE_DEVICE_TABLE(of, uniphier_gpio_match);
496
497	static struct platform_driver uniphier_gpio_driver = {
498	.probe = uniphier_gpio_probe,
499	.remove = uniphier_gpio_remove,
500	.driver = {
501	.name = "uniphier-gpio",
502	.of_match_table = uniphier_gpio_match,
503	.pm = &uniphier_gpio_pm_ops,
504	},
505	};
506	module_platform_driver(uniphier_gpio_driver);
507
508	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
509	MODULE_DESCRIPTION("UniPhier GPIO driver");
13f9d59c	510	MODULE_LICENSE("GPL v2");