Commit | Line | Data |
---|---|---|
82c29810 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
35570ac6 | 2 | /* |
c103de24 | 3 | * Timberdale FPGA GPIO driver |
52ad9053 | 4 | * Author: Mocean Laboratories |
35570ac6 | 5 | * Copyright (c) 2009 Intel Corporation |
35570ac6 RR |
6 | */ |
7 | ||
8 | /* Supports: | |
9 | * Timberdale FPGA GPIO | |
10 | */ | |
11 | ||
52ad9053 | 12 | #include <linux/init.h> |
50fe83a3 | 13 | #include <linux/gpio/driver.h> |
35570ac6 | 14 | #include <linux/platform_device.h> |
e3cb91ce | 15 | #include <linux/irq.h> |
35570ac6 RR |
16 | #include <linux/io.h> |
17 | #include <linux/timb_gpio.h> | |
18 | #include <linux/interrupt.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
35570ac6 RR |
20 | |
21 | #define DRIVER_NAME "timb-gpio" | |
22 | ||
23 | #define TGPIOVAL 0x00 | |
24 | #define TGPIODIR 0x04 | |
25 | #define TGPIO_IER 0x08 | |
26 | #define TGPIO_ISR 0x0c | |
27 | #define TGPIO_IPR 0x10 | |
28 | #define TGPIO_ICR 0x14 | |
29 | #define TGPIO_FLR 0x18 | |
30 | #define TGPIO_LVR 0x1c | |
8c35c89a RR |
31 | #define TGPIO_VER 0x20 |
32 | #define TGPIO_BFLR 0x24 | |
35570ac6 RR |
33 | |
34 | struct timbgpio { | |
35 | void __iomem *membase; | |
36 | spinlock_t lock; /* mutual exclusion */ | |
37 | struct gpio_chip gpio; | |
38 | int irq_base; | |
76d800a5 | 39 | unsigned long last_ier; |
35570ac6 RR |
40 | }; |
41 | ||
42 | static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, | |
43 | unsigned offset, bool enabled) | |
44 | { | |
92a41e2f | 45 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
9e8bc2dd | 46 | unsigned long flags; |
35570ac6 RR |
47 | u32 reg; |
48 | ||
9e8bc2dd | 49 | spin_lock_irqsave(&tgpio->lock, flags); |
35570ac6 RR |
50 | reg = ioread32(tgpio->membase + offset); |
51 | ||
52 | if (enabled) | |
53 | reg |= (1 << index); | |
54 | else | |
55 | reg &= ~(1 << index); | |
56 | ||
57 | iowrite32(reg, tgpio->membase + offset); | |
9e8bc2dd | 58 | spin_unlock_irqrestore(&tgpio->lock, flags); |
35570ac6 RR |
59 | |
60 | return 0; | |
61 | } | |
62 | ||
63 | static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |
64 | { | |
65 | return timbgpio_update_bit(gpio, nr, TGPIODIR, true); | |
66 | } | |
67 | ||
68 | static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) | |
69 | { | |
92a41e2f | 70 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
35570ac6 RR |
71 | u32 value; |
72 | ||
73 | value = ioread32(tgpio->membase + TGPIOVAL); | |
74 | return (value & (1 << nr)) ? 1 : 0; | |
75 | } | |
76 | ||
77 | static int timbgpio_gpio_direction_output(struct gpio_chip *gpio, | |
78 | unsigned nr, int val) | |
79 | { | |
80 | return timbgpio_update_bit(gpio, nr, TGPIODIR, false); | |
81 | } | |
82 | ||
83 | static void timbgpio_gpio_set(struct gpio_chip *gpio, | |
84 | unsigned nr, int val) | |
85 | { | |
86 | timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); | |
87 | } | |
88 | ||
89 | static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) | |
90 | { | |
92a41e2f | 91 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
35570ac6 RR |
92 | |
93 | if (tgpio->irq_base <= 0) | |
94 | return -EINVAL; | |
95 | ||
96 | return tgpio->irq_base + offset; | |
97 | } | |
98 | ||
99 | /* | |
100 | * GPIO IRQ | |
101 | */ | |
a1f5f22a | 102 | static void timbgpio_irq_disable(struct irq_data *d) |
35570ac6 | 103 | { |
a1f5f22a LB |
104 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
105 | int offset = d->irq - tgpio->irq_base; | |
76d800a5 | 106 | unsigned long flags; |
35570ac6 | 107 | |
76d800a5 | 108 | spin_lock_irqsave(&tgpio->lock, flags); |
d79550a7 | 109 | tgpio->last_ier &= ~(1UL << offset); |
76d800a5 TH |
110 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); |
111 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
35570ac6 RR |
112 | } |
113 | ||
a1f5f22a | 114 | static void timbgpio_irq_enable(struct irq_data *d) |
35570ac6 | 115 | { |
a1f5f22a LB |
116 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
117 | int offset = d->irq - tgpio->irq_base; | |
76d800a5 | 118 | unsigned long flags; |
35570ac6 | 119 | |
76d800a5 | 120 | spin_lock_irqsave(&tgpio->lock, flags); |
d79550a7 | 121 | tgpio->last_ier |= 1UL << offset; |
76d800a5 TH |
122 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); |
123 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
35570ac6 RR |
124 | } |
125 | ||
a1f5f22a | 126 | static int timbgpio_irq_type(struct irq_data *d, unsigned trigger) |
35570ac6 | 127 | { |
a1f5f22a LB |
128 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
129 | int offset = d->irq - tgpio->irq_base; | |
35570ac6 | 130 | unsigned long flags; |
8c35c89a RR |
131 | u32 lvr, flr, bflr = 0; |
132 | u32 ver; | |
2a481800 | 133 | int ret = 0; |
35570ac6 RR |
134 | |
135 | if (offset < 0 || offset > tgpio->gpio.ngpio) | |
136 | return -EINVAL; | |
137 | ||
8c35c89a RR |
138 | ver = ioread32(tgpio->membase + TGPIO_VER); |
139 | ||
35570ac6 RR |
140 | spin_lock_irqsave(&tgpio->lock, flags); |
141 | ||
142 | lvr = ioread32(tgpio->membase + TGPIO_LVR); | |
143 | flr = ioread32(tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
144 | if (ver > 2) |
145 | bflr = ioread32(tgpio->membase + TGPIO_BFLR); | |
35570ac6 RR |
146 | |
147 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
8c35c89a | 148 | bflr &= ~(1 << offset); |
35570ac6 RR |
149 | flr &= ~(1 << offset); |
150 | if (trigger & IRQ_TYPE_LEVEL_HIGH) | |
151 | lvr |= 1 << offset; | |
152 | else | |
153 | lvr &= ~(1 << offset); | |
154 | } | |
155 | ||
8c35c89a | 156 | if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
2a481800 JL |
157 | if (ver < 3) { |
158 | ret = -EINVAL; | |
159 | goto out; | |
8a29a409 | 160 | } else { |
8c35c89a RR |
161 | flr |= 1 << offset; |
162 | bflr |= 1 << offset; | |
163 | } | |
164 | } else { | |
165 | bflr &= ~(1 << offset); | |
35570ac6 | 166 | flr |= 1 << offset; |
35570ac6 | 167 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
35570ac6 | 168 | lvr &= ~(1 << offset); |
8c35c89a RR |
169 | else |
170 | lvr |= 1 << offset; | |
35570ac6 RR |
171 | } |
172 | ||
173 | iowrite32(lvr, tgpio->membase + TGPIO_LVR); | |
174 | iowrite32(flr, tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
175 | if (ver > 2) |
176 | iowrite32(bflr, tgpio->membase + TGPIO_BFLR); | |
177 | ||
35570ac6 | 178 | iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); |
35570ac6 | 179 | |
2a481800 JL |
180 | out: |
181 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
182 | return ret; | |
35570ac6 RR |
183 | } |
184 | ||
bd0b9ac4 | 185 | static void timbgpio_irq(struct irq_desc *desc) |
35570ac6 | 186 | { |
476f8b4c JL |
187 | struct timbgpio *tgpio = irq_desc_get_handler_data(desc); |
188 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
35570ac6 RR |
189 | unsigned long ipr; |
190 | int offset; | |
191 | ||
476f8b4c | 192 | data->chip->irq_ack(data); |
35570ac6 RR |
193 | ipr = ioread32(tgpio->membase + TGPIO_IPR); |
194 | iowrite32(ipr, tgpio->membase + TGPIO_ICR); | |
195 | ||
76d800a5 TH |
196 | /* |
197 | * Some versions of the hardware trash the IER register if more than | |
198 | * one interrupt is received simultaneously. | |
199 | */ | |
200 | iowrite32(0, tgpio->membase + TGPIO_IER); | |
201 | ||
984b3f57 | 202 | for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) |
35570ac6 | 203 | generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); |
76d800a5 TH |
204 | |
205 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); | |
35570ac6 RR |
206 | } |
207 | ||
208 | static struct irq_chip timbgpio_irqchip = { | |
209 | .name = "GPIO", | |
a1f5f22a LB |
210 | .irq_enable = timbgpio_irq_enable, |
211 | .irq_disable = timbgpio_irq_disable, | |
212 | .irq_set_type = timbgpio_irq_type, | |
35570ac6 RR |
213 | }; |
214 | ||
3836309d | 215 | static int timbgpio_probe(struct platform_device *pdev) |
35570ac6 RR |
216 | { |
217 | int err, i; | |
0ed3398e | 218 | struct device *dev = &pdev->dev; |
35570ac6 RR |
219 | struct gpio_chip *gc; |
220 | struct timbgpio *tgpio; | |
e56aee18 | 221 | struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev); |
35570ac6 RR |
222 | int irq = platform_get_irq(pdev, 0); |
223 | ||
224 | if (!pdata || pdata->nr_pins > 32) { | |
0ed3398e | 225 | dev_err(dev, "Invalid platform data\n"); |
226 | return -EINVAL; | |
35570ac6 RR |
227 | } |
228 | ||
2c3087e1 | 229 | tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL); |
587ca5ed | 230 | if (!tgpio) |
0ed3398e | 231 | return -EINVAL; |
587ca5ed | 232 | |
35570ac6 RR |
233 | tgpio->irq_base = pdata->irq_base; |
234 | ||
235 | spin_lock_init(&tgpio->lock); | |
236 | ||
aa6c9b91 | 237 | tgpio->membase = devm_platform_ioremap_resource(pdev, 0); |
fa283db7 AKC |
238 | if (IS_ERR(tgpio->membase)) |
239 | return PTR_ERR(tgpio->membase); | |
35570ac6 RR |
240 | |
241 | gc = &tgpio->gpio; | |
242 | ||
243 | gc->label = dev_name(&pdev->dev); | |
244 | gc->owner = THIS_MODULE; | |
58383c78 | 245 | gc->parent = &pdev->dev; |
35570ac6 RR |
246 | gc->direction_input = timbgpio_gpio_direction_input; |
247 | gc->get = timbgpio_gpio_get; | |
248 | gc->direction_output = timbgpio_gpio_direction_output; | |
249 | gc->set = timbgpio_gpio_set; | |
250 | gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL; | |
251 | gc->dbg_show = NULL; | |
252 | gc->base = pdata->gpio_base; | |
253 | gc->ngpio = pdata->nr_pins; | |
9fb1f39e | 254 | gc->can_sleep = false; |
35570ac6 | 255 | |
43fad832 | 256 | err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio); |
35570ac6 | 257 | if (err) |
0ed3398e | 258 | return err; |
35570ac6 | 259 | |
35570ac6 RR |
260 | /* make sure to disable interrupts */ |
261 | iowrite32(0x0, tgpio->membase + TGPIO_IER); | |
262 | ||
263 | if (irq < 0 || tgpio->irq_base <= 0) | |
264 | return 0; | |
265 | ||
266 | for (i = 0; i < pdata->nr_pins; i++) { | |
e5428a68 LW |
267 | irq_set_chip_and_handler(tgpio->irq_base + i, |
268 | &timbgpio_irqchip, handle_simple_irq); | |
b51804bc | 269 | irq_set_chip_data(tgpio->irq_base + i, tgpio); |
23393d49 | 270 | irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE); |
35570ac6 RR |
271 | } |
272 | ||
8a52211a | 273 | irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio); |
35570ac6 RR |
274 | |
275 | return 0; | |
35570ac6 RR |
276 | } |
277 | ||
35570ac6 RR |
278 | static struct platform_driver timbgpio_platform_driver = { |
279 | .driver = { | |
52ad9053 PG |
280 | .name = DRIVER_NAME, |
281 | .suppress_bind_attrs = true, | |
35570ac6 RR |
282 | }, |
283 | .probe = timbgpio_probe, | |
35570ac6 RR |
284 | }; |
285 | ||
286 | /*--------------------------------------------------------------------------*/ | |
287 | ||
52ad9053 | 288 | builtin_platform_driver(timbgpio_platform_driver); |